1 //===-- Mips16ISelLowering.h - Mips16 DAG Lowering Interface ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Subclass of MipsTargetLowering specialized for mips16.
12 //===----------------------------------------------------------------------===//
13 #define DEBUG_TYPE "mips-lower"
14 #include "Mips16ISelLowering.h"
15 #include "MipsRegisterInfo.h"
16 #include "MipsTargetMachine.h"
17 #include "MCTargetDesc/MipsBaseInfo.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Target/TargetInstrInfo.h"
24 static cl::opt<bool> DontExpandCondPseudos16(
25 "mips16-dont-expand-cond-pseudo",
27 cl::desc("Dont expand conditional move related "
28 "pseudos for Mips 16"),
32 struct Mips16Libcall {
33 RTLIB::Libcall Libcall;
36 bool operator<(const Mips16Libcall &RHS) const {
37 return std::strcmp(Name, RHS.Name) < 0;
41 struct Mips16IntrinsicHelperType{
45 bool operator<(const Mips16IntrinsicHelperType &RHS) const {
46 return std::strcmp(Name, RHS.Name) < 0;
48 bool operator==(const Mips16IntrinsicHelperType &RHS) const {
49 return std::strcmp(Name, RHS.Name) == 0;
54 // Libcalls for which no helper is generated. Sorted by name for binary search.
55 static const Mips16Libcall HardFloatLibCalls[] = {
56 { RTLIB::ADD_F64, "__mips16_adddf3" },
57 { RTLIB::ADD_F32, "__mips16_addsf3" },
58 { RTLIB::DIV_F64, "__mips16_divdf3" },
59 { RTLIB::DIV_F32, "__mips16_divsf3" },
60 { RTLIB::OEQ_F64, "__mips16_eqdf2" },
61 { RTLIB::OEQ_F32, "__mips16_eqsf2" },
62 { RTLIB::FPEXT_F32_F64, "__mips16_extendsfdf2" },
63 { RTLIB::FPTOSINT_F64_I32, "__mips16_fix_truncdfsi" },
64 { RTLIB::FPTOSINT_F32_I32, "__mips16_fix_truncsfsi" },
65 { RTLIB::SINTTOFP_I32_F64, "__mips16_floatsidf" },
66 { RTLIB::SINTTOFP_I32_F32, "__mips16_floatsisf" },
67 { RTLIB::UINTTOFP_I32_F64, "__mips16_floatunsidf" },
68 { RTLIB::UINTTOFP_I32_F32, "__mips16_floatunsisf" },
69 { RTLIB::OGE_F64, "__mips16_gedf2" },
70 { RTLIB::OGE_F32, "__mips16_gesf2" },
71 { RTLIB::OGT_F64, "__mips16_gtdf2" },
72 { RTLIB::OGT_F32, "__mips16_gtsf2" },
73 { RTLIB::OLE_F64, "__mips16_ledf2" },
74 { RTLIB::OLE_F32, "__mips16_lesf2" },
75 { RTLIB::OLT_F64, "__mips16_ltdf2" },
76 { RTLIB::OLT_F32, "__mips16_ltsf2" },
77 { RTLIB::MUL_F64, "__mips16_muldf3" },
78 { RTLIB::MUL_F32, "__mips16_mulsf3" },
79 { RTLIB::UNE_F64, "__mips16_nedf2" },
80 { RTLIB::UNE_F32, "__mips16_nesf2" },
81 { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_dc" }, // No associated libcall.
82 { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_df" }, // No associated libcall.
83 { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_sc" }, // No associated libcall.
84 { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_sf" }, // No associated libcall.
85 { RTLIB::SUB_F64, "__mips16_subdf3" },
86 { RTLIB::SUB_F32, "__mips16_subsf3" },
87 { RTLIB::FPROUND_F64_F32, "__mips16_truncdfsf2" },
88 { RTLIB::UO_F64, "__mips16_unorddf2" },
89 { RTLIB::UO_F32, "__mips16_unordsf2" }
92 static const Mips16IntrinsicHelperType Mips16IntrinsicHelper[] = {
93 {"ceil", "__mips16_call_stub_df_2"},
94 {"ceilf", "__mips16_call_stub_sf_1"},
95 {"copysign", "__mips16_call_stub_df_10"},
96 {"copysignf", "__mips16_call_stub_sf_5"},
97 {"cos", "__mips16_call_stub_df_2"},
98 {"cosf", "__mips16_call_stub_sf_1"},
99 {"exp2", "__mips16_call_stub_df_2"},
100 {"exp2f", "__mips16_call_stub_sf_1"},
101 {"floor", "__mips16_call_stub_df_2"},
102 {"floorf", "__mips16_call_stub_sf_1"},
103 {"log2", "__mips16_call_stub_df_2"},
104 {"log2f", "__mips16_call_stub_sf_1"},
105 {"nearbyint", "__mips16_call_stub_df_2"},
106 {"nearbyintf", "__mips16_call_stub_sf_1"},
107 {"rint", "__mips16_call_stub_df_2"},
108 {"rintf", "__mips16_call_stub_sf_1"},
109 {"sin", "__mips16_call_stub_df_2"},
110 {"sinf", "__mips16_call_stub_sf_1"},
111 {"sqrt", "__mips16_call_stub_df_2"},
112 {"sqrtf", "__mips16_call_stub_sf_1"},
113 {"trunc", "__mips16_call_stub_df_2"},
114 {"truncf", "__mips16_call_stub_sf_1"},
117 Mips16TargetLowering::Mips16TargetLowering(MipsTargetMachine &TM)
118 : MipsTargetLowering(TM) {
120 // set up as if mips32 and then revert so we can test the mechanism
122 addRegisterClass(MVT::i32, &Mips::CPURegsRegClass);
123 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
124 computeRegisterProperties();
125 clearRegisterClasses();
127 // Set up the register classes
128 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
130 if (Subtarget->inMips16HardFloat())
131 setMips16HardFloatLibCalls();
133 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
134 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
135 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
136 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
137 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
138 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
139 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
140 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
141 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
142 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
143 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
144 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
145 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
147 computeRegisterProperties();
150 const MipsTargetLowering *
151 llvm::createMips16TargetLowering(MipsTargetMachine &TM) {
152 return new Mips16TargetLowering(TM);
156 Mips16TargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
161 Mips16TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
162 MachineBasicBlock *BB) const {
163 switch (MI->getOpcode()) {
165 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
167 return emitSel16(Mips::BeqzRxImm16, MI, BB);
169 return emitSel16(Mips::BnezRxImm16, MI, BB);
170 case Mips::SelTBteqZCmpi:
171 return emitSeliT16(Mips::BteqzX16, Mips::CmpiRxImmX16, MI, BB);
172 case Mips::SelTBteqZSlti:
173 return emitSeliT16(Mips::BteqzX16, Mips::SltiRxImmX16, MI, BB);
174 case Mips::SelTBteqZSltiu:
175 return emitSeliT16(Mips::BteqzX16, Mips::SltiuRxImmX16, MI, BB);
176 case Mips::SelTBtneZCmpi:
177 return emitSeliT16(Mips::BtnezX16, Mips::CmpiRxImmX16, MI, BB);
178 case Mips::SelTBtneZSlti:
179 return emitSeliT16(Mips::BtnezX16, Mips::SltiRxImmX16, MI, BB);
180 case Mips::SelTBtneZSltiu:
181 return emitSeliT16(Mips::BtnezX16, Mips::SltiuRxImmX16, MI, BB);
182 case Mips::SelTBteqZCmp:
183 return emitSelT16(Mips::BteqzX16, Mips::CmpRxRy16, MI, BB);
184 case Mips::SelTBteqZSlt:
185 return emitSelT16(Mips::BteqzX16, Mips::SltRxRy16, MI, BB);
186 case Mips::SelTBteqZSltu:
187 return emitSelT16(Mips::BteqzX16, Mips::SltuRxRy16, MI, BB);
188 case Mips::SelTBtneZCmp:
189 return emitSelT16(Mips::BtnezX16, Mips::CmpRxRy16, MI, BB);
190 case Mips::SelTBtneZSlt:
191 return emitSelT16(Mips::BtnezX16, Mips::SltRxRy16, MI, BB);
192 case Mips::SelTBtneZSltu:
193 return emitSelT16(Mips::BtnezX16, Mips::SltuRxRy16, MI, BB);
194 case Mips::BteqzT8CmpX16:
195 return emitFEXT_T8I816_ins(Mips::BteqzX16, Mips::CmpRxRy16, MI, BB);
196 case Mips::BteqzT8SltX16:
197 return emitFEXT_T8I816_ins(Mips::BteqzX16, Mips::SltRxRy16, MI, BB);
198 case Mips::BteqzT8SltuX16:
199 // TBD: figure out a way to get this or remove the instruction
201 return emitFEXT_T8I816_ins(Mips::BteqzX16, Mips::SltuRxRy16, MI, BB);
202 case Mips::BtnezT8CmpX16:
203 return emitFEXT_T8I816_ins(Mips::BtnezX16, Mips::CmpRxRy16, MI, BB);
204 case Mips::BtnezT8SltX16:
205 return emitFEXT_T8I816_ins(Mips::BtnezX16, Mips::SltRxRy16, MI, BB);
206 case Mips::BtnezT8SltuX16:
207 // TBD: figure out a way to get this or remove the instruction
209 return emitFEXT_T8I816_ins(Mips::BtnezX16, Mips::SltuRxRy16, MI, BB);
210 case Mips::BteqzT8CmpiX16: return emitFEXT_T8I8I16_ins(
211 Mips::BteqzX16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, false, MI, BB);
212 case Mips::BteqzT8SltiX16: return emitFEXT_T8I8I16_ins(
213 Mips::BteqzX16, Mips::SltiRxImm16, Mips::SltiRxImmX16, true, MI, BB);
214 case Mips::BteqzT8SltiuX16: return emitFEXT_T8I8I16_ins(
215 Mips::BteqzX16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, false, MI, BB);
216 case Mips::BtnezT8CmpiX16: return emitFEXT_T8I8I16_ins(
217 Mips::BtnezX16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, false, MI, BB);
218 case Mips::BtnezT8SltiX16: return emitFEXT_T8I8I16_ins(
219 Mips::BtnezX16, Mips::SltiRxImm16, Mips::SltiRxImmX16, true, MI, BB);
220 case Mips::BtnezT8SltiuX16: return emitFEXT_T8I8I16_ins(
221 Mips::BtnezX16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, false, MI, BB);
223 case Mips::SltCCRxRy16:
224 return emitFEXT_CCRX16_ins(Mips::SltRxRy16, MI, BB);
226 case Mips::SltiCCRxImmX16:
227 return emitFEXT_CCRXI16_ins
228 (Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB);
229 case Mips::SltiuCCRxImmX16:
230 return emitFEXT_CCRXI16_ins
231 (Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB);
232 case Mips::SltuCCRxRy16:
233 return emitFEXT_CCRX16_ins
234 (Mips::SltuRxRy16, MI, BB);
238 bool Mips16TargetLowering::
239 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
240 unsigned NextStackOffset,
241 const MipsFunctionInfo& FI) const {
242 // No tail call optimization for mips16.
246 void Mips16TargetLowering::setMips16HardFloatLibCalls() {
247 for (unsigned I = 0; I != array_lengthof(HardFloatLibCalls); ++I) {
248 assert((I == 0 || HardFloatLibCalls[I - 1] < HardFloatLibCalls[I]) &&
249 "Array not sorted!");
250 if (HardFloatLibCalls[I].Libcall != RTLIB::UNKNOWN_LIBCALL)
251 setLibcallName(HardFloatLibCalls[I].Libcall, HardFloatLibCalls[I].Name);
254 setLibcallName(RTLIB::O_F64, "__mips16_unorddf2");
255 setLibcallName(RTLIB::O_F32, "__mips16_unordsf2");
259 // The Mips16 hard float is a crazy quilt inherited from gcc. I have a much
260 // cleaner way to do all of this but it will have to wait until the traditional
261 // gcc mechanism is completed.
263 // For Pic, in order for Mips16 code to call Mips32 code which according the abi
264 // have either arguments or returned values placed in floating point registers,
265 // we use a set of helper functions. (This includes functions which return type
266 // complex which on Mips are returned in a pair of floating point registers).
268 // This is an encoding that we inherited from gcc.
269 // In Mips traditional O32, N32 ABI, floating point numbers are passed in
270 // floating point argument registers 1,2 only when the first and optionally
271 // the second arguments are float (sf) or double (df).
272 // For Mips16 we are only concerned with the situations where floating point
273 // arguments are being passed in floating point registers by the ABI, because
274 // Mips16 mode code cannot execute floating point instructions to load those
275 // values and hence helper functions are needed.
276 // The possibilities are (), (sf), (sf, sf), (sf, df), (df), (df, sf), (df, df)
277 // the helper function suffixs for these are:
278 // 0, 1, 5, 9, 2, 6, 10
279 // this suffix can then be calculated as follows:
280 // for a given argument Arg:
281 // Arg1x, Arg2x = 1 : Arg is sf
283 // 0: Arg is neither sf or df
284 // So this stub is the string for number Arg1x + Arg2x*4.
285 // However not all numbers between 0 and 10 are possible, we check anyway and
286 // assert if the impossible exists.
289 unsigned int Mips16TargetLowering::getMips16HelperFunctionStubNumber
290 (ArgListTy &Args) const {
291 unsigned int resultNum = 0;
292 if (Args.size() >= 1) {
293 Type *t = Args[0].Ty;
294 if (t->isFloatTy()) {
297 else if (t->isDoubleTy()) {
302 if (Args.size() >=2) {
303 Type *t = Args[1].Ty;
304 if (t->isFloatTy()) {
307 else if (t->isDoubleTy()) {
316 // prefixs are attached to stub numbers depending on the return type .
317 // return type: float sf_
319 // single complex sc_
320 // double complext dc_
324 // The full name of a helper function is__mips16_call_stub +
325 // return type dependent prefix + stub number
328 // This is something that probably should be in a different source file and
329 // perhaps done differently but my main purpose is to not waste runtime
330 // on something that we can enumerate in the source. Another possibility is
331 // to have a python script to generate these mapping tables. This will do
332 // for now. There are a whole series of helper function mapping arrays, one
333 // for each return type class as outlined above. There there are 11 possible
334 // entries. Ones with 0 are ones which should never be selected
336 // All the arrays are similar except for ones which return neither
337 // sf, df, sc, dc, in which only care about ones which have sf or df as a
340 #define P_ "__mips16_call_stub_"
341 #define MAX_STUB_NUMBER 10
342 #define T1 P "1", P "2", 0, 0, P "5", P "6", 0, 0, P "9", P "10"
345 static char const * vMips16Helper[MAX_STUB_NUMBER+1] =
349 static char const * sfMips16Helper[MAX_STUB_NUMBER+1] =
353 static char const * dfMips16Helper[MAX_STUB_NUMBER+1] =
357 static char const * scMips16Helper[MAX_STUB_NUMBER+1] =
361 static char const * dcMips16Helper[MAX_STUB_NUMBER+1] =
367 const char* Mips16TargetLowering::
368 getMips16HelperFunction
369 (Type* RetTy, ArgListTy &Args, bool &needHelper) const {
370 const unsigned int stubNum = getMips16HelperFunctionStubNumber(Args);
372 const unsigned int maxStubNum = 10;
373 assert(stubNum <= maxStubNum);
374 const bool validStubNum[maxStubNum+1] =
375 {true, true, true, false, false, true, true, false, false, true, true};
376 assert(validStubNum[stubNum]);
379 if (RetTy->isFloatTy()) {
380 result = sfMips16Helper[stubNum];
382 else if (RetTy ->isDoubleTy()) {
383 result = dfMips16Helper[stubNum];
385 else if (RetTy->isStructTy()) {
386 // check if it's complex
387 if (RetTy->getNumContainedTypes() == 2) {
388 if ((RetTy->getContainedType(0)->isFloatTy()) &&
389 (RetTy->getContainedType(1)->isFloatTy())) {
390 result = scMips16Helper[stubNum];
392 else if ((RetTy->getContainedType(0)->isDoubleTy()) &&
393 (RetTy->getContainedType(1)->isDoubleTy())) {
394 result = dcMips16Helper[stubNum];
397 llvm_unreachable("Uncovered condition");
401 llvm_unreachable("Uncovered condition");
409 result = vMips16Helper[stubNum];
415 void Mips16TargetLowering::
416 getOpndList(SmallVectorImpl<SDValue> &Ops,
417 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
418 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
419 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
420 SelectionDAG &DAG = CLI.DAG;
421 const char* Mips16HelperFunction = 0;
422 bool NeedMips16Helper = false;
424 if (getTargetMachine().Options.UseSoftFloat &&
425 Subtarget->inMips16HardFloat()) {
427 // currently we don't have symbols tagged with the mips16 or mips32
428 // qualifier so we will assume that we don't know what kind it is.
429 // and generate the helper
431 bool LookupHelper = true;
432 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(CLI.Callee)) {
433 Mips16Libcall Find = { RTLIB::UNKNOWN_LIBCALL, S->getSymbol() };
435 if (std::binary_search(HardFloatLibCalls, array_endof(HardFloatLibCalls),
437 LookupHelper = false;
439 Mips16IntrinsicHelperType IntrinsicFind = {S->getSymbol(), ""};
440 // one more look at list of intrinsics
441 if (std::binary_search(Mips16IntrinsicHelper,
442 array_endof(Mips16IntrinsicHelper),
444 const Mips16IntrinsicHelperType *h =(std::find(Mips16IntrinsicHelper,
445 array_endof(Mips16IntrinsicHelper),
447 Mips16HelperFunction = h->Helper;
448 NeedMips16Helper = true;
449 LookupHelper = false;
453 } else if (GlobalAddressSDNode *G =
454 dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
455 Mips16Libcall Find = { RTLIB::UNKNOWN_LIBCALL,
456 G->getGlobal()->getName().data() };
458 if (std::binary_search(HardFloatLibCalls, array_endof(HardFloatLibCalls),
460 LookupHelper = false;
462 if (LookupHelper) Mips16HelperFunction =
463 getMips16HelperFunction(CLI.RetTy, CLI.Args, NeedMips16Helper);
467 SDValue JumpTarget = Callee;
469 // T9 should contain the address of the callee function if
470 // -reloction-model=pic or it is an indirect call.
471 if (IsPICCall || !GlobalOrExternal) {
472 unsigned V0Reg = Mips::V0;
473 if (NeedMips16Helper) {
474 RegsToPass.push_front(std::make_pair(V0Reg, Callee));
475 JumpTarget = DAG.getExternalSymbol(Mips16HelperFunction, getPointerTy());
476 JumpTarget = getAddrGlobal(JumpTarget, DAG, MipsII::MO_GOT);
478 RegsToPass.push_front(std::make_pair((unsigned)Mips::T9, Callee));
481 Ops.push_back(JumpTarget);
483 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
484 InternalLinkage, CLI, Callee, Chain);
487 MachineBasicBlock *Mips16TargetLowering::
488 emitSel16(unsigned Opc, MachineInstr *MI, MachineBasicBlock *BB) const {
489 if (DontExpandCondPseudos16)
491 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
492 DebugLoc DL = MI->getDebugLoc();
493 // To "insert" a SELECT_CC instruction, we actually have to insert the
494 // diamond control-flow pattern. The incoming instruction knows the
495 // destination vreg to set, the condition code register to branch on, the
496 // true/false values to select between, and a branch opcode to use.
497 const BasicBlock *LLVM_BB = BB->getBasicBlock();
498 MachineFunction::iterator It = BB;
505 // bNE r1, r0, copy1MBB
506 // fallthrough --> copy0MBB
507 MachineBasicBlock *thisMBB = BB;
508 MachineFunction *F = BB->getParent();
509 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
510 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
511 F->insert(It, copy0MBB);
512 F->insert(It, sinkMBB);
514 // Transfer the remainder of BB and its successor edges to sinkMBB.
515 sinkMBB->splice(sinkMBB->begin(), BB,
516 llvm::next(MachineBasicBlock::iterator(MI)),
518 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
520 // Next, add the true and fallthrough blocks as its successors.
521 BB->addSuccessor(copy0MBB);
522 BB->addSuccessor(sinkMBB);
524 BuildMI(BB, DL, TII->get(Opc)).addReg(MI->getOperand(3).getReg())
529 // # fallthrough to sinkMBB
532 // Update machine-CFG edges
533 BB->addSuccessor(sinkMBB);
536 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
540 BuildMI(*BB, BB->begin(), DL,
541 TII->get(Mips::PHI), MI->getOperand(0).getReg())
542 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
543 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
545 MI->eraseFromParent(); // The pseudo instruction is gone now.
549 MachineBasicBlock *Mips16TargetLowering::emitSelT16
550 (unsigned Opc1, unsigned Opc2,
551 MachineInstr *MI, MachineBasicBlock *BB) const {
552 if (DontExpandCondPseudos16)
554 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
555 DebugLoc DL = MI->getDebugLoc();
556 // To "insert" a SELECT_CC instruction, we actually have to insert the
557 // diamond control-flow pattern. The incoming instruction knows the
558 // destination vreg to set, the condition code register to branch on, the
559 // true/false values to select between, and a branch opcode to use.
560 const BasicBlock *LLVM_BB = BB->getBasicBlock();
561 MachineFunction::iterator It = BB;
568 // bNE r1, r0, copy1MBB
569 // fallthrough --> copy0MBB
570 MachineBasicBlock *thisMBB = BB;
571 MachineFunction *F = BB->getParent();
572 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
573 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
574 F->insert(It, copy0MBB);
575 F->insert(It, sinkMBB);
577 // Transfer the remainder of BB and its successor edges to sinkMBB.
578 sinkMBB->splice(sinkMBB->begin(), BB,
579 llvm::next(MachineBasicBlock::iterator(MI)),
581 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
583 // Next, add the true and fallthrough blocks as its successors.
584 BB->addSuccessor(copy0MBB);
585 BB->addSuccessor(sinkMBB);
587 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg())
588 .addReg(MI->getOperand(4).getReg());
589 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
593 // # fallthrough to sinkMBB
596 // Update machine-CFG edges
597 BB->addSuccessor(sinkMBB);
600 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
604 BuildMI(*BB, BB->begin(), DL,
605 TII->get(Mips::PHI), MI->getOperand(0).getReg())
606 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
607 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
609 MI->eraseFromParent(); // The pseudo instruction is gone now.
614 MachineBasicBlock *Mips16TargetLowering::emitSeliT16
615 (unsigned Opc1, unsigned Opc2,
616 MachineInstr *MI, MachineBasicBlock *BB) const {
617 if (DontExpandCondPseudos16)
619 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
620 DebugLoc DL = MI->getDebugLoc();
621 // To "insert" a SELECT_CC instruction, we actually have to insert the
622 // diamond control-flow pattern. The incoming instruction knows the
623 // destination vreg to set, the condition code register to branch on, the
624 // true/false values to select between, and a branch opcode to use.
625 const BasicBlock *LLVM_BB = BB->getBasicBlock();
626 MachineFunction::iterator It = BB;
633 // bNE r1, r0, copy1MBB
634 // fallthrough --> copy0MBB
635 MachineBasicBlock *thisMBB = BB;
636 MachineFunction *F = BB->getParent();
637 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
638 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
639 F->insert(It, copy0MBB);
640 F->insert(It, sinkMBB);
642 // Transfer the remainder of BB and its successor edges to sinkMBB.
643 sinkMBB->splice(sinkMBB->begin(), BB,
644 llvm::next(MachineBasicBlock::iterator(MI)),
646 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
648 // Next, add the true and fallthrough blocks as its successors.
649 BB->addSuccessor(copy0MBB);
650 BB->addSuccessor(sinkMBB);
652 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg())
653 .addImm(MI->getOperand(4).getImm());
654 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
658 // # fallthrough to sinkMBB
661 // Update machine-CFG edges
662 BB->addSuccessor(sinkMBB);
665 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
669 BuildMI(*BB, BB->begin(), DL,
670 TII->get(Mips::PHI), MI->getOperand(0).getReg())
671 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
672 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
674 MI->eraseFromParent(); // The pseudo instruction is gone now.
680 *Mips16TargetLowering::emitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc,
682 MachineBasicBlock *BB) const {
683 if (DontExpandCondPseudos16)
685 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
686 unsigned regX = MI->getOperand(0).getReg();
687 unsigned regY = MI->getOperand(1).getReg();
688 MachineBasicBlock *target = MI->getOperand(2).getMBB();
689 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX)
691 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target);
692 MI->eraseFromParent(); // The pseudo instruction is gone now.
696 MachineBasicBlock *Mips16TargetLowering::emitFEXT_T8I8I16_ins(
697 unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc, bool ImmSigned,
698 MachineInstr *MI, MachineBasicBlock *BB) const {
699 if (DontExpandCondPseudos16)
701 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
702 unsigned regX = MI->getOperand(0).getReg();
703 int64_t imm = MI->getOperand(1).getImm();
704 MachineBasicBlock *target = MI->getOperand(2).getMBB();
708 else if ((!ImmSigned && isUInt<16>(imm)) ||
709 (ImmSigned && isInt<16>(imm)))
712 llvm_unreachable("immediate field not usable");
713 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX)
715 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target);
716 MI->eraseFromParent(); // The pseudo instruction is gone now.
720 static unsigned Mips16WhichOp8uOr16simm
721 (unsigned shortOp, unsigned longOp, int64_t Imm) {
724 else if (isInt<16>(Imm))
727 llvm_unreachable("immediate field not usable");
730 MachineBasicBlock *Mips16TargetLowering::emitFEXT_CCRX16_ins(
732 MachineInstr *MI, MachineBasicBlock *BB) const {
733 if (DontExpandCondPseudos16)
735 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
736 unsigned CC = MI->getOperand(0).getReg();
737 unsigned regX = MI->getOperand(1).getReg();
738 unsigned regY = MI->getOperand(2).getReg();
739 BuildMI(*BB, MI, MI->getDebugLoc(),
740 TII->get(SltOpc)).addReg(regX).addReg(regY);
741 BuildMI(*BB, MI, MI->getDebugLoc(),
742 TII->get(Mips::MoveR3216), CC).addReg(Mips::T8);
743 MI->eraseFromParent(); // The pseudo instruction is gone now.
747 MachineBasicBlock *Mips16TargetLowering::emitFEXT_CCRXI16_ins(
748 unsigned SltiOpc, unsigned SltiXOpc,
749 MachineInstr *MI, MachineBasicBlock *BB )const {
750 if (DontExpandCondPseudos16)
752 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
753 unsigned CC = MI->getOperand(0).getReg();
754 unsigned regX = MI->getOperand(1).getReg();
755 int64_t Imm = MI->getOperand(2).getImm();
756 unsigned SltOpc = Mips16WhichOp8uOr16simm(SltiOpc, SltiXOpc, Imm);
757 BuildMI(*BB, MI, MI->getDebugLoc(),
758 TII->get(SltOpc)).addReg(regX).addImm(Imm);
759 BuildMI(*BB, MI, MI->getDebugLoc(),
760 TII->get(Mips::MoveR3216), CC).addReg(Mips::T8);
761 MI->eraseFromParent(); // The pseudo instruction is gone now.