1 //===-- Mips16ISelLowering.h - Mips16 DAG Lowering Interface ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Subclass of MipsTargetLowering specialized for mips16.
12 //===----------------------------------------------------------------------===//
13 #define DEBUG_TYPE "mips-lower"
14 #include "Mips16ISelLowering.h"
15 #include "MipsRegisterInfo.h"
16 #include "MCTargetDesc/MipsBaseInfo.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/Support/CommandLine.h"
19 #include "llvm/Target/TargetInstrInfo.h"
25 Mips16HardFloat("mips16-hard-float", cl::NotHidden,
26 cl::desc("MIPS: mips16 hard float enable."),
29 static cl::opt<bool> DontExpandCondPseudos16(
30 "mips16-dont-expand-cond-pseudo",
32 cl::desc("Dont expand conditional move related "
33 "pseudos for Mips 16"),
37 std::set<const char*, MipsTargetLowering::LTStr> NoHelperNeeded;
40 Mips16TargetLowering::Mips16TargetLowering(MipsTargetMachine &TM)
41 : MipsTargetLowering(TM) {
42 // Set up the register classes
43 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
46 setMips16HardFloatLibCalls();
48 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
49 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
50 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
51 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
52 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
53 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
54 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
55 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
56 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
57 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
58 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
59 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
60 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
61 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
63 computeRegisterProperties();
66 const MipsTargetLowering *
67 llvm::createMips16TargetLowering(MipsTargetMachine &TM) {
68 return new Mips16TargetLowering(TM);
72 Mips16TargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
77 Mips16TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
78 MachineBasicBlock *BB) const {
79 switch (MI->getOpcode()) {
81 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
83 return emitSel16(Mips::BeqzRxImm16, MI, BB);
85 return emitSel16(Mips::BnezRxImm16, MI, BB);
86 case Mips::SelTBteqZCmpi:
87 return emitSeliT16(Mips::BteqzX16, Mips::CmpiRxImmX16, MI, BB);
88 case Mips::SelTBteqZSlti:
89 return emitSeliT16(Mips::BteqzX16, Mips::SltiRxImmX16, MI, BB);
90 case Mips::SelTBteqZSltiu:
91 return emitSeliT16(Mips::BteqzX16, Mips::SltiuRxImmX16, MI, BB);
92 case Mips::SelTBtneZCmpi:
93 return emitSeliT16(Mips::BtnezX16, Mips::CmpiRxImmX16, MI, BB);
94 case Mips::SelTBtneZSlti:
95 return emitSeliT16(Mips::BtnezX16, Mips::SltiRxImmX16, MI, BB);
96 case Mips::SelTBtneZSltiu:
97 return emitSeliT16(Mips::BtnezX16, Mips::SltiuRxImmX16, MI, BB);
98 case Mips::SelTBteqZCmp:
99 return emitSelT16(Mips::BteqzX16, Mips::CmpRxRy16, MI, BB);
100 case Mips::SelTBteqZSlt:
101 return emitSelT16(Mips::BteqzX16, Mips::SltRxRy16, MI, BB);
102 case Mips::SelTBteqZSltu:
103 return emitSelT16(Mips::BteqzX16, Mips::SltuRxRy16, MI, BB);
104 case Mips::SelTBtneZCmp:
105 return emitSelT16(Mips::BtnezX16, Mips::CmpRxRy16, MI, BB);
106 case Mips::SelTBtneZSlt:
107 return emitSelT16(Mips::BtnezX16, Mips::SltRxRy16, MI, BB);
108 case Mips::SelTBtneZSltu:
109 return emitSelT16(Mips::BtnezX16, Mips::SltuRxRy16, MI, BB);
110 case Mips::BteqzT8CmpX16:
111 return emitFEXT_T8I816_ins(Mips::BteqzX16, Mips::CmpRxRy16, MI, BB);
112 case Mips::BteqzT8SltX16:
113 return emitFEXT_T8I816_ins(Mips::BteqzX16, Mips::SltRxRy16, MI, BB);
114 case Mips::BteqzT8SltuX16:
115 // TBD: figure out a way to get this or remove the instruction
117 return emitFEXT_T8I816_ins(Mips::BteqzX16, Mips::SltuRxRy16, MI, BB);
118 case Mips::BtnezT8CmpX16:
119 return emitFEXT_T8I816_ins(Mips::BtnezX16, Mips::CmpRxRy16, MI, BB);
120 case Mips::BtnezT8SltX16:
121 return emitFEXT_T8I816_ins(Mips::BtnezX16, Mips::SltRxRy16, MI, BB);
122 case Mips::BtnezT8SltuX16:
123 // TBD: figure out a way to get this or remove the instruction
125 return emitFEXT_T8I816_ins(Mips::BtnezX16, Mips::SltuRxRy16, MI, BB);
126 case Mips::BteqzT8CmpiX16: return emitFEXT_T8I8I16_ins(
127 Mips::BteqzX16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, MI, BB);
128 case Mips::BteqzT8SltiX16: return emitFEXT_T8I8I16_ins(
129 Mips::BteqzX16, Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB);
130 case Mips::BteqzT8SltiuX16: return emitFEXT_T8I8I16_ins(
131 Mips::BteqzX16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB);
132 case Mips::BtnezT8CmpiX16: return emitFEXT_T8I8I16_ins(
133 Mips::BtnezX16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, MI, BB);
134 case Mips::BtnezT8SltiX16: return emitFEXT_T8I8I16_ins(
135 Mips::BtnezX16, Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB);
136 case Mips::BtnezT8SltiuX16: return emitFEXT_T8I8I16_ins(
137 Mips::BtnezX16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB);
139 case Mips::SltCCRxRy16:
140 return emitFEXT_CCRX16_ins(Mips::SltRxRy16, MI, BB);
142 case Mips::SltiCCRxImmX16:
143 return emitFEXT_CCRXI16_ins
144 (Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB);
145 case Mips::SltiuCCRxImmX16:
146 return emitFEXT_CCRXI16_ins
147 (Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB);
148 case Mips::SltuCCRxRy16:
149 return emitFEXT_CCRX16_ins
150 (Mips::SltuRxRy16, MI, BB);
154 bool Mips16TargetLowering::
155 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
156 unsigned NextStackOffset,
157 const MipsFunctionInfo& FI) const {
158 // No tail call optimization for mips16.
162 void Mips16TargetLowering::setMips16LibcallName
163 (RTLIB::Libcall L, const char *Name) {
164 setLibcallName(L, Name);
165 NoHelperNeeded.insert(Name);
168 void Mips16TargetLowering::setMips16HardFloatLibCalls() {
169 setMips16LibcallName(RTLIB::ADD_F32, "__mips16_addsf3");
170 setMips16LibcallName(RTLIB::ADD_F64, "__mips16_adddf3");
171 setMips16LibcallName(RTLIB::SUB_F32, "__mips16_subsf3");
172 setMips16LibcallName(RTLIB::SUB_F64, "__mips16_subdf3");
173 setMips16LibcallName(RTLIB::MUL_F32, "__mips16_mulsf3");
174 setMips16LibcallName(RTLIB::MUL_F64, "__mips16_muldf3");
175 setMips16LibcallName(RTLIB::DIV_F32, "__mips16_divsf3");
176 setMips16LibcallName(RTLIB::DIV_F64, "__mips16_divdf3");
177 setMips16LibcallName(RTLIB::FPEXT_F32_F64, "__mips16_extendsfdf2");
178 setMips16LibcallName(RTLIB::FPROUND_F64_F32, "__mips16_truncdfsf2");
179 setMips16LibcallName(RTLIB::FPTOSINT_F32_I32, "__mips16_fix_truncsfsi");
180 setMips16LibcallName(RTLIB::FPTOSINT_F64_I32, "__mips16_fix_truncdfsi");
181 setMips16LibcallName(RTLIB::SINTTOFP_I32_F32, "__mips16_floatsisf");
182 setMips16LibcallName(RTLIB::SINTTOFP_I32_F64, "__mips16_floatsidf");
183 setMips16LibcallName(RTLIB::UINTTOFP_I32_F32, "__mips16_floatunsisf");
184 setMips16LibcallName(RTLIB::UINTTOFP_I32_F64, "__mips16_floatunsidf");
185 setMips16LibcallName(RTLIB::OEQ_F32, "__mips16_eqsf2");
186 setMips16LibcallName(RTLIB::OEQ_F64, "__mips16_eqdf2");
187 setMips16LibcallName(RTLIB::UNE_F32, "__mips16_nesf2");
188 setMips16LibcallName(RTLIB::UNE_F64, "__mips16_nedf2");
189 setMips16LibcallName(RTLIB::OGE_F32, "__mips16_gesf2");
190 setMips16LibcallName(RTLIB::OGE_F64, "__mips16_gedf2");
191 setMips16LibcallName(RTLIB::OLT_F32, "__mips16_ltsf2");
192 setMips16LibcallName(RTLIB::OLT_F64, "__mips16_ltdf2");
193 setMips16LibcallName(RTLIB::OLE_F32, "__mips16_lesf2");
194 setMips16LibcallName(RTLIB::OLE_F64, "__mips16_ledf2");
195 setMips16LibcallName(RTLIB::OGT_F32, "__mips16_gtsf2");
196 setMips16LibcallName(RTLIB::OGT_F64, "__mips16_gtdf2");
197 setMips16LibcallName(RTLIB::UO_F32, "__mips16_unordsf2");
198 setMips16LibcallName(RTLIB::UO_F64, "__mips16_unorddf2");
199 setMips16LibcallName(RTLIB::O_F32, "__mips16_unordsf2");
200 setMips16LibcallName(RTLIB::O_F64, "__mips16_unorddf2");
205 // The Mips16 hard float is a crazy quilt inherited from gcc. I have a much
206 // cleaner way to do all of this but it will have to wait until the traditional
207 // gcc mechanism is completed.
209 // For Pic, in order for Mips16 code to call Mips32 code which according the abi
210 // have either arguments or returned values placed in floating point registers,
211 // we use a set of helper functions. (This includes functions which return type
212 // complex which on Mips are returned in a pair of floating point registers).
214 // This is an encoding that we inherited from gcc.
215 // In Mips traditional O32, N32 ABI, floating point numbers are passed in
216 // floating point argument registers 1,2 only when the first and optionally
217 // the second arguments are float (sf) or double (df).
218 // For Mips16 we are only concerned with the situations where floating point
219 // arguments are being passed in floating point registers by the ABI, because
220 // Mips16 mode code cannot execute floating point instructions to load those
221 // values and hence helper functions are needed.
222 // The possibilities are (), (sf), (sf, sf), (sf, df), (df), (df, sf), (df, df)
223 // the helper function suffixs for these are:
224 // 0, 1, 5, 9, 2, 6, 10
225 // this suffix can then be calculated as follows:
226 // for a given argument Arg:
227 // Arg1x, Arg2x = 1 : Arg is sf
229 // 0: Arg is neither sf or df
230 // So this stub is the string for number Arg1x + Arg2x*4.
231 // However not all numbers between 0 and 10 are possible, we check anyway and
232 // assert if the impossible exists.
235 unsigned int Mips16TargetLowering::getMips16HelperFunctionStubNumber
236 (ArgListTy &Args) const {
237 unsigned int resultNum = 0;
238 if (Args.size() >= 1) {
239 Type *t = Args[0].Ty;
240 if (t->isFloatTy()) {
243 else if (t->isDoubleTy()) {
248 if (Args.size() >=2) {
249 Type *t = Args[1].Ty;
250 if (t->isFloatTy()) {
253 else if (t->isDoubleTy()) {
262 // prefixs are attached to stub numbers depending on the return type .
263 // return type: float sf_
265 // single complex sc_
266 // double complext dc_
270 // The full name of a helper function is__mips16_call_stub +
271 // return type dependent prefix + stub number
274 // This is something that probably should be in a different source file and
275 // perhaps done differently but my main purpose is to not waste runtime
276 // on something that we can enumerate in the source. Another possibility is
277 // to have a python script to generate these mapping tables. This will do
278 // for now. There are a whole series of helper function mapping arrays, one
279 // for each return type class as outlined above. There there are 11 possible
280 // entries. Ones with 0 are ones which should never be selected
282 // All the arrays are similar except for ones which return neither
283 // sf, df, sc, dc, in which only care about ones which have sf or df as a
286 #define P_ "__mips16_call_stub_"
287 #define MAX_STUB_NUMBER 10
288 #define T1 P "1", P "2", 0, 0, P "5", P "6", 0, 0, P "9", P "10"
291 static char const * vMips16Helper[MAX_STUB_NUMBER+1] =
295 static char const * sfMips16Helper[MAX_STUB_NUMBER+1] =
299 static char const * dfMips16Helper[MAX_STUB_NUMBER+1] =
303 static char const * scMips16Helper[MAX_STUB_NUMBER+1] =
307 static char const * dcMips16Helper[MAX_STUB_NUMBER+1] =
313 const char* Mips16TargetLowering::
314 getMips16HelperFunction
315 (Type* RetTy, ArgListTy &Args, bool &needHelper) const {
316 const unsigned int stubNum = getMips16HelperFunctionStubNumber(Args);
318 const unsigned int maxStubNum = 10;
319 assert(stubNum <= maxStubNum);
320 const bool validStubNum[maxStubNum+1] =
321 {true, true, true, false, false, true, true, false, false, true, true};
322 assert(validStubNum[stubNum]);
325 if (RetTy->isFloatTy()) {
326 result = sfMips16Helper[stubNum];
328 else if (RetTy ->isDoubleTy()) {
329 result = dfMips16Helper[stubNum];
331 else if (RetTy->isStructTy()) {
332 // check if it's complex
333 if (RetTy->getNumContainedTypes() == 2) {
334 if ((RetTy->getContainedType(0)->isFloatTy()) &&
335 (RetTy->getContainedType(1)->isFloatTy())) {
336 result = scMips16Helper[stubNum];
338 else if ((RetTy->getContainedType(0)->isDoubleTy()) &&
339 (RetTy->getContainedType(1)->isDoubleTy())) {
340 result = dcMips16Helper[stubNum];
343 llvm_unreachable("Uncovered condition");
347 llvm_unreachable("Uncovered condition");
355 result = vMips16Helper[stubNum];
361 void Mips16TargetLowering::
362 getOpndList(SmallVectorImpl<SDValue> &Ops,
363 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
364 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
365 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
366 SelectionDAG &DAG = CLI.DAG;
367 const char* Mips16HelperFunction = 0;
368 bool NeedMips16Helper = false;
370 if (getTargetMachine().Options.UseSoftFloat && Mips16HardFloat) {
372 // currently we don't have symbols tagged with the mips16 or mips32
373 // qualifier so we will assume that we don't know what kind it is.
374 // and generate the helper
376 bool LookupHelper = true;
377 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(CLI.Callee)) {
378 if (NoHelperNeeded.find(S->getSymbol()) != NoHelperNeeded.end()) {
379 LookupHelper = false;
382 if (LookupHelper) Mips16HelperFunction =
383 getMips16HelperFunction(CLI.RetTy, CLI.Args, NeedMips16Helper);
387 SDValue JumpTarget = Callee;
389 // T9 should contain the address of the callee function if
390 // -reloction-model=pic or it is an indirect call.
391 if (IsPICCall || !GlobalOrExternal) {
392 unsigned V0Reg = Mips::V0;
393 if (NeedMips16Helper) {
394 RegsToPass.push_front(std::make_pair(V0Reg, Callee));
395 JumpTarget = DAG.getExternalSymbol(Mips16HelperFunction, getPointerTy());
396 JumpTarget = getAddrGlobal(JumpTarget, DAG, MipsII::MO_GOT);
398 RegsToPass.push_front(std::make_pair((unsigned)Mips::T9, Callee));
401 Ops.push_back(JumpTarget);
403 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
404 InternalLinkage, CLI, Callee, Chain);
407 MachineBasicBlock *Mips16TargetLowering::
408 emitSel16(unsigned Opc, MachineInstr *MI, MachineBasicBlock *BB) const {
409 if (DontExpandCondPseudos16)
411 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
412 DebugLoc DL = MI->getDebugLoc();
413 // To "insert" a SELECT_CC instruction, we actually have to insert the
414 // diamond control-flow pattern. The incoming instruction knows the
415 // destination vreg to set, the condition code register to branch on, the
416 // true/false values to select between, and a branch opcode to use.
417 const BasicBlock *LLVM_BB = BB->getBasicBlock();
418 MachineFunction::iterator It = BB;
425 // bNE r1, r0, copy1MBB
426 // fallthrough --> copy0MBB
427 MachineBasicBlock *thisMBB = BB;
428 MachineFunction *F = BB->getParent();
429 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
430 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
431 F->insert(It, copy0MBB);
432 F->insert(It, sinkMBB);
434 // Transfer the remainder of BB and its successor edges to sinkMBB.
435 sinkMBB->splice(sinkMBB->begin(), BB,
436 llvm::next(MachineBasicBlock::iterator(MI)),
438 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
440 // Next, add the true and fallthrough blocks as its successors.
441 BB->addSuccessor(copy0MBB);
442 BB->addSuccessor(sinkMBB);
444 BuildMI(BB, DL, TII->get(Opc)).addReg(MI->getOperand(3).getReg())
449 // # fallthrough to sinkMBB
452 // Update machine-CFG edges
453 BB->addSuccessor(sinkMBB);
456 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
460 BuildMI(*BB, BB->begin(), DL,
461 TII->get(Mips::PHI), MI->getOperand(0).getReg())
462 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
463 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
465 MI->eraseFromParent(); // The pseudo instruction is gone now.
469 MachineBasicBlock *Mips16TargetLowering::emitSelT16
470 (unsigned Opc1, unsigned Opc2,
471 MachineInstr *MI, MachineBasicBlock *BB) const {
472 if (DontExpandCondPseudos16)
474 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
475 DebugLoc DL = MI->getDebugLoc();
476 // To "insert" a SELECT_CC instruction, we actually have to insert the
477 // diamond control-flow pattern. The incoming instruction knows the
478 // destination vreg to set, the condition code register to branch on, the
479 // true/false values to select between, and a branch opcode to use.
480 const BasicBlock *LLVM_BB = BB->getBasicBlock();
481 MachineFunction::iterator It = BB;
488 // bNE r1, r0, copy1MBB
489 // fallthrough --> copy0MBB
490 MachineBasicBlock *thisMBB = BB;
491 MachineFunction *F = BB->getParent();
492 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
493 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
494 F->insert(It, copy0MBB);
495 F->insert(It, sinkMBB);
497 // Transfer the remainder of BB and its successor edges to sinkMBB.
498 sinkMBB->splice(sinkMBB->begin(), BB,
499 llvm::next(MachineBasicBlock::iterator(MI)),
501 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
503 // Next, add the true and fallthrough blocks as its successors.
504 BB->addSuccessor(copy0MBB);
505 BB->addSuccessor(sinkMBB);
507 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg())
508 .addReg(MI->getOperand(4).getReg());
509 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
513 // # fallthrough to sinkMBB
516 // Update machine-CFG edges
517 BB->addSuccessor(sinkMBB);
520 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
524 BuildMI(*BB, BB->begin(), DL,
525 TII->get(Mips::PHI), MI->getOperand(0).getReg())
526 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
527 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
529 MI->eraseFromParent(); // The pseudo instruction is gone now.
534 MachineBasicBlock *Mips16TargetLowering::emitSeliT16
535 (unsigned Opc1, unsigned Opc2,
536 MachineInstr *MI, MachineBasicBlock *BB) const {
537 if (DontExpandCondPseudos16)
539 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
540 DebugLoc DL = MI->getDebugLoc();
541 // To "insert" a SELECT_CC instruction, we actually have to insert the
542 // diamond control-flow pattern. The incoming instruction knows the
543 // destination vreg to set, the condition code register to branch on, the
544 // true/false values to select between, and a branch opcode to use.
545 const BasicBlock *LLVM_BB = BB->getBasicBlock();
546 MachineFunction::iterator It = BB;
553 // bNE r1, r0, copy1MBB
554 // fallthrough --> copy0MBB
555 MachineBasicBlock *thisMBB = BB;
556 MachineFunction *F = BB->getParent();
557 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
558 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
559 F->insert(It, copy0MBB);
560 F->insert(It, sinkMBB);
562 // Transfer the remainder of BB and its successor edges to sinkMBB.
563 sinkMBB->splice(sinkMBB->begin(), BB,
564 llvm::next(MachineBasicBlock::iterator(MI)),
566 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
568 // Next, add the true and fallthrough blocks as its successors.
569 BB->addSuccessor(copy0MBB);
570 BB->addSuccessor(sinkMBB);
572 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg())
573 .addImm(MI->getOperand(4).getImm());
574 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
578 // # fallthrough to sinkMBB
581 // Update machine-CFG edges
582 BB->addSuccessor(sinkMBB);
585 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
589 BuildMI(*BB, BB->begin(), DL,
590 TII->get(Mips::PHI), MI->getOperand(0).getReg())
591 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
592 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
594 MI->eraseFromParent(); // The pseudo instruction is gone now.
600 *Mips16TargetLowering::emitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc,
602 MachineBasicBlock *BB) const {
603 if (DontExpandCondPseudos16)
605 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
606 unsigned regX = MI->getOperand(0).getReg();
607 unsigned regY = MI->getOperand(1).getReg();
608 MachineBasicBlock *target = MI->getOperand(2).getMBB();
609 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX).addReg(regY);
610 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target);
611 MI->eraseFromParent(); // The pseudo instruction is gone now.
615 MachineBasicBlock *Mips16TargetLowering::emitFEXT_T8I8I16_ins(
616 unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc,
617 MachineInstr *MI, MachineBasicBlock *BB) const {
618 if (DontExpandCondPseudos16)
620 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
621 unsigned regX = MI->getOperand(0).getReg();
622 int64_t imm = MI->getOperand(1).getImm();
623 MachineBasicBlock *target = MI->getOperand(2).getMBB();
627 else if (isUInt<16>(imm))
630 llvm_unreachable("immediate field not usable");
631 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX).addImm(imm);
632 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target);
633 MI->eraseFromParent(); // The pseudo instruction is gone now.
637 static unsigned Mips16WhichOp8uOr16simm
638 (unsigned shortOp, unsigned longOp, int64_t Imm) {
641 else if (isInt<16>(Imm))
644 llvm_unreachable("immediate field not usable");
647 MachineBasicBlock *Mips16TargetLowering::emitFEXT_CCRX16_ins(
649 MachineInstr *MI, MachineBasicBlock *BB) const {
650 if (DontExpandCondPseudos16)
652 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
653 unsigned CC = MI->getOperand(0).getReg();
654 unsigned regX = MI->getOperand(1).getReg();
655 unsigned regY = MI->getOperand(2).getReg();
656 BuildMI(*BB, MI, MI->getDebugLoc(),
657 TII->get(SltOpc)).addReg(regX).addReg(regY);
658 BuildMI(*BB, MI, MI->getDebugLoc(),
659 TII->get(Mips::MoveR3216), CC).addReg(Mips::T8);
660 MI->eraseFromParent(); // The pseudo instruction is gone now.
664 MachineBasicBlock *Mips16TargetLowering::emitFEXT_CCRXI16_ins(
665 unsigned SltiOpc, unsigned SltiXOpc,
666 MachineInstr *MI, MachineBasicBlock *BB )const {
667 if (DontExpandCondPseudos16)
669 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
670 unsigned CC = MI->getOperand(0).getReg();
671 unsigned regX = MI->getOperand(1).getReg();
672 int64_t Imm = MI->getOperand(2).getImm();
673 unsigned SltOpc = Mips16WhichOp8uOr16simm(SltiOpc, SltiXOpc, Imm);
674 BuildMI(*BB, MI, MI->getDebugLoc(),
675 TII->get(SltOpc)).addReg(regX).addImm(Imm);
676 BuildMI(*BB, MI, MI->getDebugLoc(),
677 TII->get(Mips::MoveR3216), CC).addReg(Mips::T8);
678 MI->eraseFromParent(); // The pseudo instruction is gone now.