1 def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
3 def simm4 : Operand<i32> {
4 let DecoderMethod = "DecodeSimm4";
6 def simm7 : Operand<i32>;
7 def li_simm7 : Operand<i32> {
8 let DecoderMethod = "DecodeLiSimm7";
11 def simm12 : Operand<i32> {
12 let DecoderMethod = "DecodeSimm12";
15 def uimm5_lsl2 : Operand<OtherVT> {
16 let EncoderMethod = "getUImm5Lsl2Encoding";
17 let DecoderMethod = "DecodeUImm5lsl2";
20 def uimm6_lsl2 : Operand<i32> {
21 let EncoderMethod = "getUImm6Lsl2Encoding";
22 let DecoderMethod = "DecodeUImm6Lsl2";
25 def simm9_addiusp : Operand<i32> {
26 let EncoderMethod = "getSImm9AddiuspValue";
27 let DecoderMethod = "DecodeSimm9SP";
30 def uimm3_shift : Operand<i32> {
31 let EncoderMethod = "getUImm3Mod8Encoding";
34 def simm3_lsa2 : Operand<i32> {
35 let EncoderMethod = "getSImm3Lsa2Value";
36 let DecoderMethod = "DecodeAddiur2Simm7";
39 def uimm4_andi : Operand<i32> {
40 let EncoderMethod = "getUImm4AndValue";
41 let DecoderMethod = "DecodeANDI16Imm";
44 def immSExtAddiur2 : ImmLeaf<i32, [{return Imm == 1 || Imm == -1 ||
46 Imm < 28 && Imm > 0);}]>;
48 def immSExtAddius5 : ImmLeaf<i32, [{return Imm >= -8 && Imm <= 7;}]>;
50 def immZExtAndi16 : ImmLeaf<i32,
51 [{return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
52 Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
53 Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );}]>;
55 def immZExt2Shift : ImmLeaf<i32, [{return Imm >= 1 && Imm <= 8;}]>;
57 def immLi16 : ImmLeaf<i32, [{return Imm >= -1 && Imm <= 126;}]>;
59 def MicroMipsMemGPRMM16AsmOperand : AsmOperandClass {
60 let Name = "MicroMipsMem";
61 let RenderMethod = "addMicroMipsMemOperands";
62 let ParserMethod = "parseMemOperand";
63 let PredicateMethod = "isMemWithGRPMM16Base";
66 class mem_mm_4_generic : Operand<i32> {
67 let PrintMethod = "printMemOperand";
68 let MIOperandInfo = (ops ptr_rc, simm4);
69 let OperandType = "OPERAND_MEMORY";
70 let ParserMatchClass = MicroMipsMemGPRMM16AsmOperand;
73 def mem_mm_4 : mem_mm_4_generic {
74 let EncoderMethod = "getMemEncodingMMImm4";
77 def mem_mm_4_lsl1 : mem_mm_4_generic {
78 let EncoderMethod = "getMemEncodingMMImm4Lsl1";
81 def mem_mm_4_lsl2 : mem_mm_4_generic {
82 let EncoderMethod = "getMemEncodingMMImm4Lsl2";
85 def MicroMipsMemSPAsmOperand : AsmOperandClass {
86 let Name = "MicroMipsMemSP";
87 let RenderMethod = "addMemOperands";
88 let ParserMethod = "parseMemOperand";
89 let PredicateMethod = "isMemWithUimmWordAlignedOffsetSP<7>";
92 def mem_mm_sp_imm5_lsl2 : Operand<i32> {
93 let PrintMethod = "printMemOperand";
94 let MIOperandInfo = (ops GPR32:$base, simm5:$offset);
95 let OperandType = "OPERAND_MEMORY";
96 let ParserMatchClass = MicroMipsMemSPAsmOperand;
97 let EncoderMethod = "getMemEncodingMMSPImm5Lsl2";
100 def mem_mm_gp_imm7_lsl2 : Operand<i32> {
101 let PrintMethod = "printMemOperand";
102 let MIOperandInfo = (ops GPRMM16:$base, simm7:$offset);
103 let OperandType = "OPERAND_MEMORY";
104 let EncoderMethod = "getMemEncodingMMGPImm7Lsl2";
107 def mem_mm_12 : Operand<i32> {
108 let PrintMethod = "printMemOperand";
109 let MIOperandInfo = (ops GPR32, simm12);
110 let EncoderMethod = "getMemEncodingMMImm12";
111 let ParserMatchClass = MipsMemAsmOperand;
112 let OperandType = "OPERAND_MEMORY";
115 def MipsMemUimm4AsmOperand : AsmOperandClass {
116 let Name = "MemOffsetUimm4";
117 let SuperClasses = [MipsMemAsmOperand];
118 let RenderMethod = "addMemOperands";
119 let ParserMethod = "parseMemOperand";
120 let PredicateMethod = "isMemWithUimmOffsetSP<6>";
123 def mem_mm_4sp : Operand<i32> {
124 let PrintMethod = "printMemOperand";
125 let MIOperandInfo = (ops GPR32, uimm8);
126 let EncoderMethod = "getMemEncodingMMImm4sp";
127 let ParserMatchClass = MipsMemUimm4AsmOperand;
128 let OperandType = "OPERAND_MEMORY";
131 def jmptarget_mm : Operand<OtherVT> {
132 let EncoderMethod = "getJumpTargetOpValueMM";
135 def calltarget_mm : Operand<iPTR> {
136 let EncoderMethod = "getJumpTargetOpValueMM";
139 def brtarget7_mm : Operand<OtherVT> {
140 let EncoderMethod = "getBranchTarget7OpValueMM";
141 let OperandType = "OPERAND_PCREL";
142 let DecoderMethod = "DecodeBranchTarget7MM";
143 let ParserMatchClass = MipsJumpTargetAsmOperand;
146 def brtarget10_mm : Operand<OtherVT> {
147 let EncoderMethod = "getBranchTargetOpValueMMPC10";
148 let OperandType = "OPERAND_PCREL";
149 let DecoderMethod = "DecodeBranchTarget10MM";
150 let ParserMatchClass = MipsJumpTargetAsmOperand;
153 def brtarget_mm : Operand<OtherVT> {
154 let EncoderMethod = "getBranchTargetOpValueMM";
155 let OperandType = "OPERAND_PCREL";
156 let DecoderMethod = "DecodeBranchTargetMM";
157 let ParserMatchClass = MipsJumpTargetAsmOperand;
160 def simm23_lsl2 : Operand<i32> {
161 let EncoderMethod = "getSimm23Lsl2Encoding";
162 let DecoderMethod = "DecodeSimm23Lsl2";
165 class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op,
166 RegisterOperand RO> :
167 InstSE<(outs), (ins RO:$rs, opnd:$offset),
168 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI> {
170 let isTerminator = 1;
171 let hasDelaySlot = 0;
175 let canFoldAsLoad = 1 in
176 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
178 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
179 !strconcat(opstr, "\t$rt, $addr"),
180 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
182 let DecoderMethod = "DecodeMemMMImm12";
183 string Constraints = "$src = $rt";
186 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
188 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
189 !strconcat(opstr, "\t$rt, $addr"),
190 [(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> {
191 let DecoderMethod = "DecodeMemMMImm12";
194 /// A register pair used by load/store pair instructions.
195 def RegPairAsmOperand : AsmOperandClass {
196 let Name = "RegPair";
197 let ParserMethod = "parseRegisterPair";
200 def regpair : Operand<i32> {
201 let EncoderMethod = "getRegisterPairOpValue";
202 let ParserMatchClass = RegPairAsmOperand;
203 let PrintMethod = "printRegisterPair";
204 let DecoderMethod = "DecodeRegPairOperand";
205 let MIOperandInfo = (ops GPR32Opnd, GPR32Opnd);
208 class StorePairMM<string opstr, InstrItinClass Itin = NoItinerary,
209 ComplexPattern Addr = addr> :
210 InstSE<(outs), (ins regpair:$rt, mem_mm_12:$addr),
211 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
212 let DecoderMethod = "DecodeMemMMImm12";
216 class LoadPairMM<string opstr, InstrItinClass Itin = NoItinerary,
217 ComplexPattern Addr = addr> :
218 InstSE<(outs regpair:$rt), (ins mem_mm_12:$addr),
219 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
220 let DecoderMethod = "DecodeMemMMImm12";
224 class LLBaseMM<string opstr, RegisterOperand RO> :
225 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
226 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
227 let DecoderMethod = "DecodeMemMMImm12";
231 class SCBaseMM<string opstr, RegisterOperand RO> :
232 InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
233 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
234 let DecoderMethod = "DecodeMemMMImm12";
236 let Constraints = "$rt = $dst";
239 class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
240 InstrItinClass Itin = NoItinerary> :
241 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
242 !strconcat(opstr, "\t$rt, $addr"),
243 [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI> {
244 let DecoderMethod = "DecodeMemMMImm12";
245 let canFoldAsLoad = 1;
249 class ArithRMM16<string opstr, RegisterOperand RO, bit isComm = 0,
250 InstrItinClass Itin = NoItinerary,
251 SDPatternOperator OpNode = null_frag> :
252 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, RO:$rt),
253 !strconcat(opstr, "\t$rd, $rs, $rt"),
254 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
255 let isCommutable = isComm;
258 class AndImmMM16<string opstr, RegisterOperand RO,
259 InstrItinClass Itin = NoItinerary> :
260 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, uimm4_andi:$imm),
261 !strconcat(opstr, "\t$rd, $rs, $imm"), [], Itin, FrmI>;
263 class LogicRMM16<string opstr, RegisterOperand RO,
264 InstrItinClass Itin = NoItinerary,
265 SDPatternOperator OpNode = null_frag> :
266 MicroMipsInst16<(outs RO:$dst), (ins RO:$rs, RO:$rt),
267 !strconcat(opstr, "\t$rt, $rs"),
268 [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
269 let isCommutable = 1;
270 let Constraints = "$rt = $dst";
273 class NotMM16<string opstr, RegisterOperand RO> :
274 MicroMipsInst16<(outs RO:$rt), (ins RO:$rs),
275 !strconcat(opstr, "\t$rt, $rs"),
276 [(set RO:$rt, (not RO:$rs))], NoItinerary, FrmR>;
278 class ShiftIMM16<string opstr, Operand ImmOpnd, RegisterOperand RO,
279 InstrItinClass Itin = NoItinerary> :
280 MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
281 !strconcat(opstr, "\t$rd, $rt, $shamt"), [], Itin, FrmR>;
283 class LoadMM16<string opstr, DAGOperand RO, SDPatternOperator OpNode,
284 InstrItinClass Itin, Operand MemOpnd> :
285 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$addr),
286 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
287 let DecoderMethod = "DecodeMemMMImm4";
288 let canFoldAsLoad = 1;
292 class StoreMM16<string opstr, DAGOperand RTOpnd, DAGOperand RO,
293 SDPatternOperator OpNode, InstrItinClass Itin,
295 MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),
296 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
297 let DecoderMethod = "DecodeMemMMImm4";
301 class LoadSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
303 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
304 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
305 let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
306 let canFoldAsLoad = 1;
310 class StoreSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
312 MicroMipsInst16<(outs), (ins RO:$rt, MemOpnd:$offset),
313 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
314 let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
318 class LoadGPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
320 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
321 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
322 let DecoderMethod = "DecodeMemMMGPImm7Lsl2";
323 let canFoldAsLoad = 1;
327 class AddImmUR2<string opstr, RegisterOperand RO> :
328 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, simm3_lsa2:$imm),
329 !strconcat(opstr, "\t$rd, $rs, $imm"),
330 [], NoItinerary, FrmR> {
331 let isCommutable = 1;
334 class AddImmUS5<string opstr, RegisterOperand RO> :
335 MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm),
336 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR> {
337 let Constraints = "$rd = $dst";
340 class AddImmUR1SP<string opstr, RegisterOperand RO> :
341 MicroMipsInst16<(outs RO:$rd), (ins uimm6_lsl2:$imm),
342 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR>;
344 class AddImmUSP<string opstr> :
345 MicroMipsInst16<(outs), (ins simm9_addiusp:$imm),
346 !strconcat(opstr, "\t$imm"), [], NoItinerary, FrmI>;
348 class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
349 MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
350 [], II_MFHI_MFLO, FrmR> {
352 let hasSideEffects = 0;
355 class MoveMM16<string opstr, RegisterOperand RO, bit isComm = 0,
356 InstrItinClass Itin = NoItinerary> :
357 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),
358 !strconcat(opstr, "\t$rd, $rs"), [], Itin, FrmR> {
359 let isCommutable = isComm;
360 let isReMaterializable = 1;
363 class LoadImmMM16<string opstr, Operand Od, RegisterOperand RO> :
364 MicroMipsInst16<(outs RO:$rd), (ins Od:$imm),
365 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmI> {
366 let isReMaterializable = 1;
369 // 16-bit Jump and Link (Call)
370 class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
371 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
372 [(MipsJmpLink RO:$rs)], IIBranch, FrmR> {
374 let hasDelaySlot = 1;
379 class JumpRegMM16<string opstr, RegisterOperand RO> :
380 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
381 [], IIBranch, FrmR> {
382 let hasDelaySlot = 1;
384 let isIndirectBranch = 1;
387 // Base class for JRADDIUSP instruction.
388 class JumpRAddiuStackMM16 :
389 MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jraddiusp\t$imm",
390 [], IIBranch, FrmR> {
391 let isTerminator = 1;
394 let isIndirectBranch = 1;
397 // 16-bit Jump and Link (Call) - Short Delay Slot
398 class JumpLinkRegSMM16<string opstr, RegisterOperand RO> :
399 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
400 [], IIBranch, FrmR> {
402 let hasDelaySlot = 1;
406 // 16-bit Jump Register Compact - No delay slot
407 class JumpRegCMM16<string opstr, RegisterOperand RO> :
408 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
409 [], IIBranch, FrmR> {
410 let isTerminator = 1;
413 let isIndirectBranch = 1;
416 // Break16 and Sdbbp16
417 class BrkSdbbp16MM<string opstr> :
418 MicroMipsInst16<(outs), (ins uimm4:$code_),
419 !strconcat(opstr, "\t$code_"),
420 [], NoItinerary, FrmOther>;
422 class CBranchZeroMM<string opstr, DAGOperand opnd, RegisterOperand RO> :
423 MicroMipsInst16<(outs), (ins RO:$rs, opnd:$offset),
424 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI> {
426 let isTerminator = 1;
427 let hasDelaySlot = 1;
431 // MicroMIPS Jump and Link (Call) - Short Delay Slot
432 let isCall = 1, hasDelaySlot = 1, Defs = [RA] in {
433 class JumpLinkMM<string opstr, DAGOperand opnd> :
434 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
435 [], IIBranch, FrmJ, opstr> {
436 let DecoderMethod = "DecodeJumpTargetMM";
439 class JumpLinkRegMM<string opstr, RegisterOperand RO>:
440 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
443 class BranchCompareToZeroLinkMM<string opstr, DAGOperand opnd,
444 RegisterOperand RO> :
445 InstSE<(outs), (ins RO:$rs, opnd:$offset),
446 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
449 class LoadWordIndexedScaledMM<string opstr, RegisterOperand RO,
450 InstrItinClass Itin = NoItinerary,
451 SDPatternOperator OpNode = null_frag> :
452 InstSE<(outs RO:$rd), (ins PtrRC:$base, PtrRC:$index),
453 !strconcat(opstr, "\t$rd, ${index}(${base})"), [], Itin, FrmFI>;
455 class AddImmUPC<string opstr, RegisterOperand RO> :
456 InstSE<(outs RO:$rs), (ins simm23_lsl2:$imm),
457 !strconcat(opstr, "\t$rs, $imm"), [], NoItinerary, FrmR>;
459 /// A list of registers used by load/store multiple instructions.
460 def RegListAsmOperand : AsmOperandClass {
461 let Name = "RegList";
462 let ParserMethod = "parseRegisterList";
465 def reglist : Operand<i32> {
466 let EncoderMethod = "getRegisterListOpValue";
467 let ParserMatchClass = RegListAsmOperand;
468 let PrintMethod = "printRegisterList";
469 let DecoderMethod = "DecodeRegListOperand";
472 def RegList16AsmOperand : AsmOperandClass {
473 let Name = "RegList16";
474 let ParserMethod = "parseRegisterList";
475 let PredicateMethod = "isRegList16";
476 let RenderMethod = "addRegListOperands";
479 def reglist16 : Operand<i32> {
480 let EncoderMethod = "getRegisterListOpValue16";
481 let DecoderMethod = "DecodeRegListOperand16";
482 let PrintMethod = "printRegisterList";
483 let ParserMatchClass = RegList16AsmOperand;
486 class StoreMultMM<string opstr,
487 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
488 InstSE<(outs), (ins reglist:$rt, mem_mm_12:$addr),
489 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
490 let DecoderMethod = "DecodeMemMMImm12";
494 class LoadMultMM<string opstr,
495 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
496 InstSE<(outs reglist:$rt), (ins mem_mm_12:$addr),
497 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
498 let DecoderMethod = "DecodeMemMMImm12";
502 class StoreMultMM16<string opstr,
503 InstrItinClass Itin = NoItinerary,
504 ComplexPattern Addr = addr> :
505 MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr),
506 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
510 class LoadMultMM16<string opstr,
511 InstrItinClass Itin = NoItinerary,
512 ComplexPattern Addr = addr> :
513 MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
514 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
518 class UncondBranchMM16<string opstr> :
519 MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
520 !strconcat(opstr, "\t$offset"),
521 [], IIBranch, FrmI> {
523 let isTerminator = 1;
525 let hasDelaySlot = 1;
526 let Predicates = [RelocPIC, InMicroMips];
530 def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
532 def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
534 def ANDI16_MM : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>, ANDI_FM_MM16<0x0b>;
535 def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
537 def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
539 def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
541 def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>;
542 def SLL16_MM : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
544 def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
546 def LBU16_MM : LoadMM16<"lbu16", GPRMM16Opnd, zextloadi8, II_LBU,
547 mem_mm_4>, LOAD_STORE_FM_MM16<0x02>;
548 def LHU16_MM : LoadMM16<"lhu16", GPRMM16Opnd, zextloadi16, II_LHU,
549 mem_mm_4_lsl1>, LOAD_STORE_FM_MM16<0x0a>;
550 def LW16_MM : LoadMM16<"lw16", GPRMM16Opnd, load, II_LW, mem_mm_4_lsl2>,
551 LOAD_STORE_FM_MM16<0x1a>;
552 def SB16_MM : StoreMM16<"sb16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei8,
553 II_SB, mem_mm_4>, LOAD_STORE_FM_MM16<0x22>;
554 def SH16_MM : StoreMM16<"sh16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei16,
555 II_SH, mem_mm_4_lsl1>,
556 LOAD_STORE_FM_MM16<0x2a>;
557 def SW16_MM : StoreMM16<"sw16", GPRMM16OpndZero, GPRMM16Opnd, store, II_SW,
558 mem_mm_4_lsl2>, LOAD_STORE_FM_MM16<0x3a>;
559 def LWGP_MM : LoadGPMM16<"lw", GPRMM16Opnd, II_LW, mem_mm_gp_imm7_lsl2>,
560 LOAD_GP_FM_MM16<0x19>;
561 def LWSP_MM : LoadSPMM16<"lw", GPR32Opnd, II_LW, mem_mm_sp_imm5_lsl2>,
562 LOAD_STORE_SP_FM_MM16<0x12>;
563 def SWSP_MM : StoreSPMM16<"sw", GPR32Opnd, II_SW, mem_mm_sp_imm5_lsl2>,
564 LOAD_STORE_SP_FM_MM16<0x32>;
565 def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16;
566 def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16;
567 def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16;
568 def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16;
569 def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
570 def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
571 def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
572 def LI16_MM : LoadImmMM16<"li16", li_simm7, GPRMM16Opnd>, LI_FM_MM16,
574 def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>;
575 def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>;
576 def JRC16_MM : JumpRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>;
577 def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>;
578 def JR16_MM : JumpRegMM16<"jr16", GPR32Opnd>, JALR_FM_MM16<0x0c>;
579 def BEQZ16_MM : CBranchZeroMM<"beqz16", brtarget7_mm, GPRMM16Opnd>,
580 BEQNEZ_FM_MM16<0x23>;
581 def BNEZ16_MM : CBranchZeroMM<"bnez16", brtarget7_mm, GPRMM16Opnd>,
582 BEQNEZ_FM_MM16<0x2b>;
583 def B16_MM : UncondBranchMM16<"b16">, B16_FM;
584 def BREAK16_MM : BrkSdbbp16MM<"break16">, BRKSDBBP16_FM_MM<0x28>;
585 def SDBBP16_MM : BrkSdbbp16MM<"sdbbp16">, BRKSDBBP16_FM_MM<0x2C>;
587 class WaitMM<string opstr> :
588 InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],
589 NoItinerary, FrmOther, opstr>;
591 let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
592 /// Compact Branch Instructions
593 def BEQZC_MM : CompactBranchMM<"beqzc", brtarget_mm, seteq, GPR32Opnd>,
594 COMPACT_BRANCH_FM_MM<0x7>;
595 def BNEZC_MM : CompactBranchMM<"bnezc", brtarget_mm, setne, GPR32Opnd>,
596 COMPACT_BRANCH_FM_MM<0x5>;
598 /// Arithmetic Instructions (ALU Immediate)
599 def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>,
601 def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,
603 def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
605 def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
607 def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>,
609 def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd>,
611 def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd>,
613 def LUi_MM : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM_MM;
615 def LEA_ADDiu_MM : MMRel, EffectiveAddress<"addiu", GPR32Opnd>,
618 /// Arithmetic Instructions (3-Operand, R-Type)
619 def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd>, ADD_FM_MM<0, 0x150>;
620 def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd>, ADD_FM_MM<0, 0x1d0>;
621 def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;
622 def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;
623 def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;
624 def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
625 def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
627 def AND_MM : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
629 def OR_MM : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
631 def XOR_MM : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
633 def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
634 def MULT_MM : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
636 def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
638 def SDIV_MM : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
640 def UDIV_MM : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
643 /// Arithmetic Instructions with PC and Immediate
644 def ADDIUPC_MM : AddImmUPC<"addiupc", GPRMM16Opnd>, ADDIUPC_FM_MM;
646 /// Shift Instructions
647 def SLL_MM : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>,
649 def SRL_MM : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>,
651 def SRA_MM : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>,
653 def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV>,
655 def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV>,
657 def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>,
659 def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,
661 def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>,
664 /// Load and Store Instructions - aligned
665 let DecoderMethod = "DecodeMemMMImm16" in {
666 def LB_MM : Load<"lb", GPR32Opnd>, MMRel, LW_FM_MM<0x7>;
667 def LBu_MM : Load<"lbu", GPR32Opnd>, MMRel, LW_FM_MM<0x5>;
668 def LH_MM : Load<"lh", GPR32Opnd>, MMRel, LW_FM_MM<0xf>;
669 def LHu_MM : Load<"lhu", GPR32Opnd>, MMRel, LW_FM_MM<0xd>;
670 def LW_MM : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>;
671 def SB_MM : Store<"sb", GPR32Opnd>, MMRel, LW_FM_MM<0x6>;
672 def SH_MM : Store<"sh", GPR32Opnd>, MMRel, LW_FM_MM<0xe>;
673 def SW_MM : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
676 def LWXS_MM : LoadWordIndexedScaledMM<"lwxs", GPR32Opnd>, LWXS_FM_MM<0x118>;
678 def LWU_MM : LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU>, LL_FM_MM<0xe>;
680 /// Load and Store Instructions - unaligned
681 def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>,
683 def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12>,
685 def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12>,
687 def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>,
690 /// Load and Store Instructions - multiple
691 def SWM32_MM : StoreMultMM<"swm32">, LWM_FM_MM<0xd>;
692 def LWM32_MM : LoadMultMM<"lwm32">, LWM_FM_MM<0x5>;
693 def SWM16_MM : StoreMultMM16<"swm16">, LWM_FM_MM16<0x5>;
694 def LWM16_MM : LoadMultMM16<"lwm16">, LWM_FM_MM16<0x4>;
696 /// Load and Store Pair Instructions
697 def SWP_MM : StorePairMM<"swp">, LWM_FM_MM<0x9>;
698 def LWP_MM : LoadPairMM<"lwp">, LWM_FM_MM<0x1>;
700 /// Load and Store multiple pseudo Instructions
701 class LoadWordMultMM<string instr_asm > :
702 MipsAsmPseudoInst<(outs reglist:$rt), (ins mem_mm_12:$addr),
703 !strconcat(instr_asm, "\t$rt, $addr")> ;
705 class StoreWordMultMM<string instr_asm > :
706 MipsAsmPseudoInst<(outs), (ins reglist:$rt, mem_mm_12:$addr),
707 !strconcat(instr_asm, "\t$rt, $addr")> ;
710 def SWM_MM : StoreWordMultMM<"swm">;
711 def LWM_MM : LoadWordMultMM<"lwm">;
714 def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
715 NoItinerary>, ADD_FM_MM<0, 0x58>;
716 def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
717 NoItinerary>, ADD_FM_MM<0, 0x18>;
718 def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT>,
719 CMov_F_I_FM_MM<0x25>;
720 def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF>,
723 /// Move to/from HI/LO
724 def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>,
726 def MTLO_MM : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>,
728 def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>,
730 def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>,
733 /// Multiply Add/Sub Instructions
734 def MADD_MM : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM_MM<0x32c>;
735 def MADDU_MM : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM_MM<0x36c>;
736 def MSUB_MM : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>;
737 def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>;
740 def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM_MM<0x16c>,
742 def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM_MM<0x12c>,
745 /// Sign Ext In Register Instructions.
746 def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
747 SEB_FM_MM<0x0ac>, ISA_MIPS32R2;
748 def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
749 SEB_FM_MM<0x0ec>, ISA_MIPS32R2;
751 /// Word Swap Bytes Within Halfwords
752 def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM_MM<0x1ec>,
755 def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>,
757 def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>,
760 /// Jump Instructions
761 let DecoderMethod = "DecodeJumpTargetMM" in {
762 def J_MM : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">,
764 def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>;
766 def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>;
767 def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>;
769 /// Jump Instructions - Short Delay Slot
770 def JALS_MM : JumpLinkMM<"jals", calltarget_mm>, J_FM_MM<0x1d>;
771 def JALRS_MM : JumpLinkRegMM<"jalrs", GPR32Opnd>, JALR_FM_MM<0x13c>;
773 /// Branch Instructions
774 def BEQ_MM : MMRel, CBranch<"beq", brtarget_mm, seteq, GPR32Opnd>,
776 def BNE_MM : MMRel, CBranch<"bne", brtarget_mm, setne, GPR32Opnd>,
778 def BGEZ_MM : MMRel, CBranchZero<"bgez", brtarget_mm, setge, GPR32Opnd>,
780 def BGTZ_MM : MMRel, CBranchZero<"bgtz", brtarget_mm, setgt, GPR32Opnd>,
782 def BLEZ_MM : MMRel, CBranchZero<"blez", brtarget_mm, setle, GPR32Opnd>,
784 def BLTZ_MM : MMRel, CBranchZero<"bltz", brtarget_mm, setlt, GPR32Opnd>,
786 def BGEZAL_MM : MMRel, BGEZAL_FT<"bgezal", brtarget_mm, GPR32Opnd>,
788 def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>,
791 /// Branch Instructions - Short Delay Slot
792 def BGEZALS_MM : BranchCompareToZeroLinkMM<"bgezals", brtarget_mm,
793 GPR32Opnd>, BGEZAL_FM_MM<0x13>;
794 def BLTZALS_MM : BranchCompareToZeroLinkMM<"bltzals", brtarget_mm,
795 GPR32Opnd>, BGEZAL_FM_MM<0x11>;
797 /// Control Instructions
798 def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM;
799 def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM;
800 def SYSCALL_MM : MMRel, SYS_FT<"syscall">, SYS_FM_MM;
801 def WAIT_MM : WaitMM<"wait">, WAIT_FM_MM;
802 def ERET_MM : MMRel, ER_FT<"eret">, ER_FM_MM<0x3cd>;
803 def DERET_MM : MMRel, ER_FT<"deret">, ER_FM_MM<0x38d>;
804 def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM_MM<0x15d>,
806 def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM_MM<0x11d>,
809 /// Trap Instructions
810 def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM_MM<0x0>;
811 def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM_MM<0x08>;
812 def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM_MM<0x10>;
813 def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM_MM<0x20>;
814 def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM_MM<0x28>;
815 def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM_MM<0x30>;
817 def TEQI_MM : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM_MM<0x0e>;
818 def TGEI_MM : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM_MM<0x09>;
819 def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM_MM<0x0b>;
820 def TLTI_MM : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM_MM<0x08>;
821 def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM_MM<0x0a>;
822 def TNEI_MM : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM_MM<0x0c>;
824 /// Load-linked, Store-conditional
825 def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>;
826 def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>;
828 let DecoderMethod = "DecodeCacheOpMM" in {
829 def CACHE_MM : MMRel, CacheOp<"cache", mem_mm_12>,
830 CACHE_PREF_FM_MM<0x08, 0x6>;
831 def PREF_MM : MMRel, CacheOp<"pref", mem_mm_12>,
832 CACHE_PREF_FM_MM<0x18, 0x2>;
834 def SSNOP_MM : MMRel, Barrier<"ssnop">, BARRIER_FM_MM<0x1>;
835 def EHB_MM : MMRel, Barrier<"ehb">, BARRIER_FM_MM<0x3>;
836 def PAUSE_MM : MMRel, Barrier<"pause">, BARRIER_FM_MM<0x5>;
838 def TLBP_MM : MMRel, TLB<"tlbp">, COP0_TLB_FM_MM<0x0d>;
839 def TLBR_MM : MMRel, TLB<"tlbr">, COP0_TLB_FM_MM<0x4d>;
840 def TLBWI_MM : MMRel, TLB<"tlbwi">, COP0_TLB_FM_MM<0x8d>;
841 def TLBWR_MM : MMRel, TLB<"tlbwr">, COP0_TLB_FM_MM<0xcd>;
843 def SDBBP_MM : MMRel, SYS_FT<"sdbbp">, SDBBP_FM_MM;
844 def RDHWR_MM : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM_MM;
847 let Predicates = [InMicroMips] in {
849 //===----------------------------------------------------------------------===//
850 // MicroMips arbitrary patterns that map to one or more instructions
851 //===----------------------------------------------------------------------===//
853 def : MipsPat<(i32 immLi16:$imm),
854 (LI16_MM immLi16:$imm)>;
855 def : MipsPat<(i32 immSExt16:$imm),
856 (ADDiu_MM ZERO, immSExt16:$imm)>;
857 def : MipsPat<(i32 immZExt16:$imm),
858 (ORi_MM ZERO, immZExt16:$imm)>;
860 def : MipsPat<(add GPRMM16:$src, immSExtAddiur2:$imm),
861 (ADDIUR2_MM GPRMM16:$src, immSExtAddiur2:$imm)>;
862 def : MipsPat<(add GPR32:$src, immSExtAddius5:$imm),
863 (ADDIUS5_MM GPR32:$src, immSExtAddius5:$imm)>;
864 def : MipsPat<(add GPR32:$src, immSExt16:$imm),
865 (ADDiu_MM GPR32:$src, immSExt16:$imm)>;
867 def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
868 (ANDI16_MM GPRMM16:$src, immZExtAndi16:$imm)>;
869 def : MipsPat<(and GPR32:$src, immZExt16:$imm),
870 (ANDi_MM GPR32:$src, immZExt16:$imm)>;
872 def : MipsPat<(shl GPRMM16:$src, immZExt2Shift:$imm),
873 (SLL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
874 def : MipsPat<(shl GPR32:$src, immZExt5:$imm),
875 (SLL_MM GPR32:$src, immZExt5:$imm)>;
877 def : MipsPat<(srl GPRMM16:$src, immZExt2Shift:$imm),
878 (SRL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
879 def : MipsPat<(srl GPR32:$src, immZExt5:$imm),
880 (SRL_MM GPR32:$src, immZExt5:$imm)>;
882 //===----------------------------------------------------------------------===//
883 // MicroMips instruction aliases
884 //===----------------------------------------------------------------------===//
886 class UncondBranchMMPseudo<string opstr> :
887 MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
888 !strconcat(opstr, "\t$offset")>;
890 def B_MM_Pseudo : UncondBranchMMPseudo<"b">;
892 def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>;
893 def : MipsInstAlias<"nop", (SLL_MM ZERO, ZERO, 0), 1>;
894 def : MipsInstAlias<"nop", (MOVE16_MM ZERO, ZERO), 1>;