1 def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
2 def addrimm4lsl2 : ComplexPattern<iPTR, 2, "selectIntAddrLSL2MM", [frameindex]>;
4 def simm4 : Operand<i32> {
5 let DecoderMethod = "DecodeSimm4";
7 def simm7 : Operand<i32>;
8 def li_simm7 : Operand<i32> {
9 let DecoderMethod = "DecodeLiSimm7";
12 def simm12 : Operand<i32> {
13 let DecoderMethod = "DecodeSimm12";
16 def MipsUimm5Lsl2AsmOperand : AsmOperandClass {
17 let Name = "Uimm5Lsl2";
18 let RenderMethod = "addImmOperands";
19 let ParserMethod = "parseImm";
20 let PredicateMethod = "isUImm5Lsl2";
23 def uimm5_lsl2 : Operand<OtherVT> {
24 let EncoderMethod = "getUImm5Lsl2Encoding";
25 let DecoderMethod = "DecodeUImm5lsl2";
26 let ParserMatchClass = MipsUimm5Lsl2AsmOperand;
29 def uimm6_lsl2 : Operand<i32> {
30 let EncoderMethod = "getUImm6Lsl2Encoding";
31 let DecoderMethod = "DecodeUImm6Lsl2";
34 def simm9_addiusp : Operand<i32> {
35 let EncoderMethod = "getSImm9AddiuspValue";
36 let DecoderMethod = "DecodeSimm9SP";
39 def uimm3_shift : Operand<i32> {
40 let EncoderMethod = "getUImm3Mod8Encoding";
41 let DecoderMethod = "DecodePOOL16BEncodedField";
44 def simm3_lsa2 : Operand<i32> {
45 let EncoderMethod = "getSImm3Lsa2Value";
46 let DecoderMethod = "DecodeAddiur2Simm7";
49 def uimm4_andi : Operand<i32> {
50 let EncoderMethod = "getUImm4AndValue";
51 let DecoderMethod = "DecodeANDI16Imm";
54 def immSExtAddiur2 : ImmLeaf<i32, [{return Imm == 1 || Imm == -1 ||
56 Imm < 28 && Imm > 0);}]>;
58 def immSExtAddius5 : ImmLeaf<i32, [{return Imm >= -8 && Imm <= 7;}]>;
60 def immZExtAndi16 : ImmLeaf<i32,
61 [{return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
62 Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
63 Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );}]>;
65 def immZExt2Shift : ImmLeaf<i32, [{return Imm >= 1 && Imm <= 8;}]>;
67 def immLi16 : ImmLeaf<i32, [{return Imm >= -1 && Imm <= 126;}]>;
69 def MicroMipsMemGPRMM16AsmOperand : AsmOperandClass {
70 let Name = "MicroMipsMem";
71 let RenderMethod = "addMicroMipsMemOperands";
72 let ParserMethod = "parseMemOperand";
73 let PredicateMethod = "isMemWithGRPMM16Base";
76 class mem_mm_4_generic : Operand<i32> {
77 let PrintMethod = "printMemOperand";
78 let MIOperandInfo = (ops GPRMM16, simm4);
79 let OperandType = "OPERAND_MEMORY";
80 let ParserMatchClass = MicroMipsMemGPRMM16AsmOperand;
83 def mem_mm_4 : mem_mm_4_generic {
84 let EncoderMethod = "getMemEncodingMMImm4";
87 def mem_mm_4_lsl1 : mem_mm_4_generic {
88 let EncoderMethod = "getMemEncodingMMImm4Lsl1";
91 def mem_mm_4_lsl2 : mem_mm_4_generic {
92 let EncoderMethod = "getMemEncodingMMImm4Lsl2";
95 def MicroMipsMemSPAsmOperand : AsmOperandClass {
96 let Name = "MicroMipsMemSP";
97 let RenderMethod = "addMemOperands";
98 let ParserMethod = "parseMemOperand";
99 let PredicateMethod = "isMemWithUimmWordAlignedOffsetSP<7>";
102 def mem_mm_sp_imm5_lsl2 : Operand<i32> {
103 let PrintMethod = "printMemOperand";
104 let MIOperandInfo = (ops GPR32:$base, simm5:$offset);
105 let OperandType = "OPERAND_MEMORY";
106 let ParserMatchClass = MicroMipsMemSPAsmOperand;
107 let EncoderMethod = "getMemEncodingMMSPImm5Lsl2";
110 def mem_mm_gp_imm7_lsl2 : Operand<i32> {
111 let PrintMethod = "printMemOperand";
112 let MIOperandInfo = (ops GPRMM16:$base, simm7:$offset);
113 let OperandType = "OPERAND_MEMORY";
114 let EncoderMethod = "getMemEncodingMMGPImm7Lsl2";
117 def mem_mm_9 : Operand<i32> {
118 let PrintMethod = "printMemOperand";
119 let MIOperandInfo = (ops GPR32, simm9);
120 let EncoderMethod = "getMemEncodingMMImm9";
121 let ParserMatchClass = MipsMemAsmOperand;
122 let OperandType = "OPERAND_MEMORY";
125 def mem_mm_12 : Operand<i32> {
126 let PrintMethod = "printMemOperand";
127 let MIOperandInfo = (ops GPR32, simm12);
128 let EncoderMethod = "getMemEncodingMMImm12";
129 let ParserMatchClass = MipsMemAsmOperand;
130 let OperandType = "OPERAND_MEMORY";
133 def MipsMemUimm4AsmOperand : AsmOperandClass {
134 let Name = "MemOffsetUimm4";
135 let SuperClasses = [MipsMemAsmOperand];
136 let RenderMethod = "addMemOperands";
137 let ParserMethod = "parseMemOperand";
138 let PredicateMethod = "isMemWithUimmOffsetSP<6>";
141 def mem_mm_4sp : Operand<i32> {
142 let PrintMethod = "printMemOperand";
143 let MIOperandInfo = (ops GPR32, uimm8);
144 let EncoderMethod = "getMemEncodingMMImm4sp";
145 let ParserMatchClass = MipsMemUimm4AsmOperand;
146 let OperandType = "OPERAND_MEMORY";
149 def jmptarget_mm : Operand<OtherVT> {
150 let EncoderMethod = "getJumpTargetOpValueMM";
153 def calltarget_mm : Operand<iPTR> {
154 let EncoderMethod = "getJumpTargetOpValueMM";
157 def brtarget7_mm : Operand<OtherVT> {
158 let EncoderMethod = "getBranchTarget7OpValueMM";
159 let OperandType = "OPERAND_PCREL";
160 let DecoderMethod = "DecodeBranchTarget7MM";
161 let ParserMatchClass = MipsJumpTargetAsmOperand;
164 def brtarget10_mm : Operand<OtherVT> {
165 let EncoderMethod = "getBranchTargetOpValueMMPC10";
166 let OperandType = "OPERAND_PCREL";
167 let DecoderMethod = "DecodeBranchTarget10MM";
168 let ParserMatchClass = MipsJumpTargetAsmOperand;
171 def brtarget_mm : Operand<OtherVT> {
172 let EncoderMethod = "getBranchTargetOpValueMM";
173 let OperandType = "OPERAND_PCREL";
174 let DecoderMethod = "DecodeBranchTargetMM";
175 let ParserMatchClass = MipsJumpTargetAsmOperand;
178 def simm23_lsl2 : Operand<i32> {
179 let EncoderMethod = "getSimm23Lsl2Encoding";
180 let DecoderMethod = "DecodeSimm23Lsl2";
183 class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op,
184 RegisterOperand RO> :
185 InstSE<(outs), (ins RO:$rs, opnd:$offset),
186 !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZC, FrmI> {
188 let isTerminator = 1;
189 let hasDelaySlot = 0;
193 let canFoldAsLoad = 1 in
194 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
196 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
197 !strconcat(opstr, "\t$rt, $addr"),
198 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
200 let DecoderMethod = "DecodeMemMMImm12";
201 string Constraints = "$src = $rt";
204 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
206 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
207 !strconcat(opstr, "\t$rt, $addr"),
208 [(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> {
209 let DecoderMethod = "DecodeMemMMImm12";
212 /// A register pair used by movep instruction.
213 def MovePRegPairAsmOperand : AsmOperandClass {
214 let Name = "MovePRegPair";
215 let ParserMethod = "parseMovePRegPair";
216 let PredicateMethod = "isMovePRegPair";
219 def movep_regpair : Operand<i32> {
220 let EncoderMethod = "getMovePRegPairOpValue";
221 let ParserMatchClass = MovePRegPairAsmOperand;
222 let PrintMethod = "printRegisterList";
223 let DecoderMethod = "DecodeMovePRegPair";
224 let MIOperandInfo = (ops GPR32Opnd, GPR32Opnd);
227 class MovePMM16<string opstr, RegisterOperand RO> :
228 MicroMipsInst16<(outs movep_regpair:$dst_regs), (ins RO:$rs, RO:$rt),
229 !strconcat(opstr, "\t$dst_regs, $rs, $rt"), [],
231 let isReMaterializable = 1;
234 /// A register pair used by load/store pair instructions.
235 def RegPairAsmOperand : AsmOperandClass {
236 let Name = "RegPair";
237 let ParserMethod = "parseRegisterPair";
240 def regpair : Operand<i32> {
241 let EncoderMethod = "getRegisterPairOpValue";
242 let ParserMatchClass = RegPairAsmOperand;
243 let PrintMethod = "printRegisterPair";
244 let DecoderMethod = "DecodeRegPairOperand";
245 let MIOperandInfo = (ops GPR32Opnd, GPR32Opnd);
248 class StorePairMM<string opstr, InstrItinClass Itin = NoItinerary,
249 ComplexPattern Addr = addr> :
250 InstSE<(outs), (ins regpair:$rt, mem_mm_12:$addr),
251 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
252 let DecoderMethod = "DecodeMemMMImm12";
256 class LoadPairMM<string opstr, InstrItinClass Itin = NoItinerary,
257 ComplexPattern Addr = addr> :
258 InstSE<(outs regpair:$rt), (ins mem_mm_12:$addr),
259 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
260 let DecoderMethod = "DecodeMemMMImm12";
264 class LLBaseMM<string opstr, RegisterOperand RO> :
265 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
266 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
267 let DecoderMethod = "DecodeMemMMImm12";
271 class SCBaseMM<string opstr, RegisterOperand RO> :
272 InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
273 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
274 let DecoderMethod = "DecodeMemMMImm12";
276 let Constraints = "$rt = $dst";
279 class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
280 InstrItinClass Itin = NoItinerary> :
281 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
282 !strconcat(opstr, "\t$rt, $addr"),
283 [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI> {
284 let DecoderMethod = "DecodeMemMMImm12";
285 let canFoldAsLoad = 1;
289 class ArithRMM16<string opstr, RegisterOperand RO, bit isComm = 0,
290 InstrItinClass Itin = NoItinerary,
291 SDPatternOperator OpNode = null_frag> :
292 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, RO:$rt),
293 !strconcat(opstr, "\t$rd, $rs, $rt"),
294 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
295 let isCommutable = isComm;
298 class AndImmMM16<string opstr, RegisterOperand RO,
299 InstrItinClass Itin = NoItinerary> :
300 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, uimm4_andi:$imm),
301 !strconcat(opstr, "\t$rd, $rs, $imm"), [], Itin, FrmI>;
303 class LogicRMM16<string opstr, RegisterOperand RO,
304 InstrItinClass Itin = NoItinerary,
305 SDPatternOperator OpNode = null_frag> :
306 MicroMipsInst16<(outs RO:$dst), (ins RO:$rs, RO:$rt),
307 !strconcat(opstr, "\t$rt, $rs"),
308 [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
309 let isCommutable = 1;
310 let Constraints = "$rt = $dst";
313 class NotMM16<string opstr, RegisterOperand RO> :
314 MicroMipsInst16<(outs RO:$rt), (ins RO:$rs),
315 !strconcat(opstr, "\t$rt, $rs"),
316 [(set RO:$rt, (not RO:$rs))], NoItinerary, FrmR>;
318 class ShiftIMM16<string opstr, Operand ImmOpnd, RegisterOperand RO,
319 InstrItinClass Itin = NoItinerary> :
320 MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
321 !strconcat(opstr, "\t$rd, $rt, $shamt"), [], Itin, FrmR>;
323 class LoadMM16<string opstr, DAGOperand RO, SDPatternOperator OpNode,
324 InstrItinClass Itin, Operand MemOpnd> :
325 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$addr),
326 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
327 let DecoderMethod = "DecodeMemMMImm4";
328 let canFoldAsLoad = 1;
332 class StoreMM16<string opstr, DAGOperand RTOpnd, DAGOperand RO,
333 SDPatternOperator OpNode, InstrItinClass Itin,
335 MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),
336 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
337 let DecoderMethod = "DecodeMemMMImm4";
341 class LoadSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
343 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
344 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
345 let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
346 let canFoldAsLoad = 1;
350 class StoreSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
352 MicroMipsInst16<(outs), (ins RO:$rt, MemOpnd:$offset),
353 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
354 let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
358 class LoadGPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
360 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
361 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
362 let DecoderMethod = "DecodeMemMMGPImm7Lsl2";
363 let canFoldAsLoad = 1;
367 class AddImmUR2<string opstr, RegisterOperand RO> :
368 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, simm3_lsa2:$imm),
369 !strconcat(opstr, "\t$rd, $rs, $imm"),
370 [], NoItinerary, FrmR> {
371 let isCommutable = 1;
374 class AddImmUS5<string opstr, RegisterOperand RO> :
375 MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm),
376 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR> {
377 let Constraints = "$rd = $dst";
380 class AddImmUR1SP<string opstr, RegisterOperand RO> :
381 MicroMipsInst16<(outs RO:$rd), (ins uimm6_lsl2:$imm),
382 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR>;
384 class AddImmUSP<string opstr> :
385 MicroMipsInst16<(outs), (ins simm9_addiusp:$imm),
386 !strconcat(opstr, "\t$imm"), [], NoItinerary, FrmI>;
388 class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
389 MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
390 [], II_MFHI_MFLO, FrmR> {
392 let hasSideEffects = 0;
395 class MoveMM16<string opstr, RegisterOperand RO, bit isComm = 0,
396 InstrItinClass Itin = NoItinerary> :
397 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),
398 !strconcat(opstr, "\t$rd, $rs"), [], Itin, FrmR> {
399 let isCommutable = isComm;
400 let isReMaterializable = 1;
403 class LoadImmMM16<string opstr, Operand Od, RegisterOperand RO> :
404 MicroMipsInst16<(outs RO:$rd), (ins Od:$imm),
405 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmI> {
406 let isReMaterializable = 1;
409 // 16-bit Jump and Link (Call)
410 class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
411 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
412 [(MipsJmpLink RO:$rs)], II_JALR, FrmR>, PredicateControl {
414 let hasDelaySlot = 1;
419 class JumpRegMM16<string opstr, RegisterOperand RO> :
420 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
422 let hasDelaySlot = 1;
424 let isIndirectBranch = 1;
427 // Base class for JRADDIUSP instruction.
428 class JumpRAddiuStackMM16 :
429 MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jraddiusp\t$imm",
430 [], II_JRADDIUSP, FrmR> {
431 let isTerminator = 1;
434 let isIndirectBranch = 1;
437 // 16-bit Jump and Link (Call) - Short Delay Slot
438 class JumpLinkRegSMM16<string opstr, RegisterOperand RO> :
439 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
440 [], II_JALRS, FrmR> {
442 let hasDelaySlot = 1;
446 // 16-bit Jump Register Compact - No delay slot
447 class JumpRegCMM16<string opstr, RegisterOperand RO> :
448 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
450 let isTerminator = 1;
453 let isIndirectBranch = 1;
456 // Break16 and Sdbbp16
457 class BrkSdbbp16MM<string opstr> :
458 MicroMipsInst16<(outs), (ins uimm4:$code_),
459 !strconcat(opstr, "\t$code_"),
460 [], NoItinerary, FrmOther>;
462 class CBranchZeroMM<string opstr, DAGOperand opnd, RegisterOperand RO> :
463 MicroMipsInst16<(outs), (ins RO:$rs, opnd:$offset),
464 !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZ, FrmI> {
466 let isTerminator = 1;
467 let hasDelaySlot = 1;
471 // MicroMIPS Jump and Link (Call) - Short Delay Slot
472 let isCall = 1, hasDelaySlot = 1, Defs = [RA] in {
473 class JumpLinkMM<string opstr, DAGOperand opnd> :
474 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
475 [], II_JALS, FrmJ, opstr> {
476 let DecoderMethod = "DecodeJumpTargetMM";
479 class JumpLinkRegMM<string opstr, RegisterOperand RO>:
480 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
483 class BranchCompareToZeroLinkMM<string opstr, DAGOperand opnd,
484 RegisterOperand RO> :
485 InstSE<(outs), (ins RO:$rs, opnd:$offset),
486 !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZALS, FrmI, opstr>;
489 class LoadWordIndexedScaledMM<string opstr, RegisterOperand RO,
490 InstrItinClass Itin = NoItinerary,
491 SDPatternOperator OpNode = null_frag> :
492 InstSE<(outs RO:$rd), (ins PtrRC:$base, PtrRC:$index),
493 !strconcat(opstr, "\t$rd, ${index}(${base})"), [], Itin, FrmFI>;
495 class PrefetchIndexed<string opstr> :
496 InstSE<(outs), (ins PtrRC:$base, PtrRC:$index, uimm5:$hint),
497 !strconcat(opstr, "\t$hint, ${index}(${base})"), [], NoItinerary, FrmOther>;
499 class AddImmUPC<string opstr, RegisterOperand RO> :
500 InstSE<(outs RO:$rs), (ins simm23_lsl2:$imm),
501 !strconcat(opstr, "\t$rs, $imm"), [], NoItinerary, FrmR>;
503 /// A list of registers used by load/store multiple instructions.
504 def RegListAsmOperand : AsmOperandClass {
505 let Name = "RegList";
506 let ParserMethod = "parseRegisterList";
509 def reglist : Operand<i32> {
510 let EncoderMethod = "getRegisterListOpValue";
511 let ParserMatchClass = RegListAsmOperand;
512 let PrintMethod = "printRegisterList";
513 let DecoderMethod = "DecodeRegListOperand";
516 def RegList16AsmOperand : AsmOperandClass {
517 let Name = "RegList16";
518 let ParserMethod = "parseRegisterList";
519 let PredicateMethod = "isRegList16";
520 let RenderMethod = "addRegListOperands";
523 def reglist16 : Operand<i32> {
524 let EncoderMethod = "getRegisterListOpValue16";
525 let DecoderMethod = "DecodeRegListOperand16";
526 let PrintMethod = "printRegisterList";
527 let ParserMatchClass = RegList16AsmOperand;
530 class StoreMultMM<string opstr,
531 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
532 InstSE<(outs), (ins reglist:$rt, mem_mm_12:$addr),
533 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
534 let DecoderMethod = "DecodeMemMMImm12";
538 class LoadMultMM<string opstr,
539 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
540 InstSE<(outs reglist:$rt), (ins mem_mm_12:$addr),
541 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
542 let DecoderMethod = "DecodeMemMMImm12";
546 class StoreMultMM16<string opstr,
547 InstrItinClass Itin = NoItinerary,
548 ComplexPattern Addr = addr> :
549 MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr),
550 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
551 let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
555 class LoadMultMM16<string opstr,
556 InstrItinClass Itin = NoItinerary,
557 ComplexPattern Addr = addr> :
558 MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
559 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
560 let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
564 class UncondBranchMM16<string opstr> :
565 MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
566 !strconcat(opstr, "\t$offset"),
569 let isTerminator = 1;
571 let hasDelaySlot = 1;
572 let Predicates = [RelocPIC, InMicroMips];
576 def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
577 ARITH_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6_64R6;
578 def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
579 LOGIC_FM_MM16<0x2>, ISA_MICROMIPS_NOT_32R6_64R6;
580 def ANDI16_MM : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>, ANDI_FM_MM16<0x0b>,
581 ISA_MICROMIPS_NOT_32R6_64R6;
582 def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>,
583 ISA_MICROMIPS_NOT_32R6_64R6;
584 def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>, LOGIC_FM_MM16<0x3>,
585 ISA_MICROMIPS_NOT_32R6_64R6;
586 def SLL16_MM : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
587 SHIFT_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6_64R6;
588 def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
589 SHIFT_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6_64R6;
591 def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
593 def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
595 def LBU16_MM : LoadMM16<"lbu16", GPRMM16Opnd, zextloadi8, II_LBU,
596 mem_mm_4>, LOAD_STORE_FM_MM16<0x02>;
597 def LHU16_MM : LoadMM16<"lhu16", GPRMM16Opnd, zextloadi16, II_LHU,
598 mem_mm_4_lsl1>, LOAD_STORE_FM_MM16<0x0a>;
599 def LW16_MM : LoadMM16<"lw16", GPRMM16Opnd, load, II_LW, mem_mm_4_lsl2>,
600 LOAD_STORE_FM_MM16<0x1a>;
601 def SB16_MM : StoreMM16<"sb16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei8,
602 II_SB, mem_mm_4>, LOAD_STORE_FM_MM16<0x22>;
603 def SH16_MM : StoreMM16<"sh16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei16,
604 II_SH, mem_mm_4_lsl1>,
605 LOAD_STORE_FM_MM16<0x2a>;
606 def SW16_MM : StoreMM16<"sw16", GPRMM16OpndZero, GPRMM16Opnd, store, II_SW,
607 mem_mm_4_lsl2>, LOAD_STORE_FM_MM16<0x3a>;
608 def LWGP_MM : LoadGPMM16<"lw", GPRMM16Opnd, II_LW, mem_mm_gp_imm7_lsl2>,
609 LOAD_GP_FM_MM16<0x19>;
610 def LWSP_MM : LoadSPMM16<"lw", GPR32Opnd, II_LW, mem_mm_sp_imm5_lsl2>,
611 LOAD_STORE_SP_FM_MM16<0x12>;
612 def SWSP_MM : StoreSPMM16<"sw", GPR32Opnd, II_SW, mem_mm_sp_imm5_lsl2>,
613 LOAD_STORE_SP_FM_MM16<0x32>;
614 def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16;
615 def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16;
616 def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16;
617 def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16;
618 def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
619 def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
620 def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
621 def MOVEP_MM : MovePMM16<"movep", GPRMM16OpndMoveP>, MOVEP_FM_MM16;
622 def LI16_MM : LoadImmMM16<"li16", li_simm7, GPRMM16Opnd>, LI_FM_MM16,
624 def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>,
625 ISA_MICROMIPS32_NOT_MIPS32R6;
626 def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>;
627 def JRC16_MM : JumpRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>;
628 def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>;
629 def JR16_MM : JumpRegMM16<"jr16", GPR32Opnd>, JALR_FM_MM16<0x0c>;
630 def BEQZ16_MM : CBranchZeroMM<"beqz16", brtarget7_mm, GPRMM16Opnd>,
631 BEQNEZ_FM_MM16<0x23>;
632 def BNEZ16_MM : CBranchZeroMM<"bnez16", brtarget7_mm, GPRMM16Opnd>,
633 BEQNEZ_FM_MM16<0x2b>;
634 def B16_MM : UncondBranchMM16<"b16">, B16_FM;
635 def BREAK16_MM : BrkSdbbp16MM<"break16">, BRKSDBBP16_FM_MM<0x28>;
636 def SDBBP16_MM : BrkSdbbp16MM<"sdbbp16">, BRKSDBBP16_FM_MM<0x2C>;
638 class WaitMM<string opstr> :
639 InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],
640 NoItinerary, FrmOther, opstr>;
642 let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
643 /// Compact Branch Instructions
644 def BEQZC_MM : CompactBranchMM<"beqzc", brtarget_mm, seteq, GPR32Opnd>,
645 COMPACT_BRANCH_FM_MM<0x7>;
646 def BNEZC_MM : CompactBranchMM<"bnezc", brtarget_mm, setne, GPR32Opnd>,
647 COMPACT_BRANCH_FM_MM<0x5>;
649 /// Arithmetic Instructions (ALU Immediate)
650 def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>,
652 def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,
654 def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
656 def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
658 def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>,
660 def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd>,
662 def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd>,
664 def LUi_MM : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM_MM;
666 def LEA_ADDiu_MM : MMRel, EffectiveAddress<"addiu", GPR32Opnd>,
669 /// Arithmetic Instructions (3-Operand, R-Type)
670 def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
672 def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
674 def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;
675 def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;
676 def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;
677 def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
678 def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
680 def AND_MM : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
682 def OR_MM : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
684 def XOR_MM : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
686 def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
687 def MULT_MM : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
689 def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
691 def SDIV_MM : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
693 def UDIV_MM : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
696 /// Arithmetic Instructions with PC and Immediate
697 def ADDIUPC_MM : AddImmUPC<"addiupc", GPRMM16Opnd>, ADDIUPC_FM_MM;
699 /// Shift Instructions
700 def SLL_MM : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>,
702 def SRL_MM : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>,
704 def SRA_MM : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>,
706 def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV>,
708 def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV>,
710 def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>,
712 def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,
714 def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>,
717 /// Load and Store Instructions - aligned
718 let DecoderMethod = "DecodeMemMMImm16" in {
719 def LB_MM : Load<"lb", GPR32Opnd>, MMRel, LW_FM_MM<0x7>;
720 def LBu_MM : Load<"lbu", GPR32Opnd>, MMRel, LW_FM_MM<0x5>;
721 def LH_MM : Load<"lh", GPR32Opnd>, MMRel, LW_FM_MM<0xf>;
722 def LHu_MM : Load<"lhu", GPR32Opnd>, MMRel, LW_FM_MM<0xd>;
723 def LW_MM : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>;
724 def SB_MM : Store<"sb", GPR32Opnd>, MMRel, LW_FM_MM<0x6>;
725 def SH_MM : Store<"sh", GPR32Opnd>, MMRel, LW_FM_MM<0xe>;
726 def SW_MM : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
729 let DecoderMethod = "DecodeMemMMImm9" in {
730 def LBE_MM : Load<"lbe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x4>;
731 def LBuE_MM : Load<"lbue", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x0>;
732 def LHE_MM : Load<"lhe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x5>;
733 def LHuE_MM : Load<"lhue", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x1>;
734 def LWE_MM : Load<"lwe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x7>;
735 def SBE_MM : Store<"sbe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0xa, 0x4>;
736 def SHE_MM : Store<"she", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0xa, 0x5>;
737 def SWE_MM : StoreMemory<"swe", GPR32Opnd, mem_simm9gpr>,
738 POOL32C_LHUE_FM_MM<0x18, 0xa, 0x7>;
741 def LWXS_MM : LoadWordIndexedScaledMM<"lwxs", GPR32Opnd>, LWXS_FM_MM<0x118>;
743 def LWU_MM : LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU>, LL_FM_MM<0xe>;
745 /// Load and Store Instructions - unaligned
746 def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>,
748 def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12>,
750 def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12>,
752 def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>,
754 let DecoderMethod = "DecodeMemMMImm9" in {
755 def LWLE_MM : LoadLeftRightMM<"lwle", MipsLWL, GPR32Opnd, mem_mm_12>,
756 POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x2>;
757 def LWRE_MM : LoadLeftRightMM<"lwre", MipsLWR, GPR32Opnd, mem_mm_12>,
758 POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x3>;
759 def SWLE_MM : StoreLeftRightMM<"swle", MipsSWL, GPR32Opnd, mem_mm_12>,
760 POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x0>;
761 def SWRE_MM : StoreLeftRightMM<"swre", MipsSWR, GPR32Opnd, mem_mm_12>,
762 POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x1>, ISA_MIPS1_NOT_32R6_64R6;
765 /// Load and Store Instructions - multiple
766 def SWM32_MM : StoreMultMM<"swm32">, LWM_FM_MM<0xd>;
767 def LWM32_MM : LoadMultMM<"lwm32">, LWM_FM_MM<0x5>;
768 def SWM16_MM : StoreMultMM16<"swm16">, LWM_FM_MM16<0x5>;
769 def LWM16_MM : LoadMultMM16<"lwm16">, LWM_FM_MM16<0x4>;
771 /// Load and Store Pair Instructions
772 def SWP_MM : StorePairMM<"swp">, LWM_FM_MM<0x9>;
773 def LWP_MM : LoadPairMM<"lwp">, LWM_FM_MM<0x1>;
775 /// Load and Store multiple pseudo Instructions
776 class LoadWordMultMM<string instr_asm > :
777 MipsAsmPseudoInst<(outs reglist:$rt), (ins mem_mm_12:$addr),
778 !strconcat(instr_asm, "\t$rt, $addr")> ;
780 class StoreWordMultMM<string instr_asm > :
781 MipsAsmPseudoInst<(outs), (ins reglist:$rt, mem_mm_12:$addr),
782 !strconcat(instr_asm, "\t$rt, $addr")> ;
785 def SWM_MM : StoreWordMultMM<"swm">;
786 def LWM_MM : LoadWordMultMM<"lwm">;
789 def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
790 NoItinerary>, ADD_FM_MM<0, 0x58>;
791 def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
792 NoItinerary>, ADD_FM_MM<0, 0x18>;
793 def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT>,
794 CMov_F_I_FM_MM<0x25>;
795 def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF>,
798 /// Move to/from HI/LO
799 def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>,
801 def MTLO_MM : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>,
803 def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>,
805 def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>,
808 /// Multiply Add/Sub Instructions
809 def MADD_MM : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM_MM<0x32c>;
810 def MADDU_MM : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM_MM<0x36c>;
811 def MSUB_MM : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>;
812 def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>;
815 def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM_MM<0x16c>,
817 def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM_MM<0x12c>,
820 /// Sign Ext In Register Instructions.
821 def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
822 SEB_FM_MM<0x0ac>, ISA_MIPS32R2;
823 def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
824 SEB_FM_MM<0x0ec>, ISA_MIPS32R2;
826 /// Word Swap Bytes Within Halfwords
827 def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>,
828 SEB_FM_MM<0x1ec>, ISA_MIPS32R2;
830 def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>,
832 def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>,
835 /// Jump Instructions
836 let DecoderMethod = "DecodeJumpTargetMM" in {
837 def J_MM : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">,
839 def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>;
840 def JALX_MM : MMRel, JumpLink<"jalx", calltarget>, J_FM_MM<0x3c>;
842 def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>;
843 def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>;
845 /// Jump Instructions - Short Delay Slot
846 def JALS_MM : JumpLinkMM<"jals", calltarget_mm>, J_FM_MM<0x1d>;
847 def JALRS_MM : JumpLinkRegMM<"jalrs", GPR32Opnd>, JALR_FM_MM<0x13c>;
849 /// Branch Instructions
850 def BEQ_MM : MMRel, CBranch<"beq", brtarget_mm, seteq, GPR32Opnd>,
852 def BNE_MM : MMRel, CBranch<"bne", brtarget_mm, setne, GPR32Opnd>,
854 def BGEZ_MM : MMRel, CBranchZero<"bgez", brtarget_mm, setge, GPR32Opnd>,
856 def BGTZ_MM : MMRel, CBranchZero<"bgtz", brtarget_mm, setgt, GPR32Opnd>,
858 def BLEZ_MM : MMRel, CBranchZero<"blez", brtarget_mm, setle, GPR32Opnd>,
860 def BLTZ_MM : MMRel, CBranchZero<"bltz", brtarget_mm, setlt, GPR32Opnd>,
862 def BGEZAL_MM : MMRel, BGEZAL_FT<"bgezal", brtarget_mm, GPR32Opnd>,
864 def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>,
867 /// Branch Instructions - Short Delay Slot
868 def BGEZALS_MM : BranchCompareToZeroLinkMM<"bgezals", brtarget_mm,
869 GPR32Opnd>, BGEZAL_FM_MM<0x13>;
870 def BLTZALS_MM : BranchCompareToZeroLinkMM<"bltzals", brtarget_mm,
871 GPR32Opnd>, BGEZAL_FM_MM<0x11>;
873 /// Control Instructions
874 def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM;
875 def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM;
876 def SYSCALL_MM : MMRel, SYS_FT<"syscall">, SYS_FM_MM;
877 def WAIT_MM : WaitMM<"wait">, WAIT_FM_MM;
878 def ERET_MM : MMRel, ER_FT<"eret">, ER_FM_MM<0x3cd>;
879 def DERET_MM : MMRel, ER_FT<"deret">, ER_FM_MM<0x38d>;
880 def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM_MM<0x15d>,
882 def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM_MM<0x11d>,
885 /// Trap Instructions
886 def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM_MM<0x0>;
887 def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM_MM<0x08>;
888 def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM_MM<0x10>;
889 def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM_MM<0x20>;
890 def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM_MM<0x28>;
891 def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM_MM<0x30>;
893 def TEQI_MM : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM_MM<0x0e>;
894 def TGEI_MM : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM_MM<0x09>;
895 def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM_MM<0x0b>;
896 def TLTI_MM : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM_MM<0x08>;
897 def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM_MM<0x0a>;
898 def TNEI_MM : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM_MM<0x0c>;
900 /// Load-linked, Store-conditional
901 def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>;
902 def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>;
904 let DecoderMethod = "DecodeCacheOpMM" in {
905 def CACHE_MM : MMRel, CacheOp<"cache", mem_mm_12>,
906 CACHE_PREF_FM_MM<0x08, 0x6>;
907 def PREF_MM : MMRel, CacheOp<"pref", mem_mm_12>,
908 CACHE_PREF_FM_MM<0x18, 0x2>;
911 let DecoderMethod = "DecodePrefeOpMM" in {
912 def PREFE_MM : MMRel, CacheOp<"prefe", mem_mm_9>,
913 CACHE_PREFE_FM_MM<0x18, 0x2>;
914 def CACHEE_MM : MMRel, CacheOp<"cachee", mem_mm_9>,
915 CACHE_PREFE_FM_MM<0x18, 0x3>;
917 def SSNOP_MM : MMRel, Barrier<"ssnop">, BARRIER_FM_MM<0x1>;
918 def EHB_MM : MMRel, Barrier<"ehb">, BARRIER_FM_MM<0x3>;
919 def PAUSE_MM : MMRel, Barrier<"pause">, BARRIER_FM_MM<0x5>;
921 def TLBP_MM : MMRel, TLB<"tlbp">, COP0_TLB_FM_MM<0x0d>;
922 def TLBR_MM : MMRel, TLB<"tlbr">, COP0_TLB_FM_MM<0x4d>;
923 def TLBWI_MM : MMRel, TLB<"tlbwi">, COP0_TLB_FM_MM<0x8d>;
924 def TLBWR_MM : MMRel, TLB<"tlbwr">, COP0_TLB_FM_MM<0xcd>;
926 def SDBBP_MM : MMRel, SYS_FT<"sdbbp">, SDBBP_FM_MM;
927 def RDHWR_MM : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM_MM;
929 def PREFX_MM : PrefetchIndexed<"prefx">, POOL32F_PREFX_FM_MM<0x15, 0x1A0>;
932 let Predicates = [InMicroMips] in {
934 //===----------------------------------------------------------------------===//
935 // MicroMips arbitrary patterns that map to one or more instructions
936 //===----------------------------------------------------------------------===//
938 def : MipsPat<(i32 immLi16:$imm),
939 (LI16_MM immLi16:$imm)>;
940 def : MipsPat<(i32 immSExt16:$imm),
941 (ADDiu_MM ZERO, immSExt16:$imm)>;
942 def : MipsPat<(i32 immZExt16:$imm),
943 (ORi_MM ZERO, immZExt16:$imm)>;
944 def : MipsPat<(not GPR32:$in),
945 (NOR_MM GPR32Opnd:$in, ZERO)>;
947 def : MipsPat<(add GPRMM16:$src, immSExtAddiur2:$imm),
948 (ADDIUR2_MM GPRMM16:$src, immSExtAddiur2:$imm)>;
949 def : MipsPat<(add GPR32:$src, immSExtAddius5:$imm),
950 (ADDIUS5_MM GPR32:$src, immSExtAddius5:$imm)>;
951 def : MipsPat<(add GPR32:$src, immSExt16:$imm),
952 (ADDiu_MM GPR32:$src, immSExt16:$imm)>;
954 def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
955 (ANDI16_MM GPRMM16:$src, immZExtAndi16:$imm)>;
956 def : MipsPat<(and GPR32:$src, immZExt16:$imm),
957 (ANDi_MM GPR32:$src, immZExt16:$imm)>;
959 def : MipsPat<(shl GPRMM16:$src, immZExt2Shift:$imm),
960 (SLL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
961 def : MipsPat<(shl GPR32:$src, immZExt5:$imm),
962 (SLL_MM GPR32:$src, immZExt5:$imm)>;
964 def : MipsPat<(srl GPRMM16:$src, immZExt2Shift:$imm),
965 (SRL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
966 def : MipsPat<(srl GPR32:$src, immZExt5:$imm),
967 (SRL_MM GPR32:$src, immZExt5:$imm)>;
969 def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),
970 (SW16_MM GPRMM16:$src, addrimm4lsl2:$addr)>;
971 def : MipsPat<(store GPR32:$src, addr:$addr),
972 (SW_MM GPR32:$src, addr:$addr)>;
974 def : MipsPat<(load addrimm4lsl2:$addr),
975 (LW16_MM addrimm4lsl2:$addr)>;
976 def : MipsPat<(load addr:$addr),
979 //===----------------------------------------------------------------------===//
980 // MicroMips instruction aliases
981 //===----------------------------------------------------------------------===//
983 class UncondBranchMMPseudo<string opstr> :
984 MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
985 !strconcat(opstr, "\t$offset")>;
987 def B_MM_Pseudo : UncondBranchMMPseudo<"b">, ISA_MICROMIPS;
989 def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>;
990 def : MipsInstAlias<"nop", (SLL_MM ZERO, ZERO, 0), 1>;
991 def : MipsInstAlias<"nop", (MOVE16_MM ZERO, ZERO), 1>;
994 let Predicates = [InMicroMips] in {
995 def : MipsInstAlias<"ei", (EI_MM ZERO), 1>, ISA_MIPS32R2;
996 def : MipsInstAlias<"teq $rs, $rt",
997 (TEQ_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
998 def : MipsInstAlias<"tge $rs, $rt",
999 (TGE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1000 def : MipsInstAlias<"tgeu $rs, $rt",
1001 (TGEU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1002 def : MipsInstAlias<"tlt $rs, $rt",
1003 (TLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1004 def : MipsInstAlias<"tltu $rs, $rt",
1005 (TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1006 def : MipsInstAlias<"tne $rs, $rt",
1007 (TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;