1 def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
3 def simm4 : Operand<i32>;
4 def simm7 : Operand<i32>;
6 def simm12 : Operand<i32> {
7 let DecoderMethod = "DecodeSimm12";
10 def uimm5_lsl2 : Operand<OtherVT> {
11 let EncoderMethod = "getUImm5Lsl2Encoding";
14 def simm9_addiusp : Operand<i32> {
15 let EncoderMethod = "getSImm9AddiuspValue";
18 def uimm3_shift : Operand<i32> {
19 let EncoderMethod = "getUImm3Mod8Encoding";
22 def simm3_lsa2 : Operand<i32> {
23 let EncoderMethod = "getSImm3Lsa2Value";
26 def immZExt2Shift : ImmLeaf<i32, [{return Imm >= 1 && Imm <= 8;}]>;
28 def immLi16 : ImmLeaf<i32, [{return Imm >= -1 && Imm <= 126;}]>;
30 def mem_mm_12 : Operand<i32> {
31 let PrintMethod = "printMemOperand";
32 let MIOperandInfo = (ops GPR32, simm12);
33 let EncoderMethod = "getMemEncodingMMImm12";
34 let ParserMatchClass = MipsMemAsmOperand;
35 let OperandType = "OPERAND_MEMORY";
38 def jmptarget_mm : Operand<OtherVT> {
39 let EncoderMethod = "getJumpTargetOpValueMM";
42 def calltarget_mm : Operand<iPTR> {
43 let EncoderMethod = "getJumpTargetOpValueMM";
46 def brtarget_mm : Operand<OtherVT> {
47 let EncoderMethod = "getBranchTargetOpValueMM";
48 let OperandType = "OPERAND_PCREL";
49 let DecoderMethod = "DecodeBranchTargetMM";
52 class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op,
54 InstSE<(outs), (ins RO:$rs, opnd:$offset),
55 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI> {
62 let canFoldAsLoad = 1 in
63 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
65 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
66 !strconcat(opstr, "\t$rt, $addr"),
67 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
69 let DecoderMethod = "DecodeMemMMImm12";
70 string Constraints = "$src = $rt";
73 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
75 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
76 !strconcat(opstr, "\t$rt, $addr"),
77 [(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> {
78 let DecoderMethod = "DecodeMemMMImm12";
81 class LLBaseMM<string opstr, RegisterOperand RO> :
82 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
83 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
84 let DecoderMethod = "DecodeMemMMImm12";
88 class SCBaseMM<string opstr, RegisterOperand RO> :
89 InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
90 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
91 let DecoderMethod = "DecodeMemMMImm12";
93 let Constraints = "$rt = $dst";
96 class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
97 InstrItinClass Itin = NoItinerary> :
98 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
99 !strconcat(opstr, "\t$rt, $addr"),
100 [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI> {
101 let DecoderMethod = "DecodeMemMMImm12";
102 let canFoldAsLoad = 1;
106 class ArithRMM16<string opstr, RegisterOperand RO, bit isComm = 0,
107 InstrItinClass Itin = NoItinerary,
108 SDPatternOperator OpNode = null_frag> :
109 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, RO:$rt),
110 !strconcat(opstr, "\t$rd, $rs, $rt"),
111 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
112 let isCommutable = isComm;
115 class LogicRMM16<string opstr, RegisterOperand RO,
116 InstrItinClass Itin = NoItinerary,
117 SDPatternOperator OpNode = null_frag> :
118 MicroMipsInst16<(outs RO:$dst), (ins RO:$rs, RO:$rt),
119 !strconcat(opstr, "\t$rt, $rs"),
120 [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
121 let isCommutable = 1;
122 let Constraints = "$rt = $dst";
125 class NotMM16<string opstr, RegisterOperand RO> :
126 MicroMipsInst16<(outs RO:$rt), (ins RO:$rs),
127 !strconcat(opstr, "\t$rt, $rs"),
128 [(set RO:$rt, (not RO:$rs))], NoItinerary, FrmR>;
130 class ShiftIMM16<string opstr, Operand ImmOpnd,
131 RegisterOperand RO, SDPatternOperator OpNode = null_frag,
132 SDPatternOperator PF = null_frag,
133 InstrItinClass Itin = NoItinerary> :
134 MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
135 !strconcat(opstr, "\t$rd, $rt, $shamt"),
136 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], Itin, FrmR>;
138 class AddImmUR2<string opstr, RegisterOperand RO> :
139 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, simm3_lsa2:$imm),
140 !strconcat(opstr, "\t$rd, $rs, $imm"),
141 [], NoItinerary, FrmR> {
142 let isCommutable = 1;
145 class AddImmUS5<string opstr, RegisterOperand RO> :
146 MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm),
147 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR> {
148 let Constraints = "$rd = $dst";
149 let isCommutable = 1;
152 class AddImmUSP<string opstr> :
153 MicroMipsInst16<(outs), (ins simm9_addiusp:$imm),
154 !strconcat(opstr, "\t$imm"), [], NoItinerary, FrmI>;
156 class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
157 MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
158 [], II_MFHI_MFLO, FrmR> {
160 let hasSideEffects = 0;
163 class MoveMM16<string opstr, RegisterOperand RO, bit isComm = 0,
164 InstrItinClass Itin = NoItinerary> :
165 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),
166 !strconcat(opstr, "\t$rd, $rs"), [], Itin, FrmR> {
167 let isCommutable = isComm;
168 let isReMaterializable = 1;
171 class LoadImmMM16<string opstr, Operand Od, RegisterOperand RO,
172 SDPatternOperator imm_type = null_frag> :
173 MicroMipsInst16<(outs RO:$rd), (ins Od:$imm),
174 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmI> {
175 let isReMaterializable = 1;
178 // 16-bit Jump and Link (Call)
179 class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
180 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
181 [(MipsJmpLink RO:$rs)], IIBranch, FrmR> {
183 let hasDelaySlot = 1;
188 class JumpRegMM16<string opstr, RegisterOperand RO> :
189 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
190 [], IIBranch, FrmR> {
191 let hasDelaySlot = 1;
193 let isIndirectBranch = 1;
196 // Base class for JRADDIUSP instruction.
197 class JumpRAddiuStackMM16 :
198 MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jraddiusp\t$imm",
199 [], IIBranch, FrmR> {
200 let isTerminator = 1;
202 let hasDelaySlot = 1;
204 let isIndirectBranch = 1;
207 // 16-bit Jump and Link (Call) - Short Delay Slot
208 class JumpLinkRegSMM16<string opstr, RegisterOperand RO> :
209 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
210 [], IIBranch, FrmR> {
212 let hasDelaySlot = 1;
216 // 16-bit Jump Register Compact - No delay slot
217 class JumpRegCMM16<string opstr, RegisterOperand RO> :
218 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
219 [], IIBranch, FrmR> {
220 let isTerminator = 1;
223 let isIndirectBranch = 1;
226 // MicroMIPS Jump and Link (Call) - Short Delay Slot
227 let isCall = 1, hasDelaySlot = 1, Defs = [RA] in {
228 class JumpLinkMM<string opstr, DAGOperand opnd> :
229 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
230 [], IIBranch, FrmJ, opstr> {
231 let DecoderMethod = "DecodeJumpTargetMM";
234 class JumpLinkRegMM<string opstr, RegisterOperand RO>:
235 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
238 class BranchCompareToZeroLinkMM<string opstr, DAGOperand opnd,
239 RegisterOperand RO> :
240 InstSE<(outs), (ins RO:$rs, opnd:$offset),
241 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
244 def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
246 def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
248 def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
250 def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
252 def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
254 def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>;
255 def SLL16_MM : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, shl,
256 immZExt2Shift, II_SLL>, SHIFT_FM_MM16<0>;
257 def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, srl,
258 immZExt2Shift, II_SRL>, SHIFT_FM_MM16<1>;
259 def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16;
260 def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16;
261 def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16;
262 def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
263 def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
264 def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
265 def LI16_MM : LoadImmMM16<"li16", simm7, GPRMM16Opnd, immLi16>,
266 LI_FM_MM16, IsAsCheapAsAMove;
267 def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>;
268 def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>;
269 def JRC16_MM : JumpRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>;
270 def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>;
271 def JR16_MM : JumpRegMM16<"jr16", GPR32Opnd>, JALR_FM_MM16<0x0c>;
273 class WaitMM<string opstr> :
274 InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],
275 NoItinerary, FrmOther, opstr>;
277 let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
278 /// Compact Branch Instructions
279 def BEQZC_MM : CompactBranchMM<"beqzc", brtarget_mm, seteq, GPR32Opnd>,
280 COMPACT_BRANCH_FM_MM<0x7>;
281 def BNEZC_MM : CompactBranchMM<"bnezc", brtarget_mm, setne, GPR32Opnd>,
282 COMPACT_BRANCH_FM_MM<0x5>;
284 /// Arithmetic Instructions (ALU Immediate)
285 def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>,
287 def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,
289 def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
291 def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
293 def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>,
295 def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd>,
297 def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd>,
299 def LUi_MM : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM_MM;
301 def LEA_ADDiu_MM : MMRel, EffectiveAddress<"addiu", GPR32Opnd>,
304 /// Arithmetic Instructions (3-Operand, R-Type)
305 def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd>, ADD_FM_MM<0, 0x150>;
306 def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd>, ADD_FM_MM<0, 0x1d0>;
307 def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;
308 def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;
309 def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;
310 def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
311 def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
313 def AND_MM : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
315 def OR_MM : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
317 def XOR_MM : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
319 def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
320 def MULT_MM : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
322 def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
324 def SDIV_MM : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
326 def UDIV_MM : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
329 /// Shift Instructions
330 def SLL_MM : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>,
332 def SRL_MM : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>,
334 def SRA_MM : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>,
336 def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV>,
338 def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV>,
340 def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>,
342 def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,
344 def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>,
347 /// Load and Store Instructions - aligned
348 let DecoderMethod = "DecodeMemMMImm16" in {
349 def LB_MM : Load<"lb", GPR32Opnd>, MMRel, LW_FM_MM<0x7>;
350 def LBu_MM : Load<"lbu", GPR32Opnd>, MMRel, LW_FM_MM<0x5>;
351 def LH_MM : Load<"lh", GPR32Opnd>, MMRel, LW_FM_MM<0xf>;
352 def LHu_MM : Load<"lhu", GPR32Opnd>, MMRel, LW_FM_MM<0xd>;
353 def LW_MM : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>;
354 def SB_MM : Store<"sb", GPR32Opnd>, MMRel, LW_FM_MM<0x6>;
355 def SH_MM : Store<"sh", GPR32Opnd>, MMRel, LW_FM_MM<0xe>;
356 def SW_MM : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
359 def LWU_MM : LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU>, LL_FM_MM<0xe>;
361 /// Load and Store Instructions - unaligned
362 def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>,
364 def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12>,
366 def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12>,
368 def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>,
372 def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
373 NoItinerary>, ADD_FM_MM<0, 0x58>;
374 def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
375 NoItinerary>, ADD_FM_MM<0, 0x18>;
376 def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT>,
377 CMov_F_I_FM_MM<0x25>;
378 def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF>,
381 /// Move to/from HI/LO
382 def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>,
384 def MTLO_MM : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>,
386 def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>,
388 def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>,
391 /// Multiply Add/Sub Instructions
392 def MADD_MM : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM_MM<0x32c>;
393 def MADDU_MM : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM_MM<0x36c>;
394 def MSUB_MM : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>;
395 def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>;
398 def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM_MM<0x16c>,
400 def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM_MM<0x12c>,
403 /// Sign Ext In Register Instructions.
404 def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
405 SEB_FM_MM<0x0ac>, ISA_MIPS32R2;
406 def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
407 SEB_FM_MM<0x0ec>, ISA_MIPS32R2;
409 /// Word Swap Bytes Within Halfwords
410 def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM_MM<0x1ec>,
413 def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>,
415 def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>,
418 /// Jump Instructions
419 let DecoderMethod = "DecodeJumpTargetMM" in {
420 def J_MM : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">,
422 def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>;
424 def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>;
425 def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>;
427 /// Jump Instructions - Short Delay Slot
428 def JALS_MM : JumpLinkMM<"jals", calltarget_mm>, J_FM_MM<0x1d>;
429 def JALRS_MM : JumpLinkRegMM<"jalrs", GPR32Opnd>, JALR_FM_MM<0x13c>;
431 /// Branch Instructions
432 def BEQ_MM : MMRel, CBranch<"beq", brtarget_mm, seteq, GPR32Opnd>,
434 def BNE_MM : MMRel, CBranch<"bne", brtarget_mm, setne, GPR32Opnd>,
436 def BGEZ_MM : MMRel, CBranchZero<"bgez", brtarget_mm, setge, GPR32Opnd>,
438 def BGTZ_MM : MMRel, CBranchZero<"bgtz", brtarget_mm, setgt, GPR32Opnd>,
440 def BLEZ_MM : MMRel, CBranchZero<"blez", brtarget_mm, setle, GPR32Opnd>,
442 def BLTZ_MM : MMRel, CBranchZero<"bltz", brtarget_mm, setlt, GPR32Opnd>,
444 def BGEZAL_MM : MMRel, BGEZAL_FT<"bgezal", brtarget_mm, GPR32Opnd>,
446 def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>,
449 /// Branch Instructions - Short Delay Slot
450 def BGEZALS_MM : BranchCompareToZeroLinkMM<"bgezals", brtarget_mm,
451 GPR32Opnd>, BGEZAL_FM_MM<0x13>;
452 def BLTZALS_MM : BranchCompareToZeroLinkMM<"bltzals", brtarget_mm,
453 GPR32Opnd>, BGEZAL_FM_MM<0x11>;
455 /// Control Instructions
456 def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM;
457 def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM;
458 def SYSCALL_MM : MMRel, SYS_FT<"syscall">, SYS_FM_MM;
459 def WAIT_MM : WaitMM<"wait">, WAIT_FM_MM;
460 def ERET_MM : MMRel, ER_FT<"eret">, ER_FM_MM<0x3cd>;
461 def DERET_MM : MMRel, ER_FT<"deret">, ER_FM_MM<0x38d>;
462 def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM_MM<0x15d>,
464 def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM_MM<0x11d>,
467 /// Trap Instructions
468 def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM_MM<0x0>;
469 def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM_MM<0x08>;
470 def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM_MM<0x10>;
471 def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM_MM<0x20>;
472 def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM_MM<0x28>;
473 def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM_MM<0x30>;
475 def TEQI_MM : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM_MM<0x0e>;
476 def TGEI_MM : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM_MM<0x09>;
477 def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM_MM<0x0b>;
478 def TLTI_MM : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM_MM<0x08>;
479 def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM_MM<0x0a>;
480 def TNEI_MM : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM_MM<0x0c>;
482 /// Load-linked, Store-conditional
483 def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>;
484 def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>;
486 def TLBP_MM : MMRel, TLB<"tlbp">, COP0_TLB_FM_MM<0x0d>;
487 def TLBR_MM : MMRel, TLB<"tlbr">, COP0_TLB_FM_MM<0x4d>;
488 def TLBWI_MM : MMRel, TLB<"tlbwi">, COP0_TLB_FM_MM<0x8d>;
489 def TLBWR_MM : MMRel, TLB<"tlbwr">, COP0_TLB_FM_MM<0xcd>;
492 //===----------------------------------------------------------------------===//
493 // MicroMips instruction aliases
494 //===----------------------------------------------------------------------===//
496 let Predicates = [InMicroMips] in {
497 def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>;