1 //=- MicroMips32r6InstrInfo.td - MicroMips r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes microMIPSr6 instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
16 // Instruction Encodings
18 //===----------------------------------------------------------------------===//
19 class ADD_MMR6_ENC : ARITH_FM_MMR6<"add", 0x110>;
20 class ADDIU_MMR6_ENC : ADDI_FM_MMR6<"addiu", 0xc>;
21 class ADDU_MMR6_ENC : ARITH_FM_MMR6<"addu", 0x150>;
22 class ADDIUPC_MMR6_ENC : PCREL19_FM_MMR6<0b00>;
23 class ALUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11111>;
24 class AND_MMR6_ENC : ARITH_FM_MMR6<"and", 0x250>;
25 class ANDI_MMR6_ENC : ADDI_FM_MMR6<"andi", 0x34>;
26 class AUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11110>;
27 class ALIGN_MMR6_ENC : POOL32A_ALIGN_FM_MMR6<0b011111>;
28 class AUI_MMR6_ENC : AUI_FM_MMR6;
29 class BALC_MMR6_ENC : BRANCH_OFF26_FM<0b101101>;
30 class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>;
31 class BC16_MMR6_ENC : BC16_FM_MM16R6;
32 class BEQZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x23>;
33 class BNEZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x2b>;
34 class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>;
35 class BRK_MMR6_ENC : BREAK_MMR6_ENC<"break">;
36 class BEQZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011101>;
37 class BNEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011111>;
38 class BGTZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b111000>;
39 class BLTZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<0b111000>;
40 class BGEZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<0b110000>;
41 class BLEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b110000>;
42 class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>;
43 class CLO_MMR6_ENC : POOL32A_2R_FM_MMR6<0b0100101100>;
44 class CLZ_MMR6_ENC : SPECIAL_2R_FM_MMR6<0b010000>;
45 class DIV_MMR6_ENC : ARITH_FM_MMR6<"div", 0x118>;
46 class DIVU_MMR6_ENC : ARITH_FM_MMR6<"divu", 0x198>;
47 class EHB_MMR6_ENC : BARRIER_MMR6_ENC<"ehb", 0x3>;
48 class EI_MMR6_ENC : EIDI_MMR6_ENC<"ei", 0x15d>;
49 class ERET_MMR6_ENC : ERET_FM_MMR6<"eret">;
50 class ERETNC_MMR6_ENC : ERETNC_FM_MMR6<"eretnc">;
51 class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>;
52 class JIC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b101000>;
53 class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>;
54 class LWPC_MMR6_ENC : PCREL19_FM_MMR6<0b01>;
55 class MOD_MMR6_ENC : ARITH_FM_MMR6<"mod", 0x158>;
56 class MODU_MMR6_ENC : ARITH_FM_MMR6<"modu", 0x1d8>;
57 class MUL_MMR6_ENC : ARITH_FM_MMR6<"mul", 0x18>;
58 class MUH_MMR6_ENC : ARITH_FM_MMR6<"muh", 0x58>;
59 class MULU_MMR6_ENC : ARITH_FM_MMR6<"mulu", 0x98>;
60 class MUHU_MMR6_ENC : ARITH_FM_MMR6<"muhu", 0xd8>;
61 class NOR_MMR6_ENC : ARITH_FM_MMR6<"nor", 0x2d0>;
62 class OR_MMR6_ENC : ARITH_FM_MMR6<"or", 0x290>;
63 class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>;
64 class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>;
65 class SEB_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seb", 0b0010101100>;
66 class SEH_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seh", 0b0011101100>;
67 class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>;
68 class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>;
69 class SLL_MMR6_ENC : SHIFT_MMR6_ENC<"sll", 0x00, 0b0>;
70 class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>;
71 class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>;
72 class SW_MMR6_ENC : SW32_FM_MMR6<"sw", 0x3e>;
73 class SWE_MMR6_ENC : POOL32C_SWE_FM_MMR6<"swe", 0x18, 0xa, 0x7>;
74 class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>;
75 class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>;
77 class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
78 RegisterOperand GPROpnd>
79 : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
80 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
81 dag OutOperandList = (outs);
82 string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
83 list<Register> Defs = [AT];
86 class BEQZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"beqzalc", brtarget_mm,
88 list<Register> Defs = [RA];
91 class BGEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgezalc", brtarget_mm,
93 list<Register> Defs = [RA];
96 class BGTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgtzalc", brtarget_mm,
98 list<Register> Defs = [RA];
101 class BLEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"blezalc", brtarget_mm,
103 list<Register> Defs = [RA];
106 class BLTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzalc", brtarget_mm,
108 list<Register> Defs = [RA];
111 class BNEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bnezalc", brtarget_mm,
113 list<Register> Defs = [RA];
116 /// Floating Point Instructions
117 class FADD_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.s", 0, 0b00110000>;
118 class FADD_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.d", 1, 0b00110000>;
119 class FSUB_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.s", 0, 0b01110000>;
120 class FSUB_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.d", 1, 0b01110000>;
121 class FMUL_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.s", 0, 0b10110000>;
122 class FMUL_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.d", 1, 0b10110000>;
123 class FDIV_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.s", 0, 0b11110000>;
124 class FDIV_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.d", 1, 0b11110000>;
125 class MADDF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.s", 0, 0b110111000>;
126 class MADDF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.d", 1, 0b110111000>;
127 class MSUBF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.s", 0, 0b111111000>;
128 class MSUBF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.d", 1, 0b111111000>;
129 class FMOV_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.s", 0, 0b0000001>;
130 class FMOV_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.d", 1, 0b0000001>;
131 class FNEG_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.s", 0, 0b0101101>;
132 class FNEG_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.d", 1, 0b0101101>;
133 class MAX_S_MMR6_ENC : POOL32F_MINMAX_FM<"max.s", 0, 0b000001011>;
134 class MAX_D_MMR6_ENC : POOL32F_MINMAX_FM<"max.d", 1, 0b000001011>;
135 class MAXA_S_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.s", 0, 0b000101011>;
136 class MAXA_D_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.d", 1, 0b000101011>;
137 class MIN_S_MMR6_ENC : POOL32F_MINMAX_FM<"min.s", 0, 0b000000011>;
138 class MIN_D_MMR6_ENC : POOL32F_MINMAX_FM<"min.d", 1, 0b000000011>;
139 class MINA_S_MMR6_ENC : POOL32F_MINMAX_FM<"mina.s", 0, 0b000100011>;
140 class MINA_D_MMR6_ENC : POOL32F_MINMAX_FM<"mina.d", 1, 0b000100011>;
142 class CVT_L_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.s", 0, 0b00000100>;
143 class CVT_L_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.d", 1, 0b00000100>;
144 class CVT_W_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.s", 0, 0b00100100>;
145 class CVT_W_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.d", 1, 0b00100100>;
146 class CVT_D_S_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.s", 0, 0b1001101>;
147 class CVT_D_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.w", 1, 0b1001101>;
148 class CVT_D_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.l", 2, 0b1001101>;
149 class CVT_S_D_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.d", 0, 0b1101101>;
150 class CVT_S_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.w", 1, 0b1101101>;
151 class CVT_S_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.l", 2, 0b1101101>;
153 //===----------------------------------------------------------------------===//
155 // Operand Definitions
157 //===----------------------------------------------------------------------===//
159 def MipsMemSimm9GPRAsmOperand : AsmOperandClass {
160 let Name = "MemOffsetSimm9GPR";
161 let SuperClasses = [MipsMemAsmOperand];
162 let RenderMethod = "addMemOperands";
163 let ParserMethod = "parseMemOperand";
164 let PredicateMethod = "isMemWithSimmOffsetGPR<9>";
167 def mem_simm9gpr : mem_generic {
168 let MIOperandInfo = (ops ptr_rc, simm9);
169 let EncoderMethod = "getMemEncoding";
170 let ParserMatchClass = MipsMemSimm9GPRAsmOperand;
173 //===----------------------------------------------------------------------===//
175 // Instruction Descriptions
177 //===----------------------------------------------------------------------===//
179 class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd>;
180 class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd>;
181 class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd>;
182 class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd>;
183 class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd>;
184 class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd>;
185 class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd>;
187 class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd>
188 : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
189 dag InOperandList = (ins opnd:$offset);
190 dag OutOperandList = (outs);
191 string AsmString = !strconcat(instr_asm, "\t$offset");
195 class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26> {
197 list<Register> Defs = [RA];
199 class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26>;
201 class BC16_MMR6_DESC : MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
202 !strconcat("bc16", "\t$offset"), [],
204 MMR6Arch<"bc16">, MicroMipsR6Inst16 {
206 let isTerminator = 1;
208 let hasDelaySlot = 0;
209 let AdditionalPredicates = [RelocPIC];
213 class BEQZC_BNEZC_MM16R6_DESC_BASE<string instr_asm>
214 : CBranchZeroMM<instr_asm, brtarget7_mm, GPRMM16Opnd>, MMR6Arch<instr_asm> {
216 let isTerminator = 1;
217 let hasDelaySlot = 0;
220 class BEQZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"beqzc16">;
221 class BNEZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"bnezc16">;
223 class SUB_MMR6_DESC : ArithLogicR<"sub", GPR32Opnd>;
224 class SUBU_MMR6_DESC : ArithLogicR<"subu", GPR32Opnd>;
226 class BITSWAP_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
227 : MMR6Arch<instr_asm> {
228 dag OutOperandList = (outs GPROpnd:$rd);
229 dag InOperandList = (ins GPROpnd:$rt);
230 string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
231 list<dag> Pattern = [];
234 class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>;
236 class BRK_MMR6_DESC : BRK_FT<"break">;
238 class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd,
239 RegisterOperand GPROpnd> : MMR6Arch<instr_asm> {
240 dag OutOperandList = (outs);
241 dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
242 string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
243 list<dag> Pattern = [];
244 string DecoderMethod = "DecodeCacheOpMM";
247 class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, GPR32Opnd>;
248 class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, GPR32Opnd>;
250 class CLO_CLZ_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
251 : MMR6Arch<instr_asm> {
252 dag OutOperandList = (outs GPROpnd:$rt);
253 dag InOperandList = (ins GPROpnd:$rs);
254 string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
257 class CLO_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clo", GPR32Opnd>;
258 class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clz", GPR32Opnd>;
260 class EHB_MMR6_DESC : Barrier<"ehb">;
261 class EI_MMR6_DESC : DEI_FT<"ei", GPR32Opnd>;
263 class ERET_MMR6_DESC : ER_FT<"eret">;
264 class ERETNC_MMR6_DESC : ER_FT<"eretnc">;
266 class JMP_MMR6_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
267 RegisterOperand GPROpnd>
269 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
270 string AsmString = !strconcat(opstr, "\t$rt, $offset");
271 list<dag> Pattern = [];
272 bit isTerminator = 1;
273 bit hasDelaySlot = 0;
276 class JIALC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
279 list<Register> Defs = [RA];
282 class JIC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
285 list<Register> Defs = [AT];
288 class ALIGN_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
289 Operand ImmOpnd> : MMR6Arch<instr_asm> {
290 dag OutOperandList = (outs GPROpnd:$rd);
291 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
292 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
293 list<dag> Pattern = [];
296 class ALIGN_MMR6_DESC : ALIGN_MMR6_DESC_BASE<"align", GPR32Opnd, uimm2>;
298 class AUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
299 : MMR6Arch<instr_asm> {
300 dag OutOperandList = (outs GPROpnd:$rt);
301 dag InOperandList = (ins GPROpnd:$rs, simm16:$imm);
302 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
303 list<dag> Pattern = [];
306 class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd>;
308 class SEB_MMR6_DESC : SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>;
309 class SEH_MMR6_DESC : SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>;
310 class ALUIPC_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
311 : MMR6Arch<instr_asm> {
312 dag OutOperandList = (outs GPROpnd:$rt);
313 dag InOperandList = (ins simm16:$imm);
314 string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
315 list<dag> Pattern = [];
318 class ALUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"aluipc", GPR32Opnd>;
319 class AUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"auipc", GPR32Opnd>;
321 class LSA_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
322 Operand ImmOpnd> : MMR6Arch<instr_asm> {
323 dag OutOperandList = (outs GPROpnd:$rd);
324 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
325 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $rd, $imm2");
326 list<dag> Pattern = [];
329 class LSA_MMR6_DESC : LSA_MMR6_DESC_BASE<"lsa", GPR32Opnd, uimm2>;
331 class PCREL_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
332 Operand ImmOpnd> : MMR6Arch<instr_asm> {
333 dag OutOperandList = (outs GPROpnd:$rt);
334 dag InOperandList = (ins ImmOpnd:$imm);
335 string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
336 list<dag> Pattern = [];
339 class ADDIUPC_MMR6_DESC : PCREL_MMR6_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>;
340 class LWPC_MMR6_DESC: PCREL_MMR6_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>;
342 class SELEQNE_Z_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
343 : MMR6Arch<instr_asm> {
344 dag OutOperandList = (outs GPROpnd:$rd);
345 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
346 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
347 list<dag> Pattern = [];
350 class SELEQZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"seleqz", GPR32Opnd>;
351 class SELNEZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"selnez", GPR32Opnd>;
352 class SLL_MMR6_DESC : shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>;
353 class DIV_MMR6_DESC : ArithLogicR<"div", GPR32Opnd>;
354 class DIVU_MMR6_DESC : ArithLogicR<"divu", GPR32Opnd>;
355 class MOD_MMR6_DESC : ArithLogicR<"mod", GPR32Opnd>;
356 class MODU_MMR6_DESC : ArithLogicR<"modu", GPR32Opnd>;
357 class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd>;
358 class ANDI_MMR6_DESC : ArithLogicI<"andi", simm16, GPR32Opnd>;
359 class NOR_MMR6_DESC : ArithLogicR<"nor", GPR32Opnd>;
360 class OR_MMR6_DESC : ArithLogicR<"or", GPR32Opnd>;
361 class ORI_MMR6_DESC : ArithLogicI<"ori", simm16, GPR32Opnd>;
362 class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd>;
363 class XORI_MMR6_DESC : ArithLogicI<"xori", simm16, GPR32Opnd>;
365 class SWE_MMR6_DESC_BASE<string opstr, DAGOperand RO, DAGOperand MO,
366 SDPatternOperator OpNode = null_frag,
367 InstrItinClass Itin = NoItinerary,
368 ComplexPattern Addr = addr> :
369 InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
370 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
371 let DecoderMethod = "DecodeMem";
374 class SW_MMR6_DESC : Store<"sw", GPR32Opnd>;
375 class SWE_MMR6_DESC : SWE_MMR6_DESC_BASE<"swe", GPR32Opnd, mem_simm9gpr>;
377 /// Floating Point Instructions
378 class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC,
379 InstrItinClass Itin, bit isComm,
380 SDPatternOperator OpNode = null_frag> : HARDFLOAT {
381 dag OutOperandList = (outs RC:$fd);
382 dag InOperandList = (ins RC:$ft, RC:$fs);
383 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
384 list<dag> Pattern = [(set RC:$fd, (OpNode RC:$fs, RC:$ft))];
385 InstrItinClass Itinerary = Itin;
386 bit isCommutable = isComm;
388 class FADD_S_MMR6_DESC
389 : FARITH_MMR6_DESC_BASE<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>;
390 class FADD_D_MMR6_DESC
391 : FARITH_MMR6_DESC_BASE<"add.d", AFGR64Opnd, II_ADD_D, 1, fadd>;
392 class FSUB_S_MMR6_DESC
393 : FARITH_MMR6_DESC_BASE<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>;
394 class FSUB_D_MMR6_DESC
395 : FARITH_MMR6_DESC_BASE<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>;
396 class FMUL_S_MMR6_DESC
397 : FARITH_MMR6_DESC_BASE<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>;
398 class FMUL_D_MMR6_DESC
399 : FARITH_MMR6_DESC_BASE<"mul.d", AFGR64Opnd, II_MUL_D, 1, fmul>;
400 class FDIV_S_MMR6_DESC
401 : FARITH_MMR6_DESC_BASE<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>;
402 class FDIV_D_MMR6_DESC
403 : FARITH_MMR6_DESC_BASE<"div.d", AFGR64Opnd, II_DIV_D, 0, fdiv>;
404 class MADDF_S_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>, HARDFLOAT;
405 class MADDF_D_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>, HARDFLOAT;
406 class MSUBF_S_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>, HARDFLOAT;
407 class MSUBF_D_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>, HARDFLOAT;
409 class FMOV_FNEG_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
410 RegisterOperand SrcRC, InstrItinClass Itin,
411 SDPatternOperator OpNode = null_frag>
412 : HARDFLOAT, NeverHasSideEffects {
413 dag OutOperandList = (outs DstRC:$ft);
414 dag InOperandList = (ins SrcRC:$fs);
415 string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
416 list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
417 InstrItinClass Itinerary = Itin;
420 class FMOV_S_MMR6_DESC
421 : FMOV_FNEG_MMR6_DESC_BASE<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>;
422 class FMOV_D_MMR6_DESC
423 : FMOV_FNEG_MMR6_DESC_BASE<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>;
424 class FNEG_S_MMR6_DESC
425 : FMOV_FNEG_MMR6_DESC_BASE<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>;
426 class FNEG_D_MMR6_DESC
427 : FMOV_FNEG_MMR6_DESC_BASE<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>;
429 class MAX_S_MMR6_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>, HARDFLOAT;
430 class MAX_D_MMR6_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>, HARDFLOAT;
431 class MIN_S_MMR6_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>, HARDFLOAT;
432 class MIN_D_MMR6_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>, HARDFLOAT;
434 class MAXA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>, HARDFLOAT;
435 class MAXA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>, HARDFLOAT;
436 class MINA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>, HARDFLOAT;
437 class MINA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>, HARDFLOAT;
439 class CVT_MMR6_DESC_BASE<
440 string instr_asm, RegisterOperand DstRC, RegisterOperand SrcRC,
441 InstrItinClass Itin, SDPatternOperator OpNode = null_frag>
442 : HARDFLOAT, NeverHasSideEffects {
443 dag OutOperandList = (outs DstRC:$ft);
444 dag InOperandList = (ins SrcRC:$fs);
445 string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
446 list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
447 InstrItinClass Itinerary = Itin;
451 class CVT_L_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.s", FGR64Opnd, FGR32Opnd,
453 class CVT_L_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.d", FGR64Opnd, FGR64Opnd,
455 class CVT_W_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.s", FGR32Opnd, FGR32Opnd,
457 class CVT_W_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.d", FGR32Opnd, AFGR64Opnd,
459 class CVT_D_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.s", FGR32Opnd, AFGR64Opnd,
461 class CVT_D_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.w", FGR32Opnd, AFGR64Opnd,
463 class CVT_D_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.l", FGR64Opnd, FGR64Opnd,
465 class CVT_S_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.d", AFGR64Opnd, FGR32Opnd,
467 class CVT_S_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.w", FGR32Opnd, FGR32Opnd,
469 class CVT_S_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.l", FGR64Opnd, FGR32Opnd,
472 multiclass CMP_CC_MMR6<bits<6> format, string Typestr,
473 RegisterOperand FGROpnd> {
474 def CMP_AF_#NAME : POOL32F_CMP_FM<
475 !strconcat("cmp.af.", Typestr), format, FIELD_CMP_COND_AF>,
476 CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
478 def CMP_UN_#NAME : POOL32F_CMP_FM<
479 !strconcat("cmp.un.", Typestr), format, FIELD_CMP_COND_UN>,
480 CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
482 def CMP_EQ_#NAME : POOL32F_CMP_FM<
483 !strconcat("cmp.eq.", Typestr), format, FIELD_CMP_COND_EQ>,
484 CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
486 def CMP_UEQ_#NAME : POOL32F_CMP_FM<
487 !strconcat("cmp.ueq.", Typestr), format, FIELD_CMP_COND_UEQ>,
488 CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
490 def CMP_LT_#NAME : POOL32F_CMP_FM<
491 !strconcat("cmp.lt.", Typestr), format, FIELD_CMP_COND_LT>,
492 CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
494 def CMP_ULT_#NAME : POOL32F_CMP_FM<
495 !strconcat("cmp.ult.", Typestr), format, FIELD_CMP_COND_ULT>,
496 CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
498 def CMP_LE_#NAME : POOL32F_CMP_FM<
499 !strconcat("cmp.le.", Typestr), format, FIELD_CMP_COND_LE>,
500 CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
502 def CMP_ULE_#NAME : POOL32F_CMP_FM<
503 !strconcat("cmp.ule.", Typestr), format, FIELD_CMP_COND_ULE>,
504 CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
506 def CMP_SAF_#NAME : POOL32F_CMP_FM<
507 !strconcat("cmp.saf.", Typestr), format, FIELD_CMP_COND_SAF>,
508 CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
510 def CMP_SUN_#NAME : POOL32F_CMP_FM<
511 !strconcat("cmp.sun.", Typestr), format, FIELD_CMP_COND_SUN>,
512 CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
514 def CMP_SEQ_#NAME : POOL32F_CMP_FM<
515 !strconcat("cmp.seq.", Typestr), format, FIELD_CMP_COND_SEQ>,
516 CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
518 def CMP_SUEQ_#NAME : POOL32F_CMP_FM<
519 !strconcat("cmp.sueq.", Typestr), format, FIELD_CMP_COND_SUEQ>,
520 CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
522 def CMP_SLT_#NAME : POOL32F_CMP_FM<
523 !strconcat("cmp.slt.", Typestr), format, FIELD_CMP_COND_SLT>,
524 CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
526 def CMP_SULT_#NAME : POOL32F_CMP_FM<
527 !strconcat("cmp.sult.", Typestr), format, FIELD_CMP_COND_SULT>,
528 CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
530 def CMP_SLE_#NAME : POOL32F_CMP_FM<
531 !strconcat("cmp.sle.", Typestr), format, FIELD_CMP_COND_SLE>,
532 CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
534 def CMP_SULE_#NAME : POOL32F_CMP_FM<
535 !strconcat("cmp.sule.", Typestr), format, FIELD_CMP_COND_SULE>,
536 CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
540 //===----------------------------------------------------------------------===//
542 // Instruction Definitions
544 //===----------------------------------------------------------------------===//
546 let DecoderNamespace = "MicroMipsR6" in {
547 def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;
548 def ADDIU_MMR6 : StdMMR6Rel, ADDIU_MMR6_DESC, ADDIU_MMR6_ENC, ISA_MICROMIPS32R6;
549 def ADDU_MMR6 : StdMMR6Rel, ADDU_MMR6_DESC, ADDU_MMR6_ENC, ISA_MICROMIPS32R6;
550 def ADDIUPC_MMR6 : R6MMR6Rel, ADDIUPC_MMR6_ENC, ADDIUPC_MMR6_DESC,
552 def ALUIPC_MMR6 : R6MMR6Rel, ALUIPC_MMR6_ENC, ALUIPC_MMR6_DESC,
554 def AND_MMR6 : StdMMR6Rel, AND_MMR6_DESC, AND_MMR6_ENC, ISA_MICROMIPS32R6;
555 def ANDI_MMR6 : StdMMR6Rel, ANDI_MMR6_DESC, ANDI_MMR6_ENC, ISA_MICROMIPS32R6;
556 def AUIPC_MMR6 : R6MMR6Rel, AUIPC_MMR6_ENC, AUIPC_MMR6_DESC, ISA_MICROMIPS32R6;
557 def ALIGN_MMR6 : R6MMR6Rel, ALIGN_MMR6_ENC, ALIGN_MMR6_DESC, ISA_MICROMIPS32R6;
558 def AUI_MMR6 : R6MMR6Rel, AUI_MMR6_ENC, AUI_MMR6_DESC, ISA_MICROMIPS32R6;
559 def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6;
560 def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6;
561 def BC16_MMR6 : StdMMR6Rel, BC16_MMR6_DESC, BC16_MMR6_ENC, ISA_MICROMIPS32R6;
562 def BEQZC16_MMR6 : StdMMR6Rel, BEQZC16_MMR6_DESC, BEQZC16_MMR6_ENC,
564 def BNEZC16_MMR6 : StdMMR6Rel, BNEZC16_MMR6_DESC, BNEZC16_MMR6_ENC,
566 def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC,
568 def BEQZALC_MMR6 : R6MMR6Rel, BEQZALC_MMR6_ENC, BEQZALC_MMR6_DESC,
570 def BGEZALC_MMR6 : R6MMR6Rel, BGEZALC_MMR6_ENC, BGEZALC_MMR6_DESC,
572 def BGTZALC_MMR6 : R6MMR6Rel, BGTZALC_MMR6_ENC, BGTZALC_MMR6_DESC,
574 def BLEZALC_MMR6 : R6MMR6Rel, BLEZALC_MMR6_ENC, BLEZALC_MMR6_DESC,
576 def BLTZALC_MMR6 : R6MMR6Rel, BLTZALC_MMR6_ENC, BLTZALC_MMR6_DESC,
578 def BNEZALC_MMR6 : R6MMR6Rel, BNEZALC_MMR6_ENC, BNEZALC_MMR6_DESC,
580 def BREAK_MMR6 : StdMMR6Rel, BRK_MMR6_DESC, BRK_MMR6_ENC, ISA_MICROMIPS32R6;
581 def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6;
582 def CLO_MMR6 : R6MMR6Rel, CLO_MMR6_ENC, CLO_MMR6_DESC, ISA_MICROMIPS32R6;
583 def CLZ_MMR6 : R6MMR6Rel, CLZ_MMR6_ENC, CLZ_MMR6_DESC, ISA_MICROMIPS32R6;
584 def DIV_MMR6 : R6MMR6Rel, DIV_MMR6_DESC, DIV_MMR6_ENC, ISA_MICROMIPS32R6;
585 def DIVU_MMR6 : R6MMR6Rel, DIVU_MMR6_DESC, DIVU_MMR6_ENC, ISA_MICROMIPS32R6;
586 def EHB_MMR6 : StdMMR6Rel, EHB_MMR6_DESC, EHB_MMR6_ENC, ISA_MICROMIPS32R6;
587 def EI_MMR6 : StdMMR6Rel, EI_MMR6_DESC, EI_MMR6_ENC, ISA_MICROMIPS32R6;
588 def ERET_MMR6 : R6MMR6Rel, ERET_MMR6_DESC, ERET_MMR6_ENC, ISA_MICROMIPS32R6;
589 def ERETNC_MMR6 : R6MMR6Rel, ERETNC_MMR6_DESC, ERETNC_MMR6_ENC,
591 def JIALC_MMR6 : R6MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPS32R6;
592 def JIC_MMR6 : R6MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPS32R6;
593 def LSA_MMR6 : R6MMR6Rel, LSA_MMR6_ENC, LSA_MMR6_DESC, ISA_MICROMIPS32R6;
594 def LWPC_MMR6 : R6MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPS32R6;
595 def MOD_MMR6 : R6MMR6Rel, MOD_MMR6_DESC, MOD_MMR6_ENC, ISA_MICROMIPS32R6;
596 def MODU_MMR6 : R6MMR6Rel, MODU_MMR6_DESC, MODU_MMR6_ENC, ISA_MICROMIPS32R6;
597 def MUL_MMR6 : R6MMR6Rel, MUL_MMR6_DESC, MUL_MMR6_ENC, ISA_MICROMIPS32R6;
598 def MUH_MMR6 : R6MMR6Rel, MUH_MMR6_DESC, MUH_MMR6_ENC, ISA_MICROMIPS32R6;
599 def MULU_MMR6 : R6MMR6Rel, MULU_MMR6_DESC, MULU_MMR6_ENC, ISA_MICROMIPS32R6;
600 def MUHU_MMR6 : R6MMR6Rel, MUHU_MMR6_DESC, MUHU_MMR6_ENC, ISA_MICROMIPS32R6;
601 def NOR_MMR6 : StdMMR6Rel, NOR_MMR6_DESC, NOR_MMR6_ENC, ISA_MICROMIPS32R6;
602 def OR_MMR6 : StdMMR6Rel, OR_MMR6_DESC, OR_MMR6_ENC, ISA_MICROMIPS32R6;
603 def ORI_MMR6 : StdMMR6Rel, ORI_MMR6_DESC, ORI_MMR6_ENC, ISA_MICROMIPS32R6;
604 def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6;
605 def SEB_MMR6 : StdMMR6Rel, SEB_MMR6_DESC, SEB_MMR6_ENC, ISA_MICROMIPS32R6;
606 def SEH_MMR6 : StdMMR6Rel, SEH_MMR6_DESC, SEH_MMR6_ENC, ISA_MICROMIPS32R6;
607 def SELEQZ_MMR6 : R6MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC,
609 def SELNEZ_MMR6 : R6MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC,
611 def SLL_MMR6 : StdMMR6Rel, SLL_MMR6_DESC, SLL_MMR6_ENC, ISA_MICROMIPS32R6;
612 def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6;
613 def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6;
614 def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
615 def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;
616 let DecoderMethod = "DecodeMemMMImm16" in {
617 def SW_MMR6 : StdMMR6Rel, SW_MMR6_DESC, SW_MMR6_ENC, ISA_MICROMIPS32R6;
619 let DecoderMethod = "DecodeMemMMImm9" in {
620 def SWE_MMR6 : StdMMR6Rel, SWE_MMR6_DESC, SWE_MMR6_ENC, ISA_MICROMIPS32R6;
622 /// Floating Point Instructions
623 def FADD_S_MMR6 : StdMMR6Rel, FADD_S_MMR6_ENC, FADD_S_MMR6_DESC,
625 def FADD_D_MMR6 : StdMMR6Rel, FADD_D_MMR6_ENC, FADD_D_MMR6_DESC,
627 def FSUB_S_MMR6 : StdMMR6Rel, FSUB_S_MMR6_ENC, FSUB_S_MMR6_DESC,
629 def FSUB_D_MMR6 : StdMMR6Rel, FSUB_D_MMR6_ENC, FSUB_D_MMR6_DESC,
631 def FMUL_S_MMR6 : StdMMR6Rel, FMUL_S_MMR6_ENC, FMUL_S_MMR6_DESC,
633 def FMUL_D_MMR6 : StdMMR6Rel, FMUL_D_MMR6_ENC, FMUL_D_MMR6_DESC,
635 def FDIV_S_MMR6 : StdMMR6Rel, FDIV_S_MMR6_ENC, FDIV_S_MMR6_DESC,
637 def FDIV_D_MMR6 : StdMMR6Rel, FDIV_D_MMR6_ENC, FDIV_D_MMR6_DESC,
639 def MADDF_S_MMR6 : R6MMR6Rel, MADDF_S_MMR6_ENC, MADDF_S_MMR6_DESC,
641 def MADDF_D_MMR6 : R6MMR6Rel, MADDF_D_MMR6_ENC, MADDF_D_MMR6_DESC,
643 def MSUBF_S_MMR6 : R6MMR6Rel, MSUBF_S_MMR6_ENC, MSUBF_S_MMR6_DESC,
645 def MSUBF_D_MMR6 : R6MMR6Rel, MSUBF_D_MMR6_ENC, MSUBF_D_MMR6_DESC,
647 def FMOV_S_MMR6 : StdMMR6Rel, FMOV_S_MMR6_ENC, FMOV_S_MMR6_DESC,
649 def FMOV_D_MMR6 : StdMMR6Rel, FMOV_D_MMR6_ENC, FMOV_D_MMR6_DESC,
651 def FNEG_S_MMR6 : StdMMR6Rel, FNEG_S_MMR6_ENC, FNEG_S_MMR6_DESC,
653 def FNEG_D_MMR6 : StdMMR6Rel, FNEG_D_MMR6_ENC, FNEG_D_MMR6_DESC,
655 def MAX_S_MMR6 : R6MMR6Rel, MAX_S_MMR6_ENC, MAX_S_MMR6_DESC, ISA_MICROMIPS32R6;
656 def MAX_D_MMR6 : R6MMR6Rel, MAX_D_MMR6_ENC, MAX_D_MMR6_DESC, ISA_MICROMIPS32R6;
657 def MIN_S_MMR6 : R6MMR6Rel, MIN_S_MMR6_ENC, MIN_S_MMR6_DESC, ISA_MICROMIPS32R6;
658 def MIN_D_MMR6 : R6MMR6Rel, MIN_D_MMR6_ENC, MIN_D_MMR6_DESC, ISA_MICROMIPS32R6;
659 def MAXA_S_MMR6 : R6MMR6Rel, MAXA_S_MMR6_ENC, MAXA_S_MMR6_DESC,
661 def MAXA_D_MMR6 : R6MMR6Rel, MAXA_D_MMR6_ENC, MAXA_D_MMR6_DESC,
663 def MINA_S_MMR6 : R6MMR6Rel, MINA_S_MMR6_ENC, MINA_S_MMR6_DESC,
665 def MINA_D_MMR6 : R6MMR6Rel, MINA_D_MMR6_ENC, MINA_D_MMR6_DESC,
667 def CVT_L_S_MMR6 : StdMMR6Rel, CVT_L_S_MMR6_ENC, CVT_L_S_MMR6_DESC,
669 def CVT_L_D_MMR6 : StdMMR6Rel, CVT_L_D_MMR6_ENC, CVT_L_D_MMR6_DESC,
671 def CVT_W_S_MMR6 : StdMMR6Rel, CVT_W_S_MMR6_ENC, CVT_W_S_MMR6_DESC,
673 def CVT_W_D_MMR6 : StdMMR6Rel, CVT_W_D_MMR6_ENC, CVT_W_D_MMR6_DESC,
675 def CVT_D_S_MMR6 : StdMMR6Rel, CVT_D_S_MMR6_ENC, CVT_D_S_MMR6_DESC,
677 def CVT_D_W_MMR6 : StdMMR6Rel, CVT_D_W_MMR6_ENC, CVT_D_W_MMR6_DESC,
679 def CVT_D_L_MMR6 : StdMMR6Rel, CVT_D_L_MMR6_ENC, CVT_D_L_MMR6_DESC,
681 def CVT_S_D_MMR6 : StdMMR6Rel, CVT_S_D_MMR6_ENC, CVT_S_D_MMR6_DESC,
683 def CVT_S_W_MMR6 : StdMMR6Rel, CVT_S_W_MMR6_ENC, CVT_S_W_MMR6_DESC,
685 def CVT_S_L_MMR6 : StdMMR6Rel, CVT_S_L_MMR6_ENC, CVT_S_L_MMR6_DESC,
687 defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd>;
688 defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd>;
691 //===----------------------------------------------------------------------===//
693 // MicroMips instruction aliases
695 //===----------------------------------------------------------------------===//
697 def : MipsInstAlias<"ei", (EI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
698 def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6;
699 def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
700 !strconcat("b", "\t$offset")>,