1 //=- MicroMips32r6InstrInfo.td - MicroMips r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes microMIPSr6 instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
16 // Instruction Encodings
18 //===----------------------------------------------------------------------===//
19 class ADD_MMR6_ENC : ARITH_FM_MMR6<"add", 0x110>;
20 class ADDIU_MMR6_ENC : ADDI_FM_MMR6<"addiu", 0xc>;
21 class ADDU_MMR6_ENC : ARITH_FM_MMR6<"addu", 0x150>;
22 class ADDIUPC_MMR6_ENC : PCREL19_FM_MMR6<0b00>;
23 class ALUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11111>;
24 class AND_MMR6_ENC : ARITH_FM_MMR6<"and", 0x250>;
25 class ANDI_MMR6_ENC : ADDI_FM_MMR6<"andi", 0x34>;
26 class AUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11110>;
27 class ALIGN_MMR6_ENC : POOL32A_ALIGN_FM_MMR6<0b011111>;
28 class AUI_MMR6_ENC : AUI_FM_MMR6;
29 class BALC_MMR6_ENC : BRANCH_OFF26_FM<0b101101>;
30 class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>;
31 class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>;
32 class BRK_MMR6_ENC : BREAK_MMR6_ENC<"break">;
33 class BEQZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011101>;
34 class BNEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011111>;
35 class BGTZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b111000>;
36 class BLTZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<0b111000>;
37 class BGEZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<0b110000>;
38 class BLEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b110000>;
39 class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>;
40 class CLO_MMR6_ENC : POOL32A_2R_FM_MMR6<0b0100101100>;
41 class CLZ_MMR6_ENC : SPECIAL_2R_FM_MMR6<0b010000>;
42 class DIV_MMR6_ENC : ARITH_FM_MMR6<"div", 0x118>;
43 class DIVU_MMR6_ENC : ARITH_FM_MMR6<"divu", 0x198>;
44 class EHB_MMR6_ENC : BARRIER_MMR6_ENC<"ehb", 0x3>;
45 class EI_MMR6_ENC : EIDI_MMR6_ENC<"ei", 0x15d>;
46 class ERET_MMR6_ENC : ERET_FM_MMR6<"eret">;
47 class ERETNC_MMR6_ENC : ERETNC_FM_MMR6<"eretnc">;
48 class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>;
49 class JIC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b101000>;
50 class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>;
51 class LWPC_MMR6_ENC : PCREL19_FM_MMR6<0b01>;
52 class MOD_MMR6_ENC : ARITH_FM_MMR6<"mod", 0x158>;
53 class MODU_MMR6_ENC : ARITH_FM_MMR6<"modu", 0x1d8>;
54 class MUL_MMR6_ENC : ARITH_FM_MMR6<"mul", 0x18>;
55 class MUH_MMR6_ENC : ARITH_FM_MMR6<"muh", 0x58>;
56 class MULU_MMR6_ENC : ARITH_FM_MMR6<"mulu", 0x98>;
57 class MUHU_MMR6_ENC : ARITH_FM_MMR6<"muhu", 0xd8>;
58 class NOR_MMR6_ENC : ARITH_FM_MMR6<"nor", 0x2d0>;
59 class OR_MMR6_ENC : ARITH_FM_MMR6<"or", 0x290>;
60 class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>;
61 class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>;
62 class SEB_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seb", 0b0010101100>;
63 class SEH_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seh", 0b0011101100>;
64 class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>;
65 class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>;
66 class SLL_MMR6_ENC : SHIFT_MMR6_ENC<"sll", 0x00, 0b0>;
67 class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>;
68 class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>;
69 class SW_MMR6_ENC : SW32_FM_MMR6<"sw", 0x3e>;
70 class SWE_MMR6_ENC : POOL32C_SWE_FM_MMR6<"swe", 0x18, 0xa, 0x7>;
71 class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>;
72 class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>;
74 class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
75 RegisterOperand GPROpnd>
76 : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
77 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
78 dag OutOperandList = (outs);
79 string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
80 list<Register> Defs = [AT];
83 class BEQZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"beqzalc", brtarget_mm,
85 list<Register> Defs = [RA];
88 class BGEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgezalc", brtarget_mm,
90 list<Register> Defs = [RA];
93 class BGTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgtzalc", brtarget_mm,
95 list<Register> Defs = [RA];
98 class BLEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"blezalc", brtarget_mm,
100 list<Register> Defs = [RA];
103 class BLTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzalc", brtarget_mm,
105 list<Register> Defs = [RA];
108 class BNEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bnezalc", brtarget_mm,
110 list<Register> Defs = [RA];
113 //===----------------------------------------------------------------------===//
115 // Operand Definitions
117 //===----------------------------------------------------------------------===//
119 def MipsMemSimm9GPRAsmOperand : AsmOperandClass {
120 let Name = "MemOffsetSimm9GPR";
121 let SuperClasses = [MipsMemAsmOperand];
122 let RenderMethod = "addMemOperands";
123 let ParserMethod = "parseMemOperand";
124 let PredicateMethod = "isMemWithSimmOffsetGPR<9>";
127 def mem_simm9gpr : mem_generic {
128 let MIOperandInfo = (ops ptr_rc, simm9);
129 let EncoderMethod = "getMemEncoding";
130 let ParserMatchClass = MipsMemSimm9GPRAsmOperand;
133 //===----------------------------------------------------------------------===//
135 // Instruction Descriptions
137 //===----------------------------------------------------------------------===//
139 class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd>;
140 class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd>;
141 class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd>;
142 class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd>;
143 class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd>;
144 class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd>;
145 class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd>;
147 class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd>
148 : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
149 dag InOperandList = (ins opnd:$offset);
150 dag OutOperandList = (outs);
151 string AsmString = !strconcat(instr_asm, "\t$offset");
155 class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26> {
157 list<Register> Defs = [RA];
159 class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26>;
160 class SUB_MMR6_DESC : ArithLogicR<"sub", GPR32Opnd>;
161 class SUBU_MMR6_DESC : ArithLogicR<"subu", GPR32Opnd>;
163 class BITSWAP_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
164 : MMR6Arch<instr_asm> {
165 dag OutOperandList = (outs GPROpnd:$rd);
166 dag InOperandList = (ins GPROpnd:$rt);
167 string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
168 list<dag> Pattern = [];
171 class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>;
173 class BRK_MMR6_DESC : BRK_FT<"break">;
175 class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd,
176 RegisterOperand GPROpnd> : MMR6Arch<instr_asm> {
177 dag OutOperandList = (outs);
178 dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
179 string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
180 list<dag> Pattern = [];
181 string DecoderMethod = "DecodeCacheOpMM";
184 class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, GPR32Opnd>;
185 class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, GPR32Opnd>;
187 class CLO_CLZ_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
188 : MMR6Arch<instr_asm> {
189 dag OutOperandList = (outs GPROpnd:$rt);
190 dag InOperandList = (ins GPROpnd:$rs);
191 string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
194 class CLO_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clo", GPR32Opnd>;
195 class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clz", GPR32Opnd>;
197 class EHB_MMR6_DESC : Barrier<"ehb">;
198 class EI_MMR6_DESC : DEI_FT<"ei", GPR32Opnd>;
200 class ERET_MMR6_DESC : ER_FT<"eret">;
201 class ERETNC_MMR6_DESC : ER_FT<"eretnc">;
203 class JMP_MMR6_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
204 RegisterOperand GPROpnd>
206 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
207 string AsmString = !strconcat(opstr, "\t$rt, $offset");
208 list<dag> Pattern = [];
209 bit isTerminator = 1;
210 bit hasDelaySlot = 0;
213 class JIALC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
216 list<Register> Defs = [RA];
219 class JIC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
222 list<Register> Defs = [AT];
225 class ALIGN_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
226 Operand ImmOpnd> : MMR6Arch<instr_asm> {
227 dag OutOperandList = (outs GPROpnd:$rd);
228 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
229 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
230 list<dag> Pattern = [];
233 class ALIGN_MMR6_DESC : ALIGN_MMR6_DESC_BASE<"align", GPR32Opnd, uimm2>;
235 class AUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
236 : MMR6Arch<instr_asm> {
237 dag OutOperandList = (outs GPROpnd:$rt);
238 dag InOperandList = (ins GPROpnd:$rs, simm16:$imm);
239 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
240 list<dag> Pattern = [];
243 class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd>;
245 class SEB_MMR6_DESC : SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>;
246 class SEH_MMR6_DESC : SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>;
247 class ALUIPC_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
248 : MMR6Arch<instr_asm> {
249 dag OutOperandList = (outs GPROpnd:$rt);
250 dag InOperandList = (ins simm16:$imm);
251 string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
252 list<dag> Pattern = [];
255 class ALUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"aluipc", GPR32Opnd>;
256 class AUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"auipc", GPR32Opnd>;
258 class LSA_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
259 Operand ImmOpnd> : MMR6Arch<instr_asm> {
260 dag OutOperandList = (outs GPROpnd:$rd);
261 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
262 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $rd, $imm2");
263 list<dag> Pattern = [];
266 class LSA_MMR6_DESC : LSA_MMR6_DESC_BASE<"lsa", GPR32Opnd, uimm2>;
268 class PCREL_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
269 Operand ImmOpnd> : MMR6Arch<instr_asm> {
270 dag OutOperandList = (outs GPROpnd:$rt);
271 dag InOperandList = (ins ImmOpnd:$imm);
272 string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
273 list<dag> Pattern = [];
276 class ADDIUPC_MMR6_DESC : PCREL_MMR6_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>;
277 class LWPC_MMR6_DESC: PCREL_MMR6_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>;
279 class SELEQNE_Z_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
280 : MMR6Arch<instr_asm> {
281 dag OutOperandList = (outs GPROpnd:$rd);
282 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
283 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
284 list<dag> Pattern = [];
287 class SELEQZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"seleqz", GPR32Opnd>;
288 class SELNEZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"selnez", GPR32Opnd>;
289 class SLL_MMR6_DESC : shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>;
290 class DIV_MMR6_DESC : ArithLogicR<"div", GPR32Opnd>;
291 class DIVU_MMR6_DESC : ArithLogicR<"divu", GPR32Opnd>;
292 class MOD_MMR6_DESC : ArithLogicR<"mod", GPR32Opnd>;
293 class MODU_MMR6_DESC : ArithLogicR<"modu", GPR32Opnd>;
294 class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd>;
295 class ANDI_MMR6_DESC : ArithLogicI<"andi", simm16, GPR32Opnd>;
296 class NOR_MMR6_DESC : ArithLogicR<"nor", GPR32Opnd>;
297 class OR_MMR6_DESC : ArithLogicR<"or", GPR32Opnd>;
298 class ORI_MMR6_DESC : ArithLogicI<"ori", simm16, GPR32Opnd>;
299 class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd>;
300 class XORI_MMR6_DESC : ArithLogicI<"xori", simm16, GPR32Opnd>;
302 class SWE_MMR6_DESC_BASE<string opstr, DAGOperand RO, DAGOperand MO,
303 SDPatternOperator OpNode = null_frag,
304 InstrItinClass Itin = NoItinerary,
305 ComplexPattern Addr = addr> :
306 InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
307 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
308 let DecoderMethod = "DecodeMem";
311 class SW_MMR6_DESC : Store<"sw", GPR32Opnd>;
312 class SWE_MMR6_DESC : SWE_MMR6_DESC_BASE<"swe", GPR32Opnd, mem_simm9gpr>;
314 //===----------------------------------------------------------------------===//
316 // Instruction Definitions
318 //===----------------------------------------------------------------------===//
320 let DecoderNamespace = "MicroMipsR6" in {
321 def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;
322 def ADDIU_MMR6 : StdMMR6Rel, ADDIU_MMR6_DESC, ADDIU_MMR6_ENC, ISA_MICROMIPS32R6;
323 def ADDU_MMR6 : StdMMR6Rel, ADDU_MMR6_DESC, ADDU_MMR6_ENC, ISA_MICROMIPS32R6;
324 def ADDIUPC_MMR6 : R6MMR6Rel, ADDIUPC_MMR6_ENC, ADDIUPC_MMR6_DESC,
326 def ALUIPC_MMR6 : R6MMR6Rel, ALUIPC_MMR6_ENC, ALUIPC_MMR6_DESC,
328 def AND_MMR6 : StdMMR6Rel, AND_MMR6_DESC, AND_MMR6_ENC, ISA_MICROMIPS32R6;
329 def ANDI_MMR6 : StdMMR6Rel, ANDI_MMR6_DESC, ANDI_MMR6_ENC, ISA_MICROMIPS32R6;
330 def AUIPC_MMR6 : R6MMR6Rel, AUIPC_MMR6_ENC, AUIPC_MMR6_DESC, ISA_MICROMIPS32R6;
331 def ALIGN_MMR6 : R6MMR6Rel, ALIGN_MMR6_ENC, ALIGN_MMR6_DESC, ISA_MICROMIPS32R6;
332 def AUI_MMR6 : R6MMR6Rel, AUI_MMR6_ENC, AUI_MMR6_DESC, ISA_MICROMIPS32R6;
333 def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6;
334 def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6;
335 def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC,
337 def BEQZALC_MMR6 : R6MMR6Rel, BEQZALC_MMR6_ENC, BEQZALC_MMR6_DESC,
339 def BGEZALC_MMR6 : R6MMR6Rel, BGEZALC_MMR6_ENC, BGEZALC_MMR6_DESC,
341 def BGTZALC_MMR6 : R6MMR6Rel, BGTZALC_MMR6_ENC, BGTZALC_MMR6_DESC,
343 def BLEZALC_MMR6 : R6MMR6Rel, BLEZALC_MMR6_ENC, BLEZALC_MMR6_DESC,
345 def BLTZALC_MMR6 : R6MMR6Rel, BLTZALC_MMR6_ENC, BLTZALC_MMR6_DESC,
347 def BNEZALC_MMR6 : R6MMR6Rel, BNEZALC_MMR6_ENC, BNEZALC_MMR6_DESC,
349 def BREAK_MMR6 : StdMMR6Rel, BRK_MMR6_DESC, BRK_MMR6_ENC, ISA_MICROMIPS32R6;
350 def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6;
351 def CLO_MMR6 : R6MMR6Rel, CLO_MMR6_ENC, CLO_MMR6_DESC, ISA_MICROMIPS32R6;
352 def CLZ_MMR6 : R6MMR6Rel, CLZ_MMR6_ENC, CLZ_MMR6_DESC, ISA_MICROMIPS32R6;
353 def DIV_MMR6 : R6MMR6Rel, DIV_MMR6_DESC, DIV_MMR6_ENC, ISA_MICROMIPS32R6;
354 def DIVU_MMR6 : R6MMR6Rel, DIVU_MMR6_DESC, DIVU_MMR6_ENC, ISA_MICROMIPS32R6;
355 def EHB_MMR6 : StdMMR6Rel, EHB_MMR6_DESC, EHB_MMR6_ENC, ISA_MICROMIPS32R6;
356 def EI_MMR6 : StdMMR6Rel, EI_MMR6_DESC, EI_MMR6_ENC, ISA_MICROMIPS32R6;
357 def ERET_MMR6 : R6MMR6Rel, ERET_MMR6_DESC, ERET_MMR6_ENC, ISA_MICROMIPS32R6;
358 def ERETNC_MMR6 : R6MMR6Rel, ERETNC_MMR6_DESC, ERETNC_MMR6_ENC,
360 def JIALC_MMR6 : R6MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPS32R6;
361 def JIC_MMR6 : R6MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPS32R6;
362 def LSA_MMR6 : R6MMR6Rel, LSA_MMR6_ENC, LSA_MMR6_DESC, ISA_MICROMIPS32R6;
363 def LWPC_MMR6 : R6MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPS32R6;
364 def MOD_MMR6 : R6MMR6Rel, MOD_MMR6_DESC, MOD_MMR6_ENC, ISA_MICROMIPS32R6;
365 def MODU_MMR6 : R6MMR6Rel, MODU_MMR6_DESC, MODU_MMR6_ENC, ISA_MICROMIPS32R6;
366 def MUL_MMR6 : R6MMR6Rel, MUL_MMR6_DESC, MUL_MMR6_ENC, ISA_MICROMIPS32R6;
367 def MUH_MMR6 : R6MMR6Rel, MUH_MMR6_DESC, MUH_MMR6_ENC, ISA_MICROMIPS32R6;
368 def MULU_MMR6 : R6MMR6Rel, MULU_MMR6_DESC, MULU_MMR6_ENC, ISA_MICROMIPS32R6;
369 def MUHU_MMR6 : R6MMR6Rel, MUHU_MMR6_DESC, MUHU_MMR6_ENC, ISA_MICROMIPS32R6;
370 def NOR_MMR6 : StdMMR6Rel, NOR_MMR6_DESC, NOR_MMR6_ENC, ISA_MICROMIPS32R6;
371 def OR_MMR6 : StdMMR6Rel, OR_MMR6_DESC, OR_MMR6_ENC, ISA_MICROMIPS32R6;
372 def ORI_MMR6 : StdMMR6Rel, ORI_MMR6_DESC, ORI_MMR6_ENC, ISA_MICROMIPS32R6;
373 def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6;
374 def SEB_MMR6 : StdMMR6Rel, SEB_MMR6_DESC, SEB_MMR6_ENC, ISA_MICROMIPS32R6;
375 def SEH_MMR6 : StdMMR6Rel, SEH_MMR6_DESC, SEH_MMR6_ENC, ISA_MICROMIPS32R6;
376 def SELEQZ_MMR6 : R6MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC,
378 def SELNEZ_MMR6 : R6MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC,
380 def SLL_MMR6 : StdMMR6Rel, SLL_MMR6_DESC, SLL_MMR6_ENC, ISA_MICROMIPS32R6;
381 def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6;
382 def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6;
383 def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
384 def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;
385 let DecoderMethod = "DecodeMemMMImm16" in {
386 def SW_MMR6 : StdMMR6Rel, SW_MMR6_DESC, SW_MMR6_ENC, ISA_MICROMIPS32R6;
388 let DecoderMethod = "DecodeMemMMImm9" in {
389 def SWE_MMR6 : StdMMR6Rel, SWE_MMR6_DESC, SWE_MMR6_ENC, ISA_MICROMIPS32R6;
393 //===----------------------------------------------------------------------===//
395 // MicroMips instruction aliases
397 //===----------------------------------------------------------------------===//
399 def : MipsInstAlias<"ei", (EI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
400 def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6;