1 //=- MicroMips32r6InstrFormats.td - Mips32r6 Instruction Formats -*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes microMIPS32r6 instruction formats.
12 //===----------------------------------------------------------------------===//
14 class MMR6Arch<string opstr> {
15 string Arch = "micromipsr6";
16 string BaseOpcode = opstr;
19 // Class used for microMIPS32r6 and microMIPS64r6 instructions.
20 class MicroMipsR6Inst16 : PredicateControl {
21 string DecoderNamespace = "MicroMipsR6";
22 let InsnPredicates = [HasMicroMips32r6];
25 class BC16_FM_MM16R6 {
30 let Inst{15-10} = 0x33;
31 let Inst{9-0} = offset;
34 class BEQZC_BNEZC_FM_MM16R6<bits<6> op> : MicroMipsR6Inst16 {
42 let Inst{6-0} = offset;
45 class POOL32A_BITSWAP_FM_MMR6<bits<6> funct> : MipsR6Inst {
51 let Inst{31-26} = 0b000000;
54 let Inst{15-12} = 0b0000;
55 let Inst{11-6} = funct;
56 let Inst{5-0} = 0b111100;
59 class CACHE_PREF_FM_MMR6<bits<6> opgroup, bits<4> funct> : MipsR6Inst {
65 let Inst{31-26} = opgroup;
66 let Inst{25-21} = hint;
67 let Inst{20-16} = addr{20-16};
68 let Inst{15-12} = funct;
69 let Inst{11-0} = addr{11-0};
72 class ARITH_FM_MMR6<string instr_asm, bits<10> funct> : MMR6Arch<instr_asm> {
84 let Inst{9-0} = funct;
87 class ADDI_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> {
97 let Inst{15-0} = imm16;
100 class SIGN_EXTEND_FM_MMR6<string instr_asm, bits<10> funct>
101 : MMR6Arch<instr_asm> {
107 let Inst{31-26} = 0b000000;
108 let Inst{25-21} = rd;
109 let Inst{20-16} = rt;
110 let Inst{15-6} = funct;
111 let Inst{5-0} = 0b111100;
114 class PCREL19_FM_MMR6<bits<2> funct> : MipsR6Inst {
120 let Inst{31-26} = 0b011110;
121 let Inst{25-21} = rt;
122 let Inst{20-19} = funct;
123 let Inst{18-0} = imm;
126 class PCREL16_FM_MMR6<bits<5> funct> : MipsR6Inst {
132 let Inst{31-26} = 0b011110;
133 let Inst{25-21} = rt;
134 let Inst{20-16} = funct;
135 let Inst{15-0} = imm;
138 class POOL32A_FM_MMR6<bits<10> funct> : MipsR6Inst {
145 let Inst{31-26} = 0b000000;
146 let Inst{25-21} = rt;
147 let Inst{20-16} = rs;
148 let Inst{15-11} = rd;
150 let Inst{9-0} = funct;
153 class POOL32A_2R_FM_MMR6<bits<10> funct> : MipsR6Inst {
159 let Inst{31-26} = 0b000000;
160 let Inst{25-21} = rt;
161 let Inst{20-16} = rs;
162 let Inst{15-6} = funct;
163 let Inst{5-0} = 0b111100;
166 class SPECIAL_2R_FM_MMR6<bits<6> funct> : MipsR6Inst {
172 let Inst{31-26} = 0b000000;
173 let Inst{25-21} = rs;
174 let Inst{20-16} = 0b00000;
175 let Inst{15-11} = rt;
176 let Inst{10-6} = 0b00001;
177 let Inst{5-0} = funct;
180 class POOL32A_ALIGN_FM_MMR6<bits<6> funct> : MipsR6Inst {
188 let Inst{31-26} = 0b000000;
189 let Inst{25-21} = rs;
190 let Inst{20-16} = rt;
191 let Inst{15-11} = rd;
193 let Inst{8-6} = 0b000;
194 let Inst{5-0} = funct;
197 class AUI_FM_MMR6 : MipsR6Inst {
204 let Inst{31-26} = 0b000100;
205 let Inst{25-21} = rt;
206 let Inst{20-16} = rs;
207 let Inst{15-0} = imm;
210 class POOL32A_LSA_FM<bits<6> funct> : MipsR6Inst {
218 let Inst{31-26} = 0b000000;
219 let Inst{25-21} = rt;
220 let Inst{20-16} = rs;
221 let Inst{15-11} = rd;
222 let Inst{10-9} = imm2;
223 let Inst{8-6} = 0b000;
224 let Inst{5-0} = funct;
227 class SB32_SH32_STORE_FM_MMR6<bits<6> op> {
230 bits<5> base = addr{20-16};
231 bits<16> offset = addr{15-0};
235 let Inst{31-26} = op;
236 let Inst{25-21} = rt;
237 let Inst{20-16} = base;
238 let Inst{15-0} = offset;
241 class POOL32C_STORE_EVA_FM_MMR6<bits<3> funct> {
244 bits<5> base = addr{20-16};
245 bits<9> offset = addr{8-0};
249 let Inst{31-26} = 0b011000;
250 let Inst{25-21} = rt;
251 let Inst{20-16} = base;
252 let Inst{15-12} = 0b1010;
253 let Inst{11-9} = funct;
254 let Inst{8-0} = offset;
257 class LOAD_WORD_EVA_FM_MMR6<bits<3> funct> {
260 bits<5> base = addr{20-16};
261 bits<9> offset = addr{8-0};
265 let Inst{31-26} = 0b011000;
266 let Inst{25-21} = rt;
267 let Inst{20-16} = base;
268 let Inst{15-12} = 0b0110;
269 let Inst{11-9} = funct;
270 let Inst{8-0} = offset;
273 class LOAD_WORD_FM_MMR6 {
276 bits<5> base = addr{20-16};
277 bits<16> offset = addr{15-0};
281 let Inst{31-26} = 0b111111;
282 let Inst{25-21} = rt;
283 let Inst{20-16} = base;
284 let Inst{15-0} = offset;
287 class LOAD_UPPER_IMM_FM_MMR6 {
293 let Inst{31-26} = 0b000100;
294 let Inst{25-21} = rt;
296 let Inst{15-0} = imm16;
299 class CMP_BRANCH_1R_RT_OFF16_FM_MMR6<bits<6> funct> : MipsR6Inst {
305 let Inst{31-26} = funct;
306 let Inst{25-21} = rt;
307 let Inst{20-16} = 0b00000;
308 let Inst{15-0} = offset;
311 class CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<bits<6> funct> : MipsR6Inst {
317 let Inst{31-26} = funct;
318 let Inst{25-21} = rt;
319 let Inst{20-16} = rt;
320 let Inst{15-0} = offset;
323 class ERET_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm> {
326 let Inst{31-26} = 0x00;
327 let Inst{25-16} = 0x00;
328 let Inst{15-6} = 0x3cd;
329 let Inst{5-0} = 0x3c;
332 class ERETNC_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm> {
335 let Inst{31-26} = 0x00;
336 let Inst{25-17} = 0x00;
337 let Inst{16-16} = 0x01;
338 let Inst{15-6} = 0x3cd;
339 let Inst{5-0} = 0x3c;
342 class BREAK_MMR6_ENC<string instr_asm> : MMR6Arch<instr_asm> {
346 let Inst{31-26} = 0x0;
347 let Inst{25-16} = code_1;
348 let Inst{15-6} = code_2;
349 let Inst{5-0} = 0x07;
352 class BARRIER_MMR6_ENC<string instr_asm, bits<5> op> : MMR6Arch<instr_asm> {
355 let Inst{31-26} = 0x0;
356 let Inst{25-21} = 0x0;
357 let Inst{20-16} = 0x0;
358 let Inst{15-11} = op;
359 let Inst{10-6} = 0x0;
363 class EIDI_MMR6_ENC<string instr_asm, bits<10> funct> : MMR6Arch<instr_asm> {
365 bits<5> rt; // Actually rs but we're sharing code with the standard encodings which call it rt
367 let Inst{31-26} = 0x00;
368 let Inst{25-21} = 0x00;
369 let Inst{20-16} = rt;
370 let Inst{15-6} = funct;
371 let Inst{5-0} = 0x3c;
374 class SHIFT_MMR6_ENC<string instr_asm, bits<10> funct, bit rotate> : MMR6Arch<instr_asm> {
382 let Inst{25-21} = rd;
383 let Inst{20-16} = rt;
384 let Inst{15-11} = shamt;
385 let Inst{10} = rotate;
386 let Inst{9-0} = funct;
389 class SW32_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> {
395 let Inst{31-26} = op;
396 let Inst{25-21} = rt;
397 let Inst{20-16} = addr{20-16};
398 let Inst{15-0} = addr{15-0};
401 class POOL32C_SWE_FM_MMR6<string instr_asm, bits<6> op, bits<4> fmt,
402 bits<3> funct> : MMR6Arch<instr_asm> {
405 bits<5> base = addr{20-16};
406 bits<9> offset = addr{8-0};
410 let Inst{31-26} = op;
411 let Inst{25-21} = rt;
412 let Inst{20-16} = base;
413 let Inst{15-12} = fmt;
414 let Inst{11-9} = funct;
415 let Inst{8-0} = offset;
418 class POOL32F_ARITH_FM_MMR6<string instr_asm, bits<2> fmt, bits<8> funct>
419 : MMR6Arch<instr_asm>, MipsR6Inst {
426 let Inst{31-26} = 0b010101;
427 let Inst{25-21} = ft;
428 let Inst{20-16} = fs;
429 let Inst{15-11} = fd;
432 let Inst{7-0} = funct;
435 class POOL32F_ARITHF_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct>
436 : MMR6Arch<instr_asm>, MipsR6Inst {
443 let Inst{31-26} = 0b010101;
444 let Inst{25-21} = ft;
445 let Inst{20-16} = fs;
446 let Inst{15-11} = fd;
447 let Inst{10-9} = fmt;
448 let Inst{8-0} = funct;
451 class POOL32F_MOV_NEG_FM_MMR6<string instr_asm, bits<2> fmt, bits<7> funct>
452 : MMR6Arch<instr_asm>, MipsR6Inst {
458 let Inst{31-26} = 0b010101;
459 let Inst{25-21} = ft;
460 let Inst{20-16} = fs;
462 let Inst{14-13} = fmt;
463 let Inst{12-6} = funct;
464 let Inst{5-0} = 0b111011;
467 class POOL32F_MINMAX_FM<string instr_asm, bits<2> fmt, bits<9> funct>
468 : MMR6Arch<instr_asm>, MipsR6Inst {
475 let Inst{31-26} = 0b010101;
476 let Inst{25-21} = ft;
477 let Inst{20-16} = fs;
478 let Inst{15-11} = fd;
479 let Inst{10-9} = fmt;
480 let Inst{8-0} = funct;
483 class POOL32F_CMP_FM<string instr_asm, bits<6> format, FIELD_CMP_COND Cond>
484 : MMR6Arch<instr_asm>, MipsR6Inst {
491 let Inst{31-26} = 0b010101;
492 let Inst{25-21} = ft;
493 let Inst{20-16} = fs;
494 let Inst{15-11} = fd;
495 let Inst{10-6} = Cond.Value;
496 let Inst{5-0} = format;
499 class POOL32F_CVT_LW_FM<string instr_asm, bit fmt, bits<8> funct>
500 : MMR6Arch<instr_asm>, MipsR6Inst {
505 let Inst{31-26} = 0b010101;
506 let Inst{25-21} = ft;
507 let Inst{20-16} = fs;
510 let Inst{13-6} = funct;
511 let Inst{5-0} = 0b111011;
514 class POOL32F_CVT_DS_FM<string instr_asm, bits<2> fmt, bits<7> funct>
515 : MMR6Arch<instr_asm>, MipsR6Inst {
520 let Inst{31-26} = 0b010101;
521 let Inst{25-21} = ft;
522 let Inst{20-16} = fs;
524 let Inst{14-13} = fmt;
525 let Inst{12-6} = funct;
526 let Inst{5-0} = 0b111011;
529 class POOL32F_ABS_FM_MMR6<string instr_asm, bits<2> fmt, bits<7> funct>
530 : MMR6Arch<instr_asm>, MipsR6Inst {
536 let Inst{31-26} = 0b010101;
537 let Inst{25-21} = ft;
538 let Inst{20-16} = fs;
540 let Inst{14-13} = fmt;
541 let Inst{12-6} = funct;
542 let Inst{5-0} = 0b111011;
545 class POOL32F_MATH_FM_MMR6<string instr_asm, bits<1> fmt, bits<8> funct>
546 : MMR6Arch<instr_asm>, MipsR6Inst {
552 let Inst{31-26} = 0b010101;
553 let Inst{25-21} = ft;
554 let Inst{20-16} = fs;
557 let Inst{13-6} = funct;
558 let Inst{5-0} = 0b111011;
561 class POOL16A_ADDU16_FM_MMR6 : MicroMipsR6Inst16 {
568 let Inst{15-10} = 0b000001;
575 class POOL16C_AND16_FM_MMR6 : MicroMipsR6Inst16 {
581 let Inst{15-10} = 0b010001;
584 let Inst{3-0} = 0b0001;
587 class POOL16C_NOT16_FM_MMR6 : MicroMipsR6Inst16 {
593 let Inst{15-10} = 0x11;
596 let Inst{3-0} = 0b0000;
599 class POOL16C_OR16_FM_MMR6 : MicroMipsR6Inst16 {
605 let Inst{15-10} = 0b010001;
608 let Inst{3-0} = 0b1001;