1 //=- MicroMips32r6InstrFormats.td - Mips32r6 Instruction Formats -*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes microMIPS32r6 instruction formats.
12 //===----------------------------------------------------------------------===//
14 class MMR6Arch<string opstr> {
15 string Arch = "micromipsr6";
16 string BaseOpcode = opstr;
19 // Class used for microMIPS32r6 and microMIPS64r6 instructions.
20 class MicroMipsR6Inst16 : PredicateControl {
21 string DecoderNamespace = "MicroMipsR6";
22 let InsnPredicates = [HasMicroMips32r6];
25 class BC16_FM_MM16R6 {
30 let Inst{15-10} = 0x33;
31 let Inst{9-0} = offset;
34 class BEQZC_BNEZC_FM_MM16R6<bits<6> op> : MicroMipsR6Inst16 {
42 let Inst{6-0} = offset;
45 class POOL32A_BITSWAP_FM_MMR6<bits<6> funct> : MipsR6Inst {
51 let Inst{31-26} = 0b000000;
54 let Inst{15-12} = 0b0000;
55 let Inst{11-6} = funct;
56 let Inst{5-0} = 0b111100;
59 class CACHE_PREF_FM_MMR6<bits<6> opgroup, bits<4> funct> : MipsR6Inst {
65 let Inst{31-26} = opgroup;
66 let Inst{25-21} = hint;
67 let Inst{20-16} = addr{20-16};
68 let Inst{15-12} = funct;
69 let Inst{11-0} = addr{11-0};
72 class ARITH_FM_MMR6<string instr_asm, bits<10> funct> : MMR6Arch<instr_asm> {
84 let Inst{9-0} = funct;
87 class ADDI_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> {
97 let Inst{15-0} = imm16;
100 class SIGN_EXTEND_FM_MMR6<string instr_asm, bits<10> funct>
101 : MMR6Arch<instr_asm> {
107 let Inst{31-26} = 0b000000;
108 let Inst{25-21} = rd;
109 let Inst{20-16} = rt;
110 let Inst{15-6} = funct;
111 let Inst{5-0} = 0b111100;
114 class PCREL19_FM_MMR6<bits<2> funct> : MipsR6Inst {
120 let Inst{31-26} = 0b011110;
121 let Inst{25-21} = rt;
122 let Inst{20-19} = funct;
123 let Inst{18-0} = imm;
126 class PCREL16_FM_MMR6<bits<5> funct> : MipsR6Inst {
132 let Inst{31-26} = 0b011110;
133 let Inst{25-21} = rt;
134 let Inst{20-16} = funct;
135 let Inst{15-0} = imm;
138 class POOL32A_FM_MMR6<bits<10> funct> : MipsR6Inst {
145 let Inst{31-26} = 0b000000;
146 let Inst{25-21} = rt;
147 let Inst{20-16} = rs;
148 let Inst{15-11} = rd;
150 let Inst{9-0} = funct;
153 class POOL32A_2R_FM_MMR6<bits<10> funct> : MipsR6Inst {
159 let Inst{31-26} = 0b000000;
160 let Inst{25-21} = rt;
161 let Inst{20-16} = rs;
162 let Inst{15-6} = funct;
163 let Inst{5-0} = 0b111100;
166 class SPECIAL_2R_FM_MMR6<bits<6> funct> : MipsR6Inst {
172 let Inst{31-26} = 0b000000;
173 let Inst{25-21} = rs;
174 let Inst{20-16} = 0b00000;
175 let Inst{15-11} = rt;
176 let Inst{10-6} = 0b00001;
177 let Inst{5-0} = funct;
180 class POOL32A_ALIGN_FM_MMR6<bits<6> funct> : MipsR6Inst {
188 let Inst{31-26} = 0b000000;
189 let Inst{25-21} = rs;
190 let Inst{20-16} = rt;
191 let Inst{15-11} = rd;
193 let Inst{8-6} = 0b000;
194 let Inst{5-0} = funct;
197 class AUI_FM_MMR6 : MipsR6Inst {
204 let Inst{31-26} = 0b000100;
205 let Inst{25-21} = rt;
206 let Inst{20-16} = rs;
207 let Inst{15-0} = imm;
210 class POOL32A_LSA_FM<bits<6> funct> : MipsR6Inst {
218 let Inst{31-26} = 0b000000;
219 let Inst{25-21} = rt;
220 let Inst{20-16} = rs;
221 let Inst{15-11} = rd;
222 let Inst{10-9} = imm2;
223 let Inst{8-6} = 0b000;
224 let Inst{5-0} = funct;
227 class CMP_BRANCH_1R_RT_OFF16_FM_MMR6<bits<6> funct> : MipsR6Inst {
233 let Inst{31-26} = funct;
234 let Inst{25-21} = rt;
235 let Inst{20-16} = 0b00000;
236 let Inst{15-0} = offset;
239 class CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<bits<6> funct> : MipsR6Inst {
245 let Inst{31-26} = funct;
246 let Inst{25-21} = rt;
247 let Inst{20-16} = rt;
248 let Inst{15-0} = offset;
251 class ERET_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm> {
254 let Inst{31-26} = 0x00;
255 let Inst{25-16} = 0x00;
256 let Inst{15-6} = 0x3cd;
257 let Inst{5-0} = 0x3c;
260 class ERETNC_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm> {
263 let Inst{31-26} = 0x00;
264 let Inst{25-17} = 0x00;
265 let Inst{16-16} = 0x01;
266 let Inst{15-6} = 0x3cd;
267 let Inst{5-0} = 0x3c;
270 class BREAK_MMR6_ENC<string instr_asm> : MMR6Arch<instr_asm> {
274 let Inst{31-26} = 0x0;
275 let Inst{25-16} = code_1;
276 let Inst{15-6} = code_2;
277 let Inst{5-0} = 0x07;
280 class BARRIER_MMR6_ENC<string instr_asm, bits<5> op> : MMR6Arch<instr_asm> {
283 let Inst{31-26} = 0x0;
284 let Inst{25-21} = 0x0;
285 let Inst{20-16} = 0x0;
286 let Inst{15-11} = op;
287 let Inst{10-6} = 0x0;
291 class EIDI_MMR6_ENC<string instr_asm, bits<10> funct> : MMR6Arch<instr_asm> {
293 bits<5> rt; // Actually rs but we're sharing code with the standard encodings which call it rt
295 let Inst{31-26} = 0x00;
296 let Inst{25-21} = 0x00;
297 let Inst{20-16} = rt;
298 let Inst{15-6} = funct;
299 let Inst{5-0} = 0x3c;
302 class SHIFT_MMR6_ENC<string instr_asm, bits<10> funct, bit rotate> : MMR6Arch<instr_asm> {
310 let Inst{25-21} = rd;
311 let Inst{20-16} = rt;
312 let Inst{15-11} = shamt;
313 let Inst{10} = rotate;
314 let Inst{9-0} = funct;
317 class SW32_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> {
323 let Inst{31-26} = op;
324 let Inst{25-21} = rt;
325 let Inst{20-16} = addr{20-16};
326 let Inst{15-0} = addr{15-0};
329 class POOL32C_SWE_FM_MMR6<string instr_asm, bits<6> op, bits<4> fmt,
330 bits<3> funct> : MMR6Arch<instr_asm> {
333 bits<5> base = addr{20-16};
334 bits<9> offset = addr{8-0};
338 let Inst{31-26} = op;
339 let Inst{25-21} = rt;
340 let Inst{20-16} = base;
341 let Inst{15-12} = fmt;
342 let Inst{11-9} = funct;
343 let Inst{8-0} = offset;
346 class POOL32F_ARITH_FM_MMR6<string instr_asm, bits<2> fmt, bits<8> funct>
347 : MMR6Arch<instr_asm>, MipsR6Inst {
354 let Inst{31-26} = 0b010101;
355 let Inst{25-21} = ft;
356 let Inst{20-16} = fs;
357 let Inst{15-11} = fd;
360 let Inst{7-0} = funct;
363 class POOL32F_ARITHF_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct>
364 : MMR6Arch<instr_asm>, MipsR6Inst {
371 let Inst{31-26} = 0b010101;
372 let Inst{25-21} = ft;
373 let Inst{20-16} = fs;
374 let Inst{15-11} = fd;
375 let Inst{10-9} = fmt;
376 let Inst{8-0} = funct;
379 class POOL32F_MOV_NEG_FM_MMR6<string instr_asm, bits<2> fmt, bits<7> funct>
380 : MMR6Arch<instr_asm>, MipsR6Inst {
386 let Inst{31-26} = 0b010101;
387 let Inst{25-21} = ft;
388 let Inst{20-16} = fs;
390 let Inst{14-13} = fmt;
391 let Inst{12-6} = funct;
392 let Inst{5-0} = 0b111011;
395 class POOL32F_MINMAX_FM<string instr_asm, bits<2> fmt, bits<9> funct>
396 : MMR6Arch<instr_asm>, MipsR6Inst {
403 let Inst{31-26} = 0b010101;
404 let Inst{25-21} = ft;
405 let Inst{20-16} = fs;
406 let Inst{15-11} = fd;
407 let Inst{10-9} = fmt;
408 let Inst{8-0} = funct;
411 class POOL32F_CMP_FM<string instr_asm, bits<6> format, FIELD_CMP_COND Cond>
412 : MMR6Arch<instr_asm>, MipsR6Inst {
419 let Inst{31-26} = 0b010101;
420 let Inst{25-21} = ft;
421 let Inst{20-16} = fs;
422 let Inst{15-11} = fd;
423 let Inst{10-6} = Cond.Value;
424 let Inst{5-0} = format;
427 class POOL32F_CVT_LW_FM<string instr_asm, bit fmt, bits<8> funct>
428 : MMR6Arch<instr_asm>, MipsR6Inst {
433 let Inst{31-26} = 0b010101;
434 let Inst{25-21} = ft;
435 let Inst{20-16} = fs;
438 let Inst{13-6} = funct;
439 let Inst{5-0} = 0b111011;
442 class POOL32F_CVT_DS_FM<string instr_asm, bits<2> fmt, bits<7> funct>
443 : MMR6Arch<instr_asm>, MipsR6Inst {
448 let Inst{31-26} = 0b010101;
449 let Inst{25-21} = ft;
450 let Inst{20-16} = fs;
452 let Inst{14-13} = fmt;
453 let Inst{12-6} = funct;
454 let Inst{5-0} = 0b111011;