1 //===-- MipsMCTargetDesc.cpp - Mips Target Descriptions -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides Mips specific target descriptions.
12 //===----------------------------------------------------------------------===//
14 #include "InstPrinter/MipsInstPrinter.h"
15 #include "MipsELFStreamer.h"
16 #include "MipsMCAsmInfo.h"
17 #include "MipsMCNaCl.h"
18 #include "MipsMCTargetDesc.h"
19 #include "MipsTargetStreamer.h"
20 #include "llvm/ADT/Triple.h"
21 #include "llvm/MC/MCCodeGenInfo.h"
22 #include "llvm/MC/MCELFStreamer.h"
23 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/MC/MCSymbol.h"
27 #include "llvm/MC/MachineLocation.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/FormattedStream.h"
31 #include "llvm/Support/TargetRegistry.h"
35 #define GET_INSTRINFO_MC_DESC
36 #include "MipsGenInstrInfo.inc"
38 #define GET_SUBTARGETINFO_MC_DESC
39 #include "MipsGenSubtargetInfo.inc"
41 #define GET_REGINFO_MC_DESC
42 #include "MipsGenRegisterInfo.inc"
44 /// Select the Mips CPU for the given triple and cpu name.
45 /// FIXME: Merge with the copy in MipsSubtarget.cpp
46 static inline StringRef selectMipsCPU(StringRef TT, StringRef CPU) {
47 if (CPU.empty() || CPU == "generic") {
49 if (TheTriple.getArch() == Triple::mips ||
50 TheTriple.getArch() == Triple::mipsel)
58 static MCInstrInfo *createMipsMCInstrInfo() {
59 MCInstrInfo *X = new MCInstrInfo();
60 InitMipsMCInstrInfo(X);
64 static MCRegisterInfo *createMipsMCRegisterInfo(StringRef TT) {
65 MCRegisterInfo *X = new MCRegisterInfo();
66 InitMipsMCRegisterInfo(X, Mips::RA);
70 static MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU,
72 CPU = selectMipsCPU(TT, CPU);
73 MCSubtargetInfo *X = new MCSubtargetInfo();
74 InitMipsMCSubtargetInfo(X, TT, CPU, FS);
78 static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
79 MCAsmInfo *MAI = new MipsMCAsmInfo(TT);
81 unsigned SP = MRI.getDwarfRegNum(Mips::SP, true);
82 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, SP, 0);
83 MAI->addInitialFrameState(Inst);
88 static MCCodeGenInfo *createMipsMCCodeGenInfo(StringRef TT, Reloc::Model RM,
90 CodeGenOpt::Level OL) {
91 MCCodeGenInfo *X = new MCCodeGenInfo();
92 if (CM == CodeModel::JITDefault)
94 else if (RM == Reloc::Default)
96 X->InitMCCodeGenInfo(RM, CM, OL);
100 static MCInstPrinter *createMipsMCInstPrinter(const Target &T,
101 unsigned SyntaxVariant,
102 const MCAsmInfo &MAI,
103 const MCInstrInfo &MII,
104 const MCRegisterInfo &MRI,
105 const MCSubtargetInfo &STI) {
106 return new MipsInstPrinter(MAI, MII, MRI);
109 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
110 MCContext &Context, MCAsmBackend &MAB,
111 raw_ostream &OS, MCCodeEmitter *Emitter,
112 const MCSubtargetInfo &STI, bool RelaxAll) {
114 if (!Triple(TT).isOSNaCl())
115 S = createMipsELFStreamer(Context, MAB, OS, Emitter, STI, RelaxAll);
117 S = createMipsNaClELFStreamer(Context, MAB, OS, Emitter, STI, RelaxAll);
118 new MipsTargetELFStreamer(*S, STI);
123 createMCAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS,
124 bool isVerboseAsm, bool useDwarfDirectory,
125 MCInstPrinter *InstPrint, MCCodeEmitter *CE,
126 MCAsmBackend *TAB, bool ShowInst) {
127 MCStreamer *S = llvm::createAsmStreamer(
128 Ctx, OS, isVerboseAsm, useDwarfDirectory, InstPrint, CE, TAB, ShowInst);
129 new MipsTargetAsmStreamer(*S, OS);
133 static MCStreamer *createMipsNullStreamer(MCContext &Ctx) {
134 MCStreamer *S = llvm::createNullStreamer(Ctx);
135 new MipsTargetStreamer(*S);
139 extern "C" void LLVMInitializeMipsTargetMC() {
140 // Register the MC asm info.
141 RegisterMCAsmInfoFn X(TheMipsTarget, createMipsMCAsmInfo);
142 RegisterMCAsmInfoFn Y(TheMipselTarget, createMipsMCAsmInfo);
143 RegisterMCAsmInfoFn A(TheMips64Target, createMipsMCAsmInfo);
144 RegisterMCAsmInfoFn B(TheMips64elTarget, createMipsMCAsmInfo);
146 // Register the MC codegen info.
147 TargetRegistry::RegisterMCCodeGenInfo(TheMipsTarget,
148 createMipsMCCodeGenInfo);
149 TargetRegistry::RegisterMCCodeGenInfo(TheMipselTarget,
150 createMipsMCCodeGenInfo);
151 TargetRegistry::RegisterMCCodeGenInfo(TheMips64Target,
152 createMipsMCCodeGenInfo);
153 TargetRegistry::RegisterMCCodeGenInfo(TheMips64elTarget,
154 createMipsMCCodeGenInfo);
156 // Register the MC instruction info.
157 TargetRegistry::RegisterMCInstrInfo(TheMipsTarget, createMipsMCInstrInfo);
158 TargetRegistry::RegisterMCInstrInfo(TheMipselTarget, createMipsMCInstrInfo);
159 TargetRegistry::RegisterMCInstrInfo(TheMips64Target, createMipsMCInstrInfo);
160 TargetRegistry::RegisterMCInstrInfo(TheMips64elTarget,
161 createMipsMCInstrInfo);
163 // Register the MC register info.
164 TargetRegistry::RegisterMCRegInfo(TheMipsTarget, createMipsMCRegisterInfo);
165 TargetRegistry::RegisterMCRegInfo(TheMipselTarget, createMipsMCRegisterInfo);
166 TargetRegistry::RegisterMCRegInfo(TheMips64Target, createMipsMCRegisterInfo);
167 TargetRegistry::RegisterMCRegInfo(TheMips64elTarget,
168 createMipsMCRegisterInfo);
170 // Register the MC Code Emitter
171 TargetRegistry::RegisterMCCodeEmitter(TheMipsTarget,
172 createMipsMCCodeEmitterEB);
173 TargetRegistry::RegisterMCCodeEmitter(TheMipselTarget,
174 createMipsMCCodeEmitterEL);
175 TargetRegistry::RegisterMCCodeEmitter(TheMips64Target,
176 createMipsMCCodeEmitterEB);
177 TargetRegistry::RegisterMCCodeEmitter(TheMips64elTarget,
178 createMipsMCCodeEmitterEL);
180 // Register the object streamer.
181 TargetRegistry::RegisterMCObjectStreamer(TheMipsTarget, createMCStreamer);
182 TargetRegistry::RegisterMCObjectStreamer(TheMipselTarget, createMCStreamer);
183 TargetRegistry::RegisterMCObjectStreamer(TheMips64Target, createMCStreamer);
184 TargetRegistry::RegisterMCObjectStreamer(TheMips64elTarget,
187 // Register the asm streamer.
188 TargetRegistry::RegisterAsmStreamer(TheMipsTarget, createMCAsmStreamer);
189 TargetRegistry::RegisterAsmStreamer(TheMipselTarget, createMCAsmStreamer);
190 TargetRegistry::RegisterAsmStreamer(TheMips64Target, createMCAsmStreamer);
191 TargetRegistry::RegisterAsmStreamer(TheMips64elTarget, createMCAsmStreamer);
193 TargetRegistry::RegisterNullStreamer(TheMipsTarget, createMipsNullStreamer);
194 TargetRegistry::RegisterNullStreamer(TheMipselTarget, createMipsNullStreamer);
195 TargetRegistry::RegisterNullStreamer(TheMips64Target, createMipsNullStreamer);
196 TargetRegistry::RegisterNullStreamer(TheMips64elTarget,
197 createMipsNullStreamer);
199 // Register the asm backend.
200 TargetRegistry::RegisterMCAsmBackend(TheMipsTarget,
201 createMipsAsmBackendEB32);
202 TargetRegistry::RegisterMCAsmBackend(TheMipselTarget,
203 createMipsAsmBackendEL32);
204 TargetRegistry::RegisterMCAsmBackend(TheMips64Target,
205 createMipsAsmBackendEB64);
206 TargetRegistry::RegisterMCAsmBackend(TheMips64elTarget,
207 createMipsAsmBackendEL64);
209 // Register the MC subtarget info.
210 TargetRegistry::RegisterMCSubtargetInfo(TheMipsTarget,
211 createMipsMCSubtargetInfo);
212 TargetRegistry::RegisterMCSubtargetInfo(TheMipselTarget,
213 createMipsMCSubtargetInfo);
214 TargetRegistry::RegisterMCSubtargetInfo(TheMips64Target,
215 createMipsMCSubtargetInfo);
216 TargetRegistry::RegisterMCSubtargetInfo(TheMips64elTarget,
217 createMipsMCSubtargetInfo);
219 // Register the MCInstPrinter.
220 TargetRegistry::RegisterMCInstPrinter(TheMipsTarget,
221 createMipsMCInstPrinter);
222 TargetRegistry::RegisterMCInstPrinter(TheMipselTarget,
223 createMipsMCInstPrinter);
224 TargetRegistry::RegisterMCInstPrinter(TheMips64Target,
225 createMipsMCInstPrinter);
226 TargetRegistry::RegisterMCInstPrinter(TheMips64elTarget,
227 createMipsMCInstPrinter);