1 //===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the MipsMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
15 #include "MipsMCCodeEmitter.h"
16 #include "MCTargetDesc/MipsFixupKinds.h"
17 #include "MCTargetDesc/MipsMCExpr.h"
18 #include "MCTargetDesc/MipsMCTargetDesc.h"
19 #include "llvm/ADT/APFloat.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCFixup.h"
24 #include "llvm/MC/MCInst.h"
25 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/MC/MCSubtargetInfo.h"
27 #include "llvm/Support/raw_ostream.h"
29 #define DEBUG_TYPE "mccodeemitter"
31 #define GET_INSTRMAP_INFO
32 #include "MipsGenInstrInfo.inc"
33 #undef GET_INSTRMAP_INFO
36 MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
37 const MCRegisterInfo &MRI,
39 return new MipsMCCodeEmitter(MCII, Ctx, false);
42 MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
43 const MCRegisterInfo &MRI,
45 return new MipsMCCodeEmitter(MCII, Ctx, true);
47 } // End of namespace llvm.
49 // If the D<shift> instruction has a shift amount that is greater
50 // than 31 (checked in calling routine), lower it to a D<shift>32 instruction
51 static void LowerLargeShift(MCInst& Inst) {
53 assert(Inst.getNumOperands() == 3 && "Invalid no. of operands for shift!");
54 assert(Inst.getOperand(2).isImm());
56 int64_t Shift = Inst.getOperand(2).getImm();
62 Inst.getOperand(2).setImm(Shift);
64 switch (Inst.getOpcode()) {
66 // Calling function is not synchronized
67 llvm_unreachable("Unexpected shift instruction");
69 Inst.setOpcode(Mips::DSLL32);
72 Inst.setOpcode(Mips::DSRL32);
75 Inst.setOpcode(Mips::DSRA32);
78 Inst.setOpcode(Mips::DROTR32);
83 // Pick a DEXT or DINS instruction variant based on the pos and size operands
84 static void LowerDextDins(MCInst& InstIn) {
85 int Opcode = InstIn.getOpcode();
87 if (Opcode == Mips::DEXT)
88 assert(InstIn.getNumOperands() == 4 &&
89 "Invalid no. of machine operands for DEXT!");
90 else // Only DEXT and DINS are possible
91 assert(InstIn.getNumOperands() == 5 &&
92 "Invalid no. of machine operands for DINS!");
94 assert(InstIn.getOperand(2).isImm());
95 int64_t pos = InstIn.getOperand(2).getImm();
96 assert(InstIn.getOperand(3).isImm());
97 int64_t size = InstIn.getOperand(3).getImm();
100 if (pos < 32) // DEXT/DINS, do nothing
103 InstIn.getOperand(2).setImm(pos - 32);
104 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTU : Mips::DINSU);
108 assert(pos < 32 && "DEXT/DINS cannot have both size and pos > 32");
109 InstIn.getOperand(3).setImm(size - 32);
110 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTM : Mips::DINSM);
114 bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const {
115 return STI.getFeatureBits() & Mips::FeatureMicroMips;
118 void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS) const {
122 void MipsMCCodeEmitter::EmitInstruction(uint64_t Val, unsigned Size,
123 const MCSubtargetInfo &STI,
124 raw_ostream &OS) const {
125 // Output the instruction encoding in little endian byte order.
126 // Little-endian byte ordering:
127 // mips32r2: 4 | 3 | 2 | 1
128 // microMIPS: 2 | 1 | 4 | 3
129 if (IsLittleEndian && Size == 4 && isMicroMips(STI)) {
130 EmitInstruction(Val >> 16, 2, STI, OS);
131 EmitInstruction(Val, 2, STI, OS);
133 for (unsigned i = 0; i < Size; ++i) {
134 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
135 EmitByte((Val >> Shift) & 0xff, OS);
140 /// EncodeInstruction - Emit the instruction.
141 /// Size the instruction with Desc.getSize().
142 void MipsMCCodeEmitter::
143 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
144 SmallVectorImpl<MCFixup> &Fixups,
145 const MCSubtargetInfo &STI) const
148 // Non-pseudo instructions that get changed for direct object
149 // only based on operand values.
150 // If this list of instructions get much longer we will move
151 // the check to a function call. Until then, this is more efficient.
153 switch (MI.getOpcode()) {
154 // If shift amount is >= 32 it the inst needs to be lowered further
159 LowerLargeShift(TmpInst);
161 // Double extract instruction is chosen by pos and size operands
164 LowerDextDins(TmpInst);
167 unsigned long N = Fixups.size();
168 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
170 // Check for unimplemented opcodes.
171 // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0
172 // so we have to special check for them.
173 unsigned Opcode = TmpInst.getOpcode();
174 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) &&
175 (Opcode != Mips::SLL_MM) && !Binary)
176 llvm_unreachable("unimplemented opcode in EncodeInstruction()");
178 if (STI.getFeatureBits() & Mips::FeatureMicroMips) {
179 int NewOpcode = Mips::Std2MicroMips (Opcode, Mips::Arch_micromips);
180 if (NewOpcode != -1) {
181 if (Fixups.size() > N)
184 TmpInst.setOpcode (NewOpcode);
185 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
189 const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
191 // Get byte count of instruction
192 unsigned Size = Desc.getSize();
194 llvm_unreachable("Desc.getSize() returns 0");
196 EmitInstruction(Binary, Size, STI, OS);
199 /// getBranchTargetOpValue - Return binary encoding of the branch
200 /// target operand. If the machine operand requires relocation,
201 /// record the relocation and return zero.
202 unsigned MipsMCCodeEmitter::
203 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
204 SmallVectorImpl<MCFixup> &Fixups,
205 const MCSubtargetInfo &STI) const {
207 const MCOperand &MO = MI.getOperand(OpNo);
209 // If the destination is an immediate, divide by 4.
210 if (MO.isImm()) return MO.getImm() >> 2;
212 assert(MO.isExpr() &&
213 "getBranchTargetOpValue expects only expressions or immediates");
215 const MCExpr *Expr = MO.getExpr();
216 Fixups.push_back(MCFixup::Create(0, Expr,
217 MCFixupKind(Mips::fixup_Mips_PC16)));
221 /// getBranchTarget7OpValueMM - Return binary encoding of the microMIPS branch
222 /// target operand. If the machine operand requires relocation,
223 /// record the relocation and return zero.
224 unsigned MipsMCCodeEmitter::
225 getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo,
226 SmallVectorImpl<MCFixup> &Fixups,
227 const MCSubtargetInfo &STI) const {
229 const MCOperand &MO = MI.getOperand(OpNo);
231 // If the destination is an immediate, divide by 2.
232 if (MO.isImm()) return MO.getImm() >> 1;
234 assert(MO.isExpr() &&
235 "getBranchTargetOpValueMM expects only expressions or immediates");
237 const MCExpr *Expr = MO.getExpr();
238 Fixups.push_back(MCFixup::Create(0, Expr,
239 MCFixupKind(Mips::fixup_MICROMIPS_PC7_S1)));
243 /// getBranchTargetOpValueMMPC10 - Return binary encoding of the microMIPS
244 /// 10-bit branch target operand. If the machine operand requires relocation,
245 /// record the relocation and return zero.
246 unsigned MipsMCCodeEmitter::
247 getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo,
248 SmallVectorImpl<MCFixup> &Fixups,
249 const MCSubtargetInfo &STI) const {
251 const MCOperand &MO = MI.getOperand(OpNo);
253 // If the destination is an immediate, divide by 2.
254 if (MO.isImm()) return MO.getImm() >> 1;
256 assert(MO.isExpr() &&
257 "getBranchTargetOpValuePC10 expects only expressions or immediates");
259 const MCExpr *Expr = MO.getExpr();
260 Fixups.push_back(MCFixup::Create(0, Expr,
261 MCFixupKind(Mips::fixup_MICROMIPS_PC10_S1)));
265 /// getBranchTargetOpValue - Return binary encoding of the microMIPS branch
266 /// target operand. If the machine operand requires relocation,
267 /// record the relocation and return zero.
268 unsigned MipsMCCodeEmitter::
269 getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
270 SmallVectorImpl<MCFixup> &Fixups,
271 const MCSubtargetInfo &STI) const {
273 const MCOperand &MO = MI.getOperand(OpNo);
275 // If the destination is an immediate, divide by 2.
276 if (MO.isImm()) return MO.getImm() >> 1;
278 assert(MO.isExpr() &&
279 "getBranchTargetOpValueMM expects only expressions or immediates");
281 const MCExpr *Expr = MO.getExpr();
282 Fixups.push_back(MCFixup::Create(0, Expr,
284 fixup_MICROMIPS_PC16_S1)));
288 /// getBranchTarget21OpValue - Return binary encoding of the branch
289 /// target operand. If the machine operand requires relocation,
290 /// record the relocation and return zero.
291 unsigned MipsMCCodeEmitter::
292 getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo,
293 SmallVectorImpl<MCFixup> &Fixups,
294 const MCSubtargetInfo &STI) const {
296 const MCOperand &MO = MI.getOperand(OpNo);
298 // If the destination is an immediate, divide by 4.
299 if (MO.isImm()) return MO.getImm() >> 2;
301 assert(MO.isExpr() &&
302 "getBranchTarget21OpValue expects only expressions or immediates");
304 const MCExpr *Expr = MO.getExpr();
305 Fixups.push_back(MCFixup::Create(0, Expr,
306 MCFixupKind(Mips::fixup_MIPS_PC21_S2)));
310 /// getBranchTarget26OpValue - Return binary encoding of the branch
311 /// target operand. If the machine operand requires relocation,
312 /// record the relocation and return zero.
313 unsigned MipsMCCodeEmitter::
314 getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
315 SmallVectorImpl<MCFixup> &Fixups,
316 const MCSubtargetInfo &STI) const {
318 const MCOperand &MO = MI.getOperand(OpNo);
320 // If the destination is an immediate, divide by 4.
321 if (MO.isImm()) return MO.getImm() >> 2;
323 assert(MO.isExpr() &&
324 "getBranchTarget26OpValue expects only expressions or immediates");
326 const MCExpr *Expr = MO.getExpr();
327 Fixups.push_back(MCFixup::Create(0, Expr,
328 MCFixupKind(Mips::fixup_MIPS_PC26_S2)));
332 /// getJumpOffset16OpValue - Return binary encoding of the jump
333 /// target operand. If the machine operand requires relocation,
334 /// record the relocation and return zero.
335 unsigned MipsMCCodeEmitter::
336 getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo,
337 SmallVectorImpl<MCFixup> &Fixups,
338 const MCSubtargetInfo &STI) const {
340 const MCOperand &MO = MI.getOperand(OpNo);
342 if (MO.isImm()) return MO.getImm();
344 assert(MO.isExpr() &&
345 "getJumpOffset16OpValue expects only expressions or an immediate");
351 /// getJumpTargetOpValue - Return binary encoding of the jump
352 /// target operand. If the machine operand requires relocation,
353 /// record the relocation and return zero.
354 unsigned MipsMCCodeEmitter::
355 getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
356 SmallVectorImpl<MCFixup> &Fixups,
357 const MCSubtargetInfo &STI) const {
359 const MCOperand &MO = MI.getOperand(OpNo);
360 // If the destination is an immediate, divide by 4.
361 if (MO.isImm()) return MO.getImm()>>2;
363 assert(MO.isExpr() &&
364 "getJumpTargetOpValue expects only expressions or an immediate");
366 const MCExpr *Expr = MO.getExpr();
367 Fixups.push_back(MCFixup::Create(0, Expr,
368 MCFixupKind(Mips::fixup_Mips_26)));
372 unsigned MipsMCCodeEmitter::
373 getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
374 SmallVectorImpl<MCFixup> &Fixups,
375 const MCSubtargetInfo &STI) const {
377 const MCOperand &MO = MI.getOperand(OpNo);
378 // If the destination is an immediate, divide by 2.
379 if (MO.isImm()) return MO.getImm() >> 1;
381 assert(MO.isExpr() &&
382 "getJumpTargetOpValueMM expects only expressions or an immediate");
384 const MCExpr *Expr = MO.getExpr();
385 Fixups.push_back(MCFixup::Create(0, Expr,
386 MCFixupKind(Mips::fixup_MICROMIPS_26_S1)));
390 unsigned MipsMCCodeEmitter::
391 getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo,
392 SmallVectorImpl<MCFixup> &Fixups,
393 const MCSubtargetInfo &STI) const {
395 const MCOperand &MO = MI.getOperand(OpNo);
397 // The immediate is encoded as 'immediate << 2'.
398 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
399 assert((Res & 3) == 0);
403 assert(MO.isExpr() &&
404 "getUImm5Lsl2Encoding expects only expressions or an immediate");
409 unsigned MipsMCCodeEmitter::
410 getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo,
411 SmallVectorImpl<MCFixup> &Fixups,
412 const MCSubtargetInfo &STI) const {
414 const MCOperand &MO = MI.getOperand(OpNo);
416 int Value = MO.getImm();
423 unsigned MipsMCCodeEmitter::
424 getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo,
425 SmallVectorImpl<MCFixup> &Fixups,
426 const MCSubtargetInfo &STI) const {
428 const MCOperand &MO = MI.getOperand(OpNo);
430 unsigned Value = MO.getImm();
437 unsigned MipsMCCodeEmitter::
438 getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo,
439 SmallVectorImpl<MCFixup> &Fixups,
440 const MCSubtargetInfo &STI) const {
442 const MCOperand &MO = MI.getOperand(OpNo);
444 unsigned Binary = (MO.getImm() >> 2) & 0x0000ffff;
445 return (((Binary & 0x8000) >> 7) | (Binary & 0x00ff));
451 unsigned MipsMCCodeEmitter::
452 getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
453 const MCSubtargetInfo &STI) const {
456 if (Expr->EvaluateAsAbsolute(Res))
459 MCExpr::ExprKind Kind = Expr->getKind();
460 if (Kind == MCExpr::Constant) {
461 return cast<MCConstantExpr>(Expr)->getValue();
464 if (Kind == MCExpr::Binary) {
465 unsigned Res = getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups, STI);
466 Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups, STI);
470 if (Kind == MCExpr::Target) {
471 const MipsMCExpr *MipsExpr = cast<MipsMCExpr>(Expr);
473 Mips::Fixups FixupKind = Mips::Fixups(0);
474 switch (MipsExpr->getKind()) {
475 default: llvm_unreachable("Unsupported fixup kind for target expression!");
476 case MipsMCExpr::VK_Mips_HIGHEST:
477 FixupKind = Mips::fixup_Mips_HIGHEST;
479 case MipsMCExpr::VK_Mips_HIGHER:
480 FixupKind = Mips::fixup_Mips_HIGHER;
482 case MipsMCExpr::VK_Mips_HI:
483 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16
484 : Mips::fixup_Mips_HI16;
486 case MipsMCExpr::VK_Mips_LO:
487 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16
488 : Mips::fixup_Mips_LO16;
491 Fixups.push_back(MCFixup::Create(0, MipsExpr, MCFixupKind(FixupKind)));
495 if (Kind == MCExpr::SymbolRef) {
496 Mips::Fixups FixupKind = Mips::Fixups(0);
498 switch(cast<MCSymbolRefExpr>(Expr)->getKind()) {
499 default: llvm_unreachable("Unknown fixup kind!");
501 case MCSymbolRefExpr::VK_None:
502 FixupKind = Mips::fixup_Mips_32; // FIXME: This is ok for O32/N32 but not N64.
504 case MCSymbolRefExpr::VK_Mips_GPOFF_HI :
505 FixupKind = Mips::fixup_Mips_GPOFF_HI;
507 case MCSymbolRefExpr::VK_Mips_GPOFF_LO :
508 FixupKind = Mips::fixup_Mips_GPOFF_LO;
510 case MCSymbolRefExpr::VK_Mips_GOT_PAGE :
511 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_PAGE
512 : Mips::fixup_Mips_GOT_PAGE;
514 case MCSymbolRefExpr::VK_Mips_GOT_OFST :
515 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_OFST
516 : Mips::fixup_Mips_GOT_OFST;
518 case MCSymbolRefExpr::VK_Mips_GOT_DISP :
519 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_DISP
520 : Mips::fixup_Mips_GOT_DISP;
522 case MCSymbolRefExpr::VK_Mips_GPREL:
523 FixupKind = Mips::fixup_Mips_GPREL16;
525 case MCSymbolRefExpr::VK_Mips_GOT_CALL:
526 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_CALL16
527 : Mips::fixup_Mips_CALL16;
529 case MCSymbolRefExpr::VK_Mips_GOT16:
530 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16
531 : Mips::fixup_Mips_GOT_Global;
533 case MCSymbolRefExpr::VK_Mips_GOT:
534 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16
535 : Mips::fixup_Mips_GOT_Local;
537 case MCSymbolRefExpr::VK_Mips_ABS_HI:
538 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16
539 : Mips::fixup_Mips_HI16;
541 case MCSymbolRefExpr::VK_Mips_ABS_LO:
542 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16
543 : Mips::fixup_Mips_LO16;
545 case MCSymbolRefExpr::VK_Mips_TLSGD:
546 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_GD
547 : Mips::fixup_Mips_TLSGD;
549 case MCSymbolRefExpr::VK_Mips_TLSLDM:
550 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_LDM
551 : Mips::fixup_Mips_TLSLDM;
553 case MCSymbolRefExpr::VK_Mips_DTPREL_HI:
554 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_HI16
555 : Mips::fixup_Mips_DTPREL_HI;
557 case MCSymbolRefExpr::VK_Mips_DTPREL_LO:
558 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_LO16
559 : Mips::fixup_Mips_DTPREL_LO;
561 case MCSymbolRefExpr::VK_Mips_GOTTPREL:
562 FixupKind = Mips::fixup_Mips_GOTTPREL;
564 case MCSymbolRefExpr::VK_Mips_TPREL_HI:
565 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_HI16
566 : Mips::fixup_Mips_TPREL_HI;
568 case MCSymbolRefExpr::VK_Mips_TPREL_LO:
569 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_LO16
570 : Mips::fixup_Mips_TPREL_LO;
572 case MCSymbolRefExpr::VK_Mips_HIGHER:
573 FixupKind = Mips::fixup_Mips_HIGHER;
575 case MCSymbolRefExpr::VK_Mips_HIGHEST:
576 FixupKind = Mips::fixup_Mips_HIGHEST;
578 case MCSymbolRefExpr::VK_Mips_GOT_HI16:
579 FixupKind = Mips::fixup_Mips_GOT_HI16;
581 case MCSymbolRefExpr::VK_Mips_GOT_LO16:
582 FixupKind = Mips::fixup_Mips_GOT_LO16;
584 case MCSymbolRefExpr::VK_Mips_CALL_HI16:
585 FixupKind = Mips::fixup_Mips_CALL_HI16;
587 case MCSymbolRefExpr::VK_Mips_CALL_LO16:
588 FixupKind = Mips::fixup_Mips_CALL_LO16;
590 case MCSymbolRefExpr::VK_Mips_PCREL_HI16:
591 FixupKind = Mips::fixup_MIPS_PCHI16;
593 case MCSymbolRefExpr::VK_Mips_PCREL_LO16:
594 FixupKind = Mips::fixup_MIPS_PCLO16;
598 Fixups.push_back(MCFixup::Create(0, Expr, MCFixupKind(FixupKind)));
604 /// getMachineOpValue - Return binary encoding of operand. If the machine
605 /// operand requires relocation, record the relocation and return zero.
606 unsigned MipsMCCodeEmitter::
607 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
608 SmallVectorImpl<MCFixup> &Fixups,
609 const MCSubtargetInfo &STI) const {
611 unsigned Reg = MO.getReg();
612 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
614 } else if (MO.isImm()) {
615 return static_cast<unsigned>(MO.getImm());
616 } else if (MO.isFPImm()) {
617 return static_cast<unsigned>(APFloat(MO.getFPImm())
618 .bitcastToAPInt().getHiBits(32).getLimitedValue());
620 // MO must be an Expr.
622 return getExprOpValue(MO.getExpr(),Fixups, STI);
625 /// getMSAMemEncoding - Return binary encoding of memory operand for LD/ST
628 MipsMCCodeEmitter::getMSAMemEncoding(const MCInst &MI, unsigned OpNo,
629 SmallVectorImpl<MCFixup> &Fixups,
630 const MCSubtargetInfo &STI) const {
631 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
632 assert(MI.getOperand(OpNo).isReg());
633 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
634 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
636 // The immediate field of an LD/ST instruction is scaled which means it must
637 // be divided (when encoding) by the size (in bytes) of the instructions'
643 switch(MI.getOpcode())
646 assert (0 && "Unexpected instruction");
650 // We don't need to scale the offset in this case
666 return (OffBits & 0xFFFF) | RegBits;
669 /// getMemEncoding - Return binary encoding of memory related operand.
670 /// If the offset operand requires relocation, record the relocation.
672 MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
673 SmallVectorImpl<MCFixup> &Fixups,
674 const MCSubtargetInfo &STI) const {
675 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
676 assert(MI.getOperand(OpNo).isReg());
677 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
678 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
680 return (OffBits & 0xFFFF) | RegBits;
683 unsigned MipsMCCodeEmitter::
684 getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo,
685 SmallVectorImpl<MCFixup> &Fixups,
686 const MCSubtargetInfo &STI) const {
687 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
688 assert(MI.getOperand(OpNo).isReg());
689 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
691 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
694 return (OffBits & 0xF) | RegBits;
697 unsigned MipsMCCodeEmitter::
698 getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo,
699 SmallVectorImpl<MCFixup> &Fixups,
700 const MCSubtargetInfo &STI) const {
701 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
702 assert(MI.getOperand(OpNo).isReg());
703 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
705 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
708 return (OffBits & 0xF) | RegBits;
711 unsigned MipsMCCodeEmitter::
712 getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo,
713 SmallVectorImpl<MCFixup> &Fixups,
714 const MCSubtargetInfo &STI) const {
715 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
716 assert(MI.getOperand(OpNo).isReg());
717 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
719 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
722 return (OffBits & 0xF) | RegBits;
725 unsigned MipsMCCodeEmitter::
726 getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo,
727 SmallVectorImpl<MCFixup> &Fixups,
728 const MCSubtargetInfo &STI) const {
729 // Register is encoded in bits 9-5, offset is encoded in bits 4-0.
730 assert(MI.getOperand(OpNo).isReg() &&
731 MI.getOperand(OpNo).getReg() == Mips::SP &&
732 "Unexpected base register!");
733 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
736 return OffBits & 0x1F;
739 unsigned MipsMCCodeEmitter::
740 getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo,
741 SmallVectorImpl<MCFixup> &Fixups,
742 const MCSubtargetInfo &STI) const {
743 // Register is encoded in bits 9-7, offset is encoded in bits 6-0.
744 assert(MI.getOperand(OpNo).isReg() &&
745 MI.getOperand(OpNo).getReg() == Mips::GP &&
746 "Unexpected base register!");
748 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
751 return OffBits & 0x7F;
754 unsigned MipsMCCodeEmitter::
755 getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
756 SmallVectorImpl<MCFixup> &Fixups,
757 const MCSubtargetInfo &STI) const {
758 // opNum can be invalid if instruction had reglist as operand.
759 // MemOperand is always last operand of instruction (base + offset).
760 switch (MI.getOpcode()) {
765 OpNo = MI.getNumOperands() - 2;
769 // Base register is encoded in bits 20-16, offset is encoded in bits 11-0.
770 assert(MI.getOperand(OpNo).isReg());
771 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) << 16;
772 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
774 return (OffBits & 0x0FFF) | RegBits;
777 unsigned MipsMCCodeEmitter::
778 getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo,
779 SmallVectorImpl<MCFixup> &Fixups,
780 const MCSubtargetInfo &STI) const {
781 // opNum can be invalid if instruction had reglist as operand
782 // MemOperand is always last operand of instruction (base + offset)
783 switch (MI.getOpcode()) {
788 OpNo = MI.getNumOperands() - 2;
792 // Offset is encoded in bits 4-0.
793 assert(MI.getOperand(OpNo).isReg());
794 // Base register is always SP - thus it is not encoded.
795 assert(MI.getOperand(OpNo+1).isImm());
796 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
798 return ((OffBits >> 2) & 0x0F);
802 MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
803 SmallVectorImpl<MCFixup> &Fixups,
804 const MCSubtargetInfo &STI) const {
805 assert(MI.getOperand(OpNo).isImm());
806 unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
807 return SizeEncoding - 1;
810 // FIXME: should be called getMSBEncoding
813 MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
814 SmallVectorImpl<MCFixup> &Fixups,
815 const MCSubtargetInfo &STI) const {
816 assert(MI.getOperand(OpNo-1).isImm());
817 assert(MI.getOperand(OpNo).isImm());
818 unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups, STI);
819 unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
821 return Position + Size - 1;
825 MipsMCCodeEmitter::getLSAImmEncoding(const MCInst &MI, unsigned OpNo,
826 SmallVectorImpl<MCFixup> &Fixups,
827 const MCSubtargetInfo &STI) const {
828 assert(MI.getOperand(OpNo).isImm());
829 // The immediate is encoded as 'immediate - 1'.
830 return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) - 1;
834 MipsMCCodeEmitter::getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo,
835 SmallVectorImpl<MCFixup> &Fixups,
836 const MCSubtargetInfo &STI) const {
837 const MCOperand &MO = MI.getOperand(OpNo);
839 // The immediate is encoded as 'immediate << 2'.
840 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
841 assert((Res & 3) == 0);
845 assert(MO.isExpr() &&
846 "getSimm19Lsl2Encoding expects only expressions or an immediate");
848 const MCExpr *Expr = MO.getExpr();
849 Fixups.push_back(MCFixup::Create(0, Expr,
850 MCFixupKind(Mips::fixup_MIPS_PC19_S2)));
855 MipsMCCodeEmitter::getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo,
856 SmallVectorImpl<MCFixup> &Fixups,
857 const MCSubtargetInfo &STI) const {
858 const MCOperand &MO = MI.getOperand(OpNo);
860 // The immediate is encoded as 'immediate << 3'.
861 unsigned Res = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
862 assert((Res & 7) == 0);
866 assert(MO.isExpr() &&
867 "getSimm18Lsl2Encoding expects only expressions or an immediate");
869 const MCExpr *Expr = MO.getExpr();
870 Fixups.push_back(MCFixup::Create(0, Expr,
871 MCFixupKind(Mips::fixup_MIPS_PC18_S3)));
876 MipsMCCodeEmitter::getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo,
877 SmallVectorImpl<MCFixup> &Fixups,
878 const MCSubtargetInfo &STI) const {
879 assert(MI.getOperand(OpNo).isImm());
880 const MCOperand &MO = MI.getOperand(OpNo);
881 return MO.getImm() % 8;
885 MipsMCCodeEmitter::getUImm4AndValue(const MCInst &MI, unsigned OpNo,
886 SmallVectorImpl<MCFixup> &Fixups,
887 const MCSubtargetInfo &STI) const {
888 assert(MI.getOperand(OpNo).isImm());
889 const MCOperand &MO = MI.getOperand(OpNo);
890 unsigned Value = MO.getImm();
892 case 128: return 0x0;
905 case 255: return 0xd;
906 case 32768: return 0xe;
907 case 65535: return 0xf;
909 llvm_unreachable("Unexpected value");
913 MipsMCCodeEmitter::getRegisterListOpValue(const MCInst &MI, unsigned OpNo,
914 SmallVectorImpl<MCFixup> &Fixups,
915 const MCSubtargetInfo &STI) const {
918 // Register list operand is always first operand of instruction and it is
919 // placed before memory operand (register + imm).
921 for (unsigned I = OpNo, E = MI.getNumOperands() - 2; I < E; ++I) {
922 unsigned Reg = MI.getOperand(I).getReg();
923 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
933 MipsMCCodeEmitter::getRegisterListOpValue16(const MCInst &MI, unsigned OpNo,
934 SmallVectorImpl<MCFixup> &Fixups,
935 const MCSubtargetInfo &STI) const {
936 return (MI.getNumOperands() - 4);
940 MipsMCCodeEmitter::getRegisterPairOpValue(const MCInst &MI, unsigned OpNo,
941 SmallVectorImpl<MCFixup> &Fixups,
942 const MCSubtargetInfo &STI) const {
943 return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
947 MipsMCCodeEmitter::getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo,
948 SmallVectorImpl<MCFixup> &Fixups,
949 const MCSubtargetInfo &STI) const {
952 if (MI.getOperand(0).getReg() == Mips::A1 &&
953 MI.getOperand(1).getReg() == Mips::A2)
955 else if (MI.getOperand(0).getReg() == Mips::A1 &&
956 MI.getOperand(1).getReg() == Mips::A3)
958 else if (MI.getOperand(0).getReg() == Mips::A2 &&
959 MI.getOperand(1).getReg() == Mips::A3)
961 else if (MI.getOperand(0).getReg() == Mips::A0 &&
962 MI.getOperand(1).getReg() == Mips::S5)
964 else if (MI.getOperand(0).getReg() == Mips::A0 &&
965 MI.getOperand(1).getReg() == Mips::S6)
967 else if (MI.getOperand(0).getReg() == Mips::A0 &&
968 MI.getOperand(1).getReg() == Mips::A1)
970 else if (MI.getOperand(0).getReg() == Mips::A0 &&
971 MI.getOperand(1).getReg() == Mips::A2)
973 else if (MI.getOperand(0).getReg() == Mips::A0 &&
974 MI.getOperand(1).getReg() == Mips::A3)
981 MipsMCCodeEmitter::getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo,
982 SmallVectorImpl<MCFixup> &Fixups,
983 const MCSubtargetInfo &STI) const {
984 const MCOperand &MO = MI.getOperand(OpNo);
985 assert(MO.isImm() && "getSimm23Lsl2Encoding expects only an immediate");
986 // The immediate is encoded as 'immediate >> 2'.
987 unsigned Res = static_cast<unsigned>(MO.getImm());
988 assert((Res & 3) == 0);
992 #include "MipsGenMCCodeEmitter.inc"