1 //===-- MipsASMBackend.cpp - Mips Asm Backend ----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the MipsAsmBackend and MipsELFObjectWriter classes.
12 //===----------------------------------------------------------------------===//
15 #include "MipsFixupKinds.h"
16 #include "MCTargetDesc/MipsMCTargetDesc.h"
17 #include "llvm/ADT/Twine.h"
18 #include "llvm/MC/MCAsmBackend.h"
19 #include "llvm/MC/MCAssembler.h"
20 #include "llvm/MC/MCDirectives.h"
21 #include "llvm/MC/MCELFObjectWriter.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCMachObjectWriter.h"
24 #include "llvm/MC/MCObjectWriter.h"
25 #include "llvm/MC/MCSectionELF.h"
26 #include "llvm/MC/MCSectionMachO.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/Object/MachOFormat.h"
29 #include "llvm/Support/ELF.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/raw_ostream.h"
35 // Prepare value for the target space for it
36 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
38 // Add/subtract and shift
44 case Mips::fixup_Mips_LO16:
46 case Mips::fixup_Mips_PC16:
47 // So far we are only using this type for branches.
48 // For branches we start 1 instruction after the branch
49 // so the displacement will be one instruction size less.
51 // The displacement is then divided by 4 to give us an 18 bit
55 case Mips::fixup_Mips_26:
56 // So far we are only using this type for jumps.
57 // The displacement is then divided by 4 to give us an 28 bit
61 case Mips::fixup_Mips_HI16:
62 case Mips::fixup_Mips_GOT_Local:
63 // Get the higher 16-bits. Also add 1 if bit 15 is 1.
64 Value = (Value >> 16) + ((Value & 0x8000) != 0);
72 class MipsAsmBackend : public MCAsmBackend {
73 Triple::OSType OSType;
74 bool IsLittle; // Big or little endian
77 MipsAsmBackend(const Target &T, Triple::OSType _OSType, bool _isLittle) :
78 MCAsmBackend(), OSType(_OSType), IsLittle(_isLittle) {}
80 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
81 return createMipsELFObjectWriter(OS, OSType, IsLittle);
84 /// ApplyFixup - Apply the \arg Value for given \arg Fixup into the provided
85 /// data fragment, at the offset specified by the fixup and following the
86 /// fixup kind as appropriate.
87 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
88 uint64_t Value) const {
89 MCFixupKind Kind = Fixup.getKind();
90 Value = adjustFixupValue((unsigned)Kind, Value);
93 return; // Doesn't change encoding.
95 unsigned Offset = Fixup.getOffset();
96 // FIXME: The below code will not work across endian models
97 // How many bytes/bits are we fixing up?
98 unsigned NumBytes = ((getFixupKindInfo(Kind).TargetSize-1)/8)+1;
99 uint64_t Mask = ((uint64_t)1 << getFixupKindInfo(Kind).TargetSize) - 1;
101 // Grab current value, if any, from bits.
103 for (unsigned i = 0; i != NumBytes; ++i)
104 CurVal |= ((uint8_t)Data[Offset + i]) << (i * 8);
106 CurVal = (CurVal & ~Mask) | ((CurVal + Value) & Mask);
108 // Write out the bytes back to the code/data bits.
109 // First the unaffected bits and then the fixup.
110 for (unsigned i = 0; i != NumBytes; ++i) {
111 Data[Offset + i] = uint8_t((CurVal >> (i * 8)) & 0xff);
115 unsigned getNumFixupKinds() const { return Mips::NumTargetFixupKinds; }
117 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
118 const static MCFixupKindInfo Infos[Mips::NumTargetFixupKinds] = {
119 // This table *must* be in same the order of fixup_* kinds in
122 // name offset bits flags
123 { "fixup_Mips_16", 0, 16, 0 },
124 { "fixup_Mips_32", 0, 32, 0 },
125 { "fixup_Mips_REL32", 0, 32, 0 },
126 { "fixup_Mips_26", 0, 26, 0 },
127 { "fixup_Mips_HI16", 0, 16, 0 },
128 { "fixup_Mips_LO16", 0, 16, 0 },
129 { "fixup_Mips_GPREL16", 0, 16, 0 },
130 { "fixup_Mips_LITERAL", 0, 16, 0 },
131 { "fixup_Mips_GOT_Global", 0, 16, 0 },
132 { "fixup_Mips_GOT_Local", 0, 16, 0 },
133 { "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
134 { "fixup_Mips_CALL16", 0, 16, 0 },
135 { "fixup_Mips_GPREL32", 0, 32, 0 },
136 { "fixup_Mips_SHIFT5", 6, 5, 0 },
137 { "fixup_Mips_SHIFT6", 6, 5, 0 },
138 { "fixup_Mips_64", 0, 64, 0 },
139 { "fixup_Mips_TLSGD", 0, 16, 0 },
140 { "fixup_Mips_GOTTPREL", 0, 16, 0 },
141 { "fixup_Mips_TPREL_HI", 0, 16, 0 },
142 { "fixup_Mips_TPREL_LO", 0, 16, 0 },
143 { "fixup_Mips_TLSLDM", 0, 16, 0 },
144 { "fixup_Mips_DTPREL_HI", 0, 16, 0 },
145 { "fixup_Mips_DTPREL_LO", 0, 16, 0 },
146 { "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel }
149 if (Kind < FirstTargetFixupKind)
150 return MCAsmBackend::getFixupKindInfo(Kind);
152 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
154 return Infos[Kind - FirstTargetFixupKind];
157 /// @name Target Relaxation Interfaces
160 /// MayNeedRelaxation - Check whether the given instruction may need
163 /// \param Inst - The instruction to test.
164 bool mayNeedRelaxation(const MCInst &Inst) const {
168 /// fixupNeedsRelaxation - Target specific predicate for whether a given
169 /// fixup requires the associated instruction to be relaxed.
170 bool fixupNeedsRelaxation(const MCFixup &Fixup,
172 const MCInstFragment *DF,
173 const MCAsmLayout &Layout) const {
175 assert(0 && "RelaxInstruction() unimplemented");
179 /// RelaxInstruction - Relax the instruction in the given fragment
180 /// to the next wider instruction.
182 /// \param Inst - The instruction to relax, which may be the same
184 /// \parm Res [output] - On return, the relaxed instruction.
185 void relaxInstruction(const MCInst &Inst, MCInst &Res) const {
190 /// WriteNopData - Write an (optimal) nop sequence of Count bytes
191 /// to the given output. If the target cannot generate such a sequence,
192 /// it should return an error.
194 /// \return - True on success.
195 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const {
203 MCAsmBackend *llvm::createMipsAsmBackendEL(const Target &T, StringRef TT) {
204 return new MipsAsmBackend(T, Triple(TT).getOS(),
208 MCAsmBackend *llvm::createMipsAsmBackendEB(const Target &T, StringRef TT) {
209 return new MipsAsmBackend(T, Triple(TT).getOS(),