1 //===-- MipsASMBackend.cpp - ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the MipsAsmBackend and MipsELFObjectWriter classes.
12 //===----------------------------------------------------------------------===//
15 #include "MipsFixupKinds.h"
16 #include "MCTargetDesc/MipsMCTargetDesc.h"
17 #include "llvm/ADT/Twine.h"
18 #include "llvm/MC/MCAsmBackend.h"
19 #include "llvm/MC/MCAssembler.h"
20 #include "llvm/MC/MCDirectives.h"
21 #include "llvm/MC/MCELFObjectWriter.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCMachObjectWriter.h"
24 #include "llvm/MC/MCObjectWriter.h"
25 #include "llvm/MC/MCSectionELF.h"
26 #include "llvm/MC/MCSectionMachO.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/Object/MachOFormat.h"
29 #include "llvm/Support/ELF.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/raw_ostream.h"
35 // Prepare value for the target space for it
36 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
38 // Add/subtract and shift
44 case Mips::fixup_Mips_LO16:
46 case Mips::fixup_Mips_PC16:
47 // So far we are only using this type for branches.
48 // For branches we start 1 instruction after the branch
49 // so the displacement will be one instruction size less.
51 // The displacement is then divided by 4 to give us an 18 bit
55 case Mips::fixup_Mips_26:
56 // So far we are only using this type for jumps.
57 // The displacement is then divided by 4 to give us an 28 bit
61 case Mips::fixup_Mips_HI16:
62 case Mips::fixup_Mips_GOT_Local:
63 // Get the higher 16-bits. Also add 1 if bit 15 is 1.
64 Value = (Value >> 16) + ((Value & 0x8000) != 0);
73 class MipsELFObjectWriter : public MCELFObjectTargetWriter {
75 MipsELFObjectWriter(bool is64Bit, uint8_t OSABI, uint16_t EMachine,
76 bool HasRelocationAddend)
77 : MCELFObjectTargetWriter(is64Bit, OSABI, EMachine,
78 HasRelocationAddend) {}
81 class MipsAsmBackend : public MCAsmBackend {
83 MipsAsmBackend(const Target &T) : MCAsmBackend() {}
85 /// ApplyFixup - Apply the \arg Value for given \arg Fixup into the provided
86 /// data fragment, at the offset specified by the fixup and following the
87 /// fixup kind as appropriate.
88 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
89 uint64_t Value) const {
90 MCFixupKind Kind = Fixup.getKind();
91 Value = adjustFixupValue((unsigned)Kind, Value);
94 return; // Doesn't change encoding.
96 unsigned Offset = Fixup.getOffset();
97 // FIXME: The below code will not work across endian models
98 // How many bytes/bits are we fixing up?
99 unsigned NumBytes = ((getFixupKindInfo(Kind).TargetSize-1)/8)+1;
100 uint64_t Mask = ((uint64_t)1 << getFixupKindInfo(Kind).TargetSize) - 1;
102 // Grab current value, if any, from bits.
104 for (unsigned i = 0; i != NumBytes; ++i)
105 CurVal |= ((uint8_t)Data[Offset + i]) << (i * 8);
107 CurVal = (CurVal & ~Mask) | ((CurVal + Value) & Mask);
109 // Write out the bytes back to the code/data bits.
110 // First the unaffected bits and then the fixup.
111 for (unsigned i = 0; i != NumBytes; ++i) {
112 Data[Offset + i] = uint8_t((CurVal >> (i * 8)) & 0xff);
116 unsigned getNumFixupKinds() const { return Mips::NumTargetFixupKinds; }
118 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
119 const static MCFixupKindInfo Infos[Mips::NumTargetFixupKinds] = {
120 // This table *must* be in same the order of fixup_* kinds in
123 // name offset bits flags
124 { "fixup_Mips_16", 0, 16, 0 },
125 { "fixup_Mips_32", 0, 32, 0 },
126 { "fixup_Mips_REL32", 0, 32, 0 },
127 { "fixup_Mips_26", 0, 26, 0 },
128 { "fixup_Mips_HI16", 0, 16, 0 },
129 { "fixup_Mips_LO16", 0, 16, 0 },
130 { "fixup_Mips_GPREL16", 0, 16, 0 },
131 { "fixup_Mips_LITERAL", 0, 16, 0 },
132 { "fixup_Mips_GOT_Global", 0, 16, 0 },
133 { "fixup_Mips_GOT_Local", 0, 16, 0 },
134 { "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
135 { "fixup_Mips_CALL16", 0, 16, 0 },
136 { "fixup_Mips_GPREL32", 0, 32, 0 },
137 { "fixup_Mips_SHIFT5", 6, 5, 0 },
138 { "fixup_Mips_SHIFT6", 6, 5, 0 },
139 { "fixup_Mips_64", 0, 64, 0 },
140 { "fixup_Mips_TLSGD", 0, 16, 0 },
141 { "fixup_Mips_GOTTPREL", 0, 16, 0 },
142 { "fixup_Mips_TPREL_HI", 0, 16, 0 },
143 { "fixup_Mips_TPREL_LO", 0, 16, 0 },
144 { "fixup_Mips_TLSLDM", 0, 16, 0 },
145 { "fixup_Mips_DTPREL_HI", 0, 16, 0 },
146 { "fixup_Mips_DTPREL_LO", 0, 16, 0 },
147 { "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel }
150 if (Kind < FirstTargetFixupKind)
151 return MCAsmBackend::getFixupKindInfo(Kind);
153 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
155 return Infos[Kind - FirstTargetFixupKind];
158 /// @name Target Relaxation Interfaces
161 /// MayNeedRelaxation - Check whether the given instruction may need
164 /// \param Inst - The instruction to test.
165 bool MayNeedRelaxation(const MCInst &Inst) const {
169 /// fixupNeedsRelaxation - Target specific predicate for whether a given
170 /// fixup requires the associated instruction to be relaxed.
171 bool fixupNeedsRelaxation(const MCFixup &Fixup,
173 const MCInstFragment *DF,
174 const MCAsmLayout &Layout) const {
176 assert(0 && "RelaxInstruction() unimplemented");
180 /// RelaxInstruction - Relax the instruction in the given fragment
181 /// to the next wider instruction.
183 /// \param Inst - The instruction to relax, which may be the same
185 /// \parm Res [output] - On return, the relaxed instruction.
186 void RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
191 /// WriteNopData - Write an (optimal) nop sequence of Count bytes
192 /// to the given output. If the target cannot generate such a sequence,
193 /// it should return an error.
195 /// \return - True on success.
196 bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
201 class MipsEB_AsmBackend : public MipsAsmBackend {
205 MipsEB_AsmBackend(const Target &T, uint8_t _OSABI)
206 : MipsAsmBackend(T), OSABI(_OSABI) {}
208 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
209 return createELFObjectWriter(createELFObjectTargetWriter(),
210 OS, /*IsLittleEndian*/ false);
213 MCELFObjectTargetWriter *createELFObjectTargetWriter() const {
214 return new MipsELFObjectWriter(false, OSABI, ELF::EM_MIPS, false);
218 class MipsEL_AsmBackend : public MipsAsmBackend {
222 MipsEL_AsmBackend(const Target &T, uint8_t _OSABI)
223 : MipsAsmBackend(T), OSABI(_OSABI) {}
225 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
226 return createELFObjectWriter(createELFObjectTargetWriter(),
227 OS, /*IsLittleEndian*/ true);
230 MCELFObjectTargetWriter *createELFObjectTargetWriter() const {
231 return new MipsELFObjectWriter(false, OSABI, ELF::EM_MIPS, false);
236 MCAsmBackend *llvm::createMipsAsmBackend(const Target &T, StringRef TT) {
237 Triple TheTriple(TT);
239 // just return little endian for now
241 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS());
242 return new MipsEL_AsmBackend(T, OSABI);