lib/Target/Mips/Disassembler/MipsDisassembler.cpp

   1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file is part of the Mips Disassembler.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Mips.h"
  15 #include "MipsRegisterInfo.h"
  16 #include "MipsSubtarget.h"
  17 #include "llvm/MC/MCContext.h"
  18 #include "llvm/MC/MCDisassembler.h"
  19 #include "llvm/MC/MCFixedLenDisassembler.h"
  20 #include "llvm/MC/MCInst.h"
  21 #include "llvm/MC/MCSubtargetInfo.h"
  22 #include "llvm/Support/MathExtras.h"
  23 #include "llvm/Support/TargetRegistry.h"
  24
  25 using namespace llvm;
  26
  27 #define DEBUG_TYPE "mips-disassembler"
  28
  29 typedef MCDisassembler::DecodeStatus DecodeStatus;
  30
  31 namespace {
  32
  33 /// A disasembler class for Mips.
  34 class MipsDisassemblerBase : public MCDisassembler {
  35 public:
  36   MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx,
  37                        bool IsBigEndian)
  38       : MCDisassembler(STI, Ctx),
  39         IsGP64Bit(STI.getFeatureBits() & Mips::FeatureGP64Bit),
  40         IsBigEndian(IsBigEndian) {}
  41
  42   virtual ~MipsDisassemblerBase() {}
  43
  44   bool isGP64Bit() const { return IsGP64Bit; }
  45
  46 private:
  47   bool IsGP64Bit;
  48 protected:
  49   bool IsBigEndian;
  50 };
  51
  52 /// A disasembler class for Mips32.
  53 class MipsDisassembler : public MipsDisassemblerBase {
  54   bool IsMicroMips;
  55 public:
  56   MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool bigEndian)
  57       : MipsDisassemblerBase(STI, Ctx, bigEndian) {
  58     IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
  59   }
  60
  61   bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; }
  62   bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; }
  63   bool hasMips32r6() const {
  64     return STI.getFeatureBits() & Mips::FeatureMips32r6;
  65   }
  66
  67   bool isGP64() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; }
  68
  69   bool hasCOP3() const {
  70     // Only present in MIPS-I and MIPS-II
  71     return !hasMips32() && !hasMips3();
  72   }
  73
  74   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
  75                               ArrayRef<uint8_t> Bytes, uint64_t Address,
  76                               raw_ostream &VStream,
  77                               raw_ostream &CStream) const override;
  78 };
  79
  80 /// A disasembler class for Mips64.
  81 class Mips64Disassembler : public MipsDisassemblerBase {
  82 public:
  83   Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
  84                      bool bigEndian) :
  85     MipsDisassemblerBase(STI, Ctx, bigEndian) {}
  86
  87   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
  88                               ArrayRef<uint8_t> Bytes, uint64_t Address,
  89                               raw_ostream &VStream,
  90                               raw_ostream &CStream) const override;
  91 };
  92
  93 } // end anonymous namespace
  94
  95 // Forward declare these because the autogenerated code will reference them.
  96 // Definitions are further down.
  97 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
  98                                              unsigned RegNo,
  99                                              uint64_t Address,
 100                                              const void *Decoder);
 101
 102 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 103                                                  unsigned RegNo,
 104                                                  uint64_t Address,
 105                                                  const void *Decoder);
 106
 107 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
 108                                                unsigned RegNo,
 109                                                uint64_t Address,
 110                                                const void *Decoder);
 111
 112 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
 113                                                    unsigned RegNo,
 114                                                    uint64_t Address,
 115                                                    const void *Decoder);
 116
 117 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 118                                              unsigned RegNo,
 119                                              uint64_t Address,
 120                                              const void *Decoder);
 121
 122 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 123                                            unsigned Insn,
 124                                            uint64_t Address,
 125                                            const void *Decoder);
 126
 127 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 128                                             unsigned RegNo,
 129                                             uint64_t Address,
 130                                             const void *Decoder);
 131
 132 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 133                                              unsigned RegNo,
 134                                              uint64_t Address,
 135                                              const void *Decoder);
 136
 137 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 138                                              unsigned RegNo,
 139                                              uint64_t Address,
 140                                              const void *Decoder);
 141
 142 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 143                                            unsigned RegNo,
 144                                            uint64_t Address,
 145                                            const void *Decoder);
 146
 147 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 148                                            unsigned RegNo,
 149                                            uint64_t Address,
 150                                            const void *Decoder);
 151
 152 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
 153                                              uint64_t Address,
 154                                              const void *Decoder);
 155
 156 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 157                                               unsigned Insn,
 158                                               uint64_t Address,
 159                                               const void *Decoder);
 160
 161 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 162                                               unsigned RegNo,
 163                                               uint64_t Address,
 164                                               const void *Decoder);
 165
 166 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 167                                                 unsigned RegNo,
 168                                                 uint64_t Address,
 169                                                 const void *Decoder);
 170
 171 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 172                                                unsigned RegNo,
 173                                                uint64_t Address,
 174                                                const void *Decoder);
 175
 176 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 177                                                unsigned RegNo,
 178                                                uint64_t Address,
 179                                                const void *Decoder);
 180
 181 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
 182                                                unsigned RegNo,
 183                                                uint64_t Address,
 184                                                const void *Decoder);
 185
 186 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 187                                                unsigned RegNo,
 188                                                uint64_t Address,
 189                                                const void *Decoder);
 190
 191 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 192                                                unsigned RegNo,
 193                                                uint64_t Address,
 194                                                const void *Decoder);
 195
 196 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 197                                                unsigned RegNo,
 198                                                uint64_t Address,
 199                                                const void *Decoder);
 200
 201 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
 202                                                unsigned RegNo,
 203                                                uint64_t Address,
 204                                                const void *Decoder);
 205
 206 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
 207                                             unsigned RegNo,
 208                                             uint64_t Address,
 209                                             const void *Decoder);
 210
 211 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 212                                        unsigned Offset,
 213                                        uint64_t Address,
 214                                        const void *Decoder);
 215
 216 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 217                                      unsigned Insn,
 218                                      uint64_t Address,
 219                                      const void *Decoder);
 220
 221 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
 222                                          unsigned Offset,
 223                                          uint64_t Address,
 224                                          const void *Decoder);
 225
 226 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
 227                                          unsigned Offset,
 228                                          uint64_t Address,
 229                                          const void *Decoder);
 230
 231 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
 232 // shifted left by 1 bit.
 233 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
 234                                           unsigned Offset,
 235                                           uint64_t Address,
 236                                           const void *Decoder);
 237
 238 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
 239 // shifted left by 1 bit.
 240 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
 241                                          unsigned Offset,
 242                                          uint64_t Address,
 243                                          const void *Decoder);
 244
 245 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
 246 // shifted left by 1 bit.
 247 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
 248                                        unsigned Insn,
 249                                        uint64_t Address,
 250                                        const void *Decoder);
 251
 252 static DecodeStatus DecodeMem(MCInst &Inst,
 253                               unsigned Insn,
 254                               uint64_t Address,
 255                               const void *Decoder);
 256
 257 static DecodeStatus DecodeCacheOp(MCInst &Inst,
 258                               unsigned Insn,
 259                               uint64_t Address,
 260                               const void *Decoder);
 261
 262 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
 263                                     unsigned Insn,
 264                                     uint64_t Address,
 265                                     const void *Decoder);
 266
 267 static DecodeStatus DecodeSyncI(MCInst &Inst,
 268                                 unsigned Insn,
 269                                 uint64_t Address,
 270                                 const void *Decoder);
 271
 272 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 273                                     uint64_t Address, const void *Decoder);
 274
 275 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
 276                                     unsigned Insn,
 277                                     uint64_t Address,
 278                                     const void *Decoder);
 279
 280 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
 281                                           unsigned Insn,
 282                                           uint64_t Address,
 283                                           const void *Decoder);
 284
 285 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 286                                      unsigned Insn,
 287                                      uint64_t Address,
 288                                      const void *Decoder);
 289
 290 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 291                                      unsigned Insn,
 292                                      uint64_t Address,
 293                                      const void *Decoder);
 294
 295 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
 296                                uint64_t Address,
 297                                const void *Decoder);
 298
 299 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
 300                                uint64_t Address,
 301                                const void *Decoder);
 302
 303 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn,
 304                                uint64_t Address,
 305                                const void *Decoder);
 306
 307 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
 308                                uint64_t Address,
 309                                const void *Decoder);
 310
 311 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
 312                                        unsigned Insn,
 313                                        uint64_t Address,
 314                                        const void *Decoder);
 315
 316 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
 317                                        unsigned Value,
 318                                        uint64_t Address,
 319                                        const void *Decoder);
 320
 321 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
 322                                     unsigned Value,
 323                                     uint64_t Address,
 324                                     const void *Decoder);
 325
 326 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
 327                                   unsigned Value,
 328                                   uint64_t Address,
 329                                   const void *Decoder);
 330
 331 static DecodeStatus DecodeSimm4(MCInst &Inst,
 332                                 unsigned Value,
 333                                 uint64_t Address,
 334                                 const void *Decoder);
 335
 336 static DecodeStatus DecodeSimm16(MCInst &Inst,
 337                                  unsigned Insn,
 338                                  uint64_t Address,
 339                                  const void *Decoder);
 340
 341 // Decode the immediate field of an LSA instruction which
 342 // is off by one.
 343 static DecodeStatus DecodeLSAImm(MCInst &Inst,
 344                                  unsigned Insn,
 345                                  uint64_t Address,
 346                                  const void *Decoder);
 347
 348 static DecodeStatus DecodeInsSize(MCInst &Inst,
 349                                   unsigned Insn,
 350                                   uint64_t Address,
 351                                   const void *Decoder);
 352
 353 static DecodeStatus DecodeExtSize(MCInst &Inst,
 354                                   unsigned Insn,
 355                                   uint64_t Address,
 356                                   const void *Decoder);
 357
 358 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
 359                                      uint64_t Address, const void *Decoder);
 360
 361 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
 362                                      uint64_t Address, const void *Decoder);
 363
 364 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
 365                                   uint64_t Address, const void *Decoder);
 366
 367 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
 368                                     uint64_t Address, const void *Decoder);
 369
 370 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
 371                                    uint64_t Address, const void *Decoder);
 372
 373 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
 374 /// handle.
 375 template <typename InsnType>
 376 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 377                                    const void *Decoder);
 378
 379 template <typename InsnType>
 380 static DecodeStatus
 381 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 382                       const void *Decoder);
 383
 384 template <typename InsnType>
 385 static DecodeStatus
 386 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 387                        const void *Decoder);
 388
 389 template <typename InsnType>
 390 static DecodeStatus
 391 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 392                        const void *Decoder);
 393
 394 template <typename InsnType>
 395 static DecodeStatus
 396 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 397                        const void *Decoder);
 398
 399 template <typename InsnType>
 400 static DecodeStatus
 401 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 402                       const void *Decoder);
 403
 404 template <typename InsnType>
 405 static DecodeStatus
 406 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 407                        const void *Decoder);
 408
 409 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
 410                                          uint64_t Address,
 411                                          const void *Decoder);
 412
 413 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
 414                                            uint64_t Address,
 415                                            const void *Decoder);
 416
 417 namespace llvm {
 418 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
 419               TheMips64elTarget;
 420 }
 421
 422 static MCDisassembler *createMipsDisassembler(
 423                        const Target &T,
 424                        const MCSubtargetInfo &STI,
 425                        MCContext &Ctx) {
 426   return new MipsDisassembler(STI, Ctx, true);
 427 }
 428
 429 static MCDisassembler *createMipselDisassembler(
 430                        const Target &T,
 431                        const MCSubtargetInfo &STI,
 432                        MCContext &Ctx) {
 433   return new MipsDisassembler(STI, Ctx, false);
 434 }
 435
 436 static MCDisassembler *createMips64Disassembler(
 437                        const Target &T,
 438                        const MCSubtargetInfo &STI,
 439                        MCContext &Ctx) {
 440   return new Mips64Disassembler(STI, Ctx, true);
 441 }
 442
 443 static MCDisassembler *createMips64elDisassembler(
 444                        const Target &T,
 445                        const MCSubtargetInfo &STI,
 446                        MCContext &Ctx) {
 447   return new Mips64Disassembler(STI, Ctx, false);
 448 }
 449
 450 extern "C" void LLVMInitializeMipsDisassembler() {
 451   // Register the disassembler.
 452   TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
 453                                          createMipsDisassembler);
 454   TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
 455                                          createMipselDisassembler);
 456   TargetRegistry::RegisterMCDisassembler(TheMips64Target,
 457                                          createMips64Disassembler);
 458   TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
 459                                          createMips64elDisassembler);
 460 }
 461
 462 #include "MipsGenDisassemblerTables.inc"
 463
 464 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 465   const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
 466   const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
 467   return *(RegInfo->getRegClass(RC).begin() + RegNo);
 468 }
 469
 470 template <typename InsnType>
 471 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 472                                    const void *Decoder) {
 473   typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
 474   // The size of the n field depends on the element size
 475   // The register class also depends on this.
 476   InsnType tmp = fieldFromInstruction(insn, 17, 5);
 477   unsigned NSize = 0;
 478   DecodeFN RegDecoder = nullptr;
 479   if ((tmp & 0x18) == 0x00) { // INSVE_B
 480     NSize = 4;
 481     RegDecoder = DecodeMSA128BRegisterClass;
 482   } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
 483     NSize = 3;
 484     RegDecoder = DecodeMSA128HRegisterClass;
 485   } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
 486     NSize = 2;
 487     RegDecoder = DecodeMSA128WRegisterClass;
 488   } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
 489     NSize = 1;
 490     RegDecoder = DecodeMSA128DRegisterClass;
 491   } else
 492     llvm_unreachable("Invalid encoding");
 493
 494   assert(NSize != 0 && RegDecoder != nullptr);
 495
 496   // $wd
 497   tmp = fieldFromInstruction(insn, 6, 5);
 498   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 499     return MCDisassembler::Fail;
 500   // $wd_in
 501   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 502     return MCDisassembler::Fail;
 503   // $n
 504   tmp = fieldFromInstruction(insn, 16, NSize);
 505   MI.addOperand(MCOperand::CreateImm(tmp));
 506   // $ws
 507   tmp = fieldFromInstruction(insn, 11, 5);
 508   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 509     return MCDisassembler::Fail;
 510   // $n2
 511   MI.addOperand(MCOperand::CreateImm(0));
 512
 513   return MCDisassembler::Success;
 514 }
 515
 516 template <typename InsnType>
 517 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
 518                                           uint64_t Address,
 519                                           const void *Decoder) {
 520   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 521   // (otherwise we would have matched the ADDI instruction from the earlier
 522   // ISA's instead).
 523   //
 524   // We have:
 525   //    0b001000 sssss ttttt iiiiiiiiiiiiiiii
 526   //      BOVC if rs >= rt
 527   //      BEQZALC if rs == 0 && rt != 0
 528   //      BEQC if rs < rt && rs != 0
 529
 530   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 531   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 532   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 533   bool HasRs = false;
 534
 535   if (Rs >= Rt) {
 536     MI.setOpcode(Mips::BOVC);
 537     HasRs = true;
 538   } else if (Rs != 0 && Rs < Rt) {
 539     MI.setOpcode(Mips::BEQC);
 540     HasRs = true;
 541   } else
 542     MI.setOpcode(Mips::BEQZALC);
 543
 544   if (HasRs)
 545     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 546                                        Rs)));
 547
 548   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 549                                      Rt)));
 550   MI.addOperand(MCOperand::CreateImm(Imm));
 551
 552   return MCDisassembler::Success;
 553 }
 554
 555 template <typename InsnType>
 556 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
 557                                            uint64_t Address,
 558                                            const void *Decoder) {
 559   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 560   // (otherwise we would have matched the ADDI instruction from the earlier
 561   // ISA's instead).
 562   //
 563   // We have:
 564   //    0b011000 sssss ttttt iiiiiiiiiiiiiiii
 565   //      BNVC if rs >= rt
 566   //      BNEZALC if rs == 0 && rt != 0
 567   //      BNEC if rs < rt && rs != 0
 568
 569   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 570   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 571   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 572   bool HasRs = false;
 573
 574   if (Rs >= Rt) {
 575     MI.setOpcode(Mips::BNVC);
 576     HasRs = true;
 577   } else if (Rs != 0 && Rs < Rt) {
 578     MI.setOpcode(Mips::BNEC);
 579     HasRs = true;
 580   } else
 581     MI.setOpcode(Mips::BNEZALC);
 582
 583   if (HasRs)
 584     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 585                                        Rs)));
 586
 587   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 588                                      Rt)));
 589   MI.addOperand(MCOperand::CreateImm(Imm));
 590
 591   return MCDisassembler::Success;
 592 }
 593
 594 template <typename InsnType>
 595 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
 596                                            uint64_t Address,
 597                                            const void *Decoder) {
 598   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 599   // (otherwise we would have matched the BLEZL instruction from the earlier
 600   // ISA's instead).
 601   //
 602   // We have:
 603   //    0b010110 sssss ttttt iiiiiiiiiiiiiiii
 604   //      Invalid if rs == 0
 605   //      BLEZC   if rs == 0  && rt != 0
 606   //      BGEZC   if rs == rt && rt != 0
 607   //      BGEC    if rs != rt && rs != 0  && rt != 0
 608
 609   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 610   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 611   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 612   bool HasRs = false;
 613
 614   if (Rt == 0)
 615     return MCDisassembler::Fail;
 616   else if (Rs == 0)
 617     MI.setOpcode(Mips::BLEZC);
 618   else if (Rs == Rt)
 619     MI.setOpcode(Mips::BGEZC);
 620   else {
 621     HasRs = true;
 622     MI.setOpcode(Mips::BGEC);
 623   }
 624
 625   if (HasRs)
 626     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 627                                        Rs)));
 628
 629   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 630                                      Rt)));
 631
 632   MI.addOperand(MCOperand::CreateImm(Imm));
 633
 634   return MCDisassembler::Success;
 635 }
 636
 637 template <typename InsnType>
 638 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
 639                                            uint64_t Address,
 640                                            const void *Decoder) {
 641   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 642   // (otherwise we would have matched the BGTZL instruction from the earlier
 643   // ISA's instead).
 644   //
 645   // We have:
 646   //    0b010111 sssss ttttt iiiiiiiiiiiiiiii
 647   //      Invalid if rs == 0
 648   //      BGTZC   if rs == 0  && rt != 0
 649   //      BLTZC   if rs == rt && rt != 0
 650   //      BLTC    if rs != rt && rs != 0  && rt != 0
 651
 652   bool HasRs = false;
 653
 654   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 655   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 656   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 657
 658   if (Rt == 0)
 659     return MCDisassembler::Fail;
 660   else if (Rs == 0)
 661     MI.setOpcode(Mips::BGTZC);
 662   else if (Rs == Rt)
 663     MI.setOpcode(Mips::BLTZC);
 664   else {
 665     MI.setOpcode(Mips::BLTC);
 666     HasRs = true;
 667   }
 668
 669   if (HasRs)
 670     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 671                                               Rs)));
 672
 673   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 674                                      Rt)));
 675
 676   MI.addOperand(MCOperand::CreateImm(Imm));
 677
 678   return MCDisassembler::Success;
 679 }
 680
 681 template <typename InsnType>
 682 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
 683                                           uint64_t Address,
 684                                           const void *Decoder) {
 685   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 686   // (otherwise we would have matched the BGTZ instruction from the earlier
 687   // ISA's instead).
 688   //
 689   // We have:
 690   //    0b000111 sssss ttttt iiiiiiiiiiiiiiii
 691   //      BGTZ    if rt == 0
 692   //      BGTZALC if rs == 0 && rt != 0
 693   //      BLTZALC if rs != 0 && rs == rt
 694   //      BLTUC   if rs != 0 && rs != rt
 695
 696   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 697   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 698   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 699   bool HasRs = false;
 700   bool HasRt = false;
 701
 702   if (Rt == 0) {
 703     MI.setOpcode(Mips::BGTZ);
 704     HasRs = true;
 705   } else if (Rs == 0) {
 706     MI.setOpcode(Mips::BGTZALC);
 707     HasRt = true;
 708   } else if (Rs == Rt) {
 709     MI.setOpcode(Mips::BLTZALC);
 710     HasRs = true;
 711   } else {
 712     MI.setOpcode(Mips::BLTUC);
 713     HasRs = true;
 714     HasRt = true;
 715   }
 716
 717   if (HasRs)
 718     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 719                                        Rs)));
 720
 721   if (HasRt)
 722     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 723                                        Rt)));
 724
 725   MI.addOperand(MCOperand::CreateImm(Imm));
 726
 727   return MCDisassembler::Success;
 728 }
 729
 730 template <typename InsnType>
 731 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
 732                                            uint64_t Address,
 733                                            const void *Decoder) {
 734   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 735   // (otherwise we would have matched the BLEZL instruction from the earlier
 736   // ISA's instead).
 737   //
 738   // We have:
 739   //    0b000110 sssss ttttt iiiiiiiiiiiiiiii
 740   //      Invalid   if rs == 0
 741   //      BLEZALC   if rs == 0  && rt != 0
 742   //      BGEZALC   if rs == rt && rt != 0
 743   //      BGEUC     if rs != rt && rs != 0  && rt != 0
 744
 745   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 746   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 747   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 748   bool HasRs = false;
 749
 750   if (Rt == 0)
 751     return MCDisassembler::Fail;
 752   else if (Rs == 0)
 753     MI.setOpcode(Mips::BLEZALC);
 754   else if (Rs == Rt)
 755     MI.setOpcode(Mips::BGEZALC);
 756   else {
 757     HasRs = true;
 758     MI.setOpcode(Mips::BGEUC);
 759   }
 760
 761   if (HasRs)
 762     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 763                                        Rs)));
 764   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 765                                      Rt)));
 766
 767   MI.addOperand(MCOperand::CreateImm(Imm));
 768
 769   return MCDisassembler::Success;
 770 }
 771
 772 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted
 773 /// according to the given endianess.
 774 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
 775                                       uint64_t &Size, uint32_t &Insn,
 776                                       bool IsBigEndian) {
 777   // We want to read exactly 2 Bytes of data.
 778   if (Bytes.size() < 2) {
 779     Size = 0;
 780     return MCDisassembler::Fail;
 781   }
 782
 783   if (IsBigEndian) {
 784     Insn = (Bytes[0] << 8) | Bytes[1];
 785   } else {
 786     Insn = (Bytes[1] << 8) | Bytes[0];
 787   }
 788
 789   return MCDisassembler::Success;
 790 }
 791
 792 /// Read four bytes from the ArrayRef and return 32 bit word sorted
 793 /// according to the given endianess
 794 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
 795                                       uint64_t &Size, uint32_t &Insn,
 796                                       bool IsBigEndian, bool IsMicroMips) {
 797   // We want to read exactly 4 Bytes of data.
 798   if (Bytes.size() < 4) {
 799     Size = 0;
 800     return MCDisassembler::Fail;
 801   }
 802
 803   // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
 804   // always precede the low 16 bits in the instruction stream (that is, they
 805   // are placed at lower addresses in the instruction stream).
 806   //
 807   // microMIPS byte ordering:
 808   //   Big-endian:    0 | 1 | 2 | 3
 809   //   Little-endian: 1 | 0 | 3 | 2
 810
 811   if (IsBigEndian) {
 812     // Encoded as a big-endian 32-bit word in the stream.
 813     Insn =
 814         (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
 815   } else {
 816     if (IsMicroMips) {
 817       Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
 818              (Bytes[1] << 24);
 819     } else {
 820       Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
 821              (Bytes[3] << 24);
 822     }
 823   }
 824
 825   return MCDisassembler::Success;
 826 }
 827
 828 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
 829                                               ArrayRef<uint8_t> Bytes,
 830                                               uint64_t Address,
 831                                               raw_ostream &VStream,
 832                                               raw_ostream &CStream) const {
 833   uint32_t Insn;
 834   DecodeStatus Result;
 835
 836   if (IsMicroMips) {
 837     Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
 838
 839     DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
 840     // Calling the auto-generated decoder function.
 841     Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
 842                                this, STI);
 843     if (Result != MCDisassembler::Fail) {
 844       Size = 2;
 845       return Result;
 846     }
 847
 848     Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
 849     if (Result == MCDisassembler::Fail)
 850       return MCDisassembler::Fail;
 851
 852     DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
 853     // Calling the auto-generated decoder function.
 854     Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
 855                                this, STI);
 856     if (Result != MCDisassembler::Fail) {
 857       Size = 4;
 858       return Result;
 859     }
 860     return MCDisassembler::Fail;
 861   }
 862
 863   Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
 864   if (Result == MCDisassembler::Fail)
 865     return MCDisassembler::Fail;
 866
 867   if (hasCOP3()) {
 868     DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
 869     Result =
 870         decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
 871     if (Result != MCDisassembler::Fail) {
 872       Size = 4;
 873       return Result;
 874     }
 875   }
 876
 877   if (hasMips32r6() && isGP64()) {
 878     DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
 879     Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
 880                                Address, this, STI);
 881     if (Result != MCDisassembler::Fail) {
 882       Size = 4;
 883       return Result;
 884     }
 885   }
 886
 887   if (hasMips32r6()) {
 888     DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
 889     Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
 890                                Address, this, STI);
 891     if (Result != MCDisassembler::Fail) {
 892       Size = 4;
 893       return Result;
 894     }
 895   }
 896
 897   DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
 898   // Calling the auto-generated decoder function.
 899   Result =
 900       decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
 901   if (Result != MCDisassembler::Fail) {
 902     Size = 4;
 903     return Result;
 904   }
 905
 906   return MCDisassembler::Fail;
 907 }
 908
 909 DecodeStatus Mips64Disassembler::getInstruction(MCInst &Instr, uint64_t &Size,
 910                                                 ArrayRef<uint8_t> Bytes,
 911                                                 uint64_t Address,
 912                                                 raw_ostream &VStream,
 913                                                 raw_ostream &CStream) const {
 914   uint32_t Insn;
 915
 916   DecodeStatus Result =
 917       readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
 918   if (Result == MCDisassembler::Fail)
 919     return MCDisassembler::Fail;
 920
 921   // Calling the auto-generated decoder function.
 922   Result =
 923       decodeInstruction(DecoderTableMips6432, Instr, Insn, Address, this, STI);
 924   if (Result != MCDisassembler::Fail) {
 925     Size = 4;
 926     return Result;
 927   }
 928   // If we fail to decode in Mips64 decoder space we can try in Mips32
 929   Result =
 930       decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
 931   if (Result != MCDisassembler::Fail) {
 932     Size = 4;
 933     return Result;
 934   }
 935
 936   return MCDisassembler::Fail;
 937 }
 938
 939 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 940                                                  unsigned RegNo,
 941                                                  uint64_t Address,
 942                                                  const void *Decoder) {
 943
 944   return MCDisassembler::Fail;
 945
 946 }
 947
 948 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
 949                                              unsigned RegNo,
 950                                              uint64_t Address,
 951                                              const void *Decoder) {
 952
 953   if (RegNo > 31)
 954     return MCDisassembler::Fail;
 955
 956   unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
 957   Inst.addOperand(MCOperand::CreateReg(Reg));
 958   return MCDisassembler::Success;
 959 }
 960
 961 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
 962                                                unsigned RegNo,
 963                                                uint64_t Address,
 964                                                const void *Decoder) {
 965   if (RegNo > 7)
 966     return MCDisassembler::Fail;
 967   unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
 968   Inst.addOperand(MCOperand::CreateReg(Reg));
 969   return MCDisassembler::Success;
 970 }
 971
 972 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
 973                                                    unsigned RegNo,
 974                                                    uint64_t Address,
 975                                                    const void *Decoder) {
 976   if (RegNo > 7)
 977     return MCDisassembler::Fail;
 978   unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
 979   Inst.addOperand(MCOperand::CreateReg(Reg));
 980   return MCDisassembler::Success;
 981 }
 982
 983 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 984                                              unsigned RegNo,
 985                                              uint64_t Address,
 986                                              const void *Decoder) {
 987   if (RegNo > 31)
 988     return MCDisassembler::Fail;
 989   unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
 990   Inst.addOperand(MCOperand::CreateReg(Reg));
 991   return MCDisassembler::Success;
 992 }
 993
 994 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 995                                            unsigned RegNo,
 996                                            uint64_t Address,
 997                                            const void *Decoder) {
 998   if (static_cast<const MipsDisassembler *>(Decoder)->isGP64Bit())
 999     return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
1000
1001   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1002 }
1003
1004 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
1005                                             unsigned RegNo,
1006                                             uint64_t Address,
1007                                             const void *Decoder) {
1008   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1009 }
1010
1011 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
1012                                              unsigned RegNo,
1013                                              uint64_t Address,
1014                                              const void *Decoder) {
1015   if (RegNo > 31)
1016     return MCDisassembler::Fail;
1017
1018   unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
1019   Inst.addOperand(MCOperand::CreateReg(Reg));
1020   return MCDisassembler::Success;
1021 }
1022
1023 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
1024                                              unsigned RegNo,
1025                                              uint64_t Address,
1026                                              const void *Decoder) {
1027   if (RegNo > 31)
1028     return MCDisassembler::Fail;
1029
1030   unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
1031   Inst.addOperand(MCOperand::CreateReg(Reg));
1032   return MCDisassembler::Success;
1033 }
1034
1035 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
1036                                            unsigned RegNo,
1037                                            uint64_t Address,
1038                                            const void *Decoder) {
1039   if (RegNo > 31)
1040     return MCDisassembler::Fail;
1041   unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
1042   Inst.addOperand(MCOperand::CreateReg(Reg));
1043   return MCDisassembler::Success;
1044 }
1045
1046 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
1047                                            unsigned RegNo,
1048                                            uint64_t Address,
1049                                            const void *Decoder) {
1050   if (RegNo > 7)
1051     return MCDisassembler::Fail;
1052   unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
1053   Inst.addOperand(MCOperand::CreateReg(Reg));
1054   return MCDisassembler::Success;
1055 }
1056
1057 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
1058                                              uint64_t Address,
1059                                              const void *Decoder) {
1060   if (RegNo > 31)
1061     return MCDisassembler::Fail;
1062
1063   unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
1064   Inst.addOperand(MCOperand::CreateReg(Reg));
1065   return MCDisassembler::Success;
1066 }
1067
1068 static DecodeStatus DecodeMem(MCInst &Inst,
1069                               unsigned Insn,
1070                               uint64_t Address,
1071                               const void *Decoder) {
1072   int Offset = SignExtend32<16>(Insn & 0xffff);
1073   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1074   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1075
1076   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1077   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1078
1079   if(Inst.getOpcode() == Mips::SC ||
1080      Inst.getOpcode() == Mips::SCD){
1081     Inst.addOperand(MCOperand::CreateReg(Reg));
1082   }
1083
1084   Inst.addOperand(MCOperand::CreateReg(Reg));
1085   Inst.addOperand(MCOperand::CreateReg(Base));
1086   Inst.addOperand(MCOperand::CreateImm(Offset));
1087
1088   return MCDisassembler::Success;
1089 }
1090
1091 static DecodeStatus DecodeCacheOp(MCInst &Inst,
1092                               unsigned Insn,
1093                               uint64_t Address,
1094                               const void *Decoder) {
1095   int Offset = SignExtend32<16>(Insn & 0xffff);
1096   unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1097   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1098
1099   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1100
1101   Inst.addOperand(MCOperand::CreateReg(Base));
1102   Inst.addOperand(MCOperand::CreateImm(Offset));
1103   Inst.addOperand(MCOperand::CreateImm(Hint));
1104
1105   return MCDisassembler::Success;
1106 }
1107
1108 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
1109                                     unsigned Insn,
1110                                     uint64_t Address,
1111                                     const void *Decoder) {
1112   int Offset = SignExtend32<12>(Insn & 0xfff);
1113   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1114   unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1115
1116   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1117
1118   Inst.addOperand(MCOperand::CreateReg(Base));
1119   Inst.addOperand(MCOperand::CreateImm(Offset));
1120   Inst.addOperand(MCOperand::CreateImm(Hint));
1121
1122   return MCDisassembler::Success;
1123 }
1124
1125 static DecodeStatus DecodeSyncI(MCInst &Inst,
1126                               unsigned Insn,
1127                               uint64_t Address,
1128                               const void *Decoder) {
1129   int Offset = SignExtend32<16>(Insn & 0xffff);
1130   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1131
1132   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1133
1134   Inst.addOperand(MCOperand::CreateReg(Base));
1135   Inst.addOperand(MCOperand::CreateImm(Offset));
1136
1137   return MCDisassembler::Success;
1138 }
1139
1140 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1141                                     uint64_t Address, const void *Decoder) {
1142   int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1143   unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1144   unsigned Base = fieldFromInstruction(Insn, 11, 5);
1145
1146   Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1147   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1148
1149   Inst.addOperand(MCOperand::CreateReg(Reg));
1150   Inst.addOperand(MCOperand::CreateReg(Base));
1151
1152   // The immediate field of an LD/ST instruction is scaled which means it must
1153   // be multiplied (when decoding) by the size (in bytes) of the instructions'
1154   // data format.
1155   // .b - 1 byte
1156   // .h - 2 bytes
1157   // .w - 4 bytes
1158   // .d - 8 bytes
1159   switch(Inst.getOpcode())
1160   {
1161   default:
1162     assert (0 && "Unexpected instruction");
1163     return MCDisassembler::Fail;
1164     break;
1165   case Mips::LD_B:
1166   case Mips::ST_B:
1167     Inst.addOperand(MCOperand::CreateImm(Offset));
1168     break;
1169   case Mips::LD_H:
1170   case Mips::ST_H:
1171     Inst.addOperand(MCOperand::CreateImm(Offset * 2));
1172     break;
1173   case Mips::LD_W:
1174   case Mips::ST_W:
1175     Inst.addOperand(MCOperand::CreateImm(Offset * 4));
1176     break;
1177   case Mips::LD_D:
1178   case Mips::ST_D:
1179     Inst.addOperand(MCOperand::CreateImm(Offset * 8));
1180     break;
1181   }
1182
1183   return MCDisassembler::Success;
1184 }
1185
1186 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
1187                                     unsigned Insn,
1188                                     uint64_t Address,
1189                                     const void *Decoder) {
1190   unsigned Offset = Insn & 0xf;
1191   unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1192   unsigned Base = fieldFromInstruction(Insn, 4, 3);
1193
1194   switch (Inst.getOpcode()) {
1195     case Mips::LBU16_MM:
1196     case Mips::LHU16_MM:
1197     case Mips::LW16_MM:
1198       if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1199             == MCDisassembler::Fail)
1200         return MCDisassembler::Fail;
1201       break;
1202     case Mips::SB16_MM:
1203     case Mips::SH16_MM:
1204     case Mips::SW16_MM:
1205       if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1206             == MCDisassembler::Fail)
1207         return MCDisassembler::Fail;
1208       break;
1209   }
1210
1211   if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1212         == MCDisassembler::Fail)
1213     return MCDisassembler::Fail;
1214
1215   switch (Inst.getOpcode()) {
1216     case Mips::LBU16_MM:
1217       if (Offset == 0xf)
1218         Inst.addOperand(MCOperand::CreateImm(-1));
1219       else
1220         Inst.addOperand(MCOperand::CreateImm(Offset));
1221       break;
1222     case Mips::SB16_MM:
1223       Inst.addOperand(MCOperand::CreateImm(Offset));
1224       break;
1225     case Mips::LHU16_MM:
1226     case Mips::SH16_MM:
1227       Inst.addOperand(MCOperand::CreateImm(Offset << 1));
1228       break;
1229     case Mips::LW16_MM:
1230     case Mips::SW16_MM:
1231       Inst.addOperand(MCOperand::CreateImm(Offset << 2));
1232       break;
1233   }
1234
1235   return MCDisassembler::Success;
1236 }
1237
1238 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
1239                                           unsigned Insn,
1240                                           uint64_t Address,
1241                                           const void *Decoder) {
1242   unsigned Offset = Insn & 0x1F;
1243   unsigned Reg = fieldFromInstruction(Insn, 5, 5);
1244
1245   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1246
1247   Inst.addOperand(MCOperand::CreateReg(Reg));
1248   Inst.addOperand(MCOperand::CreateReg(Mips::SP));
1249   Inst.addOperand(MCOperand::CreateImm(Offset << 2));
1250
1251   return MCDisassembler::Success;
1252 }
1253
1254 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1255                                      unsigned Insn,
1256                                      uint64_t Address,
1257                                      const void *Decoder) {
1258   int Offset = SignExtend32<12>(Insn & 0x0fff);
1259   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1260   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1261
1262   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1263   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1264
1265   switch (Inst.getOpcode()) {
1266   case Mips::SWM32_MM:
1267   case Mips::LWM32_MM:
1268     if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1269         == MCDisassembler::Fail)
1270       return MCDisassembler::Fail;
1271     Inst.addOperand(MCOperand::CreateReg(Base));
1272     Inst.addOperand(MCOperand::CreateImm(Offset));
1273     break;
1274   case Mips::SC_MM:
1275     Inst.addOperand(MCOperand::CreateReg(Reg));
1276     // fallthrough
1277   default:
1278     Inst.addOperand(MCOperand::CreateReg(Reg));
1279     if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
1280       Inst.addOperand(MCOperand::CreateReg(Reg+1));
1281
1282     Inst.addOperand(MCOperand::CreateReg(Base));
1283     Inst.addOperand(MCOperand::CreateImm(Offset));
1284   }
1285
1286   return MCDisassembler::Success;
1287 }
1288
1289 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1290                                      unsigned Insn,
1291                                      uint64_t Address,
1292                                      const void *Decoder) {
1293   int Offset = SignExtend32<16>(Insn & 0xffff);
1294   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1295   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1296
1297   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1298   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1299
1300   Inst.addOperand(MCOperand::CreateReg(Reg));
1301   Inst.addOperand(MCOperand::CreateReg(Base));
1302   Inst.addOperand(MCOperand::CreateImm(Offset));
1303
1304   return MCDisassembler::Success;
1305 }
1306
1307 static DecodeStatus DecodeFMem(MCInst &Inst,
1308                                unsigned Insn,
1309                                uint64_t Address,
1310                                const void *Decoder) {
1311   int Offset = SignExtend32<16>(Insn & 0xffff);
1312   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1313   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1314
1315   Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1316   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1317
1318   Inst.addOperand(MCOperand::CreateReg(Reg));
1319   Inst.addOperand(MCOperand::CreateReg(Base));
1320   Inst.addOperand(MCOperand::CreateImm(Offset));
1321
1322   return MCDisassembler::Success;
1323 }
1324
1325 static DecodeStatus DecodeFMem2(MCInst &Inst,
1326                                unsigned Insn,
1327                                uint64_t Address,
1328                                const void *Decoder) {
1329   int Offset = SignExtend32<16>(Insn & 0xffff);
1330   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1331   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1332
1333   Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1334   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1335
1336   Inst.addOperand(MCOperand::CreateReg(Reg));
1337   Inst.addOperand(MCOperand::CreateReg(Base));
1338   Inst.addOperand(MCOperand::CreateImm(Offset));
1339
1340   return MCDisassembler::Success;
1341 }
1342
1343 static DecodeStatus DecodeFMem3(MCInst &Inst,
1344                                unsigned Insn,
1345                                uint64_t Address,
1346                                const void *Decoder) {
1347   int Offset = SignExtend32<16>(Insn & 0xffff);
1348   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1349   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1350
1351   Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1352   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1353
1354   Inst.addOperand(MCOperand::CreateReg(Reg));
1355   Inst.addOperand(MCOperand::CreateReg(Base));
1356   Inst.addOperand(MCOperand::CreateImm(Offset));
1357
1358   return MCDisassembler::Success;
1359 }
1360
1361 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst,
1362                                     unsigned Insn,
1363                                     uint64_t Address,
1364                                     const void *Decoder) {
1365   int Offset = SignExtend32<11>(Insn & 0x07ff);
1366   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1367   unsigned Base = fieldFromInstruction(Insn, 11, 5);
1368
1369   Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1370   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1371
1372   Inst.addOperand(MCOperand::CreateReg(Reg));
1373   Inst.addOperand(MCOperand::CreateReg(Base));
1374   Inst.addOperand(MCOperand::CreateImm(Offset));
1375
1376   return MCDisassembler::Success;
1377 }
1378 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
1379                                        unsigned Insn,
1380                                        uint64_t Address,
1381                                        const void *Decoder) {
1382   int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1383   unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1384   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1385
1386   Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1387   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1388
1389   if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1390     Inst.addOperand(MCOperand::CreateReg(Rt));
1391   }
1392
1393   Inst.addOperand(MCOperand::CreateReg(Rt));
1394   Inst.addOperand(MCOperand::CreateReg(Base));
1395   Inst.addOperand(MCOperand::CreateImm(Offset));
1396
1397   return MCDisassembler::Success;
1398 }
1399
1400 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1401                                               unsigned RegNo,
1402                                               uint64_t Address,
1403                                               const void *Decoder) {
1404   // Currently only hardware register 29 is supported.
1405   if (RegNo != 29)
1406     return  MCDisassembler::Fail;
1407   Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
1408   return MCDisassembler::Success;
1409 }
1410
1411 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1412                                               unsigned RegNo,
1413                                               uint64_t Address,
1414                                               const void *Decoder) {
1415   if (RegNo > 30 || RegNo %2)
1416     return MCDisassembler::Fail;
1417
1418   ;
1419   unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1420   Inst.addOperand(MCOperand::CreateReg(Reg));
1421   return MCDisassembler::Success;
1422 }
1423
1424 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1425                                                 unsigned RegNo,
1426                                                 uint64_t Address,
1427                                                 const void *Decoder) {
1428   if (RegNo >= 4)
1429     return MCDisassembler::Fail;
1430
1431   unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1432   Inst.addOperand(MCOperand::CreateReg(Reg));
1433   return MCDisassembler::Success;
1434 }
1435
1436 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1437                                                unsigned RegNo,
1438                                                uint64_t Address,
1439                                                const void *Decoder) {
1440   if (RegNo >= 4)
1441     return MCDisassembler::Fail;
1442
1443   unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1444   Inst.addOperand(MCOperand::CreateReg(Reg));
1445   return MCDisassembler::Success;
1446 }
1447
1448 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1449                                                unsigned RegNo,
1450                                                uint64_t Address,
1451                                                const void *Decoder) {
1452   if (RegNo >= 4)
1453     return MCDisassembler::Fail;
1454
1455   unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1456   Inst.addOperand(MCOperand::CreateReg(Reg));
1457   return MCDisassembler::Success;
1458 }
1459
1460 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1461                                                unsigned RegNo,
1462                                                uint64_t Address,
1463                                                const void *Decoder) {
1464   if (RegNo > 31)
1465     return MCDisassembler::Fail;
1466
1467   unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1468   Inst.addOperand(MCOperand::CreateReg(Reg));
1469   return MCDisassembler::Success;
1470 }
1471
1472 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1473                                                unsigned RegNo,
1474                                                uint64_t Address,
1475                                                const void *Decoder) {
1476   if (RegNo > 31)
1477     return MCDisassembler::Fail;
1478
1479   unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1480   Inst.addOperand(MCOperand::CreateReg(Reg));
1481   return MCDisassembler::Success;
1482 }
1483
1484 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1485                                                unsigned RegNo,
1486                                                uint64_t Address,
1487                                                const void *Decoder) {
1488   if (RegNo > 31)
1489     return MCDisassembler::Fail;
1490
1491   unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1492   Inst.addOperand(MCOperand::CreateReg(Reg));
1493   return MCDisassembler::Success;
1494 }
1495
1496 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1497                                                unsigned RegNo,
1498                                                uint64_t Address,
1499                                                const void *Decoder) {
1500   if (RegNo > 31)
1501     return MCDisassembler::Fail;
1502
1503   unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1504   Inst.addOperand(MCOperand::CreateReg(Reg));
1505   return MCDisassembler::Success;
1506 }
1507
1508 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1509                                                unsigned RegNo,
1510                                                uint64_t Address,
1511                                                const void *Decoder) {
1512   if (RegNo > 7)
1513     return MCDisassembler::Fail;
1514
1515   unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1516   Inst.addOperand(MCOperand::CreateReg(Reg));
1517   return MCDisassembler::Success;
1518 }
1519
1520 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1521                                             unsigned RegNo,
1522                                             uint64_t Address,
1523                                             const void *Decoder) {
1524   if (RegNo > 31)
1525     return MCDisassembler::Fail;
1526
1527   unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1528   Inst.addOperand(MCOperand::CreateReg(Reg));
1529   return MCDisassembler::Success;
1530 }
1531
1532 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1533                                        unsigned Offset,
1534                                        uint64_t Address,
1535                                        const void *Decoder) {
1536   int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
1537   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1538   return MCDisassembler::Success;
1539 }
1540
1541 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1542                                      unsigned Insn,
1543                                      uint64_t Address,
1544                                      const void *Decoder) {
1545
1546   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1547   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1548   return MCDisassembler::Success;
1549 }
1550
1551 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1552                                          unsigned Offset,
1553                                          uint64_t Address,
1554                                          const void *Decoder) {
1555   int32_t BranchOffset = SignExtend32<21>(Offset) * 4;
1556
1557   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1558   return MCDisassembler::Success;
1559 }
1560
1561 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1562                                          unsigned Offset,
1563                                          uint64_t Address,
1564                                          const void *Decoder) {
1565   int32_t BranchOffset = SignExtend32<26>(Offset) * 4;
1566
1567   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1568   return MCDisassembler::Success;
1569 }
1570
1571 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
1572                                           unsigned Offset,
1573                                           uint64_t Address,
1574                                           const void *Decoder) {
1575   int32_t BranchOffset = SignExtend32<7>(Offset) << 1;
1576   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1577   return MCDisassembler::Success;
1578 }
1579
1580 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1581                                          unsigned Offset,
1582                                          uint64_t Address,
1583                                          const void *Decoder) {
1584   int32_t BranchOffset = SignExtend32<16>(Offset) * 2;
1585   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1586   return MCDisassembler::Success;
1587 }
1588
1589 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1590                                        unsigned Insn,
1591                                        uint64_t Address,
1592                                        const void *Decoder) {
1593   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1594   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1595   return MCDisassembler::Success;
1596 }
1597
1598 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
1599                                        unsigned Value,
1600                                        uint64_t Address,
1601                                        const void *Decoder) {
1602   if (Value == 0)
1603     Inst.addOperand(MCOperand::CreateImm(1));
1604   else if (Value == 0x7)
1605     Inst.addOperand(MCOperand::CreateImm(-1));
1606   else
1607     Inst.addOperand(MCOperand::CreateImm(Value << 2));
1608   return MCDisassembler::Success;
1609 }
1610
1611 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
1612                                     unsigned Value,
1613                                     uint64_t Address,
1614                                     const void *Decoder) {
1615   Inst.addOperand(MCOperand::CreateImm(Value << 2));
1616   return MCDisassembler::Success;
1617 }
1618
1619 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
1620                                   unsigned Value,
1621                                   uint64_t Address,
1622                                   const void *Decoder) {
1623   if (Value == 0x7F)
1624     Inst.addOperand(MCOperand::CreateImm(-1));
1625   else
1626     Inst.addOperand(MCOperand::CreateImm(Value));
1627   return MCDisassembler::Success;
1628 }
1629
1630 static DecodeStatus DecodeSimm4(MCInst &Inst,
1631                                 unsigned Value,
1632                                 uint64_t Address,
1633                                 const void *Decoder) {
1634   Inst.addOperand(MCOperand::CreateImm(SignExtend32<4>(Value)));
1635   return MCDisassembler::Success;
1636 }
1637
1638 static DecodeStatus DecodeSimm16(MCInst &Inst,
1639                                  unsigned Insn,
1640                                  uint64_t Address,
1641                                  const void *Decoder) {
1642   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
1643   return MCDisassembler::Success;
1644 }
1645
1646 static DecodeStatus DecodeLSAImm(MCInst &Inst,
1647                                  unsigned Insn,
1648                                  uint64_t Address,
1649                                  const void *Decoder) {
1650   // We add one to the immediate field as it was encoded as 'imm - 1'.
1651   Inst.addOperand(MCOperand::CreateImm(Insn + 1));
1652   return MCDisassembler::Success;
1653 }
1654
1655 static DecodeStatus DecodeInsSize(MCInst &Inst,
1656                                   unsigned Insn,
1657                                   uint64_t Address,
1658                                   const void *Decoder) {
1659   // First we need to grab the pos(lsb) from MCInst.
1660   int Pos = Inst.getOperand(2).getImm();
1661   int Size = (int) Insn - Pos + 1;
1662   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1663   return MCDisassembler::Success;
1664 }
1665
1666 static DecodeStatus DecodeExtSize(MCInst &Inst,
1667                                   unsigned Insn,
1668                                   uint64_t Address,
1669                                   const void *Decoder) {
1670   int Size = (int) Insn  + 1;
1671   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1672   return MCDisassembler::Success;
1673 }
1674
1675 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1676                                      uint64_t Address, const void *Decoder) {
1677   Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) * 4));
1678   return MCDisassembler::Success;
1679 }
1680
1681 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1682                                      uint64_t Address, const void *Decoder) {
1683   Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) * 8));
1684   return MCDisassembler::Success;
1685 }
1686
1687 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
1688                                   uint64_t Address, const void *Decoder) {
1689   int32_t DecodedValue;
1690   switch (Insn) {
1691   case 0: DecodedValue = 256; break;
1692   case 1: DecodedValue = 257; break;
1693   case 510: DecodedValue = -258; break;
1694   case 511: DecodedValue = -257; break;
1695   default: DecodedValue = SignExtend32<9>(Insn); break;
1696   }
1697   Inst.addOperand(MCOperand::CreateImm(DecodedValue * 4));
1698   return MCDisassembler::Success;
1699 }
1700
1701 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
1702                                     uint64_t Address, const void *Decoder) {
1703   // Insn must be >= 0, since it is unsigned that condition is always true.
1704   assert(Insn < 16);
1705   int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
1706                              255, 32768, 65535};
1707   Inst.addOperand(MCOperand::CreateImm(DecodedValues[Insn]));
1708   return MCDisassembler::Success;
1709 }
1710
1711 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
1712                                     uint64_t Address, const void *Decoder) {
1713   Inst.addOperand(MCOperand::CreateImm(Insn << 2));
1714   return MCDisassembler::Success;
1715 }
1716
1717 static DecodeStatus DecodeRegListOperand(MCInst &Inst,
1718                                          unsigned Insn,
1719                                          uint64_t Address,
1720                                          const void *Decoder) {
1721   unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
1722                      Mips::S6, Mips::FP};
1723   unsigned RegNum;
1724
1725   unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
1726   // Empty register lists are not allowed.
1727   if (RegLst == 0)
1728     return MCDisassembler::Fail;
1729
1730   RegNum = RegLst & 0xf;
1731   for (unsigned i = 0; i < RegNum; i++)
1732     Inst.addOperand(MCOperand::CreateReg(Regs[i]));
1733
1734   if (RegLst & 0x10)
1735     Inst.addOperand(MCOperand::CreateReg(Mips::RA));
1736
1737   return MCDisassembler::Success;
1738 }
1739
1740 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
1741                                            uint64_t Address,
1742                                            const void *Decoder) {
1743   unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
1744   unsigned RegNum;
1745
1746   unsigned RegLst = fieldFromInstruction(Insn, 4, 2);
1747   // Empty register lists are not allowed.
1748   if (RegLst == 0)
1749     return MCDisassembler::Fail;
1750
1751   RegNum = RegLst & 0x3;
1752   for (unsigned i = 0; i < RegNum - 1; i++)
1753     Inst.addOperand(MCOperand::CreateReg(Regs[i]));
1754
1755   Inst.addOperand(MCOperand::CreateReg(Mips::RA));
1756
1757   return MCDisassembler::Success;
1758 }