1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the Mips Disassembler.
12 //===----------------------------------------------------------------------===//
15 #include "MipsRegisterInfo.h"
16 #include "MipsSubtarget.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCDisassembler.h"
19 #include "llvm/MC/MCFixedLenDisassembler.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/Support/MathExtras.h"
23 #include "llvm/Support/MemoryObject.h"
24 #include "llvm/Support/TargetRegistry.h"
28 #define DEBUG_TYPE "mips-disassembler"
30 typedef MCDisassembler::DecodeStatus DecodeStatus;
34 /// MipsDisassemblerBase - a disasembler class for Mips.
35 class MipsDisassemblerBase : public MCDisassembler {
37 /// Constructor - Initializes the disassembler.
39 MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx,
41 MCDisassembler(STI, Ctx),
42 IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {}
44 virtual ~MipsDisassemblerBase() {}
46 bool isN64() const { return IsN64; }
54 /// MipsDisassembler - a disasembler class for Mips32.
55 class MipsDisassembler : public MipsDisassemblerBase {
58 /// Constructor - Initializes the disassembler.
60 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
62 MipsDisassemblerBase(STI, Ctx, bigEndian) {
63 IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
66 /// getInstruction - See MCDisassembler.
67 DecodeStatus getInstruction(MCInst &instr,
69 const MemoryObject ®ion,
72 raw_ostream &cStream) const override;
76 /// Mips64Disassembler - a disasembler class for Mips64.
77 class Mips64Disassembler : public MipsDisassemblerBase {
79 /// Constructor - Initializes the disassembler.
81 Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
83 MipsDisassemblerBase(STI, Ctx, bigEndian) {}
85 /// getInstruction - See MCDisassembler.
86 DecodeStatus getInstruction(MCInst &instr,
88 const MemoryObject ®ion,
91 raw_ostream &cStream) const override;
94 } // end anonymous namespace
96 // Forward declare these because the autogenerated code will reference them.
97 // Definitions are further down.
98 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
101 const void *Decoder);
103 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
106 const void *Decoder);
108 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
111 const void *Decoder);
113 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
116 const void *Decoder);
118 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
121 const void *Decoder);
123 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
126 const void *Decoder);
128 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
131 const void *Decoder);
133 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
136 const void *Decoder);
138 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
141 const void *Decoder);
143 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
146 const void *Decoder);
148 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
151 const void *Decoder);
153 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
156 const void *Decoder);
158 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
161 const void *Decoder);
163 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
166 const void *Decoder);
168 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
171 const void *Decoder);
173 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
176 const void *Decoder);
178 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
181 const void *Decoder);
183 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
186 const void *Decoder);
188 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
191 const void *Decoder);
193 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
196 const void *Decoder);
198 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
201 const void *Decoder);
203 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
206 const void *Decoder);
208 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
209 // shifted left by 1 bit.
210 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
213 const void *Decoder);
215 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
216 // shifted left by 1 bit.
217 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
220 const void *Decoder);
222 static DecodeStatus DecodeMem(MCInst &Inst,
225 const void *Decoder);
227 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
228 uint64_t Address, const void *Decoder);
230 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
233 const void *Decoder);
235 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
238 const void *Decoder);
240 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
242 const void *Decoder);
244 static DecodeStatus DecodeSimm16(MCInst &Inst,
247 const void *Decoder);
249 // Decode the immediate field of an LSA instruction which
251 static DecodeStatus DecodeLSAImm(MCInst &Inst,
254 const void *Decoder);
256 static DecodeStatus DecodeInsSize(MCInst &Inst,
259 const void *Decoder);
261 static DecodeStatus DecodeExtSize(MCInst &Inst,
264 const void *Decoder);
266 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
267 uint64_t Address, const void *Decoder);
269 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
271 template <typename InsnType>
272 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
273 const void *Decoder);
275 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
279 static MCDisassembler *createMipsDisassembler(
281 const MCSubtargetInfo &STI,
283 return new MipsDisassembler(STI, Ctx, true);
286 static MCDisassembler *createMipselDisassembler(
288 const MCSubtargetInfo &STI,
290 return new MipsDisassembler(STI, Ctx, false);
293 static MCDisassembler *createMips64Disassembler(
295 const MCSubtargetInfo &STI,
297 return new Mips64Disassembler(STI, Ctx, true);
300 static MCDisassembler *createMips64elDisassembler(
302 const MCSubtargetInfo &STI,
304 return new Mips64Disassembler(STI, Ctx, false);
307 extern "C" void LLVMInitializeMipsDisassembler() {
308 // Register the disassembler.
309 TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
310 createMipsDisassembler);
311 TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
312 createMipselDisassembler);
313 TargetRegistry::RegisterMCDisassembler(TheMips64Target,
314 createMips64Disassembler);
315 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
316 createMips64elDisassembler);
319 #include "MipsGenDisassemblerTables.inc"
321 template <typename InsnType>
322 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
323 const void *Decoder) {
324 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
325 // The size of the n field depends on the element size
326 // The register class also depends on this.
327 InsnType tmp = fieldFromInstruction(insn, 17, 5);
329 DecodeFN RegDecoder = nullptr;
330 if ((tmp & 0x18) == 0x00) { // INSVE_B
332 RegDecoder = DecodeMSA128BRegisterClass;
333 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
335 RegDecoder = DecodeMSA128HRegisterClass;
336 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
338 RegDecoder = DecodeMSA128WRegisterClass;
339 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
341 RegDecoder = DecodeMSA128DRegisterClass;
343 llvm_unreachable("Invalid encoding");
345 assert(NSize != 0 && RegDecoder != nullptr);
348 tmp = fieldFromInstruction(insn, 6, 5);
349 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
350 return MCDisassembler::Fail;
352 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
353 return MCDisassembler::Fail;
355 tmp = fieldFromInstruction(insn, 16, NSize);
356 MI.addOperand(MCOperand::CreateImm(tmp));
358 tmp = fieldFromInstruction(insn, 11, 5);
359 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
360 return MCDisassembler::Fail;
362 MI.addOperand(MCOperand::CreateImm(0));
364 return MCDisassembler::Success;
367 /// readInstruction - read four bytes from the MemoryObject
368 /// and return 32 bit word sorted according to the given endianess
369 static DecodeStatus readInstruction32(const MemoryObject ®ion,
377 // We want to read exactly 4 Bytes of data.
378 if (region.readBytes(address, 4, Bytes) == -1) {
380 return MCDisassembler::Fail;
384 // Encoded as a big-endian 32-bit word in the stream.
385 insn = (Bytes[3] << 0) |
391 // Encoded as a small-endian 32-bit word in the stream.
392 // Little-endian byte ordering:
393 // mips32r2: 4 | 3 | 2 | 1
394 // microMIPS: 2 | 1 | 4 | 3
396 insn = (Bytes[2] << 0) |
401 insn = (Bytes[0] << 0) |
408 return MCDisassembler::Success;
412 MipsDisassembler::getInstruction(MCInst &instr,
414 const MemoryObject &Region,
416 raw_ostream &vStream,
417 raw_ostream &cStream) const {
420 DecodeStatus Result = readInstruction32(Region, Address, Size,
421 Insn, isBigEndian, IsMicroMips);
422 if (Result == MCDisassembler::Fail)
423 return MCDisassembler::Fail;
426 // Calling the auto-generated decoder function.
427 Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address,
429 if (Result != MCDisassembler::Fail) {
433 return MCDisassembler::Fail;
436 // Calling the auto-generated decoder function.
437 Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
439 if (Result != MCDisassembler::Fail) {
444 return MCDisassembler::Fail;
448 Mips64Disassembler::getInstruction(MCInst &instr,
450 const MemoryObject &Region,
452 raw_ostream &vStream,
453 raw_ostream &cStream) const {
456 DecodeStatus Result = readInstruction32(Region, Address, Size,
457 Insn, isBigEndian, false);
458 if (Result == MCDisassembler::Fail)
459 return MCDisassembler::Fail;
461 // Calling the auto-generated decoder function.
462 Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address,
464 if (Result != MCDisassembler::Fail) {
468 // If we fail to decode in Mips64 decoder space we can try in Mips32
469 Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
471 if (Result != MCDisassembler::Fail) {
476 return MCDisassembler::Fail;
479 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
480 const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
481 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
482 return *(RegInfo->getRegClass(RC).begin() + RegNo);
485 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
488 const void *Decoder) {
490 return MCDisassembler::Fail;
494 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
497 const void *Decoder) {
500 return MCDisassembler::Fail;
502 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
503 Inst.addOperand(MCOperand::CreateReg(Reg));
504 return MCDisassembler::Success;
507 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
510 const void *Decoder) {
512 return MCDisassembler::Fail;
513 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
514 Inst.addOperand(MCOperand::CreateReg(Reg));
515 return MCDisassembler::Success;
518 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
521 const void *Decoder) {
522 if (static_cast<const MipsDisassembler *>(Decoder)->isN64())
523 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
525 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
528 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
531 const void *Decoder) {
532 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
535 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
538 const void *Decoder) {
540 return MCDisassembler::Fail;
542 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
543 Inst.addOperand(MCOperand::CreateReg(Reg));
544 return MCDisassembler::Success;
547 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
550 const void *Decoder) {
552 return MCDisassembler::Fail;
554 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
555 Inst.addOperand(MCOperand::CreateReg(Reg));
556 return MCDisassembler::Success;
559 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
562 const void *Decoder) {
564 return MCDisassembler::Fail;
566 unsigned Reg = getReg(Decoder, Mips::FGRH32RegClassID, RegNo);
567 Inst.addOperand(MCOperand::CreateReg(Reg));
568 return MCDisassembler::Success;
571 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
574 const void *Decoder) {
576 return MCDisassembler::Fail;
577 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
578 Inst.addOperand(MCOperand::CreateReg(Reg));
579 return MCDisassembler::Success;
582 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
585 const void *Decoder) {
587 return MCDisassembler::Fail;
588 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
589 Inst.addOperand(MCOperand::CreateReg(Reg));
590 return MCDisassembler::Success;
593 static DecodeStatus DecodeMem(MCInst &Inst,
596 const void *Decoder) {
597 int Offset = SignExtend32<16>(Insn & 0xffff);
598 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
599 unsigned Base = fieldFromInstruction(Insn, 21, 5);
601 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
602 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
604 if(Inst.getOpcode() == Mips::SC){
605 Inst.addOperand(MCOperand::CreateReg(Reg));
608 Inst.addOperand(MCOperand::CreateReg(Reg));
609 Inst.addOperand(MCOperand::CreateReg(Base));
610 Inst.addOperand(MCOperand::CreateImm(Offset));
612 return MCDisassembler::Success;
615 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
616 uint64_t Address, const void *Decoder) {
617 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
618 unsigned Reg = fieldFromInstruction(Insn, 6, 5);
619 unsigned Base = fieldFromInstruction(Insn, 11, 5);
621 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
622 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
624 Inst.addOperand(MCOperand::CreateReg(Reg));
625 Inst.addOperand(MCOperand::CreateReg(Base));
627 // The immediate field of an LD/ST instruction is scaled which means it must
628 // be multiplied (when decoding) by the size (in bytes) of the instructions'
634 switch(Inst.getOpcode())
637 assert (0 && "Unexpected instruction");
638 return MCDisassembler::Fail;
642 Inst.addOperand(MCOperand::CreateImm(Offset));
646 Inst.addOperand(MCOperand::CreateImm(Offset << 1));
650 Inst.addOperand(MCOperand::CreateImm(Offset << 2));
654 Inst.addOperand(MCOperand::CreateImm(Offset << 3));
658 return MCDisassembler::Success;
661 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
664 const void *Decoder) {
665 int Offset = SignExtend32<12>(Insn & 0x0fff);
666 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
667 unsigned Base = fieldFromInstruction(Insn, 16, 5);
669 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
670 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
672 if (Inst.getOpcode() == Mips::SC_MM)
673 Inst.addOperand(MCOperand::CreateReg(Reg));
675 Inst.addOperand(MCOperand::CreateReg(Reg));
676 Inst.addOperand(MCOperand::CreateReg(Base));
677 Inst.addOperand(MCOperand::CreateImm(Offset));
679 return MCDisassembler::Success;
682 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
685 const void *Decoder) {
686 int Offset = SignExtend32<16>(Insn & 0xffff);
687 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
688 unsigned Base = fieldFromInstruction(Insn, 16, 5);
690 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
691 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
693 Inst.addOperand(MCOperand::CreateReg(Reg));
694 Inst.addOperand(MCOperand::CreateReg(Base));
695 Inst.addOperand(MCOperand::CreateImm(Offset));
697 return MCDisassembler::Success;
700 static DecodeStatus DecodeFMem(MCInst &Inst,
703 const void *Decoder) {
704 int Offset = SignExtend32<16>(Insn & 0xffff);
705 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
706 unsigned Base = fieldFromInstruction(Insn, 21, 5);
708 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
709 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
711 Inst.addOperand(MCOperand::CreateReg(Reg));
712 Inst.addOperand(MCOperand::CreateReg(Base));
713 Inst.addOperand(MCOperand::CreateImm(Offset));
715 return MCDisassembler::Success;
719 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
722 const void *Decoder) {
723 // Currently only hardware register 29 is supported.
725 return MCDisassembler::Fail;
726 Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
727 return MCDisassembler::Success;
730 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
733 const void *Decoder) {
734 if (RegNo > 30 || RegNo %2)
735 return MCDisassembler::Fail;
738 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
739 Inst.addOperand(MCOperand::CreateReg(Reg));
740 return MCDisassembler::Success;
743 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
746 const void *Decoder) {
748 return MCDisassembler::Fail;
750 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
751 Inst.addOperand(MCOperand::CreateReg(Reg));
752 return MCDisassembler::Success;
755 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
758 const void *Decoder) {
760 return MCDisassembler::Fail;
762 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
763 Inst.addOperand(MCOperand::CreateReg(Reg));
764 return MCDisassembler::Success;
767 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
770 const void *Decoder) {
772 return MCDisassembler::Fail;
774 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
775 Inst.addOperand(MCOperand::CreateReg(Reg));
776 return MCDisassembler::Success;
779 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
782 const void *Decoder) {
784 return MCDisassembler::Fail;
786 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
787 Inst.addOperand(MCOperand::CreateReg(Reg));
788 return MCDisassembler::Success;
791 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
794 const void *Decoder) {
796 return MCDisassembler::Fail;
798 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
799 Inst.addOperand(MCOperand::CreateReg(Reg));
800 return MCDisassembler::Success;
803 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
806 const void *Decoder) {
808 return MCDisassembler::Fail;
810 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
811 Inst.addOperand(MCOperand::CreateReg(Reg));
812 return MCDisassembler::Success;
815 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
818 const void *Decoder) {
820 return MCDisassembler::Fail;
822 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
823 Inst.addOperand(MCOperand::CreateReg(Reg));
824 return MCDisassembler::Success;
827 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
830 const void *Decoder) {
832 return MCDisassembler::Fail;
834 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
835 Inst.addOperand(MCOperand::CreateReg(Reg));
836 return MCDisassembler::Success;
839 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
842 const void *Decoder) {
843 unsigned BranchOffset = Offset & 0xffff;
844 BranchOffset = SignExtend32<18>(BranchOffset << 2) + 4;
845 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
846 return MCDisassembler::Success;
849 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
852 const void *Decoder) {
854 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
855 Inst.addOperand(MCOperand::CreateImm(JumpOffset));
856 return MCDisassembler::Success;
859 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
862 const void *Decoder) {
863 unsigned BranchOffset = Offset & 0xffff;
864 BranchOffset = SignExtend32<18>(BranchOffset << 1);
865 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
866 return MCDisassembler::Success;
869 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
872 const void *Decoder) {
873 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
874 Inst.addOperand(MCOperand::CreateImm(JumpOffset));
875 return MCDisassembler::Success;
878 static DecodeStatus DecodeSimm16(MCInst &Inst,
881 const void *Decoder) {
882 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
883 return MCDisassembler::Success;
886 static DecodeStatus DecodeLSAImm(MCInst &Inst,
889 const void *Decoder) {
890 // We add one to the immediate field as it was encoded as 'imm - 1'.
891 Inst.addOperand(MCOperand::CreateImm(Insn + 1));
892 return MCDisassembler::Success;
895 static DecodeStatus DecodeInsSize(MCInst &Inst,
898 const void *Decoder) {
899 // First we need to grab the pos(lsb) from MCInst.
900 int Pos = Inst.getOperand(2).getImm();
901 int Size = (int) Insn - Pos + 1;
902 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
903 return MCDisassembler::Success;
906 static DecodeStatus DecodeExtSize(MCInst &Inst,
909 const void *Decoder) {
910 int Size = (int) Insn + 1;
911 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
912 return MCDisassembler::Success;
915 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
916 uint64_t Address, const void *Decoder) {
917 Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) << 2));
918 return MCDisassembler::Success;