1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the Mips Disassembler.
12 //===----------------------------------------------------------------------===//
15 #include "MipsRegisterInfo.h"
16 #include "MipsSubtarget.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCDisassembler.h"
19 #include "llvm/MC/MCFixedLenDisassembler.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/Support/MathExtras.h"
23 #include "llvm/Support/MemoryObject.h"
24 #include "llvm/Support/TargetRegistry.h"
28 #define DEBUG_TYPE "mips-disassembler"
30 typedef MCDisassembler::DecodeStatus DecodeStatus;
34 /// MipsDisassemblerBase - a disasembler class for Mips.
35 class MipsDisassemblerBase : public MCDisassembler {
37 /// Constructor - Initializes the disassembler.
39 MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx,
41 MCDisassembler(STI, Ctx),
42 IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {}
44 virtual ~MipsDisassemblerBase() {}
46 bool isN64() const { return IsN64; }
54 /// MipsDisassembler - a disasembler class for Mips32.
55 class MipsDisassembler : public MipsDisassemblerBase {
58 /// Constructor - Initializes the disassembler.
60 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool bigEndian)
61 : MipsDisassemblerBase(STI, Ctx, bigEndian) {
62 IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
65 bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; }
66 bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; }
67 bool hasMips32r6() const {
68 return STI.getFeatureBits() & Mips::FeatureMips32r6;
71 bool isGP64() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; }
73 bool hasCOP3() const {
74 // Only present in MIPS-I and MIPS-II
75 return !hasMips32() && !hasMips3();
78 /// getInstruction - See MCDisassembler.
79 DecodeStatus getInstruction(MCInst &instr,
81 const MemoryObject ®ion,
84 raw_ostream &cStream) const override;
88 /// Mips64Disassembler - a disasembler class for Mips64.
89 class Mips64Disassembler : public MipsDisassemblerBase {
91 /// Constructor - Initializes the disassembler.
93 Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
95 MipsDisassemblerBase(STI, Ctx, bigEndian) {}
97 /// getInstruction - See MCDisassembler.
98 DecodeStatus getInstruction(MCInst &instr,
100 const MemoryObject ®ion,
102 raw_ostream &vStream,
103 raw_ostream &cStream) const override;
106 } // end anonymous namespace
108 // Forward declare these because the autogenerated code will reference them.
109 // Definitions are further down.
110 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
113 const void *Decoder);
115 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
118 const void *Decoder);
120 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
123 const void *Decoder);
125 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
128 const void *Decoder);
130 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
133 const void *Decoder);
135 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
138 const void *Decoder);
140 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
143 const void *Decoder);
145 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
148 const void *Decoder);
150 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
153 const void *Decoder);
155 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
158 const void *Decoder);
160 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
162 const void *Decoder);
164 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
167 const void *Decoder);
169 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
172 const void *Decoder);
174 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
177 const void *Decoder);
179 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
182 const void *Decoder);
184 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
187 const void *Decoder);
189 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
192 const void *Decoder);
194 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
197 const void *Decoder);
199 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
202 const void *Decoder);
204 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
207 const void *Decoder);
209 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
212 const void *Decoder);
214 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
217 const void *Decoder);
219 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
222 const void *Decoder);
224 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
227 const void *Decoder);
229 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
232 const void *Decoder);
234 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
237 const void *Decoder);
239 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
240 // shifted left by 1 bit.
241 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
244 const void *Decoder);
246 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
247 // shifted left by 1 bit.
248 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
251 const void *Decoder);
253 static DecodeStatus DecodeMem(MCInst &Inst,
256 const void *Decoder);
258 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
259 uint64_t Address, const void *Decoder);
261 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
264 const void *Decoder);
266 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
269 const void *Decoder);
271 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
273 const void *Decoder);
275 static DecodeStatus DecodeSimm16(MCInst &Inst,
278 const void *Decoder);
280 // Decode the immediate field of an LSA instruction which
282 static DecodeStatus DecodeLSAImm(MCInst &Inst,
285 const void *Decoder);
287 static DecodeStatus DecodeInsSize(MCInst &Inst,
290 const void *Decoder);
292 static DecodeStatus DecodeExtSize(MCInst &Inst,
295 const void *Decoder);
297 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
298 uint64_t Address, const void *Decoder);
300 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
301 uint64_t Address, const void *Decoder);
303 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
305 template <typename InsnType>
306 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
307 const void *Decoder);
309 template <typename InsnType>
311 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
312 const void *Decoder);
314 template <typename InsnType>
316 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
317 const void *Decoder);
319 template <typename InsnType>
321 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
322 const void *Decoder);
324 template <typename InsnType>
326 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
327 const void *Decoder);
329 template <typename InsnType>
331 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
332 const void *Decoder);
334 template <typename InsnType>
336 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
337 const void *Decoder);
340 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
344 static MCDisassembler *createMipsDisassembler(
346 const MCSubtargetInfo &STI,
348 return new MipsDisassembler(STI, Ctx, true);
351 static MCDisassembler *createMipselDisassembler(
353 const MCSubtargetInfo &STI,
355 return new MipsDisassembler(STI, Ctx, false);
358 static MCDisassembler *createMips64Disassembler(
360 const MCSubtargetInfo &STI,
362 return new Mips64Disassembler(STI, Ctx, true);
365 static MCDisassembler *createMips64elDisassembler(
367 const MCSubtargetInfo &STI,
369 return new Mips64Disassembler(STI, Ctx, false);
372 extern "C" void LLVMInitializeMipsDisassembler() {
373 // Register the disassembler.
374 TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
375 createMipsDisassembler);
376 TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
377 createMipselDisassembler);
378 TargetRegistry::RegisterMCDisassembler(TheMips64Target,
379 createMips64Disassembler);
380 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
381 createMips64elDisassembler);
384 #include "MipsGenDisassemblerTables.inc"
386 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
387 const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
388 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
389 return *(RegInfo->getRegClass(RC).begin() + RegNo);
392 template <typename InsnType>
393 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
394 const void *Decoder) {
395 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
396 // The size of the n field depends on the element size
397 // The register class also depends on this.
398 InsnType tmp = fieldFromInstruction(insn, 17, 5);
400 DecodeFN RegDecoder = nullptr;
401 if ((tmp & 0x18) == 0x00) { // INSVE_B
403 RegDecoder = DecodeMSA128BRegisterClass;
404 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
406 RegDecoder = DecodeMSA128HRegisterClass;
407 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
409 RegDecoder = DecodeMSA128WRegisterClass;
410 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
412 RegDecoder = DecodeMSA128DRegisterClass;
414 llvm_unreachable("Invalid encoding");
416 assert(NSize != 0 && RegDecoder != nullptr);
419 tmp = fieldFromInstruction(insn, 6, 5);
420 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
421 return MCDisassembler::Fail;
423 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
424 return MCDisassembler::Fail;
426 tmp = fieldFromInstruction(insn, 16, NSize);
427 MI.addOperand(MCOperand::CreateImm(tmp));
429 tmp = fieldFromInstruction(insn, 11, 5);
430 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
431 return MCDisassembler::Fail;
433 MI.addOperand(MCOperand::CreateImm(0));
435 return MCDisassembler::Success;
438 template <typename InsnType>
439 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
441 const void *Decoder) {
442 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
443 // (otherwise we would have matched the ADDI instruction from the earlier
447 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii
449 // BEQZALC if rs == 0 && rt != 0
450 // BEQC if rs < rt && rs != 0
452 InsnType Rs = fieldFromInstruction(insn, 21, 5);
453 InsnType Rt = fieldFromInstruction(insn, 16, 5);
454 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
458 MI.setOpcode(Mips::BOVC);
460 } else if (Rs != 0 && Rs < Rt) {
461 MI.setOpcode(Mips::BEQC);
464 MI.setOpcode(Mips::BEQZALC);
467 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
470 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
472 MI.addOperand(MCOperand::CreateImm(Imm));
474 return MCDisassembler::Success;
477 template <typename InsnType>
478 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
480 const void *Decoder) {
481 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
482 // (otherwise we would have matched the ADDI instruction from the earlier
486 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii
488 // BNEZALC if rs == 0 && rt != 0
489 // BNEC if rs < rt && rs != 0
491 InsnType Rs = fieldFromInstruction(insn, 21, 5);
492 InsnType Rt = fieldFromInstruction(insn, 16, 5);
493 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
497 MI.setOpcode(Mips::BNVC);
499 } else if (Rs != 0 && Rs < Rt) {
500 MI.setOpcode(Mips::BNEC);
503 MI.setOpcode(Mips::BNEZALC);
506 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
509 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
511 MI.addOperand(MCOperand::CreateImm(Imm));
513 return MCDisassembler::Success;
516 template <typename InsnType>
517 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
519 const void *Decoder) {
520 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
521 // (otherwise we would have matched the BLEZL instruction from the earlier
525 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii
526 // Invalid if rs == 0
527 // BLEZC if rs == 0 && rt != 0
528 // BGEZC if rs == rt && rt != 0
529 // BGEC if rs != rt && rs != 0 && rt != 0
531 InsnType Rs = fieldFromInstruction(insn, 21, 5);
532 InsnType Rt = fieldFromInstruction(insn, 16, 5);
533 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
537 return MCDisassembler::Fail;
539 MI.setOpcode(Mips::BLEZC);
541 MI.setOpcode(Mips::BGEZC);
544 MI.setOpcode(Mips::BGEC);
548 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
551 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
554 MI.addOperand(MCOperand::CreateImm(Imm));
556 return MCDisassembler::Success;
559 template <typename InsnType>
560 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
562 const void *Decoder) {
563 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
564 // (otherwise we would have matched the BGTZL instruction from the earlier
568 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii
569 // Invalid if rs == 0
570 // BGTZC if rs == 0 && rt != 0
571 // BLTZC if rs == rt && rt != 0
572 // BLTC if rs != rt && rs != 0 && rt != 0
574 InsnType Rs = fieldFromInstruction(insn, 21, 5);
575 InsnType Rt = fieldFromInstruction(insn, 16, 5);
576 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
579 return MCDisassembler::Fail;
581 MI.setOpcode(Mips::BGTZC);
583 MI.setOpcode(Mips::BLTZC);
585 return MCDisassembler::Fail; // FIXME: BLTC is not implemented yet.
587 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
590 MI.addOperand(MCOperand::CreateImm(Imm));
592 return MCDisassembler::Success;
595 template <typename InsnType>
596 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
598 const void *Decoder) {
599 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
600 // (otherwise we would have matched the BGTZ instruction from the earlier
604 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii
606 // BGTZALC if rs == 0 && rt != 0
607 // BLTZALC if rs != 0 && rs == rt
608 // BLTUC if rs != 0 && rs != rt
610 InsnType Rs = fieldFromInstruction(insn, 21, 5);
611 InsnType Rt = fieldFromInstruction(insn, 16, 5);
612 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
617 MI.setOpcode(Mips::BGTZ);
619 } else if (Rs == 0) {
620 MI.setOpcode(Mips::BGTZALC);
622 } else if (Rs == Rt) {
623 MI.setOpcode(Mips::BLTZALC);
626 return MCDisassembler::Fail; // BLTUC not implemented yet
629 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
633 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
636 MI.addOperand(MCOperand::CreateImm(Imm));
638 return MCDisassembler::Success;
641 template <typename InsnType>
642 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
644 const void *Decoder) {
645 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
646 // (otherwise we would have matched the BLEZL instruction from the earlier
650 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii
651 // Invalid if rs == 0
652 // BLEZALC if rs == 0 && rt != 0
653 // BGEZALC if rs == rt && rt != 0
654 // BGEUC if rs != rt && rs != 0 && rt != 0
656 InsnType Rs = fieldFromInstruction(insn, 21, 5);
657 InsnType Rt = fieldFromInstruction(insn, 16, 5);
658 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
662 return MCDisassembler::Fail;
664 MI.setOpcode(Mips::BLEZALC);
666 MI.setOpcode(Mips::BGEZALC);
669 MI.setOpcode(Mips::BGEUC);
673 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
675 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
678 MI.addOperand(MCOperand::CreateImm(Imm));
680 return MCDisassembler::Success;
683 /// readInstruction - read four bytes from the MemoryObject
684 /// and return 32 bit word sorted according to the given endianess
685 static DecodeStatus readInstruction32(const MemoryObject ®ion,
693 // We want to read exactly 4 Bytes of data.
694 if (region.readBytes(address, 4, Bytes) == -1) {
696 return MCDisassembler::Fail;
700 // Encoded as a big-endian 32-bit word in the stream.
701 insn = (Bytes[3] << 0) |
707 // Encoded as a small-endian 32-bit word in the stream.
708 // Little-endian byte ordering:
709 // mips32r2: 4 | 3 | 2 | 1
710 // microMIPS: 2 | 1 | 4 | 3
712 insn = (Bytes[2] << 0) |
717 insn = (Bytes[0] << 0) |
724 return MCDisassembler::Success;
728 MipsDisassembler::getInstruction(MCInst &instr,
730 const MemoryObject &Region,
732 raw_ostream &vStream,
733 raw_ostream &cStream) const {
736 DecodeStatus Result = readInstruction32(Region, Address, Size,
737 Insn, isBigEndian, IsMicroMips);
738 if (Result == MCDisassembler::Fail)
739 return MCDisassembler::Fail;
742 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit opcodes):\n");
743 // Calling the auto-generated decoder function.
744 Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address,
746 if (Result != MCDisassembler::Fail) {
750 return MCDisassembler::Fail;
754 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
756 decodeInstruction(DecoderTableCOP3_32, instr, Insn, Address, this, STI);
757 if (Result != MCDisassembler::Fail) {
763 if (hasMips32r6() && isGP64()) {
764 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
765 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, instr, Insn,
767 if (Result != MCDisassembler::Fail) {
774 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
775 Result = decodeInstruction(DecoderTableMips32r6_64r632, instr, Insn,
777 if (Result != MCDisassembler::Fail) {
783 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
784 // Calling the auto-generated decoder function.
785 Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
787 if (Result != MCDisassembler::Fail) {
792 return MCDisassembler::Fail;
796 Mips64Disassembler::getInstruction(MCInst &instr,
798 const MemoryObject &Region,
800 raw_ostream &vStream,
801 raw_ostream &cStream) const {
804 DecodeStatus Result = readInstruction32(Region, Address, Size,
805 Insn, isBigEndian, false);
806 if (Result == MCDisassembler::Fail)
807 return MCDisassembler::Fail;
809 // Calling the auto-generated decoder function.
810 Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address,
812 if (Result != MCDisassembler::Fail) {
816 // If we fail to decode in Mips64 decoder space we can try in Mips32
817 Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
819 if (Result != MCDisassembler::Fail) {
824 return MCDisassembler::Fail;
827 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
830 const void *Decoder) {
832 return MCDisassembler::Fail;
836 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
839 const void *Decoder) {
842 return MCDisassembler::Fail;
844 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
845 Inst.addOperand(MCOperand::CreateReg(Reg));
846 return MCDisassembler::Success;
849 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
852 const void *Decoder) {
854 return MCDisassembler::Fail;
855 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
856 Inst.addOperand(MCOperand::CreateReg(Reg));
857 return MCDisassembler::Success;
860 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
863 const void *Decoder) {
864 if (static_cast<const MipsDisassembler *>(Decoder)->isN64())
865 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
867 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
870 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
873 const void *Decoder) {
874 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
877 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
880 const void *Decoder) {
882 return MCDisassembler::Fail;
884 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
885 Inst.addOperand(MCOperand::CreateReg(Reg));
886 return MCDisassembler::Success;
889 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
892 const void *Decoder) {
894 return MCDisassembler::Fail;
896 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
897 Inst.addOperand(MCOperand::CreateReg(Reg));
898 return MCDisassembler::Success;
901 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
904 const void *Decoder) {
906 return MCDisassembler::Fail;
908 unsigned Reg = getReg(Decoder, Mips::FGRH32RegClassID, RegNo);
909 Inst.addOperand(MCOperand::CreateReg(Reg));
910 return MCDisassembler::Success;
913 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
916 const void *Decoder) {
918 return MCDisassembler::Fail;
919 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
920 Inst.addOperand(MCOperand::CreateReg(Reg));
921 return MCDisassembler::Success;
924 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
927 const void *Decoder) {
929 return MCDisassembler::Fail;
930 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
931 Inst.addOperand(MCOperand::CreateReg(Reg));
932 return MCDisassembler::Success;
935 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
937 const void *Decoder) {
939 return MCDisassembler::Fail;
941 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
942 Inst.addOperand(MCOperand::CreateReg(Reg));
943 return MCDisassembler::Success;
946 static DecodeStatus DecodeMem(MCInst &Inst,
949 const void *Decoder) {
950 int Offset = SignExtend32<16>(Insn & 0xffff);
951 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
952 unsigned Base = fieldFromInstruction(Insn, 21, 5);
954 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
955 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
957 if(Inst.getOpcode() == Mips::SC){
958 Inst.addOperand(MCOperand::CreateReg(Reg));
961 Inst.addOperand(MCOperand::CreateReg(Reg));
962 Inst.addOperand(MCOperand::CreateReg(Base));
963 Inst.addOperand(MCOperand::CreateImm(Offset));
965 return MCDisassembler::Success;
968 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
969 uint64_t Address, const void *Decoder) {
970 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
971 unsigned Reg = fieldFromInstruction(Insn, 6, 5);
972 unsigned Base = fieldFromInstruction(Insn, 11, 5);
974 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
975 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
977 Inst.addOperand(MCOperand::CreateReg(Reg));
978 Inst.addOperand(MCOperand::CreateReg(Base));
980 // The immediate field of an LD/ST instruction is scaled which means it must
981 // be multiplied (when decoding) by the size (in bytes) of the instructions'
987 switch(Inst.getOpcode())
990 assert (0 && "Unexpected instruction");
991 return MCDisassembler::Fail;
995 Inst.addOperand(MCOperand::CreateImm(Offset));
999 Inst.addOperand(MCOperand::CreateImm(Offset << 1));
1003 Inst.addOperand(MCOperand::CreateImm(Offset << 2));
1007 Inst.addOperand(MCOperand::CreateImm(Offset << 3));
1011 return MCDisassembler::Success;
1014 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1017 const void *Decoder) {
1018 int Offset = SignExtend32<12>(Insn & 0x0fff);
1019 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1020 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1022 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1023 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1025 if (Inst.getOpcode() == Mips::SC_MM)
1026 Inst.addOperand(MCOperand::CreateReg(Reg));
1028 Inst.addOperand(MCOperand::CreateReg(Reg));
1029 Inst.addOperand(MCOperand::CreateReg(Base));
1030 Inst.addOperand(MCOperand::CreateImm(Offset));
1032 return MCDisassembler::Success;
1035 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1038 const void *Decoder) {
1039 int Offset = SignExtend32<16>(Insn & 0xffff);
1040 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1041 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1043 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1044 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1046 Inst.addOperand(MCOperand::CreateReg(Reg));
1047 Inst.addOperand(MCOperand::CreateReg(Base));
1048 Inst.addOperand(MCOperand::CreateImm(Offset));
1050 return MCDisassembler::Success;
1053 static DecodeStatus DecodeFMem(MCInst &Inst,
1056 const void *Decoder) {
1057 int Offset = SignExtend32<16>(Insn & 0xffff);
1058 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1059 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1061 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1062 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1064 Inst.addOperand(MCOperand::CreateReg(Reg));
1065 Inst.addOperand(MCOperand::CreateReg(Base));
1066 Inst.addOperand(MCOperand::CreateImm(Offset));
1068 return MCDisassembler::Success;
1072 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1075 const void *Decoder) {
1076 // Currently only hardware register 29 is supported.
1078 return MCDisassembler::Fail;
1079 Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
1080 return MCDisassembler::Success;
1083 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1086 const void *Decoder) {
1087 if (RegNo > 30 || RegNo %2)
1088 return MCDisassembler::Fail;
1091 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1092 Inst.addOperand(MCOperand::CreateReg(Reg));
1093 return MCDisassembler::Success;
1096 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1099 const void *Decoder) {
1101 return MCDisassembler::Fail;
1103 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1104 Inst.addOperand(MCOperand::CreateReg(Reg));
1105 return MCDisassembler::Success;
1108 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1111 const void *Decoder) {
1113 return MCDisassembler::Fail;
1115 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1116 Inst.addOperand(MCOperand::CreateReg(Reg));
1117 return MCDisassembler::Success;
1120 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1123 const void *Decoder) {
1125 return MCDisassembler::Fail;
1127 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1128 Inst.addOperand(MCOperand::CreateReg(Reg));
1129 return MCDisassembler::Success;
1132 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1135 const void *Decoder) {
1137 return MCDisassembler::Fail;
1139 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1140 Inst.addOperand(MCOperand::CreateReg(Reg));
1141 return MCDisassembler::Success;
1144 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1147 const void *Decoder) {
1149 return MCDisassembler::Fail;
1151 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1152 Inst.addOperand(MCOperand::CreateReg(Reg));
1153 return MCDisassembler::Success;
1156 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1159 const void *Decoder) {
1161 return MCDisassembler::Fail;
1163 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1164 Inst.addOperand(MCOperand::CreateReg(Reg));
1165 return MCDisassembler::Success;
1168 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1171 const void *Decoder) {
1173 return MCDisassembler::Fail;
1175 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1176 Inst.addOperand(MCOperand::CreateReg(Reg));
1177 return MCDisassembler::Success;
1180 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1183 const void *Decoder) {
1185 return MCDisassembler::Fail;
1187 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1188 Inst.addOperand(MCOperand::CreateReg(Reg));
1189 return MCDisassembler::Success;
1192 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1195 const void *Decoder) {
1197 return MCDisassembler::Fail;
1199 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1200 Inst.addOperand(MCOperand::CreateReg(Reg));
1201 return MCDisassembler::Success;
1204 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1207 const void *Decoder) {
1208 int32_t BranchOffset = (SignExtend32<16>(Offset) << 2) + 4;
1209 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1210 return MCDisassembler::Success;
1213 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1216 const void *Decoder) {
1218 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1219 Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1220 return MCDisassembler::Success;
1223 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1226 const void *Decoder) {
1227 int32_t BranchOffset = SignExtend32<21>(Offset) << 2;
1229 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1230 return MCDisassembler::Success;
1233 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1236 const void *Decoder) {
1237 int32_t BranchOffset = SignExtend32<26>(Offset) << 2;
1239 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1240 return MCDisassembler::Success;
1243 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1246 const void *Decoder) {
1247 int32_t BranchOffset = SignExtend32<16>(Offset) << 1;
1248 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1249 return MCDisassembler::Success;
1252 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1255 const void *Decoder) {
1256 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1257 Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1258 return MCDisassembler::Success;
1261 static DecodeStatus DecodeSimm16(MCInst &Inst,
1264 const void *Decoder) {
1265 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
1266 return MCDisassembler::Success;
1269 static DecodeStatus DecodeLSAImm(MCInst &Inst,
1272 const void *Decoder) {
1273 // We add one to the immediate field as it was encoded as 'imm - 1'.
1274 Inst.addOperand(MCOperand::CreateImm(Insn + 1));
1275 return MCDisassembler::Success;
1278 static DecodeStatus DecodeInsSize(MCInst &Inst,
1281 const void *Decoder) {
1282 // First we need to grab the pos(lsb) from MCInst.
1283 int Pos = Inst.getOperand(2).getImm();
1284 int Size = (int) Insn - Pos + 1;
1285 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1286 return MCDisassembler::Success;
1289 static DecodeStatus DecodeExtSize(MCInst &Inst,
1292 const void *Decoder) {
1293 int Size = (int) Insn + 1;
1294 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1295 return MCDisassembler::Success;
1298 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1299 uint64_t Address, const void *Decoder) {
1300 Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) << 2));
1301 return MCDisassembler::Success;
1304 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1305 uint64_t Address, const void *Decoder) {
1306 Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) << 3));
1307 return MCDisassembler::Success;