1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the Mips Disassembler.
12 //===----------------------------------------------------------------------===//
15 #include "MipsRegisterInfo.h"
16 #include "MipsSubtarget.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCDisassembler.h"
19 #include "llvm/MC/MCFixedLenDisassembler.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/Support/MathExtras.h"
23 #include "llvm/Support/TargetRegistry.h"
27 #define DEBUG_TYPE "mips-disassembler"
29 typedef MCDisassembler::DecodeStatus DecodeStatus;
33 /// A disasembler class for Mips.
34 class MipsDisassemblerBase : public MCDisassembler {
36 MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx,
38 : MCDisassembler(STI, Ctx),
39 IsN64(STI.getFeatureBits() & Mips::FeatureN64),
40 IsBigEndian(IsBigEndian) {}
42 virtual ~MipsDisassemblerBase() {}
44 bool isN64() const { return IsN64; }
52 /// A disasembler class for Mips32.
53 class MipsDisassembler : public MipsDisassemblerBase {
56 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool bigEndian)
57 : MipsDisassemblerBase(STI, Ctx, bigEndian) {
58 IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
61 bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; }
62 bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; }
63 bool hasMips32r6() const {
64 return STI.getFeatureBits() & Mips::FeatureMips32r6;
67 bool isGP64() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; }
69 bool hasCOP3() const {
70 // Only present in MIPS-I and MIPS-II
71 return !hasMips32() && !hasMips3();
74 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
75 ArrayRef<uint8_t> Bytes, uint64_t Address,
77 raw_ostream &CStream) const override;
80 /// A disasembler class for Mips64.
81 class Mips64Disassembler : public MipsDisassemblerBase {
83 Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
85 MipsDisassemblerBase(STI, Ctx, bigEndian) {}
87 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
88 ArrayRef<uint8_t> Bytes, uint64_t Address,
90 raw_ostream &CStream) const override;
93 } // end anonymous namespace
95 // Forward declare these because the autogenerated code will reference them.
96 // Definitions are further down.
97 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
100 const void *Decoder);
102 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
105 const void *Decoder);
107 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
110 const void *Decoder);
112 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
115 const void *Decoder);
117 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
120 const void *Decoder);
122 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
125 const void *Decoder);
127 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
130 const void *Decoder);
132 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
135 const void *Decoder);
137 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
140 const void *Decoder);
142 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
145 const void *Decoder);
147 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
149 const void *Decoder);
151 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
154 const void *Decoder);
156 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
159 const void *Decoder);
161 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
164 const void *Decoder);
166 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
169 const void *Decoder);
171 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
174 const void *Decoder);
176 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
179 const void *Decoder);
181 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
184 const void *Decoder);
186 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
189 const void *Decoder);
191 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
194 const void *Decoder);
196 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
199 const void *Decoder);
201 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
204 const void *Decoder);
206 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
209 const void *Decoder);
211 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
214 const void *Decoder);
216 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
219 const void *Decoder);
221 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
224 const void *Decoder);
226 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
227 // shifted left by 1 bit.
228 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
231 const void *Decoder);
233 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
234 // shifted left by 1 bit.
235 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
238 const void *Decoder);
240 static DecodeStatus DecodeMem(MCInst &Inst,
243 const void *Decoder);
245 static DecodeStatus DecodeCacheOp(MCInst &Inst,
248 const void *Decoder);
250 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
251 uint64_t Address, const void *Decoder);
253 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
256 const void *Decoder);
258 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
261 const void *Decoder);
263 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
265 const void *Decoder);
267 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
269 const void *Decoder);
271 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn,
273 const void *Decoder);
275 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
278 const void *Decoder);
280 static DecodeStatus DecodeSimm16(MCInst &Inst,
283 const void *Decoder);
285 // Decode the immediate field of an LSA instruction which
287 static DecodeStatus DecodeLSAImm(MCInst &Inst,
290 const void *Decoder);
292 static DecodeStatus DecodeInsSize(MCInst &Inst,
295 const void *Decoder);
297 static DecodeStatus DecodeExtSize(MCInst &Inst,
300 const void *Decoder);
302 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
303 uint64_t Address, const void *Decoder);
305 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
306 uint64_t Address, const void *Decoder);
308 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
310 template <typename InsnType>
311 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
312 const void *Decoder);
314 template <typename InsnType>
316 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
317 const void *Decoder);
319 template <typename InsnType>
321 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
322 const void *Decoder);
324 template <typename InsnType>
326 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
327 const void *Decoder);
329 template <typename InsnType>
331 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
332 const void *Decoder);
334 template <typename InsnType>
336 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
337 const void *Decoder);
339 template <typename InsnType>
341 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
342 const void *Decoder);
345 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
349 static MCDisassembler *createMipsDisassembler(
351 const MCSubtargetInfo &STI,
353 return new MipsDisassembler(STI, Ctx, true);
356 static MCDisassembler *createMipselDisassembler(
358 const MCSubtargetInfo &STI,
360 return new MipsDisassembler(STI, Ctx, false);
363 static MCDisassembler *createMips64Disassembler(
365 const MCSubtargetInfo &STI,
367 return new Mips64Disassembler(STI, Ctx, true);
370 static MCDisassembler *createMips64elDisassembler(
372 const MCSubtargetInfo &STI,
374 return new Mips64Disassembler(STI, Ctx, false);
377 extern "C" void LLVMInitializeMipsDisassembler() {
378 // Register the disassembler.
379 TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
380 createMipsDisassembler);
381 TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
382 createMipselDisassembler);
383 TargetRegistry::RegisterMCDisassembler(TheMips64Target,
384 createMips64Disassembler);
385 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
386 createMips64elDisassembler);
389 #include "MipsGenDisassemblerTables.inc"
391 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
392 const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
393 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
394 return *(RegInfo->getRegClass(RC).begin() + RegNo);
397 template <typename InsnType>
398 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
399 const void *Decoder) {
400 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
401 // The size of the n field depends on the element size
402 // The register class also depends on this.
403 InsnType tmp = fieldFromInstruction(insn, 17, 5);
405 DecodeFN RegDecoder = nullptr;
406 if ((tmp & 0x18) == 0x00) { // INSVE_B
408 RegDecoder = DecodeMSA128BRegisterClass;
409 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
411 RegDecoder = DecodeMSA128HRegisterClass;
412 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
414 RegDecoder = DecodeMSA128WRegisterClass;
415 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
417 RegDecoder = DecodeMSA128DRegisterClass;
419 llvm_unreachable("Invalid encoding");
421 assert(NSize != 0 && RegDecoder != nullptr);
424 tmp = fieldFromInstruction(insn, 6, 5);
425 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
426 return MCDisassembler::Fail;
428 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
429 return MCDisassembler::Fail;
431 tmp = fieldFromInstruction(insn, 16, NSize);
432 MI.addOperand(MCOperand::CreateImm(tmp));
434 tmp = fieldFromInstruction(insn, 11, 5);
435 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
436 return MCDisassembler::Fail;
438 MI.addOperand(MCOperand::CreateImm(0));
440 return MCDisassembler::Success;
443 template <typename InsnType>
444 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
446 const void *Decoder) {
447 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
448 // (otherwise we would have matched the ADDI instruction from the earlier
452 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii
454 // BEQZALC if rs == 0 && rt != 0
455 // BEQC if rs < rt && rs != 0
457 InsnType Rs = fieldFromInstruction(insn, 21, 5);
458 InsnType Rt = fieldFromInstruction(insn, 16, 5);
459 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
463 MI.setOpcode(Mips::BOVC);
465 } else if (Rs != 0 && Rs < Rt) {
466 MI.setOpcode(Mips::BEQC);
469 MI.setOpcode(Mips::BEQZALC);
472 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
475 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
477 MI.addOperand(MCOperand::CreateImm(Imm));
479 return MCDisassembler::Success;
482 template <typename InsnType>
483 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
485 const void *Decoder) {
486 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
487 // (otherwise we would have matched the ADDI instruction from the earlier
491 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii
493 // BNEZALC if rs == 0 && rt != 0
494 // BNEC if rs < rt && rs != 0
496 InsnType Rs = fieldFromInstruction(insn, 21, 5);
497 InsnType Rt = fieldFromInstruction(insn, 16, 5);
498 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
502 MI.setOpcode(Mips::BNVC);
504 } else if (Rs != 0 && Rs < Rt) {
505 MI.setOpcode(Mips::BNEC);
508 MI.setOpcode(Mips::BNEZALC);
511 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
514 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
516 MI.addOperand(MCOperand::CreateImm(Imm));
518 return MCDisassembler::Success;
521 template <typename InsnType>
522 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
524 const void *Decoder) {
525 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
526 // (otherwise we would have matched the BLEZL instruction from the earlier
530 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii
531 // Invalid if rs == 0
532 // BLEZC if rs == 0 && rt != 0
533 // BGEZC if rs == rt && rt != 0
534 // BGEC if rs != rt && rs != 0 && rt != 0
536 InsnType Rs = fieldFromInstruction(insn, 21, 5);
537 InsnType Rt = fieldFromInstruction(insn, 16, 5);
538 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
542 return MCDisassembler::Fail;
544 MI.setOpcode(Mips::BLEZC);
546 MI.setOpcode(Mips::BGEZC);
549 MI.setOpcode(Mips::BGEC);
553 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
556 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
559 MI.addOperand(MCOperand::CreateImm(Imm));
561 return MCDisassembler::Success;
564 template <typename InsnType>
565 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
567 const void *Decoder) {
568 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
569 // (otherwise we would have matched the BGTZL instruction from the earlier
573 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii
574 // Invalid if rs == 0
575 // BGTZC if rs == 0 && rt != 0
576 // BLTZC if rs == rt && rt != 0
577 // BLTC if rs != rt && rs != 0 && rt != 0
581 InsnType Rs = fieldFromInstruction(insn, 21, 5);
582 InsnType Rt = fieldFromInstruction(insn, 16, 5);
583 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
586 return MCDisassembler::Fail;
588 MI.setOpcode(Mips::BGTZC);
590 MI.setOpcode(Mips::BLTZC);
592 MI.setOpcode(Mips::BLTC);
597 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
600 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
603 MI.addOperand(MCOperand::CreateImm(Imm));
605 return MCDisassembler::Success;
608 template <typename InsnType>
609 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
611 const void *Decoder) {
612 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
613 // (otherwise we would have matched the BGTZ instruction from the earlier
617 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii
619 // BGTZALC if rs == 0 && rt != 0
620 // BLTZALC if rs != 0 && rs == rt
621 // BLTUC if rs != 0 && rs != rt
623 InsnType Rs = fieldFromInstruction(insn, 21, 5);
624 InsnType Rt = fieldFromInstruction(insn, 16, 5);
625 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
630 MI.setOpcode(Mips::BGTZ);
632 } else if (Rs == 0) {
633 MI.setOpcode(Mips::BGTZALC);
635 } else if (Rs == Rt) {
636 MI.setOpcode(Mips::BLTZALC);
639 MI.setOpcode(Mips::BLTUC);
645 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
649 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
652 MI.addOperand(MCOperand::CreateImm(Imm));
654 return MCDisassembler::Success;
657 template <typename InsnType>
658 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
660 const void *Decoder) {
661 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
662 // (otherwise we would have matched the BLEZL instruction from the earlier
666 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii
667 // Invalid if rs == 0
668 // BLEZALC if rs == 0 && rt != 0
669 // BGEZALC if rs == rt && rt != 0
670 // BGEUC if rs != rt && rs != 0 && rt != 0
672 InsnType Rs = fieldFromInstruction(insn, 21, 5);
673 InsnType Rt = fieldFromInstruction(insn, 16, 5);
674 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
678 return MCDisassembler::Fail;
680 MI.setOpcode(Mips::BLEZALC);
682 MI.setOpcode(Mips::BGEZALC);
685 MI.setOpcode(Mips::BGEUC);
689 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
691 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
694 MI.addOperand(MCOperand::CreateImm(Imm));
696 return MCDisassembler::Success;
699 /// Read four bytes from the ArrayRef and return 32 bit word sorted
700 /// according to the given endianess
701 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
702 uint64_t &Size, uint32_t &Insn,
703 bool IsBigEndian, bool IsMicroMips) {
704 // We want to read exactly 4 Bytes of data.
705 if (Bytes.size() < 4) {
707 return MCDisassembler::Fail;
711 // Encoded as a big-endian 32-bit word in the stream.
713 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
715 // Encoded as a small-endian 32-bit word in the stream.
716 // Little-endian byte ordering:
717 // mips32r2: 4 | 3 | 2 | 1
718 // microMIPS: 2 | 1 | 4 | 3
720 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
723 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
728 return MCDisassembler::Success;
731 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
732 ArrayRef<uint8_t> Bytes,
734 raw_ostream &VStream,
735 raw_ostream &CStream) const {
738 DecodeStatus Result =
739 readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, IsMicroMips);
740 if (Result == MCDisassembler::Fail)
741 return MCDisassembler::Fail;
744 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit opcodes):\n");
745 // Calling the auto-generated decoder function.
746 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
748 if (Result != MCDisassembler::Fail) {
752 return MCDisassembler::Fail;
756 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
758 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
759 if (Result != MCDisassembler::Fail) {
765 if (hasMips32r6() && isGP64()) {
766 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
767 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
769 if (Result != MCDisassembler::Fail) {
776 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
777 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
779 if (Result != MCDisassembler::Fail) {
785 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
786 // Calling the auto-generated decoder function.
788 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
789 if (Result != MCDisassembler::Fail) {
794 return MCDisassembler::Fail;
797 DecodeStatus Mips64Disassembler::getInstruction(MCInst &Instr, uint64_t &Size,
798 ArrayRef<uint8_t> Bytes,
800 raw_ostream &VStream,
801 raw_ostream &CStream) const {
804 DecodeStatus Result =
805 readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
806 if (Result == MCDisassembler::Fail)
807 return MCDisassembler::Fail;
809 // Calling the auto-generated decoder function.
811 decodeInstruction(DecoderTableMips6432, Instr, Insn, Address, this, STI);
812 if (Result != MCDisassembler::Fail) {
816 // If we fail to decode in Mips64 decoder space we can try in Mips32
818 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
819 if (Result != MCDisassembler::Fail) {
824 return MCDisassembler::Fail;
827 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
830 const void *Decoder) {
832 return MCDisassembler::Fail;
836 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
839 const void *Decoder) {
842 return MCDisassembler::Fail;
844 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
845 Inst.addOperand(MCOperand::CreateReg(Reg));
846 return MCDisassembler::Success;
849 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
852 const void *Decoder) {
853 return MCDisassembler::Fail;
856 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
859 const void *Decoder) {
861 return MCDisassembler::Fail;
862 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
863 Inst.addOperand(MCOperand::CreateReg(Reg));
864 return MCDisassembler::Success;
867 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
870 const void *Decoder) {
871 if (static_cast<const MipsDisassembler *>(Decoder)->isN64())
872 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
874 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
877 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
880 const void *Decoder) {
881 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
884 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
887 const void *Decoder) {
889 return MCDisassembler::Fail;
891 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
892 Inst.addOperand(MCOperand::CreateReg(Reg));
893 return MCDisassembler::Success;
896 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
899 const void *Decoder) {
901 return MCDisassembler::Fail;
903 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
904 Inst.addOperand(MCOperand::CreateReg(Reg));
905 return MCDisassembler::Success;
908 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
911 const void *Decoder) {
913 return MCDisassembler::Fail;
914 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
915 Inst.addOperand(MCOperand::CreateReg(Reg));
916 return MCDisassembler::Success;
919 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
922 const void *Decoder) {
924 return MCDisassembler::Fail;
925 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
926 Inst.addOperand(MCOperand::CreateReg(Reg));
927 return MCDisassembler::Success;
930 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
932 const void *Decoder) {
934 return MCDisassembler::Fail;
936 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
937 Inst.addOperand(MCOperand::CreateReg(Reg));
938 return MCDisassembler::Success;
941 static DecodeStatus DecodeMem(MCInst &Inst,
944 const void *Decoder) {
945 int Offset = SignExtend32<16>(Insn & 0xffff);
946 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
947 unsigned Base = fieldFromInstruction(Insn, 21, 5);
949 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
950 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
952 if(Inst.getOpcode() == Mips::SC){
953 Inst.addOperand(MCOperand::CreateReg(Reg));
956 Inst.addOperand(MCOperand::CreateReg(Reg));
957 Inst.addOperand(MCOperand::CreateReg(Base));
958 Inst.addOperand(MCOperand::CreateImm(Offset));
960 return MCDisassembler::Success;
963 static DecodeStatus DecodeCacheOp(MCInst &Inst,
966 const void *Decoder) {
967 int Offset = SignExtend32<16>(Insn & 0xffff);
968 unsigned Hint = fieldFromInstruction(Insn, 16, 5);
969 unsigned Base = fieldFromInstruction(Insn, 21, 5);
971 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
973 Inst.addOperand(MCOperand::CreateReg(Base));
974 Inst.addOperand(MCOperand::CreateImm(Offset));
975 Inst.addOperand(MCOperand::CreateImm(Hint));
977 return MCDisassembler::Success;
980 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
981 uint64_t Address, const void *Decoder) {
982 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
983 unsigned Reg = fieldFromInstruction(Insn, 6, 5);
984 unsigned Base = fieldFromInstruction(Insn, 11, 5);
986 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
987 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
989 Inst.addOperand(MCOperand::CreateReg(Reg));
990 Inst.addOperand(MCOperand::CreateReg(Base));
992 // The immediate field of an LD/ST instruction is scaled which means it must
993 // be multiplied (when decoding) by the size (in bytes) of the instructions'
999 switch(Inst.getOpcode())
1002 assert (0 && "Unexpected instruction");
1003 return MCDisassembler::Fail;
1007 Inst.addOperand(MCOperand::CreateImm(Offset));
1011 Inst.addOperand(MCOperand::CreateImm(Offset * 2));
1015 Inst.addOperand(MCOperand::CreateImm(Offset * 4));
1019 Inst.addOperand(MCOperand::CreateImm(Offset * 8));
1023 return MCDisassembler::Success;
1026 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1029 const void *Decoder) {
1030 int Offset = SignExtend32<12>(Insn & 0x0fff);
1031 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1032 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1034 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1035 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1037 if (Inst.getOpcode() == Mips::SC_MM)
1038 Inst.addOperand(MCOperand::CreateReg(Reg));
1040 Inst.addOperand(MCOperand::CreateReg(Reg));
1041 Inst.addOperand(MCOperand::CreateReg(Base));
1042 Inst.addOperand(MCOperand::CreateImm(Offset));
1044 return MCDisassembler::Success;
1047 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1050 const void *Decoder) {
1051 int Offset = SignExtend32<16>(Insn & 0xffff);
1052 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1053 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1055 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1056 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1058 Inst.addOperand(MCOperand::CreateReg(Reg));
1059 Inst.addOperand(MCOperand::CreateReg(Base));
1060 Inst.addOperand(MCOperand::CreateImm(Offset));
1062 return MCDisassembler::Success;
1065 static DecodeStatus DecodeFMem(MCInst &Inst,
1068 const void *Decoder) {
1069 int Offset = SignExtend32<16>(Insn & 0xffff);
1070 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1071 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1073 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1074 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1076 Inst.addOperand(MCOperand::CreateReg(Reg));
1077 Inst.addOperand(MCOperand::CreateReg(Base));
1078 Inst.addOperand(MCOperand::CreateImm(Offset));
1080 return MCDisassembler::Success;
1083 static DecodeStatus DecodeFMem2(MCInst &Inst,
1086 const void *Decoder) {
1087 int Offset = SignExtend32<16>(Insn & 0xffff);
1088 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1089 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1091 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1092 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1094 Inst.addOperand(MCOperand::CreateReg(Reg));
1095 Inst.addOperand(MCOperand::CreateReg(Base));
1096 Inst.addOperand(MCOperand::CreateImm(Offset));
1098 return MCDisassembler::Success;
1101 static DecodeStatus DecodeFMem3(MCInst &Inst,
1104 const void *Decoder) {
1105 int Offset = SignExtend32<16>(Insn & 0xffff);
1106 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1107 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1109 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1110 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1112 Inst.addOperand(MCOperand::CreateReg(Reg));
1113 Inst.addOperand(MCOperand::CreateReg(Base));
1114 Inst.addOperand(MCOperand::CreateImm(Offset));
1116 return MCDisassembler::Success;
1119 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
1122 const void *Decoder) {
1123 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1124 unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1125 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1127 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1128 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1130 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1131 Inst.addOperand(MCOperand::CreateReg(Rt));
1134 Inst.addOperand(MCOperand::CreateReg(Rt));
1135 Inst.addOperand(MCOperand::CreateReg(Base));
1136 Inst.addOperand(MCOperand::CreateImm(Offset));
1138 return MCDisassembler::Success;
1141 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1144 const void *Decoder) {
1145 // Currently only hardware register 29 is supported.
1147 return MCDisassembler::Fail;
1148 Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
1149 return MCDisassembler::Success;
1152 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1155 const void *Decoder) {
1156 if (RegNo > 30 || RegNo %2)
1157 return MCDisassembler::Fail;
1160 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1161 Inst.addOperand(MCOperand::CreateReg(Reg));
1162 return MCDisassembler::Success;
1165 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1168 const void *Decoder) {
1170 return MCDisassembler::Fail;
1172 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1173 Inst.addOperand(MCOperand::CreateReg(Reg));
1174 return MCDisassembler::Success;
1177 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1180 const void *Decoder) {
1182 return MCDisassembler::Fail;
1184 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1185 Inst.addOperand(MCOperand::CreateReg(Reg));
1186 return MCDisassembler::Success;
1189 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1192 const void *Decoder) {
1194 return MCDisassembler::Fail;
1196 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1197 Inst.addOperand(MCOperand::CreateReg(Reg));
1198 return MCDisassembler::Success;
1201 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1204 const void *Decoder) {
1206 return MCDisassembler::Fail;
1208 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1209 Inst.addOperand(MCOperand::CreateReg(Reg));
1210 return MCDisassembler::Success;
1213 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1216 const void *Decoder) {
1218 return MCDisassembler::Fail;
1220 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1221 Inst.addOperand(MCOperand::CreateReg(Reg));
1222 return MCDisassembler::Success;
1225 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1228 const void *Decoder) {
1230 return MCDisassembler::Fail;
1232 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1233 Inst.addOperand(MCOperand::CreateReg(Reg));
1234 return MCDisassembler::Success;
1237 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1240 const void *Decoder) {
1242 return MCDisassembler::Fail;
1244 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1245 Inst.addOperand(MCOperand::CreateReg(Reg));
1246 return MCDisassembler::Success;
1249 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1252 const void *Decoder) {
1254 return MCDisassembler::Fail;
1256 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1257 Inst.addOperand(MCOperand::CreateReg(Reg));
1258 return MCDisassembler::Success;
1261 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1264 const void *Decoder) {
1266 return MCDisassembler::Fail;
1268 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1269 Inst.addOperand(MCOperand::CreateReg(Reg));
1270 return MCDisassembler::Success;
1273 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1276 const void *Decoder) {
1277 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
1278 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1279 return MCDisassembler::Success;
1282 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1285 const void *Decoder) {
1287 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1288 Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1289 return MCDisassembler::Success;
1292 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1295 const void *Decoder) {
1296 int32_t BranchOffset = SignExtend32<21>(Offset) * 4;
1298 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1299 return MCDisassembler::Success;
1302 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1305 const void *Decoder) {
1306 int32_t BranchOffset = SignExtend32<26>(Offset) * 4;
1308 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1309 return MCDisassembler::Success;
1312 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1315 const void *Decoder) {
1316 int32_t BranchOffset = SignExtend32<16>(Offset) * 2;
1317 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1318 return MCDisassembler::Success;
1321 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1324 const void *Decoder) {
1325 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1326 Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1327 return MCDisassembler::Success;
1330 static DecodeStatus DecodeSimm16(MCInst &Inst,
1333 const void *Decoder) {
1334 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
1335 return MCDisassembler::Success;
1338 static DecodeStatus DecodeLSAImm(MCInst &Inst,
1341 const void *Decoder) {
1342 // We add one to the immediate field as it was encoded as 'imm - 1'.
1343 Inst.addOperand(MCOperand::CreateImm(Insn + 1));
1344 return MCDisassembler::Success;
1347 static DecodeStatus DecodeInsSize(MCInst &Inst,
1350 const void *Decoder) {
1351 // First we need to grab the pos(lsb) from MCInst.
1352 int Pos = Inst.getOperand(2).getImm();
1353 int Size = (int) Insn - Pos + 1;
1354 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1355 return MCDisassembler::Success;
1358 static DecodeStatus DecodeExtSize(MCInst &Inst,
1361 const void *Decoder) {
1362 int Size = (int) Insn + 1;
1363 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1364 return MCDisassembler::Success;
1367 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1368 uint64_t Address, const void *Decoder) {
1369 Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) * 4));
1370 return MCDisassembler::Success;
1373 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1374 uint64_t Address, const void *Decoder) {
1375 Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) * 8));
1376 return MCDisassembler::Success;