lib/Target/Mips/Disassembler/MipsDisassembler.cpp

   1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file is part of the Mips Disassembler.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Mips.h"
  15 #include "MipsRegisterInfo.h"
  16 #include "MipsSubtarget.h"
  17 #include "llvm/MC/MCContext.h"
  18 #include "llvm/MC/MCDisassembler.h"
  19 #include "llvm/MC/MCFixedLenDisassembler.h"
  20 #include "llvm/MC/MCInst.h"
  21 #include "llvm/MC/MCSubtargetInfo.h"
  22 #include "llvm/Support/MathExtras.h"
  23 #include "llvm/Support/MemoryObject.h"
  24 #include "llvm/Support/TargetRegistry.h"
  25
  26 using namespace llvm;
  27
  28 typedef MCDisassembler::DecodeStatus DecodeStatus;
  29
  30 namespace {
  31
  32 /// MipsDisassemblerBase - a disasembler class for Mips.
  33 class MipsDisassemblerBase : public MCDisassembler {
  34 public:
  35   /// Constructor     - Initializes the disassembler.
  36   ///
  37   MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx,
  38                        bool bigEndian) :
  39     MCDisassembler(STI, Ctx),
  40     IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {}
  41
  42   virtual ~MipsDisassemblerBase() {}
  43
  44   bool isN64() const { return IsN64; }
  45
  46 private:
  47   bool IsN64;
  48 protected:
  49   bool isBigEndian;
  50 };
  51
  52 /// MipsDisassembler - a disasembler class for Mips32.
  53 class MipsDisassembler : public MipsDisassemblerBase {
  54   bool IsMicroMips;
  55 public:
  56   /// Constructor     - Initializes the disassembler.
  57   ///
  58   MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
  59                    bool bigEndian) :
  60     MipsDisassemblerBase(STI, Ctx, bigEndian) {
  61       IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
  62     }
  63
  64   /// getInstruction - See MCDisassembler.
  65   virtual DecodeStatus getInstruction(MCInst &instr,
  66                                       uint64_t &size,
  67                                       const MemoryObject &region,
  68                                       uint64_t address,
  69                                       raw_ostream &vStream,
  70                                       raw_ostream &cStream) const;
  71 };
  72
  73
  74 /// Mips64Disassembler - a disasembler class for Mips64.
  75 class Mips64Disassembler : public MipsDisassemblerBase {
  76 public:
  77   /// Constructor     - Initializes the disassembler.
  78   ///
  79   Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
  80                      bool bigEndian) :
  81     MipsDisassemblerBase(STI, Ctx, bigEndian) {}
  82
  83   /// getInstruction - See MCDisassembler.
  84   virtual DecodeStatus getInstruction(MCInst &instr,
  85                                       uint64_t &size,
  86                                       const MemoryObject &region,
  87                                       uint64_t address,
  88                                       raw_ostream &vStream,
  89                                       raw_ostream &cStream) const;
  90 };
  91
  92 } // end anonymous namespace
  93
  94 // Forward declare these because the autogenerated code will reference them.
  95 // Definitions are further down.
  96 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
  97                                              unsigned RegNo,
  98                                              uint64_t Address,
  99                                              const void *Decoder);
 100
 101 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 102                                                  unsigned RegNo,
 103                                                  uint64_t Address,
 104                                                  const void *Decoder);
 105
 106 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 107                                              unsigned RegNo,
 108                                              uint64_t Address,
 109                                              const void *Decoder);
 110
 111 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 112                                            unsigned Insn,
 113                                            uint64_t Address,
 114                                            const void *Decoder);
 115
 116 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 117                                             unsigned RegNo,
 118                                             uint64_t Address,
 119                                             const void *Decoder);
 120
 121 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 122                                              unsigned RegNo,
 123                                              uint64_t Address,
 124                                              const void *Decoder);
 125
 126 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 127                                              unsigned RegNo,
 128                                              uint64_t Address,
 129                                              const void *Decoder);
 130
 131 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
 132                                               unsigned RegNo,
 133                                               uint64_t Address,
 134                                               const void *Decoder);
 135
 136 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 137                                            unsigned RegNo,
 138                                            uint64_t Address,
 139                                            const void *Decoder);
 140
 141 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 142                                            unsigned RegNo,
 143                                            uint64_t Address,
 144                                            const void *Decoder);
 145
 146 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 147                                               unsigned Insn,
 148                                               uint64_t Address,
 149                                               const void *Decoder);
 150
 151 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 152                                               unsigned RegNo,
 153                                               uint64_t Address,
 154                                               const void *Decoder);
 155
 156 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 157                                                 unsigned RegNo,
 158                                                 uint64_t Address,
 159                                                 const void *Decoder);
 160
 161 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 162                                                unsigned RegNo,
 163                                                uint64_t Address,
 164                                                const void *Decoder);
 165
 166 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 167                                                unsigned RegNo,
 168                                                uint64_t Address,
 169                                                const void *Decoder);
 170
 171 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
 172                                                unsigned RegNo,
 173                                                uint64_t Address,
 174                                                const void *Decoder);
 175
 176 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 177                                                unsigned RegNo,
 178                                                uint64_t Address,
 179                                                const void *Decoder);
 180
 181 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 182                                                unsigned RegNo,
 183                                                uint64_t Address,
 184                                                const void *Decoder);
 185
 186 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 187                                                unsigned RegNo,
 188                                                uint64_t Address,
 189                                                const void *Decoder);
 190
 191 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
 192                                                unsigned RegNo,
 193                                                uint64_t Address,
 194                                                const void *Decoder);
 195
 196 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 197                                        unsigned Offset,
 198                                        uint64_t Address,
 199                                        const void *Decoder);
 200
 201 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 202                                      unsigned Insn,
 203                                      uint64_t Address,
 204                                      const void *Decoder);
 205
 206 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
 207 // shifted left by 1 bit.
 208 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
 209                                          unsigned Offset,
 210                                          uint64_t Address,
 211                                          const void *Decoder);
 212
 213 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
 214 // shifted left by 1 bit.
 215 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
 216                                        unsigned Insn,
 217                                        uint64_t Address,
 218                                        const void *Decoder);
 219
 220 static DecodeStatus DecodeMem(MCInst &Inst,
 221                               unsigned Insn,
 222                               uint64_t Address,
 223                               const void *Decoder);
 224
 225 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 226                                     uint64_t Address, const void *Decoder);
 227
 228 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 229                                      unsigned Insn,
 230                                      uint64_t Address,
 231                                      const void *Decoder);
 232
 233 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 234                                      unsigned Insn,
 235                                      uint64_t Address,
 236                                      const void *Decoder);
 237
 238 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
 239                                uint64_t Address,
 240                                const void *Decoder);
 241
 242 static DecodeStatus DecodeSimm16(MCInst &Inst,
 243                                  unsigned Insn,
 244                                  uint64_t Address,
 245                                  const void *Decoder);
 246
 247 // Decode the immediate field of an LSA instruction which
 248 // is off by one.
 249 static DecodeStatus DecodeLSAImm(MCInst &Inst,
 250                                  unsigned Insn,
 251                                  uint64_t Address,
 252                                  const void *Decoder);
 253
 254 static DecodeStatus DecodeInsSize(MCInst &Inst,
 255                                   unsigned Insn,
 256                                   uint64_t Address,
 257                                   const void *Decoder);
 258
 259 static DecodeStatus DecodeExtSize(MCInst &Inst,
 260                                   unsigned Insn,
 261                                   uint64_t Address,
 262                                   const void *Decoder);
 263
 264 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
 265 /// handle.
 266 template <typename InsnType>
 267 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 268                                    const void *Decoder);
 269 namespace llvm {
 270 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
 271               TheMips64elTarget;
 272 }
 273
 274 static MCDisassembler *createMipsDisassembler(
 275                        const Target &T,
 276                        const MCSubtargetInfo &STI,
 277                        MCContext &Ctx) {
 278   return new MipsDisassembler(STI, Ctx, true);
 279 }
 280
 281 static MCDisassembler *createMipselDisassembler(
 282                        const Target &T,
 283                        const MCSubtargetInfo &STI,
 284                        MCContext &Ctx) {
 285   return new MipsDisassembler(STI, Ctx, false);
 286 }
 287
 288 static MCDisassembler *createMips64Disassembler(
 289                        const Target &T,
 290                        const MCSubtargetInfo &STI,
 291                        MCContext &Ctx) {
 292   return new Mips64Disassembler(STI, Ctx, true);
 293 }
 294
 295 static MCDisassembler *createMips64elDisassembler(
 296                        const Target &T,
 297                        const MCSubtargetInfo &STI,
 298                        MCContext &Ctx) {
 299   return new Mips64Disassembler(STI, Ctx, false);
 300 }
 301
 302 extern "C" void LLVMInitializeMipsDisassembler() {
 303   // Register the disassembler.
 304   TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
 305                                          createMipsDisassembler);
 306   TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
 307                                          createMipselDisassembler);
 308   TargetRegistry::RegisterMCDisassembler(TheMips64Target,
 309                                          createMips64Disassembler);
 310   TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
 311                                          createMips64elDisassembler);
 312 }
 313
 314 #include "MipsGenDisassemblerTables.inc"
 315
 316 template <typename InsnType>
 317 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 318                                    const void *Decoder) {
 319   typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
 320   // The size of the n field depends on the element size
 321   // The register class also depends on this.
 322   InsnType tmp = fieldFromInstruction(insn, 17, 5);
 323   unsigned NSize = 0;
 324   DecodeFN RegDecoder = nullptr;
 325   if ((tmp & 0x18) == 0x00) { // INSVE_B
 326     NSize = 4;
 327     RegDecoder = DecodeMSA128BRegisterClass;
 328   } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
 329     NSize = 3;
 330     RegDecoder = DecodeMSA128HRegisterClass;
 331   } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
 332     NSize = 2;
 333     RegDecoder = DecodeMSA128WRegisterClass;
 334   } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
 335     NSize = 1;
 336     RegDecoder = DecodeMSA128DRegisterClass;
 337   } else
 338     llvm_unreachable("Invalid encoding");
 339
 340   assert(NSize != 0 && RegDecoder != nullptr);
 341
 342   // $wd
 343   tmp = fieldFromInstruction(insn, 6, 5);
 344   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 345     return MCDisassembler::Fail;
 346   // $wd_in
 347   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 348     return MCDisassembler::Fail;
 349   // $n
 350   tmp = fieldFromInstruction(insn, 16, NSize);
 351   MI.addOperand(MCOperand::CreateImm(tmp));
 352   // $ws
 353   tmp = fieldFromInstruction(insn, 11, 5);
 354   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 355     return MCDisassembler::Fail;
 356   // $n2
 357   MI.addOperand(MCOperand::CreateImm(0));
 358
 359   return MCDisassembler::Success;
 360 }
 361
 362   /// readInstruction - read four bytes from the MemoryObject
 363   /// and return 32 bit word sorted according to the given endianess
 364 static DecodeStatus readInstruction32(const MemoryObject &region,
 365                                       uint64_t address,
 366                                       uint64_t &size,
 367                                       uint32_t &insn,
 368                                       bool isBigEndian,
 369                                       bool IsMicroMips) {
 370   uint8_t Bytes[4];
 371
 372   // We want to read exactly 4 Bytes of data.
 373   if (region.readBytes(address, 4, Bytes) == -1) {
 374     size = 0;
 375     return MCDisassembler::Fail;
 376   }
 377
 378   if (isBigEndian) {
 379     // Encoded as a big-endian 32-bit word in the stream.
 380     insn = (Bytes[3] <<  0) |
 381            (Bytes[2] <<  8) |
 382            (Bytes[1] << 16) |
 383            (Bytes[0] << 24);
 384   }
 385   else {
 386     // Encoded as a small-endian 32-bit word in the stream.
 387     // Little-endian byte ordering:
 388     //   mips32r2:   4 | 3 | 2 | 1
 389     //   microMIPS:  2 | 1 | 4 | 3
 390     if (IsMicroMips) {
 391       insn = (Bytes[2] <<  0) |
 392              (Bytes[3] <<  8) |
 393              (Bytes[0] << 16) |
 394              (Bytes[1] << 24);
 395     } else {
 396       insn = (Bytes[0] <<  0) |
 397              (Bytes[1] <<  8) |
 398              (Bytes[2] << 16) |
 399              (Bytes[3] << 24);
 400     }
 401   }
 402
 403   return MCDisassembler::Success;
 404 }
 405
 406 DecodeStatus
 407 MipsDisassembler::getInstruction(MCInst &instr,
 408                                  uint64_t &Size,
 409                                  const MemoryObject &Region,
 410                                  uint64_t Address,
 411                                  raw_ostream &vStream,
 412                                  raw_ostream &cStream) const {
 413   uint32_t Insn;
 414
 415   DecodeStatus Result = readInstruction32(Region, Address, Size,
 416                                           Insn, isBigEndian, IsMicroMips);
 417   if (Result == MCDisassembler::Fail)
 418     return MCDisassembler::Fail;
 419
 420   if (IsMicroMips) {
 421     // Calling the auto-generated decoder function.
 422     Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address,
 423                                this, STI);
 424     if (Result != MCDisassembler::Fail) {
 425       Size = 4;
 426       return Result;
 427     }
 428     return MCDisassembler::Fail;
 429   }
 430
 431   // Calling the auto-generated decoder function.
 432   Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
 433                              this, STI);
 434   if (Result != MCDisassembler::Fail) {
 435     Size = 4;
 436     return Result;
 437   }
 438
 439   return MCDisassembler::Fail;
 440 }
 441
 442 DecodeStatus
 443 Mips64Disassembler::getInstruction(MCInst &instr,
 444                                    uint64_t &Size,
 445                                    const MemoryObject &Region,
 446                                    uint64_t Address,
 447                                    raw_ostream &vStream,
 448                                    raw_ostream &cStream) const {
 449   uint32_t Insn;
 450
 451   DecodeStatus Result = readInstruction32(Region, Address, Size,
 452                                           Insn, isBigEndian, false);
 453   if (Result == MCDisassembler::Fail)
 454     return MCDisassembler::Fail;
 455
 456   // Calling the auto-generated decoder function.
 457   Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address,
 458                              this, STI);
 459   if (Result != MCDisassembler::Fail) {
 460     Size = 4;
 461     return Result;
 462   }
 463   // If we fail to decode in Mips64 decoder space we can try in Mips32
 464   Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
 465                              this, STI);
 466   if (Result != MCDisassembler::Fail) {
 467     Size = 4;
 468     return Result;
 469   }
 470
 471   return MCDisassembler::Fail;
 472 }
 473
 474 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 475   const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
 476   const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
 477   return *(RegInfo->getRegClass(RC).begin() + RegNo);
 478 }
 479
 480 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 481                                                  unsigned RegNo,
 482                                                  uint64_t Address,
 483                                                  const void *Decoder) {
 484
 485   return MCDisassembler::Fail;
 486
 487 }
 488
 489 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
 490                                              unsigned RegNo,
 491                                              uint64_t Address,
 492                                              const void *Decoder) {
 493
 494   if (RegNo > 31)
 495     return MCDisassembler::Fail;
 496
 497   unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
 498   Inst.addOperand(MCOperand::CreateReg(Reg));
 499   return MCDisassembler::Success;
 500 }
 501
 502 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 503                                              unsigned RegNo,
 504                                              uint64_t Address,
 505                                              const void *Decoder) {
 506   if (RegNo > 31)
 507     return MCDisassembler::Fail;
 508   unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
 509   Inst.addOperand(MCOperand::CreateReg(Reg));
 510   return MCDisassembler::Success;
 511 }
 512
 513 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 514                                            unsigned RegNo,
 515                                            uint64_t Address,
 516                                            const void *Decoder) {
 517   if (static_cast<const MipsDisassembler *>(Decoder)->isN64())
 518     return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
 519
 520   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 521 }
 522
 523 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 524                                             unsigned RegNo,
 525                                             uint64_t Address,
 526                                             const void *Decoder) {
 527   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 528 }
 529
 530 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 531                                              unsigned RegNo,
 532                                              uint64_t Address,
 533                                              const void *Decoder) {
 534   if (RegNo > 31)
 535     return MCDisassembler::Fail;
 536
 537   unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
 538   Inst.addOperand(MCOperand::CreateReg(Reg));
 539   return MCDisassembler::Success;
 540 }
 541
 542 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 543                                              unsigned RegNo,
 544                                              uint64_t Address,
 545                                              const void *Decoder) {
 546   if (RegNo > 31)
 547     return MCDisassembler::Fail;
 548
 549   unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
 550   Inst.addOperand(MCOperand::CreateReg(Reg));
 551   return MCDisassembler::Success;
 552 }
 553
 554 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
 555                                               unsigned RegNo,
 556                                               uint64_t Address,
 557                                               const void *Decoder) {
 558   if (RegNo > 31)
 559     return MCDisassembler::Fail;
 560
 561   unsigned Reg = getReg(Decoder, Mips::FGRH32RegClassID, RegNo);
 562   Inst.addOperand(MCOperand::CreateReg(Reg));
 563   return MCDisassembler::Success;
 564 }
 565
 566 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 567                                            unsigned RegNo,
 568                                            uint64_t Address,
 569                                            const void *Decoder) {
 570   if (RegNo > 31)
 571     return MCDisassembler::Fail;
 572   unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
 573   Inst.addOperand(MCOperand::CreateReg(Reg));
 574   return MCDisassembler::Success;
 575 }
 576
 577 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 578                                            unsigned RegNo,
 579                                            uint64_t Address,
 580                                            const void *Decoder) {
 581   if (RegNo > 7)
 582     return MCDisassembler::Fail;
 583   unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
 584   Inst.addOperand(MCOperand::CreateReg(Reg));
 585   return MCDisassembler::Success;
 586 }
 587
 588 static DecodeStatus DecodeMem(MCInst &Inst,
 589                               unsigned Insn,
 590                               uint64_t Address,
 591                               const void *Decoder) {
 592   int Offset = SignExtend32<16>(Insn & 0xffff);
 593   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
 594   unsigned Base = fieldFromInstruction(Insn, 21, 5);
 595
 596   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
 597   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 598
 599   if(Inst.getOpcode() == Mips::SC){
 600     Inst.addOperand(MCOperand::CreateReg(Reg));
 601   }
 602
 603   Inst.addOperand(MCOperand::CreateReg(Reg));
 604   Inst.addOperand(MCOperand::CreateReg(Base));
 605   Inst.addOperand(MCOperand::CreateImm(Offset));
 606
 607   return MCDisassembler::Success;
 608 }
 609
 610 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 611                                     uint64_t Address, const void *Decoder) {
 612   int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
 613   unsigned Reg = fieldFromInstruction(Insn, 6, 5);
 614   unsigned Base = fieldFromInstruction(Insn, 11, 5);
 615
 616   Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
 617   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 618
 619   Inst.addOperand(MCOperand::CreateReg(Reg));
 620   Inst.addOperand(MCOperand::CreateReg(Base));
 621
 622   // The immediate field of an LD/ST instruction is scaled which means it must
 623   // be multiplied (when decoding) by the size (in bytes) of the instructions'
 624   // data format.
 625   // .b - 1 byte
 626   // .h - 2 bytes
 627   // .w - 4 bytes
 628   // .d - 8 bytes
 629   switch(Inst.getOpcode())
 630   {
 631   default:
 632     assert (0 && "Unexpected instruction");
 633     return MCDisassembler::Fail;
 634     break;
 635   case Mips::LD_B:
 636   case Mips::ST_B:
 637     Inst.addOperand(MCOperand::CreateImm(Offset));
 638     break;
 639   case Mips::LD_H:
 640   case Mips::ST_H:
 641     Inst.addOperand(MCOperand::CreateImm(Offset << 1));
 642     break;
 643   case Mips::LD_W:
 644   case Mips::ST_W:
 645     Inst.addOperand(MCOperand::CreateImm(Offset << 2));
 646     break;
 647   case Mips::LD_D:
 648   case Mips::ST_D:
 649     Inst.addOperand(MCOperand::CreateImm(Offset << 3));
 650     break;
 651   }
 652
 653   return MCDisassembler::Success;
 654 }
 655
 656 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 657                                      unsigned Insn,
 658                                      uint64_t Address,
 659                                      const void *Decoder) {
 660   int Offset = SignExtend32<12>(Insn & 0x0fff);
 661   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
 662   unsigned Base = fieldFromInstruction(Insn, 16, 5);
 663
 664   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
 665   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 666
 667   if (Inst.getOpcode() == Mips::SC_MM)
 668     Inst.addOperand(MCOperand::CreateReg(Reg));
 669
 670   Inst.addOperand(MCOperand::CreateReg(Reg));
 671   Inst.addOperand(MCOperand::CreateReg(Base));
 672   Inst.addOperand(MCOperand::CreateImm(Offset));
 673
 674   return MCDisassembler::Success;
 675 }
 676
 677 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 678                                      unsigned Insn,
 679                                      uint64_t Address,
 680                                      const void *Decoder) {
 681   int Offset = SignExtend32<16>(Insn & 0xffff);
 682   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
 683   unsigned Base = fieldFromInstruction(Insn, 16, 5);
 684
 685   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
 686   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 687
 688   Inst.addOperand(MCOperand::CreateReg(Reg));
 689   Inst.addOperand(MCOperand::CreateReg(Base));
 690   Inst.addOperand(MCOperand::CreateImm(Offset));
 691
 692   return MCDisassembler::Success;
 693 }
 694
 695 static DecodeStatus DecodeFMem(MCInst &Inst,
 696                                unsigned Insn,
 697                                uint64_t Address,
 698                                const void *Decoder) {
 699   int Offset = SignExtend32<16>(Insn & 0xffff);
 700   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
 701   unsigned Base = fieldFromInstruction(Insn, 21, 5);
 702
 703   Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
 704   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 705
 706   Inst.addOperand(MCOperand::CreateReg(Reg));
 707   Inst.addOperand(MCOperand::CreateReg(Base));
 708   Inst.addOperand(MCOperand::CreateImm(Offset));
 709
 710   return MCDisassembler::Success;
 711 }
 712
 713
 714 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 715                                               unsigned RegNo,
 716                                               uint64_t Address,
 717                                               const void *Decoder) {
 718   // Currently only hardware register 29 is supported.
 719   if (RegNo != 29)
 720     return  MCDisassembler::Fail;
 721   Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
 722   return MCDisassembler::Success;
 723 }
 724
 725 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 726                                               unsigned RegNo,
 727                                               uint64_t Address,
 728                                               const void *Decoder) {
 729   if (RegNo > 30 || RegNo %2)
 730     return MCDisassembler::Fail;
 731
 732   ;
 733   unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
 734   Inst.addOperand(MCOperand::CreateReg(Reg));
 735   return MCDisassembler::Success;
 736 }
 737
 738 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 739                                                 unsigned RegNo,
 740                                                 uint64_t Address,
 741                                                 const void *Decoder) {
 742   if (RegNo >= 4)
 743     return MCDisassembler::Fail;
 744
 745   unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
 746   Inst.addOperand(MCOperand::CreateReg(Reg));
 747   return MCDisassembler::Success;
 748 }
 749
 750 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 751                                                unsigned RegNo,
 752                                                uint64_t Address,
 753                                                const void *Decoder) {
 754   if (RegNo >= 4)
 755     return MCDisassembler::Fail;
 756
 757   unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
 758   Inst.addOperand(MCOperand::CreateReg(Reg));
 759   return MCDisassembler::Success;
 760 }
 761
 762 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 763                                                unsigned RegNo,
 764                                                uint64_t Address,
 765                                                const void *Decoder) {
 766   if (RegNo >= 4)
 767     return MCDisassembler::Fail;
 768
 769   unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
 770   Inst.addOperand(MCOperand::CreateReg(Reg));
 771   return MCDisassembler::Success;
 772 }
 773
 774 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
 775                                                unsigned RegNo,
 776                                                uint64_t Address,
 777                                                const void *Decoder) {
 778   if (RegNo > 31)
 779     return MCDisassembler::Fail;
 780
 781   unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
 782   Inst.addOperand(MCOperand::CreateReg(Reg));
 783   return MCDisassembler::Success;
 784 }
 785
 786 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 787                                                unsigned RegNo,
 788                                                uint64_t Address,
 789                                                const void *Decoder) {
 790   if (RegNo > 31)
 791     return MCDisassembler::Fail;
 792
 793   unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
 794   Inst.addOperand(MCOperand::CreateReg(Reg));
 795   return MCDisassembler::Success;
 796 }
 797
 798 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 799                                                unsigned RegNo,
 800                                                uint64_t Address,
 801                                                const void *Decoder) {
 802   if (RegNo > 31)
 803     return MCDisassembler::Fail;
 804
 805   unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
 806   Inst.addOperand(MCOperand::CreateReg(Reg));
 807   return MCDisassembler::Success;
 808 }
 809
 810 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 811                                                unsigned RegNo,
 812                                                uint64_t Address,
 813                                                const void *Decoder) {
 814   if (RegNo > 31)
 815     return MCDisassembler::Fail;
 816
 817   unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
 818   Inst.addOperand(MCOperand::CreateReg(Reg));
 819   return MCDisassembler::Success;
 820 }
 821
 822 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
 823                                                unsigned RegNo,
 824                                                uint64_t Address,
 825                                                const void *Decoder) {
 826   if (RegNo > 7)
 827     return MCDisassembler::Fail;
 828
 829   unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
 830   Inst.addOperand(MCOperand::CreateReg(Reg));
 831   return MCDisassembler::Success;
 832 }
 833
 834 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 835                                        unsigned Offset,
 836                                        uint64_t Address,
 837                                        const void *Decoder) {
 838   unsigned BranchOffset = Offset & 0xffff;
 839   BranchOffset = SignExtend32<18>(BranchOffset << 2) + 4;
 840   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
 841   return MCDisassembler::Success;
 842 }
 843
 844 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 845                                      unsigned Insn,
 846                                      uint64_t Address,
 847                                      const void *Decoder) {
 848
 849   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
 850   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
 851   return MCDisassembler::Success;
 852 }
 853
 854 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
 855                                          unsigned Offset,
 856                                          uint64_t Address,
 857                                          const void *Decoder) {
 858   unsigned BranchOffset = Offset & 0xffff;
 859   BranchOffset = SignExtend32<18>(BranchOffset << 1);
 860   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
 861   return MCDisassembler::Success;
 862 }
 863
 864 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
 865                                        unsigned Insn,
 866                                        uint64_t Address,
 867                                        const void *Decoder) {
 868   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
 869   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
 870   return MCDisassembler::Success;
 871 }
 872
 873 static DecodeStatus DecodeSimm16(MCInst &Inst,
 874                                  unsigned Insn,
 875                                  uint64_t Address,
 876                                  const void *Decoder) {
 877   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
 878   return MCDisassembler::Success;
 879 }
 880
 881 static DecodeStatus DecodeLSAImm(MCInst &Inst,
 882                                  unsigned Insn,
 883                                  uint64_t Address,
 884                                  const void *Decoder) {
 885   // We add one to the immediate field as it was encoded as 'imm - 1'.
 886   Inst.addOperand(MCOperand::CreateImm(Insn + 1));
 887   return MCDisassembler::Success;
 888 }
 889
 890 static DecodeStatus DecodeInsSize(MCInst &Inst,
 891                                   unsigned Insn,
 892                                   uint64_t Address,
 893                                   const void *Decoder) {
 894   // First we need to grab the pos(lsb) from MCInst.
 895   int Pos = Inst.getOperand(2).getImm();
 896   int Size = (int) Insn - Pos + 1;
 897   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
 898   return MCDisassembler::Success;
 899 }
 900
 901 static DecodeStatus DecodeExtSize(MCInst &Inst,
 902                                   unsigned Insn,
 903                                   uint64_t Address,
 904                                   const void *Decoder) {
 905   int Size = (int) Insn  + 1;
 906   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
 907   return MCDisassembler::Success;
 908 }