1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the Mips Disassembler.
12 //===----------------------------------------------------------------------===//
15 #include "MipsRegisterInfo.h"
16 #include "MipsSubtarget.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCDisassembler.h"
19 #include "llvm/MC/MCFixedLenDisassembler.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/Support/MathExtras.h"
23 #include "llvm/Support/TargetRegistry.h"
27 #define DEBUG_TYPE "mips-disassembler"
29 typedef MCDisassembler::DecodeStatus DecodeStatus;
33 /// A disassembler class for Mips.
34 class MipsDisassemblerBase : public MCDisassembler {
36 MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx,
38 : MCDisassembler(STI, Ctx),
39 IsGP64Bit(STI.getFeatureBits() & Mips::FeatureGP64Bit),
40 IsBigEndian(IsBigEndian) {}
42 virtual ~MipsDisassemblerBase() {}
44 bool isGP64Bit() const { return IsGP64Bit; }
52 /// A disassembler class for Mips32.
53 class MipsDisassembler : public MipsDisassemblerBase {
56 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool bigEndian)
57 : MipsDisassemblerBase(STI, Ctx, bigEndian) {
58 IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
61 bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; }
62 bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; }
63 bool hasMips32r6() const {
64 return STI.getFeatureBits() & Mips::FeatureMips32r6;
67 bool isGP64() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; }
69 bool hasCOP3() const {
70 // Only present in MIPS-I and MIPS-II
71 return !hasMips32() && !hasMips3();
74 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
75 ArrayRef<uint8_t> Bytes, uint64_t Address,
77 raw_ostream &CStream) const override;
80 /// A disassembler class for Mips64.
81 class Mips64Disassembler : public MipsDisassemblerBase {
83 Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
85 MipsDisassemblerBase(STI, Ctx, bigEndian) {}
87 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
88 ArrayRef<uint8_t> Bytes, uint64_t Address,
90 raw_ostream &CStream) const override;
93 } // end anonymous namespace
95 // Forward declare these because the autogenerated code will reference them.
96 // Definitions are further down.
97 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
100 const void *Decoder);
102 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
105 const void *Decoder);
107 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
110 const void *Decoder);
112 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
115 const void *Decoder);
117 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
120 const void *Decoder);
122 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
125 const void *Decoder);
127 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
130 const void *Decoder);
132 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
135 const void *Decoder);
137 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
140 const void *Decoder);
142 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
145 const void *Decoder);
147 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
150 const void *Decoder);
152 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
154 const void *Decoder);
156 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
159 const void *Decoder);
161 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
164 const void *Decoder);
166 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
169 const void *Decoder);
171 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
174 const void *Decoder);
176 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
179 const void *Decoder);
181 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
184 const void *Decoder);
186 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
189 const void *Decoder);
191 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
194 const void *Decoder);
196 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
199 const void *Decoder);
201 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
204 const void *Decoder);
206 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
209 const void *Decoder);
211 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
214 const void *Decoder);
216 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
219 const void *Decoder);
221 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
224 const void *Decoder);
226 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
229 const void *Decoder);
231 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
232 // shifted left by 1 bit.
233 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
236 const void *Decoder);
238 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is
239 // shifted left by 1 bit.
240 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
243 const void *Decoder);
245 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
246 // shifted left by 1 bit.
247 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
250 const void *Decoder);
252 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
253 // shifted left by 1 bit.
254 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
257 const void *Decoder);
259 static DecodeStatus DecodeMem(MCInst &Inst,
262 const void *Decoder);
264 static DecodeStatus DecodeCacheOp(MCInst &Inst,
267 const void *Decoder);
269 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
272 const void *Decoder);
274 static DecodeStatus DecodeSyncI(MCInst &Inst,
277 const void *Decoder);
279 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
280 uint64_t Address, const void *Decoder);
282 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
285 const void *Decoder);
287 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
290 const void *Decoder);
292 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
295 const void *Decoder);
297 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
300 const void *Decoder);
302 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
305 const void *Decoder);
307 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
309 const void *Decoder);
311 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
313 const void *Decoder);
315 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn,
317 const void *Decoder);
319 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
321 const void *Decoder);
323 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
326 const void *Decoder);
328 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
331 const void *Decoder);
333 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
336 const void *Decoder);
338 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
341 const void *Decoder);
343 static DecodeStatus DecodeSimm4(MCInst &Inst,
346 const void *Decoder);
348 static DecodeStatus DecodeSimm16(MCInst &Inst,
351 const void *Decoder);
353 // Decode the immediate field of an LSA instruction which
355 static DecodeStatus DecodeLSAImm(MCInst &Inst,
358 const void *Decoder);
360 static DecodeStatus DecodeInsSize(MCInst &Inst,
363 const void *Decoder);
365 static DecodeStatus DecodeExtSize(MCInst &Inst,
368 const void *Decoder);
370 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
371 uint64_t Address, const void *Decoder);
373 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
374 uint64_t Address, const void *Decoder);
376 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
377 uint64_t Address, const void *Decoder);
379 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
380 uint64_t Address, const void *Decoder);
382 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
383 uint64_t Address, const void *Decoder);
385 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
386 uint64_t Address, const void *Decoder);
388 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
390 template <typename InsnType>
391 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
392 const void *Decoder);
394 template <typename InsnType>
396 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
397 const void *Decoder);
399 template <typename InsnType>
401 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
402 const void *Decoder);
404 template <typename InsnType>
406 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
407 const void *Decoder);
409 template <typename InsnType>
411 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
412 const void *Decoder);
414 template <typename InsnType>
416 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
417 const void *Decoder);
419 template <typename InsnType>
421 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
422 const void *Decoder);
424 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
426 const void *Decoder);
428 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
430 const void *Decoder);
433 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
437 static MCDisassembler *createMipsDisassembler(
439 const MCSubtargetInfo &STI,
441 return new MipsDisassembler(STI, Ctx, true);
444 static MCDisassembler *createMipselDisassembler(
446 const MCSubtargetInfo &STI,
448 return new MipsDisassembler(STI, Ctx, false);
451 static MCDisassembler *createMips64Disassembler(
453 const MCSubtargetInfo &STI,
455 return new Mips64Disassembler(STI, Ctx, true);
458 static MCDisassembler *createMips64elDisassembler(
460 const MCSubtargetInfo &STI,
462 return new Mips64Disassembler(STI, Ctx, false);
465 extern "C" void LLVMInitializeMipsDisassembler() {
466 // Register the disassembler.
467 TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
468 createMipsDisassembler);
469 TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
470 createMipselDisassembler);
471 TargetRegistry::RegisterMCDisassembler(TheMips64Target,
472 createMips64Disassembler);
473 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
474 createMips64elDisassembler);
477 #include "MipsGenDisassemblerTables.inc"
479 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
480 const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
481 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
482 return *(RegInfo->getRegClass(RC).begin() + RegNo);
485 template <typename InsnType>
486 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
487 const void *Decoder) {
488 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
489 // The size of the n field depends on the element size
490 // The register class also depends on this.
491 InsnType tmp = fieldFromInstruction(insn, 17, 5);
493 DecodeFN RegDecoder = nullptr;
494 if ((tmp & 0x18) == 0x00) { // INSVE_B
496 RegDecoder = DecodeMSA128BRegisterClass;
497 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
499 RegDecoder = DecodeMSA128HRegisterClass;
500 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
502 RegDecoder = DecodeMSA128WRegisterClass;
503 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
505 RegDecoder = DecodeMSA128DRegisterClass;
507 llvm_unreachable("Invalid encoding");
509 assert(NSize != 0 && RegDecoder != nullptr);
512 tmp = fieldFromInstruction(insn, 6, 5);
513 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
514 return MCDisassembler::Fail;
516 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
517 return MCDisassembler::Fail;
519 tmp = fieldFromInstruction(insn, 16, NSize);
520 MI.addOperand(MCOperand::CreateImm(tmp));
522 tmp = fieldFromInstruction(insn, 11, 5);
523 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
524 return MCDisassembler::Fail;
526 MI.addOperand(MCOperand::CreateImm(0));
528 return MCDisassembler::Success;
531 template <typename InsnType>
532 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
534 const void *Decoder) {
535 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
536 // (otherwise we would have matched the ADDI instruction from the earlier
540 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii
542 // BEQZALC if rs == 0 && rt != 0
543 // BEQC if rs < rt && rs != 0
545 InsnType Rs = fieldFromInstruction(insn, 21, 5);
546 InsnType Rt = fieldFromInstruction(insn, 16, 5);
547 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
551 MI.setOpcode(Mips::BOVC);
553 } else if (Rs != 0 && Rs < Rt) {
554 MI.setOpcode(Mips::BEQC);
557 MI.setOpcode(Mips::BEQZALC);
560 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
563 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
565 MI.addOperand(MCOperand::CreateImm(Imm));
567 return MCDisassembler::Success;
570 template <typename InsnType>
571 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
573 const void *Decoder) {
574 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
575 // (otherwise we would have matched the ADDI instruction from the earlier
579 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii
581 // BNEZALC if rs == 0 && rt != 0
582 // BNEC if rs < rt && rs != 0
584 InsnType Rs = fieldFromInstruction(insn, 21, 5);
585 InsnType Rt = fieldFromInstruction(insn, 16, 5);
586 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
590 MI.setOpcode(Mips::BNVC);
592 } else if (Rs != 0 && Rs < Rt) {
593 MI.setOpcode(Mips::BNEC);
596 MI.setOpcode(Mips::BNEZALC);
599 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
602 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
604 MI.addOperand(MCOperand::CreateImm(Imm));
606 return MCDisassembler::Success;
609 template <typename InsnType>
610 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
612 const void *Decoder) {
613 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
614 // (otherwise we would have matched the BLEZL instruction from the earlier
618 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii
619 // Invalid if rs == 0
620 // BLEZC if rs == 0 && rt != 0
621 // BGEZC if rs == rt && rt != 0
622 // BGEC if rs != rt && rs != 0 && rt != 0
624 InsnType Rs = fieldFromInstruction(insn, 21, 5);
625 InsnType Rt = fieldFromInstruction(insn, 16, 5);
626 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
630 return MCDisassembler::Fail;
632 MI.setOpcode(Mips::BLEZC);
634 MI.setOpcode(Mips::BGEZC);
637 MI.setOpcode(Mips::BGEC);
641 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
644 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
647 MI.addOperand(MCOperand::CreateImm(Imm));
649 return MCDisassembler::Success;
652 template <typename InsnType>
653 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
655 const void *Decoder) {
656 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
657 // (otherwise we would have matched the BGTZL instruction from the earlier
661 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii
662 // Invalid if rs == 0
663 // BGTZC if rs == 0 && rt != 0
664 // BLTZC if rs == rt && rt != 0
665 // BLTC if rs != rt && rs != 0 && rt != 0
669 InsnType Rs = fieldFromInstruction(insn, 21, 5);
670 InsnType Rt = fieldFromInstruction(insn, 16, 5);
671 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
674 return MCDisassembler::Fail;
676 MI.setOpcode(Mips::BGTZC);
678 MI.setOpcode(Mips::BLTZC);
680 MI.setOpcode(Mips::BLTC);
685 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
688 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
691 MI.addOperand(MCOperand::CreateImm(Imm));
693 return MCDisassembler::Success;
696 template <typename InsnType>
697 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
699 const void *Decoder) {
700 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
701 // (otherwise we would have matched the BGTZ instruction from the earlier
705 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii
707 // BGTZALC if rs == 0 && rt != 0
708 // BLTZALC if rs != 0 && rs == rt
709 // BLTUC if rs != 0 && rs != rt
711 InsnType Rs = fieldFromInstruction(insn, 21, 5);
712 InsnType Rt = fieldFromInstruction(insn, 16, 5);
713 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
718 MI.setOpcode(Mips::BGTZ);
720 } else if (Rs == 0) {
721 MI.setOpcode(Mips::BGTZALC);
723 } else if (Rs == Rt) {
724 MI.setOpcode(Mips::BLTZALC);
727 MI.setOpcode(Mips::BLTUC);
733 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
737 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
740 MI.addOperand(MCOperand::CreateImm(Imm));
742 return MCDisassembler::Success;
745 template <typename InsnType>
746 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
748 const void *Decoder) {
749 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
750 // (otherwise we would have matched the BLEZL instruction from the earlier
754 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii
755 // Invalid if rs == 0
756 // BLEZALC if rs == 0 && rt != 0
757 // BGEZALC if rs == rt && rt != 0
758 // BGEUC if rs != rt && rs != 0 && rt != 0
760 InsnType Rs = fieldFromInstruction(insn, 21, 5);
761 InsnType Rt = fieldFromInstruction(insn, 16, 5);
762 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
766 return MCDisassembler::Fail;
768 MI.setOpcode(Mips::BLEZALC);
770 MI.setOpcode(Mips::BGEZALC);
773 MI.setOpcode(Mips::BGEUC);
777 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
779 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
782 MI.addOperand(MCOperand::CreateImm(Imm));
784 return MCDisassembler::Success;
787 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted
788 /// according to the given endianess.
789 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
790 uint64_t &Size, uint32_t &Insn,
792 // We want to read exactly 2 Bytes of data.
793 if (Bytes.size() < 2) {
795 return MCDisassembler::Fail;
799 Insn = (Bytes[0] << 8) | Bytes[1];
801 Insn = (Bytes[1] << 8) | Bytes[0];
804 return MCDisassembler::Success;
807 /// Read four bytes from the ArrayRef and return 32 bit word sorted
808 /// according to the given endianess
809 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
810 uint64_t &Size, uint32_t &Insn,
811 bool IsBigEndian, bool IsMicroMips) {
812 // We want to read exactly 4 Bytes of data.
813 if (Bytes.size() < 4) {
815 return MCDisassembler::Fail;
818 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
819 // always precede the low 16 bits in the instruction stream (that is, they
820 // are placed at lower addresses in the instruction stream).
822 // microMIPS byte ordering:
823 // Big-endian: 0 | 1 | 2 | 3
824 // Little-endian: 1 | 0 | 3 | 2
827 // Encoded as a big-endian 32-bit word in the stream.
829 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
832 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
835 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
840 return MCDisassembler::Success;
843 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
844 ArrayRef<uint8_t> Bytes,
846 raw_ostream &VStream,
847 raw_ostream &CStream) const {
852 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
854 DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
855 // Calling the auto-generated decoder function.
856 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
858 if (Result != MCDisassembler::Fail) {
863 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
864 if (Result == MCDisassembler::Fail)
865 return MCDisassembler::Fail;
867 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
868 // Calling the auto-generated decoder function.
869 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
871 if (Result != MCDisassembler::Fail) {
875 return MCDisassembler::Fail;
878 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
879 if (Result == MCDisassembler::Fail)
880 return MCDisassembler::Fail;
883 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
885 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
886 if (Result != MCDisassembler::Fail) {
892 if (hasMips32r6() && isGP64()) {
893 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
894 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
896 if (Result != MCDisassembler::Fail) {
903 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
904 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
906 if (Result != MCDisassembler::Fail) {
912 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
913 // Calling the auto-generated decoder function.
915 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
916 if (Result != MCDisassembler::Fail) {
921 return MCDisassembler::Fail;
924 DecodeStatus Mips64Disassembler::getInstruction(MCInst &Instr, uint64_t &Size,
925 ArrayRef<uint8_t> Bytes,
927 raw_ostream &VStream,
928 raw_ostream &CStream) const {
931 DecodeStatus Result =
932 readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
933 if (Result == MCDisassembler::Fail)
934 return MCDisassembler::Fail;
936 // Calling the auto-generated decoder function.
938 decodeInstruction(DecoderTableMips6432, Instr, Insn, Address, this, STI);
939 if (Result != MCDisassembler::Fail) {
943 // If we fail to decode in Mips64 decoder space we can try in Mips32
945 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
946 if (Result != MCDisassembler::Fail) {
951 return MCDisassembler::Fail;
954 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
957 const void *Decoder) {
959 return MCDisassembler::Fail;
963 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
966 const void *Decoder) {
969 return MCDisassembler::Fail;
971 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
972 Inst.addOperand(MCOperand::CreateReg(Reg));
973 return MCDisassembler::Success;
976 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
979 const void *Decoder) {
981 return MCDisassembler::Fail;
982 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
983 Inst.addOperand(MCOperand::CreateReg(Reg));
984 return MCDisassembler::Success;
987 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
990 const void *Decoder) {
992 return MCDisassembler::Fail;
993 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
994 Inst.addOperand(MCOperand::CreateReg(Reg));
995 return MCDisassembler::Success;
998 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
1001 const void *Decoder) {
1003 return MCDisassembler::Fail;
1004 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
1005 Inst.addOperand(MCOperand::CreateReg(Reg));
1006 return MCDisassembler::Success;
1009 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
1012 const void *Decoder) {
1013 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64Bit())
1014 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
1016 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1019 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
1022 const void *Decoder) {
1023 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1026 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
1029 const void *Decoder) {
1031 return MCDisassembler::Fail;
1033 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
1034 Inst.addOperand(MCOperand::CreateReg(Reg));
1035 return MCDisassembler::Success;
1038 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
1041 const void *Decoder) {
1043 return MCDisassembler::Fail;
1045 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
1046 Inst.addOperand(MCOperand::CreateReg(Reg));
1047 return MCDisassembler::Success;
1050 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
1053 const void *Decoder) {
1055 return MCDisassembler::Fail;
1056 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
1057 Inst.addOperand(MCOperand::CreateReg(Reg));
1058 return MCDisassembler::Success;
1061 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
1064 const void *Decoder) {
1066 return MCDisassembler::Fail;
1067 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
1068 Inst.addOperand(MCOperand::CreateReg(Reg));
1069 return MCDisassembler::Success;
1072 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
1074 const void *Decoder) {
1076 return MCDisassembler::Fail;
1078 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
1079 Inst.addOperand(MCOperand::CreateReg(Reg));
1080 return MCDisassembler::Success;
1083 static DecodeStatus DecodeMem(MCInst &Inst,
1086 const void *Decoder) {
1087 int Offset = SignExtend32<16>(Insn & 0xffff);
1088 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1089 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1091 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1092 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1094 if(Inst.getOpcode() == Mips::SC ||
1095 Inst.getOpcode() == Mips::SCD){
1096 Inst.addOperand(MCOperand::CreateReg(Reg));
1099 Inst.addOperand(MCOperand::CreateReg(Reg));
1100 Inst.addOperand(MCOperand::CreateReg(Base));
1101 Inst.addOperand(MCOperand::CreateImm(Offset));
1103 return MCDisassembler::Success;
1106 static DecodeStatus DecodeCacheOp(MCInst &Inst,
1109 const void *Decoder) {
1110 int Offset = SignExtend32<16>(Insn & 0xffff);
1111 unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1112 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1114 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1116 Inst.addOperand(MCOperand::CreateReg(Base));
1117 Inst.addOperand(MCOperand::CreateImm(Offset));
1118 Inst.addOperand(MCOperand::CreateImm(Hint));
1120 return MCDisassembler::Success;
1123 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
1126 const void *Decoder) {
1127 int Offset = SignExtend32<12>(Insn & 0xfff);
1128 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1129 unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1131 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1133 Inst.addOperand(MCOperand::CreateReg(Base));
1134 Inst.addOperand(MCOperand::CreateImm(Offset));
1135 Inst.addOperand(MCOperand::CreateImm(Hint));
1137 return MCDisassembler::Success;
1140 static DecodeStatus DecodeSyncI(MCInst &Inst,
1143 const void *Decoder) {
1144 int Offset = SignExtend32<16>(Insn & 0xffff);
1145 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1147 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1149 Inst.addOperand(MCOperand::CreateReg(Base));
1150 Inst.addOperand(MCOperand::CreateImm(Offset));
1152 return MCDisassembler::Success;
1155 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1156 uint64_t Address, const void *Decoder) {
1157 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1158 unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1159 unsigned Base = fieldFromInstruction(Insn, 11, 5);
1161 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1162 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1164 Inst.addOperand(MCOperand::CreateReg(Reg));
1165 Inst.addOperand(MCOperand::CreateReg(Base));
1167 // The immediate field of an LD/ST instruction is scaled which means it must
1168 // be multiplied (when decoding) by the size (in bytes) of the instructions'
1174 switch(Inst.getOpcode())
1177 assert (0 && "Unexpected instruction");
1178 return MCDisassembler::Fail;
1182 Inst.addOperand(MCOperand::CreateImm(Offset));
1186 Inst.addOperand(MCOperand::CreateImm(Offset * 2));
1190 Inst.addOperand(MCOperand::CreateImm(Offset * 4));
1194 Inst.addOperand(MCOperand::CreateImm(Offset * 8));
1198 return MCDisassembler::Success;
1201 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
1204 const void *Decoder) {
1205 unsigned Offset = Insn & 0xf;
1206 unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1207 unsigned Base = fieldFromInstruction(Insn, 4, 3);
1209 switch (Inst.getOpcode()) {
1210 case Mips::LBU16_MM:
1211 case Mips::LHU16_MM:
1213 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1214 == MCDisassembler::Fail)
1215 return MCDisassembler::Fail;
1220 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1221 == MCDisassembler::Fail)
1222 return MCDisassembler::Fail;
1226 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1227 == MCDisassembler::Fail)
1228 return MCDisassembler::Fail;
1230 switch (Inst.getOpcode()) {
1231 case Mips::LBU16_MM:
1233 Inst.addOperand(MCOperand::CreateImm(-1));
1235 Inst.addOperand(MCOperand::CreateImm(Offset));
1238 Inst.addOperand(MCOperand::CreateImm(Offset));
1240 case Mips::LHU16_MM:
1242 Inst.addOperand(MCOperand::CreateImm(Offset << 1));
1246 Inst.addOperand(MCOperand::CreateImm(Offset << 2));
1250 return MCDisassembler::Success;
1253 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
1256 const void *Decoder) {
1257 unsigned Offset = Insn & 0x1F;
1258 unsigned Reg = fieldFromInstruction(Insn, 5, 5);
1260 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1262 Inst.addOperand(MCOperand::CreateReg(Reg));
1263 Inst.addOperand(MCOperand::CreateReg(Mips::SP));
1264 Inst.addOperand(MCOperand::CreateImm(Offset << 2));
1266 return MCDisassembler::Success;
1269 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
1272 const void *Decoder) {
1273 unsigned Offset = Insn & 0x7F;
1274 unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1276 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1278 Inst.addOperand(MCOperand::CreateReg(Reg));
1279 Inst.addOperand(MCOperand::CreateReg(Mips::GP));
1280 Inst.addOperand(MCOperand::CreateImm(Offset << 2));
1282 return MCDisassembler::Success;
1285 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1288 const void *Decoder) {
1289 int Offset = SignExtend32<12>(Insn & 0x0fff);
1290 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1291 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1293 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1294 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1296 switch (Inst.getOpcode()) {
1297 case Mips::SWM32_MM:
1298 case Mips::LWM32_MM:
1299 if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1300 == MCDisassembler::Fail)
1301 return MCDisassembler::Fail;
1302 Inst.addOperand(MCOperand::CreateReg(Base));
1303 Inst.addOperand(MCOperand::CreateImm(Offset));
1306 Inst.addOperand(MCOperand::CreateReg(Reg));
1309 Inst.addOperand(MCOperand::CreateReg(Reg));
1310 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
1311 Inst.addOperand(MCOperand::CreateReg(Reg+1));
1313 Inst.addOperand(MCOperand::CreateReg(Base));
1314 Inst.addOperand(MCOperand::CreateImm(Offset));
1317 return MCDisassembler::Success;
1320 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1323 const void *Decoder) {
1324 int Offset = SignExtend32<16>(Insn & 0xffff);
1325 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1326 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1328 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1329 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1331 Inst.addOperand(MCOperand::CreateReg(Reg));
1332 Inst.addOperand(MCOperand::CreateReg(Base));
1333 Inst.addOperand(MCOperand::CreateImm(Offset));
1335 return MCDisassembler::Success;
1338 static DecodeStatus DecodeFMem(MCInst &Inst,
1341 const void *Decoder) {
1342 int Offset = SignExtend32<16>(Insn & 0xffff);
1343 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1344 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1346 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1347 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1349 Inst.addOperand(MCOperand::CreateReg(Reg));
1350 Inst.addOperand(MCOperand::CreateReg(Base));
1351 Inst.addOperand(MCOperand::CreateImm(Offset));
1353 return MCDisassembler::Success;
1356 static DecodeStatus DecodeFMem2(MCInst &Inst,
1359 const void *Decoder) {
1360 int Offset = SignExtend32<16>(Insn & 0xffff);
1361 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1362 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1364 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1365 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1367 Inst.addOperand(MCOperand::CreateReg(Reg));
1368 Inst.addOperand(MCOperand::CreateReg(Base));
1369 Inst.addOperand(MCOperand::CreateImm(Offset));
1371 return MCDisassembler::Success;
1374 static DecodeStatus DecodeFMem3(MCInst &Inst,
1377 const void *Decoder) {
1378 int Offset = SignExtend32<16>(Insn & 0xffff);
1379 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1380 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1382 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1383 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1385 Inst.addOperand(MCOperand::CreateReg(Reg));
1386 Inst.addOperand(MCOperand::CreateReg(Base));
1387 Inst.addOperand(MCOperand::CreateImm(Offset));
1389 return MCDisassembler::Success;
1392 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst,
1395 const void *Decoder) {
1396 int Offset = SignExtend32<11>(Insn & 0x07ff);
1397 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1398 unsigned Base = fieldFromInstruction(Insn, 11, 5);
1400 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1401 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1403 Inst.addOperand(MCOperand::CreateReg(Reg));
1404 Inst.addOperand(MCOperand::CreateReg(Base));
1405 Inst.addOperand(MCOperand::CreateImm(Offset));
1407 return MCDisassembler::Success;
1409 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
1412 const void *Decoder) {
1413 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1414 unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1415 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1417 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1418 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1420 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1421 Inst.addOperand(MCOperand::CreateReg(Rt));
1424 Inst.addOperand(MCOperand::CreateReg(Rt));
1425 Inst.addOperand(MCOperand::CreateReg(Base));
1426 Inst.addOperand(MCOperand::CreateImm(Offset));
1428 return MCDisassembler::Success;
1431 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1434 const void *Decoder) {
1435 // Currently only hardware register 29 is supported.
1437 return MCDisassembler::Fail;
1438 Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
1439 return MCDisassembler::Success;
1442 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1445 const void *Decoder) {
1446 if (RegNo > 30 || RegNo %2)
1447 return MCDisassembler::Fail;
1450 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1451 Inst.addOperand(MCOperand::CreateReg(Reg));
1452 return MCDisassembler::Success;
1455 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1458 const void *Decoder) {
1460 return MCDisassembler::Fail;
1462 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1463 Inst.addOperand(MCOperand::CreateReg(Reg));
1464 return MCDisassembler::Success;
1467 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1470 const void *Decoder) {
1472 return MCDisassembler::Fail;
1474 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1475 Inst.addOperand(MCOperand::CreateReg(Reg));
1476 return MCDisassembler::Success;
1479 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1482 const void *Decoder) {
1484 return MCDisassembler::Fail;
1486 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1487 Inst.addOperand(MCOperand::CreateReg(Reg));
1488 return MCDisassembler::Success;
1491 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1494 const void *Decoder) {
1496 return MCDisassembler::Fail;
1498 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1499 Inst.addOperand(MCOperand::CreateReg(Reg));
1500 return MCDisassembler::Success;
1503 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1506 const void *Decoder) {
1508 return MCDisassembler::Fail;
1510 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1511 Inst.addOperand(MCOperand::CreateReg(Reg));
1512 return MCDisassembler::Success;
1515 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1518 const void *Decoder) {
1520 return MCDisassembler::Fail;
1522 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1523 Inst.addOperand(MCOperand::CreateReg(Reg));
1524 return MCDisassembler::Success;
1527 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1530 const void *Decoder) {
1532 return MCDisassembler::Fail;
1534 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1535 Inst.addOperand(MCOperand::CreateReg(Reg));
1536 return MCDisassembler::Success;
1539 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1542 const void *Decoder) {
1544 return MCDisassembler::Fail;
1546 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1547 Inst.addOperand(MCOperand::CreateReg(Reg));
1548 return MCDisassembler::Success;
1551 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1554 const void *Decoder) {
1556 return MCDisassembler::Fail;
1558 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1559 Inst.addOperand(MCOperand::CreateReg(Reg));
1560 return MCDisassembler::Success;
1563 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1566 const void *Decoder) {
1567 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
1568 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1569 return MCDisassembler::Success;
1572 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1575 const void *Decoder) {
1577 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1578 Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1579 return MCDisassembler::Success;
1582 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1585 const void *Decoder) {
1586 int32_t BranchOffset = SignExtend32<21>(Offset) * 4;
1588 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1589 return MCDisassembler::Success;
1592 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1595 const void *Decoder) {
1596 int32_t BranchOffset = SignExtend32<26>(Offset) * 4;
1598 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1599 return MCDisassembler::Success;
1602 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
1605 const void *Decoder) {
1606 int32_t BranchOffset = SignExtend32<7>(Offset) << 1;
1607 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1608 return MCDisassembler::Success;
1611 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
1614 const void *Decoder) {
1615 int32_t BranchOffset = SignExtend32<10>(Offset) << 1;
1616 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1617 return MCDisassembler::Success;
1620 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1623 const void *Decoder) {
1624 int32_t BranchOffset = SignExtend32<16>(Offset) * 2;
1625 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1626 return MCDisassembler::Success;
1629 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1632 const void *Decoder) {
1633 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1634 Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1635 return MCDisassembler::Success;
1638 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
1641 const void *Decoder) {
1643 Inst.addOperand(MCOperand::CreateImm(1));
1644 else if (Value == 0x7)
1645 Inst.addOperand(MCOperand::CreateImm(-1));
1647 Inst.addOperand(MCOperand::CreateImm(Value << 2));
1648 return MCDisassembler::Success;
1651 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
1654 const void *Decoder) {
1655 Inst.addOperand(MCOperand::CreateImm(Value << 2));
1656 return MCDisassembler::Success;
1659 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
1662 const void *Decoder) {
1664 Inst.addOperand(MCOperand::CreateImm(-1));
1666 Inst.addOperand(MCOperand::CreateImm(Value));
1667 return MCDisassembler::Success;
1670 static DecodeStatus DecodeSimm4(MCInst &Inst,
1673 const void *Decoder) {
1674 Inst.addOperand(MCOperand::CreateImm(SignExtend32<4>(Value)));
1675 return MCDisassembler::Success;
1678 static DecodeStatus DecodeSimm16(MCInst &Inst,
1681 const void *Decoder) {
1682 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
1683 return MCDisassembler::Success;
1686 static DecodeStatus DecodeLSAImm(MCInst &Inst,
1689 const void *Decoder) {
1690 // We add one to the immediate field as it was encoded as 'imm - 1'.
1691 Inst.addOperand(MCOperand::CreateImm(Insn + 1));
1692 return MCDisassembler::Success;
1695 static DecodeStatus DecodeInsSize(MCInst &Inst,
1698 const void *Decoder) {
1699 // First we need to grab the pos(lsb) from MCInst.
1700 int Pos = Inst.getOperand(2).getImm();
1701 int Size = (int) Insn - Pos + 1;
1702 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1703 return MCDisassembler::Success;
1706 static DecodeStatus DecodeExtSize(MCInst &Inst,
1709 const void *Decoder) {
1710 int Size = (int) Insn + 1;
1711 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1712 return MCDisassembler::Success;
1715 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1716 uint64_t Address, const void *Decoder) {
1717 Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) * 4));
1718 return MCDisassembler::Success;
1721 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1722 uint64_t Address, const void *Decoder) {
1723 Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) * 8));
1724 return MCDisassembler::Success;
1727 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
1728 uint64_t Address, const void *Decoder) {
1729 int32_t DecodedValue;
1731 case 0: DecodedValue = 256; break;
1732 case 1: DecodedValue = 257; break;
1733 case 510: DecodedValue = -258; break;
1734 case 511: DecodedValue = -257; break;
1735 default: DecodedValue = SignExtend32<9>(Insn); break;
1737 Inst.addOperand(MCOperand::CreateImm(DecodedValue * 4));
1738 return MCDisassembler::Success;
1741 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
1742 uint64_t Address, const void *Decoder) {
1743 // Insn must be >= 0, since it is unsigned that condition is always true.
1745 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
1747 Inst.addOperand(MCOperand::CreateImm(DecodedValues[Insn]));
1748 return MCDisassembler::Success;
1751 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
1752 uint64_t Address, const void *Decoder) {
1753 Inst.addOperand(MCOperand::CreateImm(Insn << 2));
1754 return MCDisassembler::Success;
1757 static DecodeStatus DecodeRegListOperand(MCInst &Inst,
1760 const void *Decoder) {
1761 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
1762 Mips::S6, Mips::FP};
1765 unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
1766 // Empty register lists are not allowed.
1768 return MCDisassembler::Fail;
1770 RegNum = RegLst & 0xf;
1771 for (unsigned i = 0; i < RegNum; i++)
1772 Inst.addOperand(MCOperand::CreateReg(Regs[i]));
1775 Inst.addOperand(MCOperand::CreateReg(Mips::RA));
1777 return MCDisassembler::Success;
1780 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
1782 const void *Decoder) {
1783 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
1786 unsigned RegLst = fieldFromInstruction(Insn, 4, 2);
1787 // Empty register lists are not allowed.
1789 return MCDisassembler::Fail;
1791 RegNum = RegLst & 0x3;
1792 for (unsigned i = 0; i < RegNum - 1; i++)
1793 Inst.addOperand(MCOperand::CreateReg(Regs[i]));
1795 Inst.addOperand(MCOperand::CreateReg(Mips::RA));
1797 return MCDisassembler::Success;
1800 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
1801 uint64_t Address, const void *Decoder) {
1802 Inst.addOperand(MCOperand::CreateImm(SignExtend32<23>(Insn) << 2));
1803 return MCDisassembler::Success;