1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the Mips Disassembler.
12 //===----------------------------------------------------------------------===//
15 #include "MipsRegisterInfo.h"
16 #include "MipsSubtarget.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCDisassembler.h"
19 #include "llvm/MC/MCFixedLenDisassembler.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/Support/MathExtras.h"
23 #include "llvm/Support/TargetRegistry.h"
27 #define DEBUG_TYPE "mips-disassembler"
29 typedef MCDisassembler::DecodeStatus DecodeStatus;
33 /// A disassembler class for Mips.
34 class MipsDisassemblerBase : public MCDisassembler {
36 MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx,
38 : MCDisassembler(STI, Ctx),
39 IsGP64Bit(STI.getFeatureBits() & Mips::FeatureGP64Bit),
40 IsBigEndian(IsBigEndian) {}
42 virtual ~MipsDisassemblerBase() {}
44 bool isGP64Bit() const { return IsGP64Bit; }
52 /// A disassembler class for Mips32.
53 class MipsDisassembler : public MipsDisassemblerBase {
56 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool bigEndian)
57 : MipsDisassemblerBase(STI, Ctx, bigEndian) {
58 IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
61 bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; }
62 bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; }
63 bool hasMips32r6() const {
64 return STI.getFeatureBits() & Mips::FeatureMips32r6;
67 bool isGP64() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; }
69 bool hasCOP3() const {
70 // Only present in MIPS-I and MIPS-II
71 return !hasMips32() && !hasMips3();
74 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
75 ArrayRef<uint8_t> Bytes, uint64_t Address,
77 raw_ostream &CStream) const override;
80 /// A disassembler class for Mips64.
81 class Mips64Disassembler : public MipsDisassemblerBase {
83 Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
85 MipsDisassemblerBase(STI, Ctx, bigEndian) {}
87 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
88 ArrayRef<uint8_t> Bytes, uint64_t Address,
90 raw_ostream &CStream) const override;
93 } // end anonymous namespace
95 // Forward declare these because the autogenerated code will reference them.
96 // Definitions are further down.
97 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
100 const void *Decoder);
102 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
105 const void *Decoder);
107 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
110 const void *Decoder);
112 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
115 const void *Decoder);
117 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
120 const void *Decoder);
122 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
125 const void *Decoder);
127 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
130 const void *Decoder);
132 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
135 const void *Decoder);
137 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
140 const void *Decoder);
142 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
145 const void *Decoder);
147 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
150 const void *Decoder);
152 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
154 const void *Decoder);
156 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
159 const void *Decoder);
161 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
164 const void *Decoder);
166 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
169 const void *Decoder);
171 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
174 const void *Decoder);
176 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
179 const void *Decoder);
181 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
184 const void *Decoder);
186 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
189 const void *Decoder);
191 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
194 const void *Decoder);
196 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
199 const void *Decoder);
201 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
204 const void *Decoder);
206 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
209 const void *Decoder);
211 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
214 const void *Decoder);
216 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
219 const void *Decoder);
221 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
224 const void *Decoder);
226 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
229 const void *Decoder);
231 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
232 // shifted left by 1 bit.
233 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
236 const void *Decoder);
238 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is
239 // shifted left by 1 bit.
240 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
243 const void *Decoder);
245 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
246 // shifted left by 1 bit.
247 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
250 const void *Decoder);
252 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
253 // shifted left by 1 bit.
254 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
257 const void *Decoder);
259 static DecodeStatus DecodeMem(MCInst &Inst,
262 const void *Decoder);
264 static DecodeStatus DecodeCacheOp(MCInst &Inst,
267 const void *Decoder);
269 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
272 const void *Decoder);
274 static DecodeStatus DecodeSyncI(MCInst &Inst,
277 const void *Decoder);
279 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
280 uint64_t Address, const void *Decoder);
282 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
285 const void *Decoder);
287 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
290 const void *Decoder);
292 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
295 const void *Decoder);
297 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
300 const void *Decoder);
302 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
304 const void *Decoder);
306 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
308 const void *Decoder);
310 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn,
312 const void *Decoder);
314 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
316 const void *Decoder);
318 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
321 const void *Decoder);
323 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
326 const void *Decoder);
328 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
331 const void *Decoder);
333 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
336 const void *Decoder);
338 static DecodeStatus DecodeSimm4(MCInst &Inst,
341 const void *Decoder);
343 static DecodeStatus DecodeSimm16(MCInst &Inst,
346 const void *Decoder);
348 // Decode the immediate field of an LSA instruction which
350 static DecodeStatus DecodeLSAImm(MCInst &Inst,
353 const void *Decoder);
355 static DecodeStatus DecodeInsSize(MCInst &Inst,
358 const void *Decoder);
360 static DecodeStatus DecodeExtSize(MCInst &Inst,
363 const void *Decoder);
365 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
366 uint64_t Address, const void *Decoder);
368 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
369 uint64_t Address, const void *Decoder);
371 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
372 uint64_t Address, const void *Decoder);
374 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
375 uint64_t Address, const void *Decoder);
377 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
378 uint64_t Address, const void *Decoder);
380 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
381 uint64_t Address, const void *Decoder);
383 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
385 template <typename InsnType>
386 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
387 const void *Decoder);
389 template <typename InsnType>
391 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
392 const void *Decoder);
394 template <typename InsnType>
396 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
397 const void *Decoder);
399 template <typename InsnType>
401 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
402 const void *Decoder);
404 template <typename InsnType>
406 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
407 const void *Decoder);
409 template <typename InsnType>
411 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
412 const void *Decoder);
414 template <typename InsnType>
416 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
417 const void *Decoder);
419 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
421 const void *Decoder);
423 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
425 const void *Decoder);
428 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
432 static MCDisassembler *createMipsDisassembler(
434 const MCSubtargetInfo &STI,
436 return new MipsDisassembler(STI, Ctx, true);
439 static MCDisassembler *createMipselDisassembler(
441 const MCSubtargetInfo &STI,
443 return new MipsDisassembler(STI, Ctx, false);
446 static MCDisassembler *createMips64Disassembler(
448 const MCSubtargetInfo &STI,
450 return new Mips64Disassembler(STI, Ctx, true);
453 static MCDisassembler *createMips64elDisassembler(
455 const MCSubtargetInfo &STI,
457 return new Mips64Disassembler(STI, Ctx, false);
460 extern "C" void LLVMInitializeMipsDisassembler() {
461 // Register the disassembler.
462 TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
463 createMipsDisassembler);
464 TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
465 createMipselDisassembler);
466 TargetRegistry::RegisterMCDisassembler(TheMips64Target,
467 createMips64Disassembler);
468 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
469 createMips64elDisassembler);
472 #include "MipsGenDisassemblerTables.inc"
474 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
475 const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
476 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
477 return *(RegInfo->getRegClass(RC).begin() + RegNo);
480 template <typename InsnType>
481 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
482 const void *Decoder) {
483 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
484 // The size of the n field depends on the element size
485 // The register class also depends on this.
486 InsnType tmp = fieldFromInstruction(insn, 17, 5);
488 DecodeFN RegDecoder = nullptr;
489 if ((tmp & 0x18) == 0x00) { // INSVE_B
491 RegDecoder = DecodeMSA128BRegisterClass;
492 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
494 RegDecoder = DecodeMSA128HRegisterClass;
495 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
497 RegDecoder = DecodeMSA128WRegisterClass;
498 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
500 RegDecoder = DecodeMSA128DRegisterClass;
502 llvm_unreachable("Invalid encoding");
504 assert(NSize != 0 && RegDecoder != nullptr);
507 tmp = fieldFromInstruction(insn, 6, 5);
508 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
509 return MCDisassembler::Fail;
511 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
512 return MCDisassembler::Fail;
514 tmp = fieldFromInstruction(insn, 16, NSize);
515 MI.addOperand(MCOperand::CreateImm(tmp));
517 tmp = fieldFromInstruction(insn, 11, 5);
518 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
519 return MCDisassembler::Fail;
521 MI.addOperand(MCOperand::CreateImm(0));
523 return MCDisassembler::Success;
526 template <typename InsnType>
527 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
529 const void *Decoder) {
530 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
531 // (otherwise we would have matched the ADDI instruction from the earlier
535 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii
537 // BEQZALC if rs == 0 && rt != 0
538 // BEQC if rs < rt && rs != 0
540 InsnType Rs = fieldFromInstruction(insn, 21, 5);
541 InsnType Rt = fieldFromInstruction(insn, 16, 5);
542 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
546 MI.setOpcode(Mips::BOVC);
548 } else if (Rs != 0 && Rs < Rt) {
549 MI.setOpcode(Mips::BEQC);
552 MI.setOpcode(Mips::BEQZALC);
555 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
558 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
560 MI.addOperand(MCOperand::CreateImm(Imm));
562 return MCDisassembler::Success;
565 template <typename InsnType>
566 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
568 const void *Decoder) {
569 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
570 // (otherwise we would have matched the ADDI instruction from the earlier
574 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii
576 // BNEZALC if rs == 0 && rt != 0
577 // BNEC if rs < rt && rs != 0
579 InsnType Rs = fieldFromInstruction(insn, 21, 5);
580 InsnType Rt = fieldFromInstruction(insn, 16, 5);
581 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
585 MI.setOpcode(Mips::BNVC);
587 } else if (Rs != 0 && Rs < Rt) {
588 MI.setOpcode(Mips::BNEC);
591 MI.setOpcode(Mips::BNEZALC);
594 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
597 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
599 MI.addOperand(MCOperand::CreateImm(Imm));
601 return MCDisassembler::Success;
604 template <typename InsnType>
605 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
607 const void *Decoder) {
608 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
609 // (otherwise we would have matched the BLEZL instruction from the earlier
613 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii
614 // Invalid if rs == 0
615 // BLEZC if rs == 0 && rt != 0
616 // BGEZC if rs == rt && rt != 0
617 // BGEC if rs != rt && rs != 0 && rt != 0
619 InsnType Rs = fieldFromInstruction(insn, 21, 5);
620 InsnType Rt = fieldFromInstruction(insn, 16, 5);
621 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
625 return MCDisassembler::Fail;
627 MI.setOpcode(Mips::BLEZC);
629 MI.setOpcode(Mips::BGEZC);
632 MI.setOpcode(Mips::BGEC);
636 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
639 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
642 MI.addOperand(MCOperand::CreateImm(Imm));
644 return MCDisassembler::Success;
647 template <typename InsnType>
648 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
650 const void *Decoder) {
651 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
652 // (otherwise we would have matched the BGTZL instruction from the earlier
656 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii
657 // Invalid if rs == 0
658 // BGTZC if rs == 0 && rt != 0
659 // BLTZC if rs == rt && rt != 0
660 // BLTC if rs != rt && rs != 0 && rt != 0
664 InsnType Rs = fieldFromInstruction(insn, 21, 5);
665 InsnType Rt = fieldFromInstruction(insn, 16, 5);
666 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
669 return MCDisassembler::Fail;
671 MI.setOpcode(Mips::BGTZC);
673 MI.setOpcode(Mips::BLTZC);
675 MI.setOpcode(Mips::BLTC);
680 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
683 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
686 MI.addOperand(MCOperand::CreateImm(Imm));
688 return MCDisassembler::Success;
691 template <typename InsnType>
692 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
694 const void *Decoder) {
695 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
696 // (otherwise we would have matched the BGTZ instruction from the earlier
700 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii
702 // BGTZALC if rs == 0 && rt != 0
703 // BLTZALC if rs != 0 && rs == rt
704 // BLTUC if rs != 0 && rs != rt
706 InsnType Rs = fieldFromInstruction(insn, 21, 5);
707 InsnType Rt = fieldFromInstruction(insn, 16, 5);
708 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
713 MI.setOpcode(Mips::BGTZ);
715 } else if (Rs == 0) {
716 MI.setOpcode(Mips::BGTZALC);
718 } else if (Rs == Rt) {
719 MI.setOpcode(Mips::BLTZALC);
722 MI.setOpcode(Mips::BLTUC);
728 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
732 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
735 MI.addOperand(MCOperand::CreateImm(Imm));
737 return MCDisassembler::Success;
740 template <typename InsnType>
741 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
743 const void *Decoder) {
744 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
745 // (otherwise we would have matched the BLEZL instruction from the earlier
749 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii
750 // Invalid if rs == 0
751 // BLEZALC if rs == 0 && rt != 0
752 // BGEZALC if rs == rt && rt != 0
753 // BGEUC if rs != rt && rs != 0 && rt != 0
755 InsnType Rs = fieldFromInstruction(insn, 21, 5);
756 InsnType Rt = fieldFromInstruction(insn, 16, 5);
757 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
761 return MCDisassembler::Fail;
763 MI.setOpcode(Mips::BLEZALC);
765 MI.setOpcode(Mips::BGEZALC);
768 MI.setOpcode(Mips::BGEUC);
772 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
774 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
777 MI.addOperand(MCOperand::CreateImm(Imm));
779 return MCDisassembler::Success;
782 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted
783 /// according to the given endianess.
784 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
785 uint64_t &Size, uint32_t &Insn,
787 // We want to read exactly 2 Bytes of data.
788 if (Bytes.size() < 2) {
790 return MCDisassembler::Fail;
794 Insn = (Bytes[0] << 8) | Bytes[1];
796 Insn = (Bytes[1] << 8) | Bytes[0];
799 return MCDisassembler::Success;
802 /// Read four bytes from the ArrayRef and return 32 bit word sorted
803 /// according to the given endianess
804 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
805 uint64_t &Size, uint32_t &Insn,
806 bool IsBigEndian, bool IsMicroMips) {
807 // We want to read exactly 4 Bytes of data.
808 if (Bytes.size() < 4) {
810 return MCDisassembler::Fail;
813 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
814 // always precede the low 16 bits in the instruction stream (that is, they
815 // are placed at lower addresses in the instruction stream).
817 // microMIPS byte ordering:
818 // Big-endian: 0 | 1 | 2 | 3
819 // Little-endian: 1 | 0 | 3 | 2
822 // Encoded as a big-endian 32-bit word in the stream.
824 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
827 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
830 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
835 return MCDisassembler::Success;
838 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
839 ArrayRef<uint8_t> Bytes,
841 raw_ostream &VStream,
842 raw_ostream &CStream) const {
847 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
849 DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
850 // Calling the auto-generated decoder function.
851 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
853 if (Result != MCDisassembler::Fail) {
858 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
859 if (Result == MCDisassembler::Fail)
860 return MCDisassembler::Fail;
862 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
863 // Calling the auto-generated decoder function.
864 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
866 if (Result != MCDisassembler::Fail) {
870 return MCDisassembler::Fail;
873 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
874 if (Result == MCDisassembler::Fail)
875 return MCDisassembler::Fail;
878 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
880 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
881 if (Result != MCDisassembler::Fail) {
887 if (hasMips32r6() && isGP64()) {
888 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
889 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
891 if (Result != MCDisassembler::Fail) {
898 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
899 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
901 if (Result != MCDisassembler::Fail) {
907 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
908 // Calling the auto-generated decoder function.
910 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
911 if (Result != MCDisassembler::Fail) {
916 return MCDisassembler::Fail;
919 DecodeStatus Mips64Disassembler::getInstruction(MCInst &Instr, uint64_t &Size,
920 ArrayRef<uint8_t> Bytes,
922 raw_ostream &VStream,
923 raw_ostream &CStream) const {
926 DecodeStatus Result =
927 readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
928 if (Result == MCDisassembler::Fail)
929 return MCDisassembler::Fail;
931 // Calling the auto-generated decoder function.
933 decodeInstruction(DecoderTableMips6432, Instr, Insn, Address, this, STI);
934 if (Result != MCDisassembler::Fail) {
938 // If we fail to decode in Mips64 decoder space we can try in Mips32
940 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
941 if (Result != MCDisassembler::Fail) {
946 return MCDisassembler::Fail;
949 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
952 const void *Decoder) {
954 return MCDisassembler::Fail;
958 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
961 const void *Decoder) {
964 return MCDisassembler::Fail;
966 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
967 Inst.addOperand(MCOperand::CreateReg(Reg));
968 return MCDisassembler::Success;
971 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
974 const void *Decoder) {
976 return MCDisassembler::Fail;
977 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
978 Inst.addOperand(MCOperand::CreateReg(Reg));
979 return MCDisassembler::Success;
982 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
985 const void *Decoder) {
987 return MCDisassembler::Fail;
988 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
989 Inst.addOperand(MCOperand::CreateReg(Reg));
990 return MCDisassembler::Success;
993 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
996 const void *Decoder) {
998 return MCDisassembler::Fail;
999 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
1000 Inst.addOperand(MCOperand::CreateReg(Reg));
1001 return MCDisassembler::Success;
1004 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
1007 const void *Decoder) {
1008 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64Bit())
1009 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
1011 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1014 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
1017 const void *Decoder) {
1018 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1021 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
1024 const void *Decoder) {
1026 return MCDisassembler::Fail;
1028 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
1029 Inst.addOperand(MCOperand::CreateReg(Reg));
1030 return MCDisassembler::Success;
1033 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
1036 const void *Decoder) {
1038 return MCDisassembler::Fail;
1040 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
1041 Inst.addOperand(MCOperand::CreateReg(Reg));
1042 return MCDisassembler::Success;
1045 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
1048 const void *Decoder) {
1050 return MCDisassembler::Fail;
1051 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
1052 Inst.addOperand(MCOperand::CreateReg(Reg));
1053 return MCDisassembler::Success;
1056 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
1059 const void *Decoder) {
1061 return MCDisassembler::Fail;
1062 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
1063 Inst.addOperand(MCOperand::CreateReg(Reg));
1064 return MCDisassembler::Success;
1067 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
1069 const void *Decoder) {
1071 return MCDisassembler::Fail;
1073 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
1074 Inst.addOperand(MCOperand::CreateReg(Reg));
1075 return MCDisassembler::Success;
1078 static DecodeStatus DecodeMem(MCInst &Inst,
1081 const void *Decoder) {
1082 int Offset = SignExtend32<16>(Insn & 0xffff);
1083 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1084 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1086 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1087 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1089 if(Inst.getOpcode() == Mips::SC ||
1090 Inst.getOpcode() == Mips::SCD){
1091 Inst.addOperand(MCOperand::CreateReg(Reg));
1094 Inst.addOperand(MCOperand::CreateReg(Reg));
1095 Inst.addOperand(MCOperand::CreateReg(Base));
1096 Inst.addOperand(MCOperand::CreateImm(Offset));
1098 return MCDisassembler::Success;
1101 static DecodeStatus DecodeCacheOp(MCInst &Inst,
1104 const void *Decoder) {
1105 int Offset = SignExtend32<16>(Insn & 0xffff);
1106 unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1107 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1109 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1111 Inst.addOperand(MCOperand::CreateReg(Base));
1112 Inst.addOperand(MCOperand::CreateImm(Offset));
1113 Inst.addOperand(MCOperand::CreateImm(Hint));
1115 return MCDisassembler::Success;
1118 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
1121 const void *Decoder) {
1122 int Offset = SignExtend32<12>(Insn & 0xfff);
1123 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1124 unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1126 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1128 Inst.addOperand(MCOperand::CreateReg(Base));
1129 Inst.addOperand(MCOperand::CreateImm(Offset));
1130 Inst.addOperand(MCOperand::CreateImm(Hint));
1132 return MCDisassembler::Success;
1135 static DecodeStatus DecodeSyncI(MCInst &Inst,
1138 const void *Decoder) {
1139 int Offset = SignExtend32<16>(Insn & 0xffff);
1140 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1142 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1144 Inst.addOperand(MCOperand::CreateReg(Base));
1145 Inst.addOperand(MCOperand::CreateImm(Offset));
1147 return MCDisassembler::Success;
1150 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1151 uint64_t Address, const void *Decoder) {
1152 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1153 unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1154 unsigned Base = fieldFromInstruction(Insn, 11, 5);
1156 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1157 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1159 Inst.addOperand(MCOperand::CreateReg(Reg));
1160 Inst.addOperand(MCOperand::CreateReg(Base));
1162 // The immediate field of an LD/ST instruction is scaled which means it must
1163 // be multiplied (when decoding) by the size (in bytes) of the instructions'
1169 switch(Inst.getOpcode())
1172 assert (0 && "Unexpected instruction");
1173 return MCDisassembler::Fail;
1177 Inst.addOperand(MCOperand::CreateImm(Offset));
1181 Inst.addOperand(MCOperand::CreateImm(Offset * 2));
1185 Inst.addOperand(MCOperand::CreateImm(Offset * 4));
1189 Inst.addOperand(MCOperand::CreateImm(Offset * 8));
1193 return MCDisassembler::Success;
1196 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
1199 const void *Decoder) {
1200 unsigned Offset = Insn & 0xf;
1201 unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1202 unsigned Base = fieldFromInstruction(Insn, 4, 3);
1204 switch (Inst.getOpcode()) {
1205 case Mips::LBU16_MM:
1206 case Mips::LHU16_MM:
1208 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1209 == MCDisassembler::Fail)
1210 return MCDisassembler::Fail;
1215 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1216 == MCDisassembler::Fail)
1217 return MCDisassembler::Fail;
1221 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1222 == MCDisassembler::Fail)
1223 return MCDisassembler::Fail;
1225 switch (Inst.getOpcode()) {
1226 case Mips::LBU16_MM:
1228 Inst.addOperand(MCOperand::CreateImm(-1));
1230 Inst.addOperand(MCOperand::CreateImm(Offset));
1233 Inst.addOperand(MCOperand::CreateImm(Offset));
1235 case Mips::LHU16_MM:
1237 Inst.addOperand(MCOperand::CreateImm(Offset << 1));
1241 Inst.addOperand(MCOperand::CreateImm(Offset << 2));
1245 return MCDisassembler::Success;
1248 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
1251 const void *Decoder) {
1252 unsigned Offset = Insn & 0x1F;
1253 unsigned Reg = fieldFromInstruction(Insn, 5, 5);
1255 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1257 Inst.addOperand(MCOperand::CreateReg(Reg));
1258 Inst.addOperand(MCOperand::CreateReg(Mips::SP));
1259 Inst.addOperand(MCOperand::CreateImm(Offset << 2));
1261 return MCDisassembler::Success;
1264 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1267 const void *Decoder) {
1268 int Offset = SignExtend32<12>(Insn & 0x0fff);
1269 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1270 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1272 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1273 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1275 switch (Inst.getOpcode()) {
1276 case Mips::SWM32_MM:
1277 case Mips::LWM32_MM:
1278 if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1279 == MCDisassembler::Fail)
1280 return MCDisassembler::Fail;
1281 Inst.addOperand(MCOperand::CreateReg(Base));
1282 Inst.addOperand(MCOperand::CreateImm(Offset));
1285 Inst.addOperand(MCOperand::CreateReg(Reg));
1288 Inst.addOperand(MCOperand::CreateReg(Reg));
1289 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
1290 Inst.addOperand(MCOperand::CreateReg(Reg+1));
1292 Inst.addOperand(MCOperand::CreateReg(Base));
1293 Inst.addOperand(MCOperand::CreateImm(Offset));
1296 return MCDisassembler::Success;
1299 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1302 const void *Decoder) {
1303 int Offset = SignExtend32<16>(Insn & 0xffff);
1304 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1305 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1307 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1308 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1310 Inst.addOperand(MCOperand::CreateReg(Reg));
1311 Inst.addOperand(MCOperand::CreateReg(Base));
1312 Inst.addOperand(MCOperand::CreateImm(Offset));
1314 return MCDisassembler::Success;
1317 static DecodeStatus DecodeFMem(MCInst &Inst,
1320 const void *Decoder) {
1321 int Offset = SignExtend32<16>(Insn & 0xffff);
1322 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1323 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1325 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1326 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1328 Inst.addOperand(MCOperand::CreateReg(Reg));
1329 Inst.addOperand(MCOperand::CreateReg(Base));
1330 Inst.addOperand(MCOperand::CreateImm(Offset));
1332 return MCDisassembler::Success;
1335 static DecodeStatus DecodeFMem2(MCInst &Inst,
1338 const void *Decoder) {
1339 int Offset = SignExtend32<16>(Insn & 0xffff);
1340 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1341 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1343 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1344 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1346 Inst.addOperand(MCOperand::CreateReg(Reg));
1347 Inst.addOperand(MCOperand::CreateReg(Base));
1348 Inst.addOperand(MCOperand::CreateImm(Offset));
1350 return MCDisassembler::Success;
1353 static DecodeStatus DecodeFMem3(MCInst &Inst,
1356 const void *Decoder) {
1357 int Offset = SignExtend32<16>(Insn & 0xffff);
1358 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1359 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1361 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1362 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1364 Inst.addOperand(MCOperand::CreateReg(Reg));
1365 Inst.addOperand(MCOperand::CreateReg(Base));
1366 Inst.addOperand(MCOperand::CreateImm(Offset));
1368 return MCDisassembler::Success;
1371 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst,
1374 const void *Decoder) {
1375 int Offset = SignExtend32<11>(Insn & 0x07ff);
1376 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1377 unsigned Base = fieldFromInstruction(Insn, 11, 5);
1379 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1380 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1382 Inst.addOperand(MCOperand::CreateReg(Reg));
1383 Inst.addOperand(MCOperand::CreateReg(Base));
1384 Inst.addOperand(MCOperand::CreateImm(Offset));
1386 return MCDisassembler::Success;
1388 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
1391 const void *Decoder) {
1392 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1393 unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1394 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1396 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1397 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1399 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1400 Inst.addOperand(MCOperand::CreateReg(Rt));
1403 Inst.addOperand(MCOperand::CreateReg(Rt));
1404 Inst.addOperand(MCOperand::CreateReg(Base));
1405 Inst.addOperand(MCOperand::CreateImm(Offset));
1407 return MCDisassembler::Success;
1410 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1413 const void *Decoder) {
1414 // Currently only hardware register 29 is supported.
1416 return MCDisassembler::Fail;
1417 Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
1418 return MCDisassembler::Success;
1421 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1424 const void *Decoder) {
1425 if (RegNo > 30 || RegNo %2)
1426 return MCDisassembler::Fail;
1429 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1430 Inst.addOperand(MCOperand::CreateReg(Reg));
1431 return MCDisassembler::Success;
1434 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1437 const void *Decoder) {
1439 return MCDisassembler::Fail;
1441 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1442 Inst.addOperand(MCOperand::CreateReg(Reg));
1443 return MCDisassembler::Success;
1446 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1449 const void *Decoder) {
1451 return MCDisassembler::Fail;
1453 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1454 Inst.addOperand(MCOperand::CreateReg(Reg));
1455 return MCDisassembler::Success;
1458 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1461 const void *Decoder) {
1463 return MCDisassembler::Fail;
1465 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1466 Inst.addOperand(MCOperand::CreateReg(Reg));
1467 return MCDisassembler::Success;
1470 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1473 const void *Decoder) {
1475 return MCDisassembler::Fail;
1477 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1478 Inst.addOperand(MCOperand::CreateReg(Reg));
1479 return MCDisassembler::Success;
1482 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1485 const void *Decoder) {
1487 return MCDisassembler::Fail;
1489 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1490 Inst.addOperand(MCOperand::CreateReg(Reg));
1491 return MCDisassembler::Success;
1494 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1497 const void *Decoder) {
1499 return MCDisassembler::Fail;
1501 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1502 Inst.addOperand(MCOperand::CreateReg(Reg));
1503 return MCDisassembler::Success;
1506 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1509 const void *Decoder) {
1511 return MCDisassembler::Fail;
1513 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1514 Inst.addOperand(MCOperand::CreateReg(Reg));
1515 return MCDisassembler::Success;
1518 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1521 const void *Decoder) {
1523 return MCDisassembler::Fail;
1525 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1526 Inst.addOperand(MCOperand::CreateReg(Reg));
1527 return MCDisassembler::Success;
1530 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1533 const void *Decoder) {
1535 return MCDisassembler::Fail;
1537 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1538 Inst.addOperand(MCOperand::CreateReg(Reg));
1539 return MCDisassembler::Success;
1542 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1545 const void *Decoder) {
1546 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
1547 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1548 return MCDisassembler::Success;
1551 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1554 const void *Decoder) {
1556 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1557 Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1558 return MCDisassembler::Success;
1561 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1564 const void *Decoder) {
1565 int32_t BranchOffset = SignExtend32<21>(Offset) * 4;
1567 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1568 return MCDisassembler::Success;
1571 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1574 const void *Decoder) {
1575 int32_t BranchOffset = SignExtend32<26>(Offset) * 4;
1577 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1578 return MCDisassembler::Success;
1581 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
1584 const void *Decoder) {
1585 int32_t BranchOffset = SignExtend32<7>(Offset) << 1;
1586 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1587 return MCDisassembler::Success;
1590 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
1593 const void *Decoder) {
1594 int32_t BranchOffset = SignExtend32<10>(Offset) << 1;
1595 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1596 return MCDisassembler::Success;
1599 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1602 const void *Decoder) {
1603 int32_t BranchOffset = SignExtend32<16>(Offset) * 2;
1604 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1605 return MCDisassembler::Success;
1608 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1611 const void *Decoder) {
1612 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1613 Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1614 return MCDisassembler::Success;
1617 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
1620 const void *Decoder) {
1622 Inst.addOperand(MCOperand::CreateImm(1));
1623 else if (Value == 0x7)
1624 Inst.addOperand(MCOperand::CreateImm(-1));
1626 Inst.addOperand(MCOperand::CreateImm(Value << 2));
1627 return MCDisassembler::Success;
1630 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
1633 const void *Decoder) {
1634 Inst.addOperand(MCOperand::CreateImm(Value << 2));
1635 return MCDisassembler::Success;
1638 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
1641 const void *Decoder) {
1643 Inst.addOperand(MCOperand::CreateImm(-1));
1645 Inst.addOperand(MCOperand::CreateImm(Value));
1646 return MCDisassembler::Success;
1649 static DecodeStatus DecodeSimm4(MCInst &Inst,
1652 const void *Decoder) {
1653 Inst.addOperand(MCOperand::CreateImm(SignExtend32<4>(Value)));
1654 return MCDisassembler::Success;
1657 static DecodeStatus DecodeSimm16(MCInst &Inst,
1660 const void *Decoder) {
1661 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
1662 return MCDisassembler::Success;
1665 static DecodeStatus DecodeLSAImm(MCInst &Inst,
1668 const void *Decoder) {
1669 // We add one to the immediate field as it was encoded as 'imm - 1'.
1670 Inst.addOperand(MCOperand::CreateImm(Insn + 1));
1671 return MCDisassembler::Success;
1674 static DecodeStatus DecodeInsSize(MCInst &Inst,
1677 const void *Decoder) {
1678 // First we need to grab the pos(lsb) from MCInst.
1679 int Pos = Inst.getOperand(2).getImm();
1680 int Size = (int) Insn - Pos + 1;
1681 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1682 return MCDisassembler::Success;
1685 static DecodeStatus DecodeExtSize(MCInst &Inst,
1688 const void *Decoder) {
1689 int Size = (int) Insn + 1;
1690 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1691 return MCDisassembler::Success;
1694 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1695 uint64_t Address, const void *Decoder) {
1696 Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) * 4));
1697 return MCDisassembler::Success;
1700 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1701 uint64_t Address, const void *Decoder) {
1702 Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) * 8));
1703 return MCDisassembler::Success;
1706 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
1707 uint64_t Address, const void *Decoder) {
1708 int32_t DecodedValue;
1710 case 0: DecodedValue = 256; break;
1711 case 1: DecodedValue = 257; break;
1712 case 510: DecodedValue = -258; break;
1713 case 511: DecodedValue = -257; break;
1714 default: DecodedValue = SignExtend32<9>(Insn); break;
1716 Inst.addOperand(MCOperand::CreateImm(DecodedValue * 4));
1717 return MCDisassembler::Success;
1720 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
1721 uint64_t Address, const void *Decoder) {
1722 // Insn must be >= 0, since it is unsigned that condition is always true.
1724 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
1726 Inst.addOperand(MCOperand::CreateImm(DecodedValues[Insn]));
1727 return MCDisassembler::Success;
1730 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
1731 uint64_t Address, const void *Decoder) {
1732 Inst.addOperand(MCOperand::CreateImm(Insn << 2));
1733 return MCDisassembler::Success;
1736 static DecodeStatus DecodeRegListOperand(MCInst &Inst,
1739 const void *Decoder) {
1740 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
1741 Mips::S6, Mips::FP};
1744 unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
1745 // Empty register lists are not allowed.
1747 return MCDisassembler::Fail;
1749 RegNum = RegLst & 0xf;
1750 for (unsigned i = 0; i < RegNum; i++)
1751 Inst.addOperand(MCOperand::CreateReg(Regs[i]));
1754 Inst.addOperand(MCOperand::CreateReg(Mips::RA));
1756 return MCDisassembler::Success;
1759 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
1761 const void *Decoder) {
1762 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
1765 unsigned RegLst = fieldFromInstruction(Insn, 4, 2);
1766 // Empty register lists are not allowed.
1768 return MCDisassembler::Fail;
1770 RegNum = RegLst & 0x3;
1771 for (unsigned i = 0; i < RegNum - 1; i++)
1772 Inst.addOperand(MCOperand::CreateReg(Regs[i]));
1774 Inst.addOperand(MCOperand::CreateReg(Mips::RA));
1776 return MCDisassembler::Success;
1779 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
1780 uint64_t Address, const void *Decoder) {
1781 Inst.addOperand(MCOperand::CreateImm(SignExtend32<23>(Insn) << 2));
1782 return MCDisassembler::Success;