1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/MipsMCExpr.h"
11 #include "MCTargetDesc/MipsMCTargetDesc.h"
12 #include "MipsRegisterInfo.h"
13 #include "MipsTargetStreamer.h"
14 #include "llvm/ADT/APInt.h"
15 #include "llvm/ADT/StringSwitch.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstBuilder.h"
20 #include "llvm/MC/MCParser/MCAsmLexer.h"
21 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
22 #include "llvm/MC/MCStreamer.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCSymbol.h"
25 #include "llvm/MC/MCTargetAsmParser.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Support/TargetRegistry.h"
32 #define DEBUG_TYPE "mips-asm-parser"
39 class MipsAssemblerOptions {
41 MipsAssemblerOptions() : aTReg(1), reorder(true), macro(true) {}
43 unsigned getATRegNum() { return aTReg; }
44 bool setATReg(unsigned Reg);
46 bool isReorder() { return reorder; }
47 void setReorder() { reorder = true; }
48 void setNoreorder() { reorder = false; }
50 bool isMacro() { return macro; }
51 void setMacro() { macro = true; }
52 void setNomacro() { macro = false; }
62 class MipsAsmParser : public MCTargetAsmParser {
63 MipsTargetStreamer &getTargetStreamer() {
64 MCTargetStreamer &TS = *Parser.getStreamer().getTargetStreamer();
65 return static_cast<MipsTargetStreamer &>(TS);
70 MipsAssemblerOptions Options;
72 #define GET_ASSEMBLER_HEADER
73 #include "MipsGenAsmMatcher.inc"
75 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
77 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
78 OperandVector &Operands, MCStreamer &Out,
80 bool MatchingInlineAsm) override;
82 /// Parse a register as used in CFI directives
83 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
85 bool ParseParenSuffix(StringRef Name, OperandVector &Operands);
87 bool ParseBracketSuffix(StringRef Name, OperandVector &Operands);
89 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
90 SMLoc NameLoc, OperandVector &Operands) override;
92 bool ParseDirective(AsmToken DirectiveID) override;
94 MipsAsmParser::OperandMatchResultTy parseMemOperand(OperandVector &Operands);
96 MipsAsmParser::OperandMatchResultTy
97 MatchAnyRegisterNameWithoutDollar(OperandVector &Operands,
98 StringRef Identifier, SMLoc S);
100 MipsAsmParser::OperandMatchResultTy
101 MatchAnyRegisterWithoutDollar(OperandVector &Operands, SMLoc S);
103 MipsAsmParser::OperandMatchResultTy ParseAnyRegister(OperandVector &Operands);
105 MipsAsmParser::OperandMatchResultTy ParseImm(OperandVector &Operands);
107 MipsAsmParser::OperandMatchResultTy ParseJumpTarget(OperandVector &Operands);
109 MipsAsmParser::OperandMatchResultTy parseInvNum(OperandVector &Operands);
111 MipsAsmParser::OperandMatchResultTy ParseLSAImm(OperandVector &Operands);
113 bool searchSymbolAlias(OperandVector &Operands);
115 bool ParseOperand(OperandVector &, StringRef Mnemonic);
117 bool needsExpansion(MCInst &Inst);
119 // Expands assembly pseudo instructions.
120 // Returns false on success, true otherwise.
121 bool expandInstruction(MCInst &Inst, SMLoc IDLoc,
122 SmallVectorImpl<MCInst> &Instructions);
124 bool expandLoadImm(MCInst &Inst, SMLoc IDLoc,
125 SmallVectorImpl<MCInst> &Instructions);
127 bool expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
128 SmallVectorImpl<MCInst> &Instructions);
130 bool expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
131 SmallVectorImpl<MCInst> &Instructions);
133 void expandMemInst(MCInst &Inst, SMLoc IDLoc,
134 SmallVectorImpl<MCInst> &Instructions, bool isLoad,
136 bool reportParseError(StringRef ErrorMsg);
137 bool reportParseError(SMLoc Loc, StringRef ErrorMsg);
139 bool parseMemOffset(const MCExpr *&Res, bool isParenExpr);
140 bool parseRelocOperand(const MCExpr *&Res);
142 const MCExpr *evaluateRelocExpr(const MCExpr *Expr, StringRef RelocStr);
144 bool isEvaluated(const MCExpr *Expr);
145 bool parseSetFeature(uint64_t Feature);
146 bool parseDirectiveCPLoad(SMLoc Loc);
147 bool parseDirectiveCPSetup();
148 bool parseDirectiveNaN();
149 bool parseDirectiveSet();
150 bool parseDirectiveOption();
152 bool parseSetAtDirective();
153 bool parseSetNoAtDirective();
154 bool parseSetMacroDirective();
155 bool parseSetNoMacroDirective();
156 bool parseSetReorderDirective();
157 bool parseSetNoReorderDirective();
158 bool parseSetNoMips16Directive();
160 bool parseSetAssignment();
162 bool parseDataDirective(unsigned Size, SMLoc L);
163 bool parseDirectiveGpWord();
164 bool parseDirectiveGpDWord();
166 MCSymbolRefExpr::VariantKind getVariantKind(StringRef Symbol);
168 bool isGP64() const {
169 return (STI.getFeatureBits() & Mips::FeatureGP64Bit) != 0;
172 bool isFP64() const {
173 return (STI.getFeatureBits() & Mips::FeatureFP64Bit) != 0;
176 bool isN32() const { return STI.getFeatureBits() & Mips::FeatureN32; }
177 bool isN64() const { return STI.getFeatureBits() & Mips::FeatureN64; }
179 bool isMicroMips() const {
180 return STI.getFeatureBits() & Mips::FeatureMicroMips;
183 bool hasMips4() const { return STI.getFeatureBits() & Mips::FeatureMips4; }
184 bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; }
185 bool hasMips32r6() const {
186 return STI.getFeatureBits() & Mips::FeatureMips32r6;
188 bool hasMips64r6() const {
189 return STI.getFeatureBits() & Mips::FeatureMips64r6;
192 bool eatComma(StringRef ErrorStr);
194 int matchCPURegisterName(StringRef Symbol);
196 int matchRegisterByNumber(unsigned RegNum, unsigned RegClass);
198 int matchFPURegisterName(StringRef Name);
200 int matchFCCRegisterName(StringRef Name);
202 int matchACRegisterName(StringRef Name);
204 int matchMSA128RegisterName(StringRef Name);
206 int matchMSA128CtrlRegisterName(StringRef Name);
208 unsigned getReg(int RC, int RegNo);
210 unsigned getGPR(int RegNo);
212 int getATReg(SMLoc Loc);
214 bool processInstruction(MCInst &Inst, SMLoc IDLoc,
215 SmallVectorImpl<MCInst> &Instructions);
217 // Helper function that checks if the value of a vector index is within the
218 // boundaries of accepted values for each RegisterKind
219 // Example: INSERT.B $w0[n], $1 => 16 > n >= 0
220 bool validateMSAIndex(int Val, int RegKind);
222 void setFeatureBits(unsigned Feature, StringRef FeatureString) {
223 if (!(STI.getFeatureBits() & Feature)) {
224 setAvailableFeatures(
225 ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
229 void clearFeatureBits(unsigned Feature, StringRef FeatureString) {
230 if (STI.getFeatureBits() & Feature) {
231 setAvailableFeatures(
232 ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
237 enum MipsMatchResultTy {
238 Match_RequiresDifferentSrcAndDst = FIRST_TARGET_MATCH_RESULT_TY
239 #define GET_OPERAND_DIAGNOSTIC_TYPES
240 #include "MipsGenAsmMatcher.inc"
241 #undef GET_OPERAND_DIAGNOSTIC_TYPES
245 MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
246 const MCInstrInfo &MII,
247 const MCTargetOptions &Options)
248 : MCTargetAsmParser(), STI(sti), Parser(parser) {
249 // Initialize the set of available features.
250 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
252 // Assert exactly one ABI was chosen.
253 assert((((STI.getFeatureBits() & Mips::FeatureO32) != 0) +
254 ((STI.getFeatureBits() & Mips::FeatureEABI) != 0) +
255 ((STI.getFeatureBits() & Mips::FeatureN32) != 0) +
256 ((STI.getFeatureBits() & Mips::FeatureN64) != 0)) == 1);
259 MCAsmParser &getParser() const { return Parser; }
260 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
262 /// True if all of $fcc0 - $fcc7 exist for the current ISA.
263 bool hasEightFccRegisters() const { return hasMips4() || hasMips32(); }
265 /// Warn if RegNo is the current assembler temporary.
266 void WarnIfAssemblerTemporary(int RegNo, SMLoc Loc);
272 /// MipsOperand - Instances of this class represent a parsed Mips machine
274 class MipsOperand : public MCParsedAsmOperand {
276 /// Broad categories of register classes
277 /// The exact class is finalized by the render method.
279 RegKind_GPR = 1, /// GPR32 and GPR64 (depending on isGP64())
280 RegKind_FGR = 2, /// FGR32, FGR64, AFGR64 (depending on context and
282 RegKind_FCC = 4, /// FCC
283 RegKind_MSA128 = 8, /// MSA128[BHWD] (makes no difference which)
284 RegKind_MSACtrl = 16, /// MSA control registers
285 RegKind_COP2 = 32, /// COP2
286 RegKind_ACC = 64, /// HI32DSP, LO32DSP, and ACC64DSP (depending on
288 RegKind_CCR = 128, /// CCR
289 RegKind_HWRegs = 256, /// HWRegs
290 RegKind_COP3 = 512, /// COP3
292 /// Potentially any (e.g. $1)
293 RegKind_Numeric = RegKind_GPR | RegKind_FGR | RegKind_FCC | RegKind_MSA128 |
294 RegKind_MSACtrl | RegKind_COP2 | RegKind_ACC |
295 RegKind_CCR | RegKind_HWRegs | RegKind_COP3
300 k_Immediate, /// An immediate (possibly involving symbol references)
301 k_Memory, /// Base + Offset Memory Address
302 k_PhysRegister, /// A physical register from the Mips namespace
303 k_RegisterIndex, /// A register index in one or more RegKind.
304 k_Token /// A simple token
308 MipsOperand(KindTy K, MipsAsmParser &Parser)
309 : MCParsedAsmOperand(), Kind(K), AsmParser(Parser) {}
312 /// For diagnostics, and checking the assembler temporary
313 MipsAsmParser &AsmParser;
321 unsigned Num; /// Register Number
325 unsigned Index; /// Index into the register class
326 RegKind Kind; /// Bitfield of the kinds it could possibly be
327 const MCRegisterInfo *RegInfo;
341 struct PhysRegOp PhysReg;
342 struct RegIdxOp RegIdx;
347 SMLoc StartLoc, EndLoc;
349 /// Internal constructor for register kinds
350 static std::unique_ptr<MipsOperand> CreateReg(unsigned Index, RegKind RegKind,
351 const MCRegisterInfo *RegInfo,
353 MipsAsmParser &Parser) {
354 auto Op = make_unique<MipsOperand>(k_RegisterIndex, Parser);
355 Op->RegIdx.Index = Index;
356 Op->RegIdx.RegInfo = RegInfo;
357 Op->RegIdx.Kind = RegKind;
364 /// Coerce the register to GPR32 and return the real register for the current
366 unsigned getGPR32Reg() const {
367 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
368 AsmParser.WarnIfAssemblerTemporary(RegIdx.Index, StartLoc);
369 unsigned ClassID = Mips::GPR32RegClassID;
370 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
373 /// Coerce the register to GPR64 and return the real register for the current
375 unsigned getGPR64Reg() const {
376 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
377 unsigned ClassID = Mips::GPR64RegClassID;
378 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
382 /// Coerce the register to AFGR64 and return the real register for the current
384 unsigned getAFGR64Reg() const {
385 assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
386 if (RegIdx.Index % 2 != 0)
387 AsmParser.Warning(StartLoc, "Float register should be even.");
388 return RegIdx.RegInfo->getRegClass(Mips::AFGR64RegClassID)
389 .getRegister(RegIdx.Index / 2);
392 /// Coerce the register to FGR64 and return the real register for the current
394 unsigned getFGR64Reg() const {
395 assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
396 return RegIdx.RegInfo->getRegClass(Mips::FGR64RegClassID)
397 .getRegister(RegIdx.Index);
400 /// Coerce the register to FGR32 and return the real register for the current
402 unsigned getFGR32Reg() const {
403 assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
404 return RegIdx.RegInfo->getRegClass(Mips::FGR32RegClassID)
405 .getRegister(RegIdx.Index);
408 /// Coerce the register to FGRH32 and return the real register for the current
410 unsigned getFGRH32Reg() const {
411 assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
412 return RegIdx.RegInfo->getRegClass(Mips::FGRH32RegClassID)
413 .getRegister(RegIdx.Index);
416 /// Coerce the register to FCC and return the real register for the current
418 unsigned getFCCReg() const {
419 assert(isRegIdx() && (RegIdx.Kind & RegKind_FCC) && "Invalid access!");
420 return RegIdx.RegInfo->getRegClass(Mips::FCCRegClassID)
421 .getRegister(RegIdx.Index);
424 /// Coerce the register to MSA128 and return the real register for the current
426 unsigned getMSA128Reg() const {
427 assert(isRegIdx() && (RegIdx.Kind & RegKind_MSA128) && "Invalid access!");
428 // It doesn't matter which of the MSA128[BHWD] classes we use. They are all
430 unsigned ClassID = Mips::MSA128BRegClassID;
431 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
434 /// Coerce the register to MSACtrl and return the real register for the
436 unsigned getMSACtrlReg() const {
437 assert(isRegIdx() && (RegIdx.Kind & RegKind_MSACtrl) && "Invalid access!");
438 unsigned ClassID = Mips::MSACtrlRegClassID;
439 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
442 /// Coerce the register to COP2 and return the real register for the
444 unsigned getCOP2Reg() const {
445 assert(isRegIdx() && (RegIdx.Kind & RegKind_COP2) && "Invalid access!");
446 unsigned ClassID = Mips::COP2RegClassID;
447 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
450 /// Coerce the register to COP3 and return the real register for the
452 unsigned getCOP3Reg() const {
453 assert(isRegIdx() && (RegIdx.Kind & RegKind_COP3) && "Invalid access!");
454 unsigned ClassID = Mips::COP3RegClassID;
455 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
458 /// Coerce the register to ACC64DSP and return the real register for the
460 unsigned getACC64DSPReg() const {
461 assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");
462 unsigned ClassID = Mips::ACC64DSPRegClassID;
463 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
466 /// Coerce the register to HI32DSP and return the real register for the
468 unsigned getHI32DSPReg() const {
469 assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");
470 unsigned ClassID = Mips::HI32DSPRegClassID;
471 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
474 /// Coerce the register to LO32DSP and return the real register for the
476 unsigned getLO32DSPReg() const {
477 assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");
478 unsigned ClassID = Mips::LO32DSPRegClassID;
479 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
482 /// Coerce the register to CCR and return the real register for the
484 unsigned getCCRReg() const {
485 assert(isRegIdx() && (RegIdx.Kind & RegKind_CCR) && "Invalid access!");
486 unsigned ClassID = Mips::CCRRegClassID;
487 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
490 /// Coerce the register to HWRegs and return the real register for the
492 unsigned getHWRegsReg() const {
493 assert(isRegIdx() && (RegIdx.Kind & RegKind_HWRegs) && "Invalid access!");
494 unsigned ClassID = Mips::HWRegsRegClassID;
495 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
499 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
500 // Add as immediate when possible. Null MCExpr = 0.
502 Inst.addOperand(MCOperand::CreateImm(0));
503 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
504 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
506 Inst.addOperand(MCOperand::CreateExpr(Expr));
509 void addRegOperands(MCInst &Inst, unsigned N) const {
510 llvm_unreachable("Use a custom parser instead");
513 /// Render the operand to an MCInst as a GPR32
514 /// Asserts if the wrong number of operands are requested, or the operand
515 /// is not a k_RegisterIndex compatible with RegKind_GPR
516 void addGPR32AsmRegOperands(MCInst &Inst, unsigned N) const {
517 assert(N == 1 && "Invalid number of operands!");
518 Inst.addOperand(MCOperand::CreateReg(getGPR32Reg()));
521 /// Render the operand to an MCInst as a GPR64
522 /// Asserts if the wrong number of operands are requested, or the operand
523 /// is not a k_RegisterIndex compatible with RegKind_GPR
524 void addGPR64AsmRegOperands(MCInst &Inst, unsigned N) const {
525 assert(N == 1 && "Invalid number of operands!");
526 Inst.addOperand(MCOperand::CreateReg(getGPR64Reg()));
529 void addAFGR64AsmRegOperands(MCInst &Inst, unsigned N) const {
530 assert(N == 1 && "Invalid number of operands!");
531 Inst.addOperand(MCOperand::CreateReg(getAFGR64Reg()));
534 void addFGR64AsmRegOperands(MCInst &Inst, unsigned N) const {
535 assert(N == 1 && "Invalid number of operands!");
536 Inst.addOperand(MCOperand::CreateReg(getFGR64Reg()));
539 void addFGR32AsmRegOperands(MCInst &Inst, unsigned N) const {
540 assert(N == 1 && "Invalid number of operands!");
541 Inst.addOperand(MCOperand::CreateReg(getFGR32Reg()));
544 void addFGRH32AsmRegOperands(MCInst &Inst, unsigned N) const {
545 assert(N == 1 && "Invalid number of operands!");
546 Inst.addOperand(MCOperand::CreateReg(getFGRH32Reg()));
549 void addFCCAsmRegOperands(MCInst &Inst, unsigned N) const {
550 assert(N == 1 && "Invalid number of operands!");
551 Inst.addOperand(MCOperand::CreateReg(getFCCReg()));
554 void addMSA128AsmRegOperands(MCInst &Inst, unsigned N) const {
555 assert(N == 1 && "Invalid number of operands!");
556 Inst.addOperand(MCOperand::CreateReg(getMSA128Reg()));
559 void addMSACtrlAsmRegOperands(MCInst &Inst, unsigned N) const {
560 assert(N == 1 && "Invalid number of operands!");
561 Inst.addOperand(MCOperand::CreateReg(getMSACtrlReg()));
564 void addCOP2AsmRegOperands(MCInst &Inst, unsigned N) const {
565 assert(N == 1 && "Invalid number of operands!");
566 Inst.addOperand(MCOperand::CreateReg(getCOP2Reg()));
569 void addCOP3AsmRegOperands(MCInst &Inst, unsigned N) const {
570 assert(N == 1 && "Invalid number of operands!");
571 Inst.addOperand(MCOperand::CreateReg(getCOP3Reg()));
574 void addACC64DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
575 assert(N == 1 && "Invalid number of operands!");
576 Inst.addOperand(MCOperand::CreateReg(getACC64DSPReg()));
579 void addHI32DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
580 assert(N == 1 && "Invalid number of operands!");
581 Inst.addOperand(MCOperand::CreateReg(getHI32DSPReg()));
584 void addLO32DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
585 assert(N == 1 && "Invalid number of operands!");
586 Inst.addOperand(MCOperand::CreateReg(getLO32DSPReg()));
589 void addCCRAsmRegOperands(MCInst &Inst, unsigned N) const {
590 assert(N == 1 && "Invalid number of operands!");
591 Inst.addOperand(MCOperand::CreateReg(getCCRReg()));
594 void addHWRegsAsmRegOperands(MCInst &Inst, unsigned N) const {
595 assert(N == 1 && "Invalid number of operands!");
596 Inst.addOperand(MCOperand::CreateReg(getHWRegsReg()));
599 void addImmOperands(MCInst &Inst, unsigned N) const {
600 assert(N == 1 && "Invalid number of operands!");
601 const MCExpr *Expr = getImm();
605 void addMemOperands(MCInst &Inst, unsigned N) const {
606 assert(N == 2 && "Invalid number of operands!");
608 Inst.addOperand(MCOperand::CreateReg(getMemBase()->getGPR32Reg()));
610 const MCExpr *Expr = getMemOff();
614 bool isReg() const override {
615 // As a special case until we sort out the definition of div/divu, pretend
616 // that $0/$zero are k_PhysRegister so that MCK_ZERO works correctly.
617 if (isGPRAsmReg() && RegIdx.Index == 0)
620 return Kind == k_PhysRegister;
622 bool isRegIdx() const { return Kind == k_RegisterIndex; }
623 bool isImm() const override { return Kind == k_Immediate; }
624 bool isConstantImm() const {
625 return isImm() && dyn_cast<MCConstantExpr>(getImm());
627 bool isToken() const override {
628 // Note: It's not possible to pretend that other operand kinds are tokens.
629 // The matcher emitter checks tokens first.
630 return Kind == k_Token;
632 bool isMem() const override { return Kind == k_Memory; }
633 bool isConstantMemOff() const {
634 return isMem() && dyn_cast<MCConstantExpr>(getMemOff());
636 template <unsigned Bits> bool isMemWithSimmOffset() const {
637 return isMem() && isConstantMemOff() && isInt<Bits>(getConstantMemOff());
639 bool isInvNum() const { return Kind == k_Immediate; }
640 bool isLSAImm() const {
641 if (!isConstantImm())
643 int64_t Val = getConstantImm();
644 return 1 <= Val && Val <= 4;
647 StringRef getToken() const {
648 assert(Kind == k_Token && "Invalid access!");
649 return StringRef(Tok.Data, Tok.Length);
652 unsigned getReg() const override {
653 // As a special case until we sort out the definition of div/divu, pretend
654 // that $0/$zero are k_PhysRegister so that MCK_ZERO works correctly.
655 if (Kind == k_RegisterIndex && RegIdx.Index == 0 &&
656 RegIdx.Kind & RegKind_GPR)
657 return getGPR32Reg(); // FIXME: GPR64 too
659 assert(Kind == k_PhysRegister && "Invalid access!");
663 const MCExpr *getImm() const {
664 assert((Kind == k_Immediate) && "Invalid access!");
668 int64_t getConstantImm() const {
669 const MCExpr *Val = getImm();
670 return static_cast<const MCConstantExpr *>(Val)->getValue();
673 MipsOperand *getMemBase() const {
674 assert((Kind == k_Memory) && "Invalid access!");
678 const MCExpr *getMemOff() const {
679 assert((Kind == k_Memory) && "Invalid access!");
683 int64_t getConstantMemOff() const {
684 return static_cast<const MCConstantExpr *>(getMemOff())->getValue();
687 static std::unique_ptr<MipsOperand> CreateToken(StringRef Str, SMLoc S,
688 MipsAsmParser &Parser) {
689 auto Op = make_unique<MipsOperand>(k_Token, Parser);
690 Op->Tok.Data = Str.data();
691 Op->Tok.Length = Str.size();
697 /// Create a numeric register (e.g. $1). The exact register remains
698 /// unresolved until an instruction successfully matches
699 static std::unique_ptr<MipsOperand>
700 CreateNumericReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S,
701 SMLoc E, MipsAsmParser &Parser) {
702 DEBUG(dbgs() << "CreateNumericReg(" << Index << ", ...)\n");
703 return CreateReg(Index, RegKind_Numeric, RegInfo, S, E, Parser);
706 /// Create a register that is definitely a GPR.
707 /// This is typically only used for named registers such as $gp.
708 static std::unique_ptr<MipsOperand>
709 CreateGPRReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E,
710 MipsAsmParser &Parser) {
711 return CreateReg(Index, RegKind_GPR, RegInfo, S, E, Parser);
714 /// Create a register that is definitely a FGR.
715 /// This is typically only used for named registers such as $f0.
716 static std::unique_ptr<MipsOperand>
717 CreateFGRReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E,
718 MipsAsmParser &Parser) {
719 return CreateReg(Index, RegKind_FGR, RegInfo, S, E, Parser);
722 /// Create a register that is definitely an FCC.
723 /// This is typically only used for named registers such as $fcc0.
724 static std::unique_ptr<MipsOperand>
725 CreateFCCReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E,
726 MipsAsmParser &Parser) {
727 return CreateReg(Index, RegKind_FCC, RegInfo, S, E, Parser);
730 /// Create a register that is definitely an ACC.
731 /// This is typically only used for named registers such as $ac0.
732 static std::unique_ptr<MipsOperand>
733 CreateACCReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E,
734 MipsAsmParser &Parser) {
735 return CreateReg(Index, RegKind_ACC, RegInfo, S, E, Parser);
738 /// Create a register that is definitely an MSA128.
739 /// This is typically only used for named registers such as $w0.
740 static std::unique_ptr<MipsOperand>
741 CreateMSA128Reg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S,
742 SMLoc E, MipsAsmParser &Parser) {
743 return CreateReg(Index, RegKind_MSA128, RegInfo, S, E, Parser);
746 /// Create a register that is definitely an MSACtrl.
747 /// This is typically only used for named registers such as $msaaccess.
748 static std::unique_ptr<MipsOperand>
749 CreateMSACtrlReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S,
750 SMLoc E, MipsAsmParser &Parser) {
751 return CreateReg(Index, RegKind_MSACtrl, RegInfo, S, E, Parser);
754 static std::unique_ptr<MipsOperand>
755 CreateImm(const MCExpr *Val, SMLoc S, SMLoc E, MipsAsmParser &Parser) {
756 auto Op = make_unique<MipsOperand>(k_Immediate, Parser);
763 static std::unique_ptr<MipsOperand>
764 CreateMem(std::unique_ptr<MipsOperand> Base, const MCExpr *Off, SMLoc S,
765 SMLoc E, MipsAsmParser &Parser) {
766 auto Op = make_unique<MipsOperand>(k_Memory, Parser);
767 Op->Mem.Base = Base.release();
774 bool isGPRAsmReg() const {
775 return isRegIdx() && RegIdx.Kind & RegKind_GPR && RegIdx.Index <= 31;
777 bool isFGRAsmReg() const {
778 // AFGR64 is $0-$15 but we handle this in getAFGR64()
779 return isRegIdx() && RegIdx.Kind & RegKind_FGR && RegIdx.Index <= 31;
781 bool isHWRegsAsmReg() const {
782 return isRegIdx() && RegIdx.Kind & RegKind_HWRegs && RegIdx.Index <= 31;
784 bool isCCRAsmReg() const {
785 return isRegIdx() && RegIdx.Kind & RegKind_CCR && RegIdx.Index <= 31;
787 bool isFCCAsmReg() const {
788 if (!(isRegIdx() && RegIdx.Kind & RegKind_FCC))
790 if (!AsmParser.hasEightFccRegisters())
791 return RegIdx.Index == 0;
792 return RegIdx.Index <= 7;
794 bool isACCAsmReg() const {
795 return isRegIdx() && RegIdx.Kind & RegKind_ACC && RegIdx.Index <= 3;
797 bool isCOP2AsmReg() const {
798 return isRegIdx() && RegIdx.Kind & RegKind_COP2 && RegIdx.Index <= 31;
800 bool isCOP3AsmReg() const {
801 return isRegIdx() && RegIdx.Kind & RegKind_COP3 && RegIdx.Index <= 31;
803 bool isMSA128AsmReg() const {
804 return isRegIdx() && RegIdx.Kind & RegKind_MSA128 && RegIdx.Index <= 31;
806 bool isMSACtrlAsmReg() const {
807 return isRegIdx() && RegIdx.Kind & RegKind_MSACtrl && RegIdx.Index <= 7;
810 /// getStartLoc - Get the location of the first token of this operand.
811 SMLoc getStartLoc() const override { return StartLoc; }
812 /// getEndLoc - Get the location of the last token of this operand.
813 SMLoc getEndLoc() const override { return EndLoc; }
815 virtual ~MipsOperand() {
823 case k_RegisterIndex:
829 void print(raw_ostream &OS) const override {
844 OS << "PhysReg<" << PhysReg.Num << ">";
846 case k_RegisterIndex:
847 OS << "RegIdx<" << RegIdx.Index << ":" << RegIdx.Kind << ">";
854 }; // class MipsOperand
858 extern const MCInstrDesc MipsInsts[];
860 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
861 return MipsInsts[Opcode];
864 bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
865 SmallVectorImpl<MCInst> &Instructions) {
866 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
870 if (MCID.isBranch() || MCID.isCall()) {
871 const unsigned Opcode = Inst.getOpcode();
881 assert(MCID.getNumOperands() == 3 && "unexpected number of operands");
882 Offset = Inst.getOperand(2);
884 break; // We'll deal with this situation later on when applying fixups.
885 if (!isIntN(isMicroMips() ? 17 : 18, Offset.getImm()))
886 return Error(IDLoc, "branch target out of range");
887 if (OffsetToAlignment(Offset.getImm(), 1LL << (isMicroMips() ? 1 : 2)))
888 return Error(IDLoc, "branch to misaligned address");
902 case Mips::BGEZAL_MM:
903 case Mips::BLTZAL_MM:
906 assert(MCID.getNumOperands() == 2 && "unexpected number of operands");
907 Offset = Inst.getOperand(1);
909 break; // We'll deal with this situation later on when applying fixups.
910 if (!isIntN(isMicroMips() ? 17 : 18, Offset.getImm()))
911 return Error(IDLoc, "branch target out of range");
912 if (OffsetToAlignment(Offset.getImm(), 1LL << (isMicroMips() ? 1 : 2)))
913 return Error(IDLoc, "branch to misaligned address");
918 // SSNOP is deprecated on MIPS32r6/MIPS64r6
919 // We still accept it but it is a normal nop.
920 if (hasMips32r6() && Inst.getOpcode() == Mips::SSNOP) {
921 std::string ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
922 Warning(IDLoc, "ssnop is deprecated for " + ISA + " and is equivalent to a "
926 if (MCID.hasDelaySlot() && Options.isReorder()) {
927 // If this instruction has a delay slot and .set reorder is active,
928 // emit a NOP after it.
929 Instructions.push_back(Inst);
931 NopInst.setOpcode(Mips::SLL);
932 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
933 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
934 NopInst.addOperand(MCOperand::CreateImm(0));
935 Instructions.push_back(NopInst);
939 if (MCID.mayLoad() || MCID.mayStore()) {
940 // Check the offset of memory operand, if it is a symbol
941 // reference or immediate we may have to expand instructions.
942 for (unsigned i = 0; i < MCID.getNumOperands(); i++) {
943 const MCOperandInfo &OpInfo = MCID.OpInfo[i];
944 if ((OpInfo.OperandType == MCOI::OPERAND_MEMORY) ||
945 (OpInfo.OperandType == MCOI::OPERAND_UNKNOWN)) {
946 MCOperand &Op = Inst.getOperand(i);
948 int MemOffset = Op.getImm();
949 if (MemOffset < -32768 || MemOffset > 32767) {
950 // Offset can't exceed 16bit value.
951 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), true);
954 } else if (Op.isExpr()) {
955 const MCExpr *Expr = Op.getExpr();
956 if (Expr->getKind() == MCExpr::SymbolRef) {
957 const MCSymbolRefExpr *SR =
958 static_cast<const MCSymbolRefExpr *>(Expr);
959 if (SR->getKind() == MCSymbolRefExpr::VK_None) {
961 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false);
964 } else if (!isEvaluated(Expr)) {
965 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false);
973 if (needsExpansion(Inst))
974 return expandInstruction(Inst, IDLoc, Instructions);
976 Instructions.push_back(Inst);
981 bool MipsAsmParser::needsExpansion(MCInst &Inst) {
983 switch (Inst.getOpcode()) {
984 case Mips::LoadImm32Reg:
985 case Mips::LoadAddr32Imm:
986 case Mips::LoadAddr32Reg:
987 case Mips::LoadImm64Reg:
994 bool MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
995 SmallVectorImpl<MCInst> &Instructions) {
996 switch (Inst.getOpcode()) {
997 default: assert(0 && "unimplemented expansion");
999 case Mips::LoadImm32Reg:
1000 return expandLoadImm(Inst, IDLoc, Instructions);
1001 case Mips::LoadImm64Reg:
1003 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
1006 return expandLoadImm(Inst, IDLoc, Instructions);
1007 case Mips::LoadAddr32Imm:
1008 return expandLoadAddressImm(Inst, IDLoc, Instructions);
1009 case Mips::LoadAddr32Reg:
1010 return expandLoadAddressReg(Inst, IDLoc, Instructions);
1015 template <int Shift, bool PerformShift>
1016 void createShiftOr(int64_t Value, unsigned RegNo, SMLoc IDLoc,
1017 SmallVectorImpl<MCInst> &Instructions) {
1020 tmpInst.setOpcode(Mips::DSLL);
1021 tmpInst.addOperand(MCOperand::CreateReg(RegNo));
1022 tmpInst.addOperand(MCOperand::CreateReg(RegNo));
1023 tmpInst.addOperand(MCOperand::CreateImm(16));
1024 tmpInst.setLoc(IDLoc);
1025 Instructions.push_back(tmpInst);
1028 tmpInst.setOpcode(Mips::ORi);
1029 tmpInst.addOperand(MCOperand::CreateReg(RegNo));
1030 tmpInst.addOperand(MCOperand::CreateReg(RegNo));
1032 MCOperand::CreateImm(((Value & (0xffffLL << Shift)) >> Shift)));
1033 tmpInst.setLoc(IDLoc);
1034 Instructions.push_back(tmpInst);
1038 bool MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
1039 SmallVectorImpl<MCInst> &Instructions) {
1041 const MCOperand &ImmOp = Inst.getOperand(1);
1042 assert(ImmOp.isImm() && "expected immediate operand kind");
1043 const MCOperand &RegOp = Inst.getOperand(0);
1044 assert(RegOp.isReg() && "expected register operand kind");
1046 int64_t ImmValue = ImmOp.getImm();
1047 tmpInst.setLoc(IDLoc);
1048 // FIXME: gas has a special case for values that are 000...1111, which
1049 // becomes a li -1 and then a dsrl
1050 if (0 <= ImmValue && ImmValue <= 65535) {
1051 // For 0 <= j <= 65535.
1052 // li d,j => ori d,$zero,j
1053 tmpInst.setOpcode(Mips::ORi);
1054 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1055 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
1056 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
1057 Instructions.push_back(tmpInst);
1058 } else if (ImmValue < 0 && ImmValue >= -32768) {
1059 // For -32768 <= j < 0.
1060 // li d,j => addiu d,$zero,j
1061 tmpInst.setOpcode(Mips::ADDiu);
1062 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1063 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
1064 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
1065 Instructions.push_back(tmpInst);
1066 } else if ((ImmValue & 0xffffffff) == ImmValue) {
1067 // For any value of j that is representable as a 32-bit integer, create
1069 // li d,j => lui d,hi16(j)
1071 tmpInst.setOpcode(Mips::LUi);
1072 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1073 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
1074 Instructions.push_back(tmpInst);
1075 createShiftOr<0, false>(ImmValue, RegOp.getReg(), IDLoc, Instructions);
1076 } else if ((ImmValue & (0xffffLL << 48)) == 0) {
1078 Error (IDLoc, "instruction requires a CPU feature not currently enabled");
1082 // <------- lo32 ------>
1083 // <------- hi32 ------>
1084 // <- hi16 -> <- lo16 ->
1085 // _________________________________
1087 // | 16-bytes | 16-bytes | 16-bytes |
1088 // |__________|__________|__________|
1090 // For any value of j that is representable as a 48-bit integer, create
1092 // li d,j => lui d,hi16(j)
1093 // ori d,d,hi16(lo32(j))
1095 // ori d,d,lo16(lo32(j))
1096 tmpInst.setOpcode(Mips::LUi);
1097 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1099 MCOperand::CreateImm((ImmValue & (0xffffLL << 32)) >> 32));
1100 Instructions.push_back(tmpInst);
1101 createShiftOr<16, false>(ImmValue, RegOp.getReg(), IDLoc, Instructions);
1102 createShiftOr<0, true>(ImmValue, RegOp.getReg(), IDLoc, Instructions);
1105 Error (IDLoc, "instruction requires a CPU feature not currently enabled");
1109 // <------- hi32 ------> <------- lo32 ------>
1110 // <- hi16 -> <- lo16 ->
1111 // ___________________________________________
1113 // | 16-bytes | 16-bytes | 16-bytes | 16-bytes |
1114 // |__________|__________|__________|__________|
1116 // For any value of j that isn't representable as a 48-bit integer.
1117 // li d,j => lui d,hi16(j)
1118 // ori d,d,lo16(hi32(j))
1120 // ori d,d,hi16(lo32(j))
1122 // ori d,d,lo16(lo32(j))
1123 tmpInst.setOpcode(Mips::LUi);
1124 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1126 MCOperand::CreateImm((ImmValue & (0xffffLL << 48)) >> 48));
1127 Instructions.push_back(tmpInst);
1128 createShiftOr<32, false>(ImmValue, RegOp.getReg(), IDLoc, Instructions);
1129 createShiftOr<16, true>(ImmValue, RegOp.getReg(), IDLoc, Instructions);
1130 createShiftOr<0, true>(ImmValue, RegOp.getReg(), IDLoc, Instructions);
1136 MipsAsmParser::expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
1137 SmallVectorImpl<MCInst> &Instructions) {
1139 const MCOperand &ImmOp = Inst.getOperand(2);
1140 assert(ImmOp.isImm() && "expected immediate operand kind");
1141 const MCOperand &SrcRegOp = Inst.getOperand(1);
1142 assert(SrcRegOp.isReg() && "expected register operand kind");
1143 const MCOperand &DstRegOp = Inst.getOperand(0);
1144 assert(DstRegOp.isReg() && "expected register operand kind");
1145 int ImmValue = ImmOp.getImm();
1146 if (-32768 <= ImmValue && ImmValue <= 65535) {
1147 // For -32768 <= j <= 65535.
1148 // la d,j(s) => addiu d,s,j
1149 tmpInst.setOpcode(Mips::ADDiu);
1150 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1151 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
1152 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
1153 Instructions.push_back(tmpInst);
1155 // For any other value of j that is representable as a 32-bit integer.
1156 // la d,j(s) => lui d,hi16(j)
1159 tmpInst.setOpcode(Mips::LUi);
1160 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1161 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
1162 Instructions.push_back(tmpInst);
1164 tmpInst.setOpcode(Mips::ORi);
1165 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1166 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1167 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
1168 Instructions.push_back(tmpInst);
1170 tmpInst.setOpcode(Mips::ADDu);
1171 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1172 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1173 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
1174 Instructions.push_back(tmpInst);
1180 MipsAsmParser::expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
1181 SmallVectorImpl<MCInst> &Instructions) {
1183 const MCOperand &ImmOp = Inst.getOperand(1);
1184 assert(ImmOp.isImm() && "expected immediate operand kind");
1185 const MCOperand &RegOp = Inst.getOperand(0);
1186 assert(RegOp.isReg() && "expected register operand kind");
1187 int ImmValue = ImmOp.getImm();
1188 if (-32768 <= ImmValue && ImmValue <= 65535) {
1189 // For -32768 <= j <= 65535.
1190 // la d,j => addiu d,$zero,j
1191 tmpInst.setOpcode(Mips::ADDiu);
1192 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1193 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
1194 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
1195 Instructions.push_back(tmpInst);
1197 // For any other value of j that is representable as a 32-bit integer.
1198 // la d,j => lui d,hi16(j)
1200 tmpInst.setOpcode(Mips::LUi);
1201 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1202 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
1203 Instructions.push_back(tmpInst);
1205 tmpInst.setOpcode(Mips::ORi);
1206 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1207 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1208 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
1209 Instructions.push_back(tmpInst);
1214 void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc,
1215 SmallVectorImpl<MCInst> &Instructions,
1216 bool isLoad, bool isImmOpnd) {
1217 const MCSymbolRefExpr *SR;
1219 unsigned ImmOffset, HiOffset, LoOffset;
1220 const MCExpr *ExprOffset;
1222 // 1st operand is either the source or destination register.
1223 assert(Inst.getOperand(0).isReg() && "expected register operand kind");
1224 unsigned RegOpNum = Inst.getOperand(0).getReg();
1225 // 2nd operand is the base register.
1226 assert(Inst.getOperand(1).isReg() && "expected register operand kind");
1227 unsigned BaseRegNum = Inst.getOperand(1).getReg();
1228 // 3rd operand is either an immediate or expression.
1230 assert(Inst.getOperand(2).isImm() && "expected immediate operand kind");
1231 ImmOffset = Inst.getOperand(2).getImm();
1232 LoOffset = ImmOffset & 0x0000ffff;
1233 HiOffset = (ImmOffset & 0xffff0000) >> 16;
1234 // If msb of LoOffset is 1(negative number) we must increment HiOffset.
1235 if (LoOffset & 0x8000)
1238 ExprOffset = Inst.getOperand(2).getExpr();
1239 // All instructions will have the same location.
1240 TempInst.setLoc(IDLoc);
1241 // These are some of the types of expansions we perform here:
1242 // 1) lw $8, sym => lui $8, %hi(sym)
1243 // lw $8, %lo(sym)($8)
1244 // 2) lw $8, offset($9) => lui $8, %hi(offset)
1246 // lw $8, %lo(offset)($9)
1247 // 3) lw $8, offset($8) => lui $at, %hi(offset)
1249 // lw $8, %lo(offset)($at)
1250 // 4) sw $8, sym => lui $at, %hi(sym)
1251 // sw $8, %lo(sym)($at)
1252 // 5) sw $8, offset($8) => lui $at, %hi(offset)
1254 // sw $8, %lo(offset)($at)
1255 // 6) ldc1 $f0, sym => lui $at, %hi(sym)
1256 // ldc1 $f0, %lo(sym)($at)
1258 // For load instructions we can use the destination register as a temporary
1259 // if base and dst are different (examples 1 and 2) and if the base register
1260 // is general purpose otherwise we must use $at (example 6) and error if it's
1261 // not available. For stores we must use $at (examples 4 and 5) because we
1262 // must not clobber the source register setting up the offset.
1263 const MCInstrDesc &Desc = getInstDesc(Inst.getOpcode());
1264 int16_t RegClassOp0 = Desc.OpInfo[0].RegClass;
1265 unsigned RegClassIDOp0 =
1266 getContext().getRegisterInfo()->getRegClass(RegClassOp0).getID();
1267 bool IsGPR = (RegClassIDOp0 == Mips::GPR32RegClassID) ||
1268 (RegClassIDOp0 == Mips::GPR64RegClassID);
1269 if (isLoad && IsGPR && (BaseRegNum != RegOpNum))
1270 TmpRegNum = RegOpNum;
1272 int AT = getATReg(IDLoc);
1273 // At this point we need AT to perform the expansions and we exit if it is
1278 getReg((isGP64()) ? Mips::GPR64RegClassID : Mips::GPR32RegClassID, AT);
1281 TempInst.setOpcode(Mips::LUi);
1282 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
1284 TempInst.addOperand(MCOperand::CreateImm(HiOffset));
1286 if (ExprOffset->getKind() == MCExpr::SymbolRef) {
1287 SR = static_cast<const MCSymbolRefExpr *>(ExprOffset);
1288 const MCSymbolRefExpr *HiExpr = MCSymbolRefExpr::Create(
1289 SR->getSymbol().getName(), MCSymbolRefExpr::VK_Mips_ABS_HI,
1291 TempInst.addOperand(MCOperand::CreateExpr(HiExpr));
1293 const MCExpr *HiExpr = evaluateRelocExpr(ExprOffset, "hi");
1294 TempInst.addOperand(MCOperand::CreateExpr(HiExpr));
1297 // Add the instruction to the list.
1298 Instructions.push_back(TempInst);
1299 // Prepare TempInst for next instruction.
1301 // Add temp register to base.
1302 TempInst.setOpcode(Mips::ADDu);
1303 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
1304 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
1305 TempInst.addOperand(MCOperand::CreateReg(BaseRegNum));
1306 Instructions.push_back(TempInst);
1308 // And finally, create original instruction with low part
1309 // of offset and new base.
1310 TempInst.setOpcode(Inst.getOpcode());
1311 TempInst.addOperand(MCOperand::CreateReg(RegOpNum));
1312 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
1314 TempInst.addOperand(MCOperand::CreateImm(LoOffset));
1316 if (ExprOffset->getKind() == MCExpr::SymbolRef) {
1317 const MCSymbolRefExpr *LoExpr = MCSymbolRefExpr::Create(
1318 SR->getSymbol().getName(), MCSymbolRefExpr::VK_Mips_ABS_LO,
1320 TempInst.addOperand(MCOperand::CreateExpr(LoExpr));
1322 const MCExpr *LoExpr = evaluateRelocExpr(ExprOffset, "lo");
1323 TempInst.addOperand(MCOperand::CreateExpr(LoExpr));
1326 Instructions.push_back(TempInst);
1330 unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
1331 // As described by the Mips32r2 spec, the registers Rd and Rs for
1332 // jalr.hb must be different.
1333 unsigned Opcode = Inst.getOpcode();
1335 if (Opcode == Mips::JALR_HB &&
1336 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()))
1337 return Match_RequiresDifferentSrcAndDst;
1339 return Match_Success;
1342 bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1343 OperandVector &Operands,
1345 unsigned &ErrorInfo,
1346 bool MatchingInlineAsm) {
1349 SmallVector<MCInst, 8> Instructions;
1350 unsigned MatchResult =
1351 MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
1353 switch (MatchResult) {
1356 case Match_Success: {
1357 if (processInstruction(Inst, IDLoc, Instructions))
1359 for (unsigned i = 0; i < Instructions.size(); i++)
1360 Out.EmitInstruction(Instructions[i], STI);
1363 case Match_MissingFeature:
1364 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
1366 case Match_InvalidOperand: {
1367 SMLoc ErrorLoc = IDLoc;
1368 if (ErrorInfo != ~0U) {
1369 if (ErrorInfo >= Operands.size())
1370 return Error(IDLoc, "too few operands for instruction");
1372 ErrorLoc = ((MipsOperand &)*Operands[ErrorInfo]).getStartLoc();
1373 if (ErrorLoc == SMLoc())
1377 return Error(ErrorLoc, "invalid operand for instruction");
1379 case Match_MnemonicFail:
1380 return Error(IDLoc, "invalid instruction");
1381 case Match_RequiresDifferentSrcAndDst:
1382 return Error(IDLoc, "source and destination must be different");
1387 void MipsAsmParser::WarnIfAssemblerTemporary(int RegIndex, SMLoc Loc) {
1388 if ((RegIndex != 0) && ((int)Options.getATRegNum() == RegIndex)) {
1390 Warning(Loc, "Used $at without \".set noat\"");
1392 Warning(Loc, Twine("Used $") + Twine(RegIndex) + " with \".set at=$" +
1393 Twine(RegIndex) + "\"");
1397 int MipsAsmParser::matchCPURegisterName(StringRef Name) {
1400 CC = StringSwitch<unsigned>(Name)
1436 if (isN32() || isN64()) {
1437 // Although SGI documentation just cuts out t0-t3 for n32/n64,
1438 // GNU pushes the values of t0-t3 to override the o32/o64 values for t4-t7
1439 // We are supporting both cases, so for t0-t3 we'll just push them to t4-t7.
1440 if (8 <= CC && CC <= 11)
1444 CC = StringSwitch<unsigned>(Name)
1457 int MipsAsmParser::matchFPURegisterName(StringRef Name) {
1459 if (Name[0] == 'f') {
1460 StringRef NumString = Name.substr(1);
1462 if (NumString.getAsInteger(10, IntVal))
1463 return -1; // This is not an integer.
1464 if (IntVal > 31) // Maximum index for fpu register.
1471 int MipsAsmParser::matchFCCRegisterName(StringRef Name) {
1473 if (Name.startswith("fcc")) {
1474 StringRef NumString = Name.substr(3);
1476 if (NumString.getAsInteger(10, IntVal))
1477 return -1; // This is not an integer.
1478 if (IntVal > 7) // There are only 8 fcc registers.
1485 int MipsAsmParser::matchACRegisterName(StringRef Name) {
1487 if (Name.startswith("ac")) {
1488 StringRef NumString = Name.substr(2);
1490 if (NumString.getAsInteger(10, IntVal))
1491 return -1; // This is not an integer.
1492 if (IntVal > 3) // There are only 3 acc registers.
1499 int MipsAsmParser::matchMSA128RegisterName(StringRef Name) {
1502 if (Name.front() != 'w' || Name.drop_front(1).getAsInteger(10, IntVal))
1511 int MipsAsmParser::matchMSA128CtrlRegisterName(StringRef Name) {
1514 CC = StringSwitch<unsigned>(Name)
1517 .Case("msaaccess", 2)
1519 .Case("msamodify", 4)
1520 .Case("msarequest", 5)
1522 .Case("msaunmap", 7)
1528 bool MipsAssemblerOptions::setATReg(unsigned Reg) {
1536 int MipsAsmParser::getATReg(SMLoc Loc) {
1537 int AT = Options.getATRegNum();
1539 reportParseError(Loc,
1540 "Pseudo instruction requires $at, which is not available");
1544 unsigned MipsAsmParser::getReg(int RC, int RegNo) {
1545 return *(getContext().getRegisterInfo()->getRegClass(RC).begin() + RegNo);
1548 unsigned MipsAsmParser::getGPR(int RegNo) {
1549 return getReg(isGP64() ? Mips::GPR64RegClassID : Mips::GPR32RegClassID,
1553 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) {
1555 getContext().getRegisterInfo()->getRegClass(RegClass).getNumRegs() - 1)
1558 return getReg(RegClass, RegNum);
1561 bool MipsAsmParser::ParseOperand(OperandVector &Operands, StringRef Mnemonic) {
1562 DEBUG(dbgs() << "ParseOperand\n");
1564 // Check if the current operand has a custom associated parser, if so, try to
1565 // custom parse the operand, or fallback to the general approach.
1566 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1567 if (ResTy == MatchOperand_Success)
1569 // If there wasn't a custom match, try the generic matcher below. Otherwise,
1570 // there was a match, but an error occurred, in which case, just return that
1571 // the operand parsing failed.
1572 if (ResTy == MatchOperand_ParseFail)
1575 DEBUG(dbgs() << ".. Generic Parser\n");
1577 switch (getLexer().getKind()) {
1579 Error(Parser.getTok().getLoc(), "unexpected token in operand");
1581 case AsmToken::Dollar: {
1582 // Parse the register.
1583 SMLoc S = Parser.getTok().getLoc();
1585 // Almost all registers have been parsed by custom parsers. There is only
1586 // one exception to this. $zero (and it's alias $0) will reach this point
1587 // for div, divu, and similar instructions because it is not an operand
1588 // to the instruction definition but an explicit register. Special case
1589 // this situation for now.
1590 if (ParseAnyRegister(Operands) != MatchOperand_NoMatch)
1593 // Maybe it is a symbol reference.
1594 StringRef Identifier;
1595 if (Parser.parseIdentifier(Identifier))
1598 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1599 MCSymbol *Sym = getContext().GetOrCreateSymbol("$" + Identifier);
1600 // Otherwise create a symbol reference.
1602 MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None, getContext());
1604 Operands.push_back(MipsOperand::CreateImm(Res, S, E, *this));
1607 // Else drop to expression parsing.
1608 case AsmToken::LParen:
1609 case AsmToken::Minus:
1610 case AsmToken::Plus:
1611 case AsmToken::Integer:
1612 case AsmToken::Tilde:
1613 case AsmToken::String: {
1614 DEBUG(dbgs() << ".. generic integer\n");
1615 OperandMatchResultTy ResTy = ParseImm(Operands);
1616 return ResTy != MatchOperand_Success;
1618 case AsmToken::Percent: {
1619 // It is a symbol reference or constant expression.
1620 const MCExpr *IdVal;
1621 SMLoc S = Parser.getTok().getLoc(); // Start location of the operand.
1622 if (parseRelocOperand(IdVal))
1625 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1627 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E, *this));
1629 } // case AsmToken::Percent
1630 } // switch(getLexer().getKind())
1634 const MCExpr *MipsAsmParser::evaluateRelocExpr(const MCExpr *Expr,
1635 StringRef RelocStr) {
1637 // Check the type of the expression.
1638 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(Expr)) {
1639 // It's a constant, evaluate reloc value.
1641 switch (getVariantKind(RelocStr)) {
1642 case MCSymbolRefExpr::VK_Mips_ABS_LO:
1643 // Get the 1st 16-bits.
1644 Val = MCE->getValue() & 0xffff;
1646 case MCSymbolRefExpr::VK_Mips_ABS_HI:
1647 // Get the 2nd 16-bits. Also add 1 if bit 15 is 1, to compensate for low
1648 // 16 bits being negative.
1649 Val = ((MCE->getValue() + 0x8000) >> 16) & 0xffff;
1651 case MCSymbolRefExpr::VK_Mips_HIGHER:
1652 // Get the 3rd 16-bits.
1653 Val = ((MCE->getValue() + 0x80008000LL) >> 32) & 0xffff;
1655 case MCSymbolRefExpr::VK_Mips_HIGHEST:
1656 // Get the 4th 16-bits.
1657 Val = ((MCE->getValue() + 0x800080008000LL) >> 48) & 0xffff;
1660 report_fatal_error("Unsupported reloc value!");
1662 return MCConstantExpr::Create(Val, getContext());
1665 if (const MCSymbolRefExpr *MSRE = dyn_cast<MCSymbolRefExpr>(Expr)) {
1666 // It's a symbol, create a symbolic expression from the symbol.
1667 StringRef Symbol = MSRE->getSymbol().getName();
1668 MCSymbolRefExpr::VariantKind VK = getVariantKind(RelocStr);
1669 Res = MCSymbolRefExpr::Create(Symbol, VK, getContext());
1673 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
1674 MCSymbolRefExpr::VariantKind VK = getVariantKind(RelocStr);
1676 // Try to create target expression.
1677 if (MipsMCExpr::isSupportedBinaryExpr(VK, BE))
1678 return MipsMCExpr::Create(VK, Expr, getContext());
1680 const MCExpr *LExp = evaluateRelocExpr(BE->getLHS(), RelocStr);
1681 const MCExpr *RExp = evaluateRelocExpr(BE->getRHS(), RelocStr);
1682 Res = MCBinaryExpr::Create(BE->getOpcode(), LExp, RExp, getContext());
1686 if (const MCUnaryExpr *UN = dyn_cast<MCUnaryExpr>(Expr)) {
1687 const MCExpr *UnExp = evaluateRelocExpr(UN->getSubExpr(), RelocStr);
1688 Res = MCUnaryExpr::Create(UN->getOpcode(), UnExp, getContext());
1691 // Just return the original expression.
1695 bool MipsAsmParser::isEvaluated(const MCExpr *Expr) {
1697 switch (Expr->getKind()) {
1698 case MCExpr::Constant:
1700 case MCExpr::SymbolRef:
1701 return (cast<MCSymbolRefExpr>(Expr)->getKind() != MCSymbolRefExpr::VK_None);
1702 case MCExpr::Binary:
1703 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
1704 if (!isEvaluated(BE->getLHS()))
1706 return isEvaluated(BE->getRHS());
1709 return isEvaluated(cast<MCUnaryExpr>(Expr)->getSubExpr());
1710 case MCExpr::Target:
1716 bool MipsAsmParser::parseRelocOperand(const MCExpr *&Res) {
1717 Parser.Lex(); // Eat the % token.
1718 const AsmToken &Tok = Parser.getTok(); // Get next token, operation.
1719 if (Tok.isNot(AsmToken::Identifier))
1722 std::string Str = Tok.getIdentifier().str();
1724 Parser.Lex(); // Eat the identifier.
1725 // Now make an expression from the rest of the operand.
1726 const MCExpr *IdVal;
1729 if (getLexer().getKind() == AsmToken::LParen) {
1731 Parser.Lex(); // Eat the '(' token.
1732 if (getLexer().getKind() == AsmToken::Percent) {
1733 Parser.Lex(); // Eat the % token.
1734 const AsmToken &nextTok = Parser.getTok();
1735 if (nextTok.isNot(AsmToken::Identifier))
1738 Str += nextTok.getIdentifier();
1739 Parser.Lex(); // Eat the identifier.
1740 if (getLexer().getKind() != AsmToken::LParen)
1745 if (getParser().parseParenExpression(IdVal, EndLoc))
1748 while (getLexer().getKind() == AsmToken::RParen)
1749 Parser.Lex(); // Eat the ')' token.
1752 return true; // Parenthesis must follow the relocation operand.
1754 Res = evaluateRelocExpr(IdVal, Str);
1758 bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1760 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands;
1761 OperandMatchResultTy ResTy = ParseAnyRegister(Operands);
1762 if (ResTy == MatchOperand_Success) {
1763 assert(Operands.size() == 1);
1764 MipsOperand &Operand = static_cast<MipsOperand &>(*Operands.front());
1765 StartLoc = Operand.getStartLoc();
1766 EndLoc = Operand.getEndLoc();
1768 // AFAIK, we only support numeric registers and named GPR's in CFI
1770 // Don't worry about eating tokens before failing. Using an unrecognised
1771 // register is a parse error.
1772 if (Operand.isGPRAsmReg()) {
1773 // Resolve to GPR32 or GPR64 appropriately.
1774 RegNo = isGP64() ? Operand.getGPR64Reg() : Operand.getGPR32Reg();
1777 return (RegNo == (unsigned)-1);
1780 assert(Operands.size() == 0);
1781 return (RegNo == (unsigned)-1);
1784 bool MipsAsmParser::parseMemOffset(const MCExpr *&Res, bool isParenExpr) {
1788 while (getLexer().getKind() == AsmToken::LParen)
1791 switch (getLexer().getKind()) {
1794 case AsmToken::Identifier:
1795 case AsmToken::LParen:
1796 case AsmToken::Integer:
1797 case AsmToken::Minus:
1798 case AsmToken::Plus:
1800 Result = getParser().parseParenExpression(Res, S);
1802 Result = (getParser().parseExpression(Res));
1803 while (getLexer().getKind() == AsmToken::RParen)
1806 case AsmToken::Percent:
1807 Result = parseRelocOperand(Res);
1812 MipsAsmParser::OperandMatchResultTy
1813 MipsAsmParser::parseMemOperand(OperandVector &Operands) {
1814 DEBUG(dbgs() << "parseMemOperand\n");
1815 const MCExpr *IdVal = nullptr;
1817 bool isParenExpr = false;
1818 MipsAsmParser::OperandMatchResultTy Res = MatchOperand_NoMatch;
1819 // First operand is the offset.
1820 S = Parser.getTok().getLoc();
1822 if (getLexer().getKind() == AsmToken::LParen) {
1827 if (getLexer().getKind() != AsmToken::Dollar) {
1828 if (parseMemOffset(IdVal, isParenExpr))
1829 return MatchOperand_ParseFail;
1831 const AsmToken &Tok = Parser.getTok(); // Get the next token.
1832 if (Tok.isNot(AsmToken::LParen)) {
1833 MipsOperand &Mnemonic = static_cast<MipsOperand &>(*Operands[0]);
1834 if (Mnemonic.getToken() == "la") {
1836 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1837 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E, *this));
1838 return MatchOperand_Success;
1840 if (Tok.is(AsmToken::EndOfStatement)) {
1842 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1844 // Zero register assumed, add a memory operand with ZERO as its base.
1845 // "Base" will be managed by k_Memory.
1846 auto Base = MipsOperand::CreateGPRReg(0, getContext().getRegisterInfo(),
1849 MipsOperand::CreateMem(std::move(Base), IdVal, S, E, *this));
1850 return MatchOperand_Success;
1852 Error(Parser.getTok().getLoc(), "'(' expected");
1853 return MatchOperand_ParseFail;
1856 Parser.Lex(); // Eat the '(' token.
1859 Res = ParseAnyRegister(Operands);
1860 if (Res != MatchOperand_Success)
1863 if (Parser.getTok().isNot(AsmToken::RParen)) {
1864 Error(Parser.getTok().getLoc(), "')' expected");
1865 return MatchOperand_ParseFail;
1868 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1870 Parser.Lex(); // Eat the ')' token.
1873 IdVal = MCConstantExpr::Create(0, getContext());
1875 // Replace the register operand with the memory operand.
1876 std::unique_ptr<MipsOperand> op(
1877 static_cast<MipsOperand *>(Operands.back().release()));
1878 // Remove the register from the operands.
1879 // "op" will be managed by k_Memory.
1880 Operands.pop_back();
1881 // Add the memory operand.
1882 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(IdVal)) {
1884 if (IdVal->EvaluateAsAbsolute(Imm))
1885 IdVal = MCConstantExpr::Create(Imm, getContext());
1886 else if (BE->getLHS()->getKind() != MCExpr::SymbolRef)
1887 IdVal = MCBinaryExpr::Create(BE->getOpcode(), BE->getRHS(), BE->getLHS(),
1891 Operands.push_back(MipsOperand::CreateMem(std::move(op), IdVal, S, E, *this));
1892 return MatchOperand_Success;
1895 bool MipsAsmParser::searchSymbolAlias(OperandVector &Operands) {
1897 MCSymbol *Sym = getContext().LookupSymbol(Parser.getTok().getIdentifier());
1899 SMLoc S = Parser.getTok().getLoc();
1901 if (Sym->isVariable())
1902 Expr = Sym->getVariableValue();
1905 if (Expr->getKind() == MCExpr::SymbolRef) {
1906 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr *>(Expr);
1907 const StringRef DefSymbol = Ref->getSymbol().getName();
1908 if (DefSymbol.startswith("$")) {
1909 OperandMatchResultTy ResTy =
1910 MatchAnyRegisterNameWithoutDollar(Operands, DefSymbol.substr(1), S);
1911 if (ResTy == MatchOperand_Success) {
1914 } else if (ResTy == MatchOperand_ParseFail)
1915 llvm_unreachable("Should never ParseFail");
1918 } else if (Expr->getKind() == MCExpr::Constant) {
1920 const MCConstantExpr *Const = static_cast<const MCConstantExpr *>(Expr);
1922 MipsOperand::CreateImm(Const, S, Parser.getTok().getLoc(), *this));
1929 MipsAsmParser::OperandMatchResultTy
1930 MipsAsmParser::MatchAnyRegisterNameWithoutDollar(OperandVector &Operands,
1931 StringRef Identifier,
1933 int Index = matchCPURegisterName(Identifier);
1935 Operands.push_back(MipsOperand::CreateGPRReg(
1936 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1937 return MatchOperand_Success;
1940 Index = matchFPURegisterName(Identifier);
1942 Operands.push_back(MipsOperand::CreateFGRReg(
1943 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1944 return MatchOperand_Success;
1947 Index = matchFCCRegisterName(Identifier);
1949 Operands.push_back(MipsOperand::CreateFCCReg(
1950 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1951 return MatchOperand_Success;
1954 Index = matchACRegisterName(Identifier);
1956 Operands.push_back(MipsOperand::CreateACCReg(
1957 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1958 return MatchOperand_Success;
1961 Index = matchMSA128RegisterName(Identifier);
1963 Operands.push_back(MipsOperand::CreateMSA128Reg(
1964 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1965 return MatchOperand_Success;
1968 Index = matchMSA128CtrlRegisterName(Identifier);
1970 Operands.push_back(MipsOperand::CreateMSACtrlReg(
1971 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1972 return MatchOperand_Success;
1975 return MatchOperand_NoMatch;
1978 MipsAsmParser::OperandMatchResultTy
1979 MipsAsmParser::MatchAnyRegisterWithoutDollar(OperandVector &Operands, SMLoc S) {
1980 auto Token = Parser.getLexer().peekTok(false);
1982 if (Token.is(AsmToken::Identifier)) {
1983 DEBUG(dbgs() << ".. identifier\n");
1984 StringRef Identifier = Token.getIdentifier();
1985 OperandMatchResultTy ResTy =
1986 MatchAnyRegisterNameWithoutDollar(Operands, Identifier, S);
1988 } else if (Token.is(AsmToken::Integer)) {
1989 DEBUG(dbgs() << ".. integer\n");
1990 Operands.push_back(MipsOperand::CreateNumericReg(
1991 Token.getIntVal(), getContext().getRegisterInfo(), S, Token.getLoc(),
1993 return MatchOperand_Success;
1996 DEBUG(dbgs() << Parser.getTok().getKind() << "\n");
1998 return MatchOperand_NoMatch;
2001 MipsAsmParser::OperandMatchResultTy
2002 MipsAsmParser::ParseAnyRegister(OperandVector &Operands) {
2003 DEBUG(dbgs() << "ParseAnyRegister\n");
2005 auto Token = Parser.getTok();
2007 SMLoc S = Token.getLoc();
2009 if (Token.isNot(AsmToken::Dollar)) {
2010 DEBUG(dbgs() << ".. !$ -> try sym aliasing\n");
2011 if (Token.is(AsmToken::Identifier)) {
2012 if (searchSymbolAlias(Operands))
2013 return MatchOperand_Success;
2015 DEBUG(dbgs() << ".. !symalias -> NoMatch\n");
2016 return MatchOperand_NoMatch;
2018 DEBUG(dbgs() << ".. $\n");
2020 OperandMatchResultTy ResTy = MatchAnyRegisterWithoutDollar(Operands, S);
2021 if (ResTy == MatchOperand_Success) {
2023 Parser.Lex(); // identifier
2028 MipsAsmParser::OperandMatchResultTy
2029 MipsAsmParser::ParseImm(OperandVector &Operands) {
2030 switch (getLexer().getKind()) {
2032 return MatchOperand_NoMatch;
2033 case AsmToken::LParen:
2034 case AsmToken::Minus:
2035 case AsmToken::Plus:
2036 case AsmToken::Integer:
2037 case AsmToken::Tilde:
2038 case AsmToken::String:
2042 const MCExpr *IdVal;
2043 SMLoc S = Parser.getTok().getLoc();
2044 if (getParser().parseExpression(IdVal))
2045 return MatchOperand_ParseFail;
2047 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2048 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E, *this));
2049 return MatchOperand_Success;
2052 MipsAsmParser::OperandMatchResultTy
2053 MipsAsmParser::ParseJumpTarget(OperandVector &Operands) {
2054 DEBUG(dbgs() << "ParseJumpTarget\n");
2056 SMLoc S = getLexer().getLoc();
2058 // Integers and expressions are acceptable
2059 OperandMatchResultTy ResTy = ParseImm(Operands);
2060 if (ResTy != MatchOperand_NoMatch)
2063 // Registers are a valid target and have priority over symbols.
2064 ResTy = ParseAnyRegister(Operands);
2065 if (ResTy != MatchOperand_NoMatch)
2068 const MCExpr *Expr = nullptr;
2069 if (Parser.parseExpression(Expr)) {
2070 // We have no way of knowing if a symbol was consumed so we must ParseFail
2071 return MatchOperand_ParseFail;
2074 MipsOperand::CreateImm(Expr, S, getLexer().getLoc(), *this));
2075 return MatchOperand_Success;
2078 MipsAsmParser::OperandMatchResultTy
2079 MipsAsmParser::parseInvNum(OperandVector &Operands) {
2080 const MCExpr *IdVal;
2081 // If the first token is '$' we may have register operand.
2082 if (Parser.getTok().is(AsmToken::Dollar))
2083 return MatchOperand_NoMatch;
2084 SMLoc S = Parser.getTok().getLoc();
2085 if (getParser().parseExpression(IdVal))
2086 return MatchOperand_ParseFail;
2087 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(IdVal);
2088 assert(MCE && "Unexpected MCExpr type.");
2089 int64_t Val = MCE->getValue();
2090 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2091 Operands.push_back(MipsOperand::CreateImm(
2092 MCConstantExpr::Create(0 - Val, getContext()), S, E, *this));
2093 return MatchOperand_Success;
2096 MipsAsmParser::OperandMatchResultTy
2097 MipsAsmParser::ParseLSAImm(OperandVector &Operands) {
2098 switch (getLexer().getKind()) {
2100 return MatchOperand_NoMatch;
2101 case AsmToken::LParen:
2102 case AsmToken::Plus:
2103 case AsmToken::Minus:
2104 case AsmToken::Integer:
2109 SMLoc S = Parser.getTok().getLoc();
2111 if (getParser().parseExpression(Expr))
2112 return MatchOperand_ParseFail;
2115 if (!Expr->EvaluateAsAbsolute(Val)) {
2116 Error(S, "expected immediate value");
2117 return MatchOperand_ParseFail;
2120 // The LSA instruction allows a 2-bit unsigned immediate. For this reason
2121 // and because the CPU always adds one to the immediate field, the allowed
2122 // range becomes 1..4. We'll only check the range here and will deal
2123 // with the addition/subtraction when actually decoding/encoding
2125 if (Val < 1 || Val > 4) {
2126 Error(S, "immediate not in range (1..4)");
2127 return MatchOperand_ParseFail;
2131 MipsOperand::CreateImm(Expr, S, Parser.getTok().getLoc(), *this));
2132 return MatchOperand_Success;
2135 MCSymbolRefExpr::VariantKind MipsAsmParser::getVariantKind(StringRef Symbol) {
2137 MCSymbolRefExpr::VariantKind VK =
2138 StringSwitch<MCSymbolRefExpr::VariantKind>(Symbol)
2139 .Case("hi", MCSymbolRefExpr::VK_Mips_ABS_HI)
2140 .Case("lo", MCSymbolRefExpr::VK_Mips_ABS_LO)
2141 .Case("gp_rel", MCSymbolRefExpr::VK_Mips_GPREL)
2142 .Case("call16", MCSymbolRefExpr::VK_Mips_GOT_CALL)
2143 .Case("got", MCSymbolRefExpr::VK_Mips_GOT)
2144 .Case("tlsgd", MCSymbolRefExpr::VK_Mips_TLSGD)
2145 .Case("tlsldm", MCSymbolRefExpr::VK_Mips_TLSLDM)
2146 .Case("dtprel_hi", MCSymbolRefExpr::VK_Mips_DTPREL_HI)
2147 .Case("dtprel_lo", MCSymbolRefExpr::VK_Mips_DTPREL_LO)
2148 .Case("gottprel", MCSymbolRefExpr::VK_Mips_GOTTPREL)
2149 .Case("tprel_hi", MCSymbolRefExpr::VK_Mips_TPREL_HI)
2150 .Case("tprel_lo", MCSymbolRefExpr::VK_Mips_TPREL_LO)
2151 .Case("got_disp", MCSymbolRefExpr::VK_Mips_GOT_DISP)
2152 .Case("got_page", MCSymbolRefExpr::VK_Mips_GOT_PAGE)
2153 .Case("got_ofst", MCSymbolRefExpr::VK_Mips_GOT_OFST)
2154 .Case("hi(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_HI)
2155 .Case("lo(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_LO)
2156 .Case("got_hi", MCSymbolRefExpr::VK_Mips_GOT_HI16)
2157 .Case("got_lo", MCSymbolRefExpr::VK_Mips_GOT_LO16)
2158 .Case("call_hi", MCSymbolRefExpr::VK_Mips_CALL_HI16)
2159 .Case("call_lo", MCSymbolRefExpr::VK_Mips_CALL_LO16)
2160 .Case("higher", MCSymbolRefExpr::VK_Mips_HIGHER)
2161 .Case("highest", MCSymbolRefExpr::VK_Mips_HIGHEST)
2162 .Case("pcrel_hi", MCSymbolRefExpr::VK_Mips_PCREL_HI16)
2163 .Case("pcrel_lo", MCSymbolRefExpr::VK_Mips_PCREL_LO16)
2164 .Default(MCSymbolRefExpr::VK_None);
2166 assert(VK != MCSymbolRefExpr::VK_None);
2171 /// Sometimes (i.e. load/stores) the operand may be followed immediately by
2173 /// ::= '(', register, ')'
2174 /// handle it before we iterate so we don't get tripped up by the lack of
2176 bool MipsAsmParser::ParseParenSuffix(StringRef Name, OperandVector &Operands) {
2177 if (getLexer().is(AsmToken::LParen)) {
2179 MipsOperand::CreateToken("(", getLexer().getLoc(), *this));
2181 if (ParseOperand(Operands, Name)) {
2182 SMLoc Loc = getLexer().getLoc();
2183 Parser.eatToEndOfStatement();
2184 return Error(Loc, "unexpected token in argument list");
2186 if (Parser.getTok().isNot(AsmToken::RParen)) {
2187 SMLoc Loc = getLexer().getLoc();
2188 Parser.eatToEndOfStatement();
2189 return Error(Loc, "unexpected token, expected ')'");
2192 MipsOperand::CreateToken(")", getLexer().getLoc(), *this));
2198 /// Sometimes (i.e. in MSA) the operand may be followed immediately by
2199 /// either one of these.
2200 /// ::= '[', register, ']'
2201 /// ::= '[', integer, ']'
2202 /// handle it before we iterate so we don't get tripped up by the lack of
2204 bool MipsAsmParser::ParseBracketSuffix(StringRef Name,
2205 OperandVector &Operands) {
2206 if (getLexer().is(AsmToken::LBrac)) {
2208 MipsOperand::CreateToken("[", getLexer().getLoc(), *this));
2210 if (ParseOperand(Operands, Name)) {
2211 SMLoc Loc = getLexer().getLoc();
2212 Parser.eatToEndOfStatement();
2213 return Error(Loc, "unexpected token in argument list");
2215 if (Parser.getTok().isNot(AsmToken::RBrac)) {
2216 SMLoc Loc = getLexer().getLoc();
2217 Parser.eatToEndOfStatement();
2218 return Error(Loc, "unexpected token, expected ']'");
2221 MipsOperand::CreateToken("]", getLexer().getLoc(), *this));
2227 bool MipsAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
2228 SMLoc NameLoc, OperandVector &Operands) {
2229 DEBUG(dbgs() << "ParseInstruction\n");
2230 // Check if we have valid mnemonic
2231 if (!mnemonicIsValid(Name, 0)) {
2232 Parser.eatToEndOfStatement();
2233 return Error(NameLoc, "Unknown instruction");
2235 // First operand in MCInst is instruction mnemonic.
2236 Operands.push_back(MipsOperand::CreateToken(Name, NameLoc, *this));
2238 // Read the remaining operands.
2239 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2240 // Read the first operand.
2241 if (ParseOperand(Operands, Name)) {
2242 SMLoc Loc = getLexer().getLoc();
2243 Parser.eatToEndOfStatement();
2244 return Error(Loc, "unexpected token in argument list");
2246 if (getLexer().is(AsmToken::LBrac) && ParseBracketSuffix(Name, Operands))
2248 // AFAIK, parenthesis suffixes are never on the first operand
2250 while (getLexer().is(AsmToken::Comma)) {
2251 Parser.Lex(); // Eat the comma.
2252 // Parse and remember the operand.
2253 if (ParseOperand(Operands, Name)) {
2254 SMLoc Loc = getLexer().getLoc();
2255 Parser.eatToEndOfStatement();
2256 return Error(Loc, "unexpected token in argument list");
2258 // Parse bracket and parenthesis suffixes before we iterate
2259 if (getLexer().is(AsmToken::LBrac)) {
2260 if (ParseBracketSuffix(Name, Operands))
2262 } else if (getLexer().is(AsmToken::LParen) &&
2263 ParseParenSuffix(Name, Operands))
2267 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2268 SMLoc Loc = getLexer().getLoc();
2269 Parser.eatToEndOfStatement();
2270 return Error(Loc, "unexpected token in argument list");
2272 Parser.Lex(); // Consume the EndOfStatement.
2276 bool MipsAsmParser::reportParseError(StringRef ErrorMsg) {
2277 SMLoc Loc = getLexer().getLoc();
2278 Parser.eatToEndOfStatement();
2279 return Error(Loc, ErrorMsg);
2282 bool MipsAsmParser::reportParseError(SMLoc Loc, StringRef ErrorMsg) {
2283 return Error(Loc, ErrorMsg);
2286 bool MipsAsmParser::parseSetNoAtDirective() {
2287 // Line should look like: ".set noat".
2289 Options.setATReg(0);
2292 // If this is not the end of the statement, report an error.
2293 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2294 reportParseError("unexpected token in statement");
2297 Parser.Lex(); // Consume the EndOfStatement.
2301 bool MipsAsmParser::parseSetAtDirective() {
2302 // Line can be .set at - defaults to $1
2306 if (getLexer().is(AsmToken::EndOfStatement)) {
2307 Options.setATReg(1);
2308 Parser.Lex(); // Consume the EndOfStatement.
2310 } else if (getLexer().is(AsmToken::Equal)) {
2311 getParser().Lex(); // Eat the '='.
2312 if (getLexer().isNot(AsmToken::Dollar)) {
2313 reportParseError("unexpected token in statement");
2316 Parser.Lex(); // Eat the '$'.
2317 const AsmToken &Reg = Parser.getTok();
2318 if (Reg.is(AsmToken::Identifier)) {
2319 AtRegNo = matchCPURegisterName(Reg.getIdentifier());
2320 } else if (Reg.is(AsmToken::Integer)) {
2321 AtRegNo = Reg.getIntVal();
2323 reportParseError("unexpected token in statement");
2327 if (AtRegNo < 0 || AtRegNo > 31) {
2328 reportParseError("unexpected token in statement");
2332 if (!Options.setATReg(AtRegNo)) {
2333 reportParseError("unexpected token in statement");
2336 getParser().Lex(); // Eat the register.
2338 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2339 reportParseError("unexpected token in statement");
2342 Parser.Lex(); // Consume the EndOfStatement.
2345 reportParseError("unexpected token in statement");
2350 bool MipsAsmParser::parseSetReorderDirective() {
2352 // If this is not the end of the statement, report an error.
2353 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2354 reportParseError("unexpected token in statement");
2357 Options.setReorder();
2358 getTargetStreamer().emitDirectiveSetReorder();
2359 Parser.Lex(); // Consume the EndOfStatement.
2363 bool MipsAsmParser::parseSetNoReorderDirective() {
2365 // If this is not the end of the statement, report an error.
2366 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2367 reportParseError("unexpected token in statement");
2370 Options.setNoreorder();
2371 getTargetStreamer().emitDirectiveSetNoReorder();
2372 Parser.Lex(); // Consume the EndOfStatement.
2376 bool MipsAsmParser::parseSetMacroDirective() {
2378 // If this is not the end of the statement, report an error.
2379 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2380 reportParseError("unexpected token in statement");
2384 Parser.Lex(); // Consume the EndOfStatement.
2388 bool MipsAsmParser::parseSetNoMacroDirective() {
2390 // If this is not the end of the statement, report an error.
2391 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2392 reportParseError("`noreorder' must be set before `nomacro'");
2395 if (Options.isReorder()) {
2396 reportParseError("`noreorder' must be set before `nomacro'");
2399 Options.setNomacro();
2400 Parser.Lex(); // Consume the EndOfStatement.
2404 bool MipsAsmParser::parseSetNoMips16Directive() {
2406 // If this is not the end of the statement, report an error.
2407 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2408 reportParseError("unexpected token in statement");
2411 // For now do nothing.
2412 Parser.Lex(); // Consume the EndOfStatement.
2416 bool MipsAsmParser::parseSetAssignment() {
2418 const MCExpr *Value;
2420 if (Parser.parseIdentifier(Name))
2421 reportParseError("expected identifier after .set");
2423 if (getLexer().isNot(AsmToken::Comma))
2424 return reportParseError("unexpected token in .set directive");
2427 if (Parser.parseExpression(Value))
2428 return reportParseError("expected valid expression after comma");
2430 // Check if the Name already exists as a symbol.
2431 MCSymbol *Sym = getContext().LookupSymbol(Name);
2433 return reportParseError("symbol already defined");
2434 Sym = getContext().GetOrCreateSymbol(Name);
2435 Sym->setVariableValue(Value);
2440 bool MipsAsmParser::parseSetFeature(uint64_t Feature) {
2442 if (getLexer().isNot(AsmToken::EndOfStatement))
2443 return reportParseError("unexpected token in .set directive");
2447 llvm_unreachable("Unimplemented feature");
2448 case Mips::FeatureDSP:
2449 setFeatureBits(Mips::FeatureDSP, "dsp");
2450 getTargetStreamer().emitDirectiveSetDsp();
2452 case Mips::FeatureMicroMips:
2453 getTargetStreamer().emitDirectiveSetMicroMips();
2455 case Mips::FeatureMips16:
2456 getTargetStreamer().emitDirectiveSetMips16();
2458 case Mips::FeatureMips32r2:
2459 setFeatureBits(Mips::FeatureMips32r2, "mips32r2");
2460 getTargetStreamer().emitDirectiveSetMips32R2();
2462 case Mips::FeatureMips64:
2463 setFeatureBits(Mips::FeatureMips64, "mips64");
2464 getTargetStreamer().emitDirectiveSetMips64();
2466 case Mips::FeatureMips64r2:
2467 setFeatureBits(Mips::FeatureMips64r2, "mips64r2");
2468 getTargetStreamer().emitDirectiveSetMips64R2();
2474 bool MipsAsmParser::eatComma(StringRef ErrorStr) {
2475 if (getLexer().isNot(AsmToken::Comma)) {
2476 SMLoc Loc = getLexer().getLoc();
2477 Parser.eatToEndOfStatement();
2478 return Error(Loc, ErrorStr);
2481 Parser.Lex(); // Eat the comma.
2485 bool MipsAsmParser::parseDirectiveCPLoad(SMLoc Loc) {
2486 if (Options.isReorder())
2487 Warning(Loc, ".cpload in reorder section");
2489 // FIXME: Warn if cpload is used in Mips16 mode.
2491 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Reg;
2492 OperandMatchResultTy ResTy = ParseAnyRegister(Reg);
2493 if (ResTy == MatchOperand_NoMatch || ResTy == MatchOperand_ParseFail) {
2494 reportParseError("expected register containing function address");
2498 MipsOperand &RegOpnd = static_cast<MipsOperand &>(*Reg[0]);
2499 if (!RegOpnd.isGPRAsmReg()) {
2500 reportParseError(RegOpnd.getStartLoc(), "invalid register");
2504 getTargetStreamer().emitDirectiveCpload(RegOpnd.getGPR32Reg());
2508 bool MipsAsmParser::parseDirectiveCPSetup() {
2511 bool SaveIsReg = true;
2513 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> TmpReg;
2514 OperandMatchResultTy ResTy = ParseAnyRegister(TmpReg);
2515 if (ResTy == MatchOperand_NoMatch) {
2516 reportParseError("expected register containing function address");
2517 Parser.eatToEndOfStatement();
2521 MipsOperand &FuncRegOpnd = static_cast<MipsOperand &>(*TmpReg[0]);
2522 if (!FuncRegOpnd.isGPRAsmReg()) {
2523 reportParseError(FuncRegOpnd.getStartLoc(), "invalid register");
2524 Parser.eatToEndOfStatement();
2528 FuncReg = FuncRegOpnd.getGPR32Reg();
2531 if (!eatComma("expected comma parsing directive"))
2534 ResTy = ParseAnyRegister(TmpReg);
2535 if (ResTy == MatchOperand_NoMatch) {
2536 const AsmToken &Tok = Parser.getTok();
2537 if (Tok.is(AsmToken::Integer)) {
2538 Save = Tok.getIntVal();
2542 reportParseError("expected save register or stack offset");
2543 Parser.eatToEndOfStatement();
2547 MipsOperand &SaveOpnd = static_cast<MipsOperand &>(*TmpReg[0]);
2548 if (!SaveOpnd.isGPRAsmReg()) {
2549 reportParseError(SaveOpnd.getStartLoc(), "invalid register");
2550 Parser.eatToEndOfStatement();
2553 Save = SaveOpnd.getGPR32Reg();
2556 if (!eatComma("expected comma parsing directive"))
2560 if (Parser.parseIdentifier(Name))
2561 reportParseError("expected identifier");
2562 MCSymbol *Sym = getContext().GetOrCreateSymbol(Name);
2564 getTargetStreamer().emitDirectiveCpsetup(FuncReg, Save, *Sym, SaveIsReg);
2568 bool MipsAsmParser::parseDirectiveNaN() {
2569 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2570 const AsmToken &Tok = Parser.getTok();
2572 if (Tok.getString() == "2008") {
2574 getTargetStreamer().emitDirectiveNaN2008();
2576 } else if (Tok.getString() == "legacy") {
2578 getTargetStreamer().emitDirectiveNaNLegacy();
2582 // If we don't recognize the option passed to the .nan
2583 // directive (e.g. no option or unknown option), emit an error.
2584 reportParseError("invalid option in .nan directive");
2588 bool MipsAsmParser::parseDirectiveSet() {
2590 // Get the next token.
2591 const AsmToken &Tok = Parser.getTok();
2593 if (Tok.getString() == "noat") {
2594 return parseSetNoAtDirective();
2595 } else if (Tok.getString() == "at") {
2596 return parseSetAtDirective();
2597 } else if (Tok.getString() == "reorder") {
2598 return parseSetReorderDirective();
2599 } else if (Tok.getString() == "noreorder") {
2600 return parseSetNoReorderDirective();
2601 } else if (Tok.getString() == "macro") {
2602 return parseSetMacroDirective();
2603 } else if (Tok.getString() == "nomacro") {
2604 return parseSetNoMacroDirective();
2605 } else if (Tok.getString() == "mips16") {
2606 return parseSetFeature(Mips::FeatureMips16);
2607 } else if (Tok.getString() == "nomips16") {
2608 return parseSetNoMips16Directive();
2609 } else if (Tok.getString() == "nomicromips") {
2610 getTargetStreamer().emitDirectiveSetNoMicroMips();
2611 Parser.eatToEndOfStatement();
2613 } else if (Tok.getString() == "micromips") {
2614 return parseSetFeature(Mips::FeatureMicroMips);
2615 } else if (Tok.getString() == "mips32r2") {
2616 return parseSetFeature(Mips::FeatureMips32r2);
2617 } else if (Tok.getString() == "mips64") {
2618 return parseSetFeature(Mips::FeatureMips64);
2619 } else if (Tok.getString() == "mips64r2") {
2620 return parseSetFeature(Mips::FeatureMips64r2);
2621 } else if (Tok.getString() == "dsp") {
2622 return parseSetFeature(Mips::FeatureDSP);
2624 // It is just an identifier, look for an assignment.
2625 parseSetAssignment();
2632 /// parseDataDirective
2633 /// ::= .word [ expression (, expression)* ]
2634 bool MipsAsmParser::parseDataDirective(unsigned Size, SMLoc L) {
2635 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2637 const MCExpr *Value;
2638 if (getParser().parseExpression(Value))
2641 getParser().getStreamer().EmitValue(Value, Size);
2643 if (getLexer().is(AsmToken::EndOfStatement))
2646 // FIXME: Improve diagnostic.
2647 if (getLexer().isNot(AsmToken::Comma))
2648 return Error(L, "unexpected token in directive");
2657 /// parseDirectiveGpWord
2658 /// ::= .gpword local_sym
2659 bool MipsAsmParser::parseDirectiveGpWord() {
2660 const MCExpr *Value;
2661 // EmitGPRel32Value requires an expression, so we are using base class
2662 // method to evaluate the expression.
2663 if (getParser().parseExpression(Value))
2665 getParser().getStreamer().EmitGPRel32Value(Value);
2667 if (getLexer().isNot(AsmToken::EndOfStatement))
2668 return Error(getLexer().getLoc(), "unexpected token in directive");
2669 Parser.Lex(); // Eat EndOfStatement token.
2673 /// parseDirectiveGpDWord
2674 /// ::= .gpdword local_sym
2675 bool MipsAsmParser::parseDirectiveGpDWord() {
2676 const MCExpr *Value;
2677 // EmitGPRel64Value requires an expression, so we are using base class
2678 // method to evaluate the expression.
2679 if (getParser().parseExpression(Value))
2681 getParser().getStreamer().EmitGPRel64Value(Value);
2683 if (getLexer().isNot(AsmToken::EndOfStatement))
2684 return Error(getLexer().getLoc(), "unexpected token in directive");
2685 Parser.Lex(); // Eat EndOfStatement token.
2689 bool MipsAsmParser::parseDirectiveOption() {
2690 // Get the option token.
2691 AsmToken Tok = Parser.getTok();
2692 // At the moment only identifiers are supported.
2693 if (Tok.isNot(AsmToken::Identifier)) {
2694 Error(Parser.getTok().getLoc(), "unexpected token in .option directive");
2695 Parser.eatToEndOfStatement();
2699 StringRef Option = Tok.getIdentifier();
2701 if (Option == "pic0") {
2702 getTargetStreamer().emitDirectiveOptionPic0();
2704 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
2705 Error(Parser.getTok().getLoc(),
2706 "unexpected token in .option pic0 directive");
2707 Parser.eatToEndOfStatement();
2712 if (Option == "pic2") {
2713 getTargetStreamer().emitDirectiveOptionPic2();
2715 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
2716 Error(Parser.getTok().getLoc(),
2717 "unexpected token in .option pic2 directive");
2718 Parser.eatToEndOfStatement();
2724 Warning(Parser.getTok().getLoc(), "unknown option in .option directive");
2725 Parser.eatToEndOfStatement();
2729 bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) {
2730 StringRef IDVal = DirectiveID.getString();
2732 if (IDVal == ".cpload")
2733 return parseDirectiveCPLoad(DirectiveID.getLoc());
2734 if (IDVal == ".dword") {
2735 parseDataDirective(8, DirectiveID.getLoc());
2739 if (IDVal == ".ent") {
2740 // Ignore this directive for now.
2745 if (IDVal == ".end") {
2746 // Ignore this directive for now.
2751 if (IDVal == ".frame") {
2752 // Ignore this directive for now.
2753 Parser.eatToEndOfStatement();
2757 if (IDVal == ".set") {
2758 return parseDirectiveSet();
2761 if (IDVal == ".fmask") {
2762 // Ignore this directive for now.
2763 Parser.eatToEndOfStatement();
2767 if (IDVal == ".mask") {
2768 // Ignore this directive for now.
2769 Parser.eatToEndOfStatement();
2773 if (IDVal == ".nan")
2774 return parseDirectiveNaN();
2776 if (IDVal == ".gpword") {
2777 parseDirectiveGpWord();
2781 if (IDVal == ".gpdword") {
2782 parseDirectiveGpDWord();
2786 if (IDVal == ".word") {
2787 parseDataDirective(4, DirectiveID.getLoc());
2791 if (IDVal == ".option")
2792 return parseDirectiveOption();
2794 if (IDVal == ".abicalls") {
2795 getTargetStreamer().emitDirectiveAbiCalls();
2796 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
2797 Error(Parser.getTok().getLoc(), "unexpected token in directive");
2799 Parser.eatToEndOfStatement();
2804 if (IDVal == ".cpsetup")
2805 return parseDirectiveCPSetup();
2810 extern "C" void LLVMInitializeMipsAsmParser() {
2811 RegisterMCAsmParser<MipsAsmParser> X(TheMipsTarget);
2812 RegisterMCAsmParser<MipsAsmParser> Y(TheMipselTarget);
2813 RegisterMCAsmParser<MipsAsmParser> A(TheMips64Target);
2814 RegisterMCAsmParser<MipsAsmParser> B(TheMips64elTarget);
2817 #define GET_REGISTER_MATCHER
2818 #define GET_MATCHER_IMPLEMENTATION
2819 #include "MipsGenAsmMatcher.inc"