1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/MipsMCExpr.h"
11 #include "MCTargetDesc/MipsMCTargetDesc.h"
12 #include "MipsRegisterInfo.h"
13 #include "MipsTargetStreamer.h"
14 #include "llvm/ADT/APInt.h"
15 #include "llvm/ADT/StringSwitch.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstBuilder.h"
20 #include "llvm/MC/MCParser/MCAsmLexer.h"
21 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
22 #include "llvm/MC/MCStreamer.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCSymbol.h"
25 #include "llvm/MC/MCTargetAsmParser.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Support/TargetRegistry.h"
32 #define DEBUG_TYPE "mips-asm-parser"
39 class MipsAssemblerOptions {
41 MipsAssemblerOptions() : aTReg(1), reorder(true), macro(true) {}
43 unsigned getATRegNum() { return aTReg; }
44 bool setATReg(unsigned Reg);
46 bool isReorder() { return reorder; }
47 void setReorder() { reorder = true; }
48 void setNoreorder() { reorder = false; }
50 bool isMacro() { return macro; }
51 void setMacro() { macro = true; }
52 void setNomacro() { macro = false; }
62 class MipsAsmParser : public MCTargetAsmParser {
63 MipsTargetStreamer &getTargetStreamer() {
64 MCTargetStreamer &TS = *Parser.getStreamer().getTargetStreamer();
65 return static_cast<MipsTargetStreamer &>(TS);
70 MipsAssemblerOptions Options;
72 #define GET_ASSEMBLER_HEADER
73 #include "MipsGenAsmMatcher.inc"
75 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
77 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
78 OperandVector &Operands, MCStreamer &Out,
80 bool MatchingInlineAsm) override;
82 /// Parse a register as used in CFI directives
83 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
85 bool ParseParenSuffix(StringRef Name, OperandVector &Operands);
87 bool ParseBracketSuffix(StringRef Name, OperandVector &Operands);
89 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
90 SMLoc NameLoc, OperandVector &Operands) override;
92 bool ParseDirective(AsmToken DirectiveID) override;
94 MipsAsmParser::OperandMatchResultTy parseMemOperand(OperandVector &Operands);
96 MipsAsmParser::OperandMatchResultTy
97 MatchAnyRegisterNameWithoutDollar(OperandVector &Operands,
98 StringRef Identifier, SMLoc S);
100 MipsAsmParser::OperandMatchResultTy
101 MatchAnyRegisterWithoutDollar(OperandVector &Operands, SMLoc S);
103 MipsAsmParser::OperandMatchResultTy ParseAnyRegister(OperandVector &Operands);
105 MipsAsmParser::OperandMatchResultTy ParseImm(OperandVector &Operands);
107 MipsAsmParser::OperandMatchResultTy ParseJumpTarget(OperandVector &Operands);
109 MipsAsmParser::OperandMatchResultTy parseInvNum(OperandVector &Operands);
111 MipsAsmParser::OperandMatchResultTy ParseLSAImm(OperandVector &Operands);
113 bool searchSymbolAlias(OperandVector &Operands);
115 bool ParseOperand(OperandVector &, StringRef Mnemonic);
117 bool needsExpansion(MCInst &Inst);
119 void expandInstruction(MCInst &Inst, SMLoc IDLoc,
120 SmallVectorImpl<MCInst> &Instructions);
121 void expandLoadImm(MCInst &Inst, SMLoc IDLoc,
122 SmallVectorImpl<MCInst> &Instructions);
123 void expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
124 SmallVectorImpl<MCInst> &Instructions);
125 void expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
126 SmallVectorImpl<MCInst> &Instructions);
127 void expandMemInst(MCInst &Inst, SMLoc IDLoc,
128 SmallVectorImpl<MCInst> &Instructions, bool isLoad,
130 bool reportParseError(StringRef ErrorMsg);
131 bool reportParseError(SMLoc Loc, StringRef ErrorMsg);
133 bool parseMemOffset(const MCExpr *&Res, bool isParenExpr);
134 bool parseRelocOperand(const MCExpr *&Res);
136 const MCExpr *evaluateRelocExpr(const MCExpr *Expr, StringRef RelocStr);
138 bool isEvaluated(const MCExpr *Expr);
139 bool parseSetFeature(uint64_t Feature);
140 bool parseDirectiveCPLoad(SMLoc Loc);
141 bool parseDirectiveCPSetup();
142 bool parseDirectiveNaN();
143 bool parseDirectiveSet();
144 bool parseDirectiveOption();
146 bool parseSetAtDirective();
147 bool parseSetNoAtDirective();
148 bool parseSetMacroDirective();
149 bool parseSetNoMacroDirective();
150 bool parseSetReorderDirective();
151 bool parseSetNoReorderDirective();
152 bool parseSetNoMips16Directive();
154 bool parseSetAssignment();
156 bool parseDataDirective(unsigned Size, SMLoc L);
157 bool parseDirectiveGpWord();
158 bool parseDirectiveGpDWord();
160 MCSymbolRefExpr::VariantKind getVariantKind(StringRef Symbol);
162 bool isGP64() const {
163 return (STI.getFeatureBits() & Mips::FeatureGP64Bit) != 0;
166 bool isFP64() const {
167 return (STI.getFeatureBits() & Mips::FeatureFP64Bit) != 0;
170 bool isN32() const { return STI.getFeatureBits() & Mips::FeatureN32; }
171 bool isN64() const { return STI.getFeatureBits() & Mips::FeatureN64; }
173 bool isMicroMips() const {
174 return STI.getFeatureBits() & Mips::FeatureMicroMips;
177 bool hasMips4() const { return STI.getFeatureBits() & Mips::FeatureMips4; }
178 bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; }
179 bool hasMips32r6() const {
180 return STI.getFeatureBits() & Mips::FeatureMips32r6;
182 bool hasMips64r6() const {
183 return STI.getFeatureBits() & Mips::FeatureMips64r6;
186 bool eatComma(StringRef ErrorStr);
188 int matchCPURegisterName(StringRef Symbol);
190 int matchRegisterByNumber(unsigned RegNum, unsigned RegClass);
192 int matchFPURegisterName(StringRef Name);
194 int matchFCCRegisterName(StringRef Name);
196 int matchACRegisterName(StringRef Name);
198 int matchMSA128RegisterName(StringRef Name);
200 int matchMSA128CtrlRegisterName(StringRef Name);
202 unsigned getReg(int RC, int RegNo);
204 unsigned getGPR(int RegNo);
208 bool processInstruction(MCInst &Inst, SMLoc IDLoc,
209 SmallVectorImpl<MCInst> &Instructions);
211 // Helper function that checks if the value of a vector index is within the
212 // boundaries of accepted values for each RegisterKind
213 // Example: INSERT.B $w0[n], $1 => 16 > n >= 0
214 bool validateMSAIndex(int Val, int RegKind);
216 void setFeatureBits(unsigned Feature, StringRef FeatureString) {
217 if (!(STI.getFeatureBits() & Feature)) {
218 setAvailableFeatures(
219 ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
223 void clearFeatureBits(unsigned Feature, StringRef FeatureString) {
224 if (STI.getFeatureBits() & Feature) {
225 setAvailableFeatures(
226 ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
231 enum MipsMatchResultTy {
232 Match_RequiresDifferentSrcAndDst = FIRST_TARGET_MATCH_RESULT_TY
233 #define GET_OPERAND_DIAGNOSTIC_TYPES
234 #include "MipsGenAsmMatcher.inc"
235 #undef GET_OPERAND_DIAGNOSTIC_TYPES
239 MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
240 const MCInstrInfo &MII,
241 const MCTargetOptions &Options)
242 : MCTargetAsmParser(), STI(sti), Parser(parser) {
243 // Initialize the set of available features.
244 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
246 // Assert exactly one ABI was chosen.
247 assert((((STI.getFeatureBits() & Mips::FeatureO32) != 0) +
248 ((STI.getFeatureBits() & Mips::FeatureEABI) != 0) +
249 ((STI.getFeatureBits() & Mips::FeatureN32) != 0) +
250 ((STI.getFeatureBits() & Mips::FeatureN64) != 0)) == 1);
253 MCAsmParser &getParser() const { return Parser; }
254 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
256 /// True if all of $fcc0 - $fcc7 exist for the current ISA.
257 bool hasEightFccRegisters() const { return hasMips4() || hasMips32(); }
259 /// Warn if RegNo is the current assembler temporary.
260 void WarnIfAssemblerTemporary(int RegNo, SMLoc Loc);
266 /// MipsOperand - Instances of this class represent a parsed Mips machine
268 class MipsOperand : public MCParsedAsmOperand {
270 /// Broad categories of register classes
271 /// The exact class is finalized by the render method.
273 RegKind_GPR = 1, /// GPR32 and GPR64 (depending on isGP64())
274 RegKind_FGR = 2, /// FGR32, FGR64, AFGR64 (depending on context and
276 RegKind_FCC = 4, /// FCC
277 RegKind_MSA128 = 8, /// MSA128[BHWD] (makes no difference which)
278 RegKind_MSACtrl = 16, /// MSA control registers
279 RegKind_COP2 = 32, /// COP2
280 RegKind_ACC = 64, /// HI32DSP, LO32DSP, and ACC64DSP (depending on
282 RegKind_CCR = 128, /// CCR
283 RegKind_HWRegs = 256, /// HWRegs
284 RegKind_COP3 = 512, /// COP3
286 /// Potentially any (e.g. $1)
287 RegKind_Numeric = RegKind_GPR | RegKind_FGR | RegKind_FCC | RegKind_MSA128 |
288 RegKind_MSACtrl | RegKind_COP2 | RegKind_ACC |
289 RegKind_CCR | RegKind_HWRegs | RegKind_COP3
294 k_Immediate, /// An immediate (possibly involving symbol references)
295 k_Memory, /// Base + Offset Memory Address
296 k_PhysRegister, /// A physical register from the Mips namespace
297 k_RegisterIndex, /// A register index in one or more RegKind.
298 k_Token /// A simple token
302 MipsOperand(KindTy K, MipsAsmParser &Parser)
303 : MCParsedAsmOperand(), Kind(K), AsmParser(Parser) {}
306 /// For diagnostics, and checking the assembler temporary
307 MipsAsmParser &AsmParser;
315 unsigned Num; /// Register Number
319 unsigned Index; /// Index into the register class
320 RegKind Kind; /// Bitfield of the kinds it could possibly be
321 const MCRegisterInfo *RegInfo;
335 struct PhysRegOp PhysReg;
336 struct RegIdxOp RegIdx;
341 SMLoc StartLoc, EndLoc;
343 /// Internal constructor for register kinds
344 static std::unique_ptr<MipsOperand> CreateReg(unsigned Index, RegKind RegKind,
345 const MCRegisterInfo *RegInfo,
347 MipsAsmParser &Parser) {
348 auto Op = make_unique<MipsOperand>(k_RegisterIndex, Parser);
349 Op->RegIdx.Index = Index;
350 Op->RegIdx.RegInfo = RegInfo;
351 Op->RegIdx.Kind = RegKind;
358 /// Coerce the register to GPR32 and return the real register for the current
360 unsigned getGPR32Reg() const {
361 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
362 AsmParser.WarnIfAssemblerTemporary(RegIdx.Index, StartLoc);
363 unsigned ClassID = Mips::GPR32RegClassID;
364 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
367 /// Coerce the register to GPR64 and return the real register for the current
369 unsigned getGPR64Reg() const {
370 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
371 unsigned ClassID = Mips::GPR64RegClassID;
372 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
376 /// Coerce the register to AFGR64 and return the real register for the current
378 unsigned getAFGR64Reg() const {
379 assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
380 if (RegIdx.Index % 2 != 0)
381 AsmParser.Warning(StartLoc, "Float register should be even.");
382 return RegIdx.RegInfo->getRegClass(Mips::AFGR64RegClassID)
383 .getRegister(RegIdx.Index / 2);
386 /// Coerce the register to FGR64 and return the real register for the current
388 unsigned getFGR64Reg() const {
389 assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
390 return RegIdx.RegInfo->getRegClass(Mips::FGR64RegClassID)
391 .getRegister(RegIdx.Index);
394 /// Coerce the register to FGR32 and return the real register for the current
396 unsigned getFGR32Reg() const {
397 assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
398 return RegIdx.RegInfo->getRegClass(Mips::FGR32RegClassID)
399 .getRegister(RegIdx.Index);
402 /// Coerce the register to FGRH32 and return the real register for the current
404 unsigned getFGRH32Reg() const {
405 assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
406 return RegIdx.RegInfo->getRegClass(Mips::FGRH32RegClassID)
407 .getRegister(RegIdx.Index);
410 /// Coerce the register to FCC and return the real register for the current
412 unsigned getFCCReg() const {
413 assert(isRegIdx() && (RegIdx.Kind & RegKind_FCC) && "Invalid access!");
414 return RegIdx.RegInfo->getRegClass(Mips::FCCRegClassID)
415 .getRegister(RegIdx.Index);
418 /// Coerce the register to MSA128 and return the real register for the current
420 unsigned getMSA128Reg() const {
421 assert(isRegIdx() && (RegIdx.Kind & RegKind_MSA128) && "Invalid access!");
422 // It doesn't matter which of the MSA128[BHWD] classes we use. They are all
424 unsigned ClassID = Mips::MSA128BRegClassID;
425 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
428 /// Coerce the register to MSACtrl and return the real register for the
430 unsigned getMSACtrlReg() const {
431 assert(isRegIdx() && (RegIdx.Kind & RegKind_MSACtrl) && "Invalid access!");
432 unsigned ClassID = Mips::MSACtrlRegClassID;
433 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
436 /// Coerce the register to COP2 and return the real register for the
438 unsigned getCOP2Reg() const {
439 assert(isRegIdx() && (RegIdx.Kind & RegKind_COP2) && "Invalid access!");
440 unsigned ClassID = Mips::COP2RegClassID;
441 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
444 /// Coerce the register to COP3 and return the real register for the
446 unsigned getCOP3Reg() const {
447 assert(isRegIdx() && (RegIdx.Kind & RegKind_COP3) && "Invalid access!");
448 unsigned ClassID = Mips::COP3RegClassID;
449 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
452 /// Coerce the register to ACC64DSP and return the real register for the
454 unsigned getACC64DSPReg() const {
455 assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");
456 unsigned ClassID = Mips::ACC64DSPRegClassID;
457 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
460 /// Coerce the register to HI32DSP and return the real register for the
462 unsigned getHI32DSPReg() const {
463 assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");
464 unsigned ClassID = Mips::HI32DSPRegClassID;
465 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
468 /// Coerce the register to LO32DSP and return the real register for the
470 unsigned getLO32DSPReg() const {
471 assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");
472 unsigned ClassID = Mips::LO32DSPRegClassID;
473 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
476 /// Coerce the register to CCR and return the real register for the
478 unsigned getCCRReg() const {
479 assert(isRegIdx() && (RegIdx.Kind & RegKind_CCR) && "Invalid access!");
480 unsigned ClassID = Mips::CCRRegClassID;
481 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
484 /// Coerce the register to HWRegs and return the real register for the
486 unsigned getHWRegsReg() const {
487 assert(isRegIdx() && (RegIdx.Kind & RegKind_HWRegs) && "Invalid access!");
488 unsigned ClassID = Mips::HWRegsRegClassID;
489 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
493 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
494 // Add as immediate when possible. Null MCExpr = 0.
496 Inst.addOperand(MCOperand::CreateImm(0));
497 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
498 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
500 Inst.addOperand(MCOperand::CreateExpr(Expr));
503 void addRegOperands(MCInst &Inst, unsigned N) const {
504 llvm_unreachable("Use a custom parser instead");
507 /// Render the operand to an MCInst as a GPR32
508 /// Asserts if the wrong number of operands are requested, or the operand
509 /// is not a k_RegisterIndex compatible with RegKind_GPR
510 void addGPR32AsmRegOperands(MCInst &Inst, unsigned N) const {
511 assert(N == 1 && "Invalid number of operands!");
512 Inst.addOperand(MCOperand::CreateReg(getGPR32Reg()));
515 /// Render the operand to an MCInst as a GPR64
516 /// Asserts if the wrong number of operands are requested, or the operand
517 /// is not a k_RegisterIndex compatible with RegKind_GPR
518 void addGPR64AsmRegOperands(MCInst &Inst, unsigned N) const {
519 assert(N == 1 && "Invalid number of operands!");
520 Inst.addOperand(MCOperand::CreateReg(getGPR64Reg()));
523 void addAFGR64AsmRegOperands(MCInst &Inst, unsigned N) const {
524 assert(N == 1 && "Invalid number of operands!");
525 Inst.addOperand(MCOperand::CreateReg(getAFGR64Reg()));
528 void addFGR64AsmRegOperands(MCInst &Inst, unsigned N) const {
529 assert(N == 1 && "Invalid number of operands!");
530 Inst.addOperand(MCOperand::CreateReg(getFGR64Reg()));
533 void addFGR32AsmRegOperands(MCInst &Inst, unsigned N) const {
534 assert(N == 1 && "Invalid number of operands!");
535 Inst.addOperand(MCOperand::CreateReg(getFGR32Reg()));
538 void addFGRH32AsmRegOperands(MCInst &Inst, unsigned N) const {
539 assert(N == 1 && "Invalid number of operands!");
540 Inst.addOperand(MCOperand::CreateReg(getFGRH32Reg()));
543 void addFCCAsmRegOperands(MCInst &Inst, unsigned N) const {
544 assert(N == 1 && "Invalid number of operands!");
545 Inst.addOperand(MCOperand::CreateReg(getFCCReg()));
548 void addMSA128AsmRegOperands(MCInst &Inst, unsigned N) const {
549 assert(N == 1 && "Invalid number of operands!");
550 Inst.addOperand(MCOperand::CreateReg(getMSA128Reg()));
553 void addMSACtrlAsmRegOperands(MCInst &Inst, unsigned N) const {
554 assert(N == 1 && "Invalid number of operands!");
555 Inst.addOperand(MCOperand::CreateReg(getMSACtrlReg()));
558 void addCOP2AsmRegOperands(MCInst &Inst, unsigned N) const {
559 assert(N == 1 && "Invalid number of operands!");
560 Inst.addOperand(MCOperand::CreateReg(getCOP2Reg()));
563 void addCOP3AsmRegOperands(MCInst &Inst, unsigned N) const {
564 assert(N == 1 && "Invalid number of operands!");
565 Inst.addOperand(MCOperand::CreateReg(getCOP3Reg()));
568 void addACC64DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
569 assert(N == 1 && "Invalid number of operands!");
570 Inst.addOperand(MCOperand::CreateReg(getACC64DSPReg()));
573 void addHI32DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
574 assert(N == 1 && "Invalid number of operands!");
575 Inst.addOperand(MCOperand::CreateReg(getHI32DSPReg()));
578 void addLO32DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
579 assert(N == 1 && "Invalid number of operands!");
580 Inst.addOperand(MCOperand::CreateReg(getLO32DSPReg()));
583 void addCCRAsmRegOperands(MCInst &Inst, unsigned N) const {
584 assert(N == 1 && "Invalid number of operands!");
585 Inst.addOperand(MCOperand::CreateReg(getCCRReg()));
588 void addHWRegsAsmRegOperands(MCInst &Inst, unsigned N) const {
589 assert(N == 1 && "Invalid number of operands!");
590 Inst.addOperand(MCOperand::CreateReg(getHWRegsReg()));
593 void addImmOperands(MCInst &Inst, unsigned N) const {
594 assert(N == 1 && "Invalid number of operands!");
595 const MCExpr *Expr = getImm();
599 void addMemOperands(MCInst &Inst, unsigned N) const {
600 assert(N == 2 && "Invalid number of operands!");
602 Inst.addOperand(MCOperand::CreateReg(getMemBase()->getGPR32Reg()));
604 const MCExpr *Expr = getMemOff();
608 bool isReg() const override {
609 // As a special case until we sort out the definition of div/divu, pretend
610 // that $0/$zero are k_PhysRegister so that MCK_ZERO works correctly.
611 if (isGPRAsmReg() && RegIdx.Index == 0)
614 return Kind == k_PhysRegister;
616 bool isRegIdx() const { return Kind == k_RegisterIndex; }
617 bool isImm() const override { return Kind == k_Immediate; }
618 bool isConstantImm() const {
619 return isImm() && dyn_cast<MCConstantExpr>(getImm());
621 bool isToken() const override {
622 // Note: It's not possible to pretend that other operand kinds are tokens.
623 // The matcher emitter checks tokens first.
624 return Kind == k_Token;
626 bool isMem() const override { return Kind == k_Memory; }
627 bool isConstantMemOff() const {
628 return isMem() && dyn_cast<MCConstantExpr>(getMemOff());
630 template <unsigned Bits> bool isMemWithSimmOffset() const {
631 return isMem() && isConstantMemOff() && isInt<Bits>(getConstantMemOff());
633 bool isInvNum() const { return Kind == k_Immediate; }
634 bool isLSAImm() const {
635 if (!isConstantImm())
637 int64_t Val = getConstantImm();
638 return 1 <= Val && Val <= 4;
641 StringRef getToken() const {
642 assert(Kind == k_Token && "Invalid access!");
643 return StringRef(Tok.Data, Tok.Length);
646 unsigned getReg() const override {
647 // As a special case until we sort out the definition of div/divu, pretend
648 // that $0/$zero are k_PhysRegister so that MCK_ZERO works correctly.
649 if (Kind == k_RegisterIndex && RegIdx.Index == 0 &&
650 RegIdx.Kind & RegKind_GPR)
651 return getGPR32Reg(); // FIXME: GPR64 too
653 assert(Kind == k_PhysRegister && "Invalid access!");
657 const MCExpr *getImm() const {
658 assert((Kind == k_Immediate) && "Invalid access!");
662 int64_t getConstantImm() const {
663 const MCExpr *Val = getImm();
664 return static_cast<const MCConstantExpr *>(Val)->getValue();
667 MipsOperand *getMemBase() const {
668 assert((Kind == k_Memory) && "Invalid access!");
672 const MCExpr *getMemOff() const {
673 assert((Kind == k_Memory) && "Invalid access!");
677 int64_t getConstantMemOff() const {
678 return static_cast<const MCConstantExpr *>(getMemOff())->getValue();
681 static std::unique_ptr<MipsOperand> CreateToken(StringRef Str, SMLoc S,
682 MipsAsmParser &Parser) {
683 auto Op = make_unique<MipsOperand>(k_Token, Parser);
684 Op->Tok.Data = Str.data();
685 Op->Tok.Length = Str.size();
691 /// Create a numeric register (e.g. $1). The exact register remains
692 /// unresolved until an instruction successfully matches
693 static std::unique_ptr<MipsOperand>
694 CreateNumericReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S,
695 SMLoc E, MipsAsmParser &Parser) {
696 DEBUG(dbgs() << "CreateNumericReg(" << Index << ", ...)\n");
697 return CreateReg(Index, RegKind_Numeric, RegInfo, S, E, Parser);
700 /// Create a register that is definitely a GPR.
701 /// This is typically only used for named registers such as $gp.
702 static std::unique_ptr<MipsOperand>
703 CreateGPRReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E,
704 MipsAsmParser &Parser) {
705 return CreateReg(Index, RegKind_GPR, RegInfo, S, E, Parser);
708 /// Create a register that is definitely a FGR.
709 /// This is typically only used for named registers such as $f0.
710 static std::unique_ptr<MipsOperand>
711 CreateFGRReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E,
712 MipsAsmParser &Parser) {
713 return CreateReg(Index, RegKind_FGR, RegInfo, S, E, Parser);
716 /// Create a register that is definitely an FCC.
717 /// This is typically only used for named registers such as $fcc0.
718 static std::unique_ptr<MipsOperand>
719 CreateFCCReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E,
720 MipsAsmParser &Parser) {
721 return CreateReg(Index, RegKind_FCC, RegInfo, S, E, Parser);
724 /// Create a register that is definitely an ACC.
725 /// This is typically only used for named registers such as $ac0.
726 static std::unique_ptr<MipsOperand>
727 CreateACCReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E,
728 MipsAsmParser &Parser) {
729 return CreateReg(Index, RegKind_ACC, RegInfo, S, E, Parser);
732 /// Create a register that is definitely an MSA128.
733 /// This is typically only used for named registers such as $w0.
734 static std::unique_ptr<MipsOperand>
735 CreateMSA128Reg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S,
736 SMLoc E, MipsAsmParser &Parser) {
737 return CreateReg(Index, RegKind_MSA128, RegInfo, S, E, Parser);
740 /// Create a register that is definitely an MSACtrl.
741 /// This is typically only used for named registers such as $msaaccess.
742 static std::unique_ptr<MipsOperand>
743 CreateMSACtrlReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S,
744 SMLoc E, MipsAsmParser &Parser) {
745 return CreateReg(Index, RegKind_MSACtrl, RegInfo, S, E, Parser);
748 static std::unique_ptr<MipsOperand>
749 CreateImm(const MCExpr *Val, SMLoc S, SMLoc E, MipsAsmParser &Parser) {
750 auto Op = make_unique<MipsOperand>(k_Immediate, Parser);
757 static std::unique_ptr<MipsOperand>
758 CreateMem(std::unique_ptr<MipsOperand> Base, const MCExpr *Off, SMLoc S,
759 SMLoc E, MipsAsmParser &Parser) {
760 auto Op = make_unique<MipsOperand>(k_Memory, Parser);
761 Op->Mem.Base = Base.release();
768 bool isGPRAsmReg() const {
769 return isRegIdx() && RegIdx.Kind & RegKind_GPR && RegIdx.Index <= 31;
771 bool isFGRAsmReg() const {
772 // AFGR64 is $0-$15 but we handle this in getAFGR64()
773 return isRegIdx() && RegIdx.Kind & RegKind_FGR && RegIdx.Index <= 31;
775 bool isHWRegsAsmReg() const {
776 return isRegIdx() && RegIdx.Kind & RegKind_HWRegs && RegIdx.Index <= 31;
778 bool isCCRAsmReg() const {
779 return isRegIdx() && RegIdx.Kind & RegKind_CCR && RegIdx.Index <= 31;
781 bool isFCCAsmReg() const {
782 if (!(isRegIdx() && RegIdx.Kind & RegKind_FCC))
784 if (!AsmParser.hasEightFccRegisters())
785 return RegIdx.Index == 0;
786 return RegIdx.Index <= 7;
788 bool isACCAsmReg() const {
789 return isRegIdx() && RegIdx.Kind & RegKind_ACC && RegIdx.Index <= 3;
791 bool isCOP2AsmReg() const {
792 return isRegIdx() && RegIdx.Kind & RegKind_COP2 && RegIdx.Index <= 31;
794 bool isCOP3AsmReg() const {
795 return isRegIdx() && RegIdx.Kind & RegKind_COP3 && RegIdx.Index <= 31;
797 bool isMSA128AsmReg() const {
798 return isRegIdx() && RegIdx.Kind & RegKind_MSA128 && RegIdx.Index <= 31;
800 bool isMSACtrlAsmReg() const {
801 return isRegIdx() && RegIdx.Kind & RegKind_MSACtrl && RegIdx.Index <= 7;
804 /// getStartLoc - Get the location of the first token of this operand.
805 SMLoc getStartLoc() const override { return StartLoc; }
806 /// getEndLoc - Get the location of the last token of this operand.
807 SMLoc getEndLoc() const override { return EndLoc; }
809 virtual ~MipsOperand() {
817 case k_RegisterIndex:
823 void print(raw_ostream &OS) const override {
838 OS << "PhysReg<" << PhysReg.Num << ">";
840 case k_RegisterIndex:
841 OS << "RegIdx<" << RegIdx.Index << ":" << RegIdx.Kind << ">";
848 }; // class MipsOperand
852 extern const MCInstrDesc MipsInsts[];
854 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
855 return MipsInsts[Opcode];
858 bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
859 SmallVectorImpl<MCInst> &Instructions) {
860 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
864 if (MCID.isBranch() || MCID.isCall()) {
865 const unsigned Opcode = Inst.getOpcode();
875 assert(MCID.getNumOperands() == 3 && "unexpected number of operands");
876 Offset = Inst.getOperand(2);
878 break; // We'll deal with this situation later on when applying fixups.
879 if (!isIntN(isMicroMips() ? 17 : 18, Offset.getImm()))
880 return Error(IDLoc, "branch target out of range");
881 if (OffsetToAlignment(Offset.getImm(), 1LL << (isMicroMips() ? 1 : 2)))
882 return Error(IDLoc, "branch to misaligned address");
896 case Mips::BGEZAL_MM:
897 case Mips::BLTZAL_MM:
900 assert(MCID.getNumOperands() == 2 && "unexpected number of operands");
901 Offset = Inst.getOperand(1);
903 break; // We'll deal with this situation later on when applying fixups.
904 if (!isIntN(isMicroMips() ? 17 : 18, Offset.getImm()))
905 return Error(IDLoc, "branch target out of range");
906 if (OffsetToAlignment(Offset.getImm(), 1LL << (isMicroMips() ? 1 : 2)))
907 return Error(IDLoc, "branch to misaligned address");
912 // SSNOP is deprecated on MIPS32r6/MIPS64r6
913 // We still accept it but it is a normal nop.
914 if (hasMips32r6() && Inst.getOpcode() == Mips::SSNOP) {
915 std::string ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
916 Warning(IDLoc, "ssnop is deprecated for " + ISA + " and is equivalent to a "
920 if (MCID.hasDelaySlot() && Options.isReorder()) {
921 // If this instruction has a delay slot and .set reorder is active,
922 // emit a NOP after it.
923 Instructions.push_back(Inst);
925 NopInst.setOpcode(Mips::SLL);
926 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
927 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
928 NopInst.addOperand(MCOperand::CreateImm(0));
929 Instructions.push_back(NopInst);
933 if (MCID.mayLoad() || MCID.mayStore()) {
934 // Check the offset of memory operand, if it is a symbol
935 // reference or immediate we may have to expand instructions.
936 for (unsigned i = 0; i < MCID.getNumOperands(); i++) {
937 const MCOperandInfo &OpInfo = MCID.OpInfo[i];
938 if ((OpInfo.OperandType == MCOI::OPERAND_MEMORY) ||
939 (OpInfo.OperandType == MCOI::OPERAND_UNKNOWN)) {
940 MCOperand &Op = Inst.getOperand(i);
942 int MemOffset = Op.getImm();
943 if (MemOffset < -32768 || MemOffset > 32767) {
944 // Offset can't exceed 16bit value.
945 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), true);
948 } else if (Op.isExpr()) {
949 const MCExpr *Expr = Op.getExpr();
950 if (Expr->getKind() == MCExpr::SymbolRef) {
951 const MCSymbolRefExpr *SR =
952 static_cast<const MCSymbolRefExpr *>(Expr);
953 if (SR->getKind() == MCSymbolRefExpr::VK_None) {
955 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false);
958 } else if (!isEvaluated(Expr)) {
959 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false);
967 if (needsExpansion(Inst))
968 expandInstruction(Inst, IDLoc, Instructions);
970 Instructions.push_back(Inst);
975 bool MipsAsmParser::needsExpansion(MCInst &Inst) {
977 switch (Inst.getOpcode()) {
978 case Mips::LoadImm32Reg:
979 case Mips::LoadAddr32Imm:
980 case Mips::LoadAddr32Reg:
987 void MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
988 SmallVectorImpl<MCInst> &Instructions) {
989 switch (Inst.getOpcode()) {
990 case Mips::LoadImm32Reg:
991 return expandLoadImm(Inst, IDLoc, Instructions);
992 case Mips::LoadAddr32Imm:
993 return expandLoadAddressImm(Inst, IDLoc, Instructions);
994 case Mips::LoadAddr32Reg:
995 return expandLoadAddressReg(Inst, IDLoc, Instructions);
999 void MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
1000 SmallVectorImpl<MCInst> &Instructions) {
1002 const MCOperand &ImmOp = Inst.getOperand(1);
1003 assert(ImmOp.isImm() && "expected immediate operand kind");
1004 const MCOperand &RegOp = Inst.getOperand(0);
1005 assert(RegOp.isReg() && "expected register operand kind");
1007 int ImmValue = ImmOp.getImm();
1008 tmpInst.setLoc(IDLoc);
1009 if (0 <= ImmValue && ImmValue <= 65535) {
1010 // For 0 <= j <= 65535.
1011 // li d,j => ori d,$zero,j
1012 tmpInst.setOpcode(Mips::ORi);
1013 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1014 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
1015 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
1016 Instructions.push_back(tmpInst);
1017 } else if (ImmValue < 0 && ImmValue >= -32768) {
1018 // For -32768 <= j < 0.
1019 // li d,j => addiu d,$zero,j
1020 tmpInst.setOpcode(Mips::ADDiu);
1021 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1022 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
1023 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
1024 Instructions.push_back(tmpInst);
1026 // For any other value of j that is representable as a 32-bit integer.
1027 // li d,j => lui d,hi16(j)
1029 tmpInst.setOpcode(Mips::LUi);
1030 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1031 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
1032 Instructions.push_back(tmpInst);
1034 tmpInst.setOpcode(Mips::ORi);
1035 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1036 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1037 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
1038 tmpInst.setLoc(IDLoc);
1039 Instructions.push_back(tmpInst);
1044 MipsAsmParser::expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
1045 SmallVectorImpl<MCInst> &Instructions) {
1047 const MCOperand &ImmOp = Inst.getOperand(2);
1048 assert(ImmOp.isImm() && "expected immediate operand kind");
1049 const MCOperand &SrcRegOp = Inst.getOperand(1);
1050 assert(SrcRegOp.isReg() && "expected register operand kind");
1051 const MCOperand &DstRegOp = Inst.getOperand(0);
1052 assert(DstRegOp.isReg() && "expected register operand kind");
1053 int ImmValue = ImmOp.getImm();
1054 if (-32768 <= ImmValue && ImmValue <= 65535) {
1055 // For -32768 <= j <= 65535.
1056 // la d,j(s) => addiu d,s,j
1057 tmpInst.setOpcode(Mips::ADDiu);
1058 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1059 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
1060 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
1061 Instructions.push_back(tmpInst);
1063 // For any other value of j that is representable as a 32-bit integer.
1064 // la d,j(s) => lui d,hi16(j)
1067 tmpInst.setOpcode(Mips::LUi);
1068 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1069 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
1070 Instructions.push_back(tmpInst);
1072 tmpInst.setOpcode(Mips::ORi);
1073 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1074 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1075 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
1076 Instructions.push_back(tmpInst);
1078 tmpInst.setOpcode(Mips::ADDu);
1079 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1080 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1081 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
1082 Instructions.push_back(tmpInst);
1087 MipsAsmParser::expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
1088 SmallVectorImpl<MCInst> &Instructions) {
1090 const MCOperand &ImmOp = Inst.getOperand(1);
1091 assert(ImmOp.isImm() && "expected immediate operand kind");
1092 const MCOperand &RegOp = Inst.getOperand(0);
1093 assert(RegOp.isReg() && "expected register operand kind");
1094 int ImmValue = ImmOp.getImm();
1095 if (-32768 <= ImmValue && ImmValue <= 65535) {
1096 // For -32768 <= j <= 65535.
1097 // la d,j => addiu d,$zero,j
1098 tmpInst.setOpcode(Mips::ADDiu);
1099 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1100 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
1101 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
1102 Instructions.push_back(tmpInst);
1104 // For any other value of j that is representable as a 32-bit integer.
1105 // la d,j => lui d,hi16(j)
1107 tmpInst.setOpcode(Mips::LUi);
1108 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1109 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
1110 Instructions.push_back(tmpInst);
1112 tmpInst.setOpcode(Mips::ORi);
1113 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1114 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1115 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
1116 Instructions.push_back(tmpInst);
1120 void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc,
1121 SmallVectorImpl<MCInst> &Instructions,
1122 bool isLoad, bool isImmOpnd) {
1123 const MCSymbolRefExpr *SR;
1125 unsigned ImmOffset, HiOffset, LoOffset;
1126 const MCExpr *ExprOffset;
1128 // 1st operand is either the source or destination register.
1129 assert(Inst.getOperand(0).isReg() && "expected register operand kind");
1130 unsigned RegOpNum = Inst.getOperand(0).getReg();
1131 // 2nd operand is the base register.
1132 assert(Inst.getOperand(1).isReg() && "expected register operand kind");
1133 unsigned BaseRegNum = Inst.getOperand(1).getReg();
1134 // 3rd operand is either an immediate or expression.
1136 assert(Inst.getOperand(2).isImm() && "expected immediate operand kind");
1137 ImmOffset = Inst.getOperand(2).getImm();
1138 LoOffset = ImmOffset & 0x0000ffff;
1139 HiOffset = (ImmOffset & 0xffff0000) >> 16;
1140 // If msb of LoOffset is 1(negative number) we must increment HiOffset.
1141 if (LoOffset & 0x8000)
1144 ExprOffset = Inst.getOperand(2).getExpr();
1145 // All instructions will have the same location.
1146 TempInst.setLoc(IDLoc);
1147 // 1st instruction in expansion is LUi. For load instruction we can use
1148 // the dst register as a temporary if base and dst are different,
1149 // but for stores we must use $at.
1150 if (isLoad && (BaseRegNum != RegOpNum))
1151 TmpRegNum = RegOpNum;
1154 (isGP64()) ? Mips::GPR64RegClassID : Mips::GPR32RegClassID, getATReg());
1156 TempInst.setOpcode(Mips::LUi);
1157 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
1159 TempInst.addOperand(MCOperand::CreateImm(HiOffset));
1161 if (ExprOffset->getKind() == MCExpr::SymbolRef) {
1162 SR = static_cast<const MCSymbolRefExpr *>(ExprOffset);
1163 const MCSymbolRefExpr *HiExpr = MCSymbolRefExpr::Create(
1164 SR->getSymbol().getName(), MCSymbolRefExpr::VK_Mips_ABS_HI,
1166 TempInst.addOperand(MCOperand::CreateExpr(HiExpr));
1168 const MCExpr *HiExpr = evaluateRelocExpr(ExprOffset, "hi");
1169 TempInst.addOperand(MCOperand::CreateExpr(HiExpr));
1172 // Add the instruction to the list.
1173 Instructions.push_back(TempInst);
1174 // Prepare TempInst for next instruction.
1176 // Add temp register to base.
1177 TempInst.setOpcode(Mips::ADDu);
1178 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
1179 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
1180 TempInst.addOperand(MCOperand::CreateReg(BaseRegNum));
1181 Instructions.push_back(TempInst);
1183 // And finally, create original instruction with low part
1184 // of offset and new base.
1185 TempInst.setOpcode(Inst.getOpcode());
1186 TempInst.addOperand(MCOperand::CreateReg(RegOpNum));
1187 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
1189 TempInst.addOperand(MCOperand::CreateImm(LoOffset));
1191 if (ExprOffset->getKind() == MCExpr::SymbolRef) {
1192 const MCSymbolRefExpr *LoExpr = MCSymbolRefExpr::Create(
1193 SR->getSymbol().getName(), MCSymbolRefExpr::VK_Mips_ABS_LO,
1195 TempInst.addOperand(MCOperand::CreateExpr(LoExpr));
1197 const MCExpr *LoExpr = evaluateRelocExpr(ExprOffset, "lo");
1198 TempInst.addOperand(MCOperand::CreateExpr(LoExpr));
1201 Instructions.push_back(TempInst);
1205 unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
1206 // As described by the Mips32r2 spec, the registers Rd and Rs for
1207 // jalr.hb must be different.
1208 unsigned Opcode = Inst.getOpcode();
1210 if (Opcode == Mips::JALR_HB &&
1211 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()))
1212 return Match_RequiresDifferentSrcAndDst;
1214 return Match_Success;
1217 bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1218 OperandVector &Operands,
1220 unsigned &ErrorInfo,
1221 bool MatchingInlineAsm) {
1224 SmallVector<MCInst, 8> Instructions;
1225 unsigned MatchResult =
1226 MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
1228 switch (MatchResult) {
1231 case Match_Success: {
1232 if (processInstruction(Inst, IDLoc, Instructions))
1234 for (unsigned i = 0; i < Instructions.size(); i++)
1235 Out.EmitInstruction(Instructions[i], STI);
1238 case Match_MissingFeature:
1239 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
1241 case Match_InvalidOperand: {
1242 SMLoc ErrorLoc = IDLoc;
1243 if (ErrorInfo != ~0U) {
1244 if (ErrorInfo >= Operands.size())
1245 return Error(IDLoc, "too few operands for instruction");
1247 ErrorLoc = ((MipsOperand &)*Operands[ErrorInfo]).getStartLoc();
1248 if (ErrorLoc == SMLoc())
1252 return Error(ErrorLoc, "invalid operand for instruction");
1254 case Match_MnemonicFail:
1255 return Error(IDLoc, "invalid instruction");
1256 case Match_RequiresDifferentSrcAndDst:
1257 return Error(IDLoc, "source and destination must be different");
1262 void MipsAsmParser::WarnIfAssemblerTemporary(int RegIndex, SMLoc Loc) {
1263 if ((RegIndex != 0) && ((int)Options.getATRegNum() == RegIndex)) {
1265 Warning(Loc, "Used $at without \".set noat\"");
1267 Warning(Loc, Twine("Used $") + Twine(RegIndex) + " with \".set at=$" +
1268 Twine(RegIndex) + "\"");
1272 int MipsAsmParser::matchCPURegisterName(StringRef Name) {
1275 CC = StringSwitch<unsigned>(Name)
1311 if (isN32() || isN64()) {
1312 // Although SGI documentation just cuts out t0-t3 for n32/n64,
1313 // GNU pushes the values of t0-t3 to override the o32/o64 values for t4-t7
1314 // We are supporting both cases, so for t0-t3 we'll just push them to t4-t7.
1315 if (8 <= CC && CC <= 11)
1319 CC = StringSwitch<unsigned>(Name)
1332 int MipsAsmParser::matchFPURegisterName(StringRef Name) {
1334 if (Name[0] == 'f') {
1335 StringRef NumString = Name.substr(1);
1337 if (NumString.getAsInteger(10, IntVal))
1338 return -1; // This is not an integer.
1339 if (IntVal > 31) // Maximum index for fpu register.
1346 int MipsAsmParser::matchFCCRegisterName(StringRef Name) {
1348 if (Name.startswith("fcc")) {
1349 StringRef NumString = Name.substr(3);
1351 if (NumString.getAsInteger(10, IntVal))
1352 return -1; // This is not an integer.
1353 if (IntVal > 7) // There are only 8 fcc registers.
1360 int MipsAsmParser::matchACRegisterName(StringRef Name) {
1362 if (Name.startswith("ac")) {
1363 StringRef NumString = Name.substr(2);
1365 if (NumString.getAsInteger(10, IntVal))
1366 return -1; // This is not an integer.
1367 if (IntVal > 3) // There are only 3 acc registers.
1374 int MipsAsmParser::matchMSA128RegisterName(StringRef Name) {
1377 if (Name.front() != 'w' || Name.drop_front(1).getAsInteger(10, IntVal))
1386 int MipsAsmParser::matchMSA128CtrlRegisterName(StringRef Name) {
1389 CC = StringSwitch<unsigned>(Name)
1392 .Case("msaaccess", 2)
1394 .Case("msamodify", 4)
1395 .Case("msarequest", 5)
1397 .Case("msaunmap", 7)
1403 bool MipsAssemblerOptions::setATReg(unsigned Reg) {
1411 int MipsAsmParser::getATReg() {
1412 int AT = Options.getATRegNum();
1414 TokError("Pseudo instruction requires $at, which is not available");
1418 unsigned MipsAsmParser::getReg(int RC, int RegNo) {
1419 return *(getContext().getRegisterInfo()->getRegClass(RC).begin() + RegNo);
1422 unsigned MipsAsmParser::getGPR(int RegNo) {
1423 return getReg(isGP64() ? Mips::GPR64RegClassID : Mips::GPR32RegClassID,
1427 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) {
1429 getContext().getRegisterInfo()->getRegClass(RegClass).getNumRegs() - 1)
1432 return getReg(RegClass, RegNum);
1435 bool MipsAsmParser::ParseOperand(OperandVector &Operands, StringRef Mnemonic) {
1436 DEBUG(dbgs() << "ParseOperand\n");
1438 // Check if the current operand has a custom associated parser, if so, try to
1439 // custom parse the operand, or fallback to the general approach.
1440 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1441 if (ResTy == MatchOperand_Success)
1443 // If there wasn't a custom match, try the generic matcher below. Otherwise,
1444 // there was a match, but an error occurred, in which case, just return that
1445 // the operand parsing failed.
1446 if (ResTy == MatchOperand_ParseFail)
1449 DEBUG(dbgs() << ".. Generic Parser\n");
1451 switch (getLexer().getKind()) {
1453 Error(Parser.getTok().getLoc(), "unexpected token in operand");
1455 case AsmToken::Dollar: {
1456 // Parse the register.
1457 SMLoc S = Parser.getTok().getLoc();
1459 // Almost all registers have been parsed by custom parsers. There is only
1460 // one exception to this. $zero (and it's alias $0) will reach this point
1461 // for div, divu, and similar instructions because it is not an operand
1462 // to the instruction definition but an explicit register. Special case
1463 // this situation for now.
1464 if (ParseAnyRegister(Operands) != MatchOperand_NoMatch)
1467 // Maybe it is a symbol reference.
1468 StringRef Identifier;
1469 if (Parser.parseIdentifier(Identifier))
1472 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1473 MCSymbol *Sym = getContext().GetOrCreateSymbol("$" + Identifier);
1474 // Otherwise create a symbol reference.
1476 MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None, getContext());
1478 Operands.push_back(MipsOperand::CreateImm(Res, S, E, *this));
1481 // Else drop to expression parsing.
1482 case AsmToken::LParen:
1483 case AsmToken::Minus:
1484 case AsmToken::Plus:
1485 case AsmToken::Integer:
1486 case AsmToken::Tilde:
1487 case AsmToken::String: {
1488 DEBUG(dbgs() << ".. generic integer\n");
1489 OperandMatchResultTy ResTy = ParseImm(Operands);
1490 return ResTy != MatchOperand_Success;
1492 case AsmToken::Percent: {
1493 // It is a symbol reference or constant expression.
1494 const MCExpr *IdVal;
1495 SMLoc S = Parser.getTok().getLoc(); // Start location of the operand.
1496 if (parseRelocOperand(IdVal))
1499 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1501 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E, *this));
1503 } // case AsmToken::Percent
1504 } // switch(getLexer().getKind())
1508 const MCExpr *MipsAsmParser::evaluateRelocExpr(const MCExpr *Expr,
1509 StringRef RelocStr) {
1511 // Check the type of the expression.
1512 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(Expr)) {
1513 // It's a constant, evaluate reloc value.
1515 switch (getVariantKind(RelocStr)) {
1516 case MCSymbolRefExpr::VK_Mips_ABS_LO:
1517 // Get the 1st 16-bits.
1518 Val = MCE->getValue() & 0xffff;
1520 case MCSymbolRefExpr::VK_Mips_ABS_HI:
1521 // Get the 2nd 16-bits. Also add 1 if bit 15 is 1, to compensate for low
1522 // 16 bits being negative.
1523 Val = ((MCE->getValue() + 0x8000) >> 16) & 0xffff;
1525 case MCSymbolRefExpr::VK_Mips_HIGHER:
1526 // Get the 3rd 16-bits.
1527 Val = ((MCE->getValue() + 0x80008000LL) >> 32) & 0xffff;
1529 case MCSymbolRefExpr::VK_Mips_HIGHEST:
1530 // Get the 4th 16-bits.
1531 Val = ((MCE->getValue() + 0x800080008000LL) >> 48) & 0xffff;
1534 report_fatal_error("Unsupported reloc value!");
1536 return MCConstantExpr::Create(Val, getContext());
1539 if (const MCSymbolRefExpr *MSRE = dyn_cast<MCSymbolRefExpr>(Expr)) {
1540 // It's a symbol, create a symbolic expression from the symbol.
1541 StringRef Symbol = MSRE->getSymbol().getName();
1542 MCSymbolRefExpr::VariantKind VK = getVariantKind(RelocStr);
1543 Res = MCSymbolRefExpr::Create(Symbol, VK, getContext());
1547 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
1548 MCSymbolRefExpr::VariantKind VK = getVariantKind(RelocStr);
1550 // Try to create target expression.
1551 if (MipsMCExpr::isSupportedBinaryExpr(VK, BE))
1552 return MipsMCExpr::Create(VK, Expr, getContext());
1554 const MCExpr *LExp = evaluateRelocExpr(BE->getLHS(), RelocStr);
1555 const MCExpr *RExp = evaluateRelocExpr(BE->getRHS(), RelocStr);
1556 Res = MCBinaryExpr::Create(BE->getOpcode(), LExp, RExp, getContext());
1560 if (const MCUnaryExpr *UN = dyn_cast<MCUnaryExpr>(Expr)) {
1561 const MCExpr *UnExp = evaluateRelocExpr(UN->getSubExpr(), RelocStr);
1562 Res = MCUnaryExpr::Create(UN->getOpcode(), UnExp, getContext());
1565 // Just return the original expression.
1569 bool MipsAsmParser::isEvaluated(const MCExpr *Expr) {
1571 switch (Expr->getKind()) {
1572 case MCExpr::Constant:
1574 case MCExpr::SymbolRef:
1575 return (cast<MCSymbolRefExpr>(Expr)->getKind() != MCSymbolRefExpr::VK_None);
1576 case MCExpr::Binary:
1577 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
1578 if (!isEvaluated(BE->getLHS()))
1580 return isEvaluated(BE->getRHS());
1583 return isEvaluated(cast<MCUnaryExpr>(Expr)->getSubExpr());
1584 case MCExpr::Target:
1590 bool MipsAsmParser::parseRelocOperand(const MCExpr *&Res) {
1591 Parser.Lex(); // Eat the % token.
1592 const AsmToken &Tok = Parser.getTok(); // Get next token, operation.
1593 if (Tok.isNot(AsmToken::Identifier))
1596 std::string Str = Tok.getIdentifier().str();
1598 Parser.Lex(); // Eat the identifier.
1599 // Now make an expression from the rest of the operand.
1600 const MCExpr *IdVal;
1603 if (getLexer().getKind() == AsmToken::LParen) {
1605 Parser.Lex(); // Eat the '(' token.
1606 if (getLexer().getKind() == AsmToken::Percent) {
1607 Parser.Lex(); // Eat the % token.
1608 const AsmToken &nextTok = Parser.getTok();
1609 if (nextTok.isNot(AsmToken::Identifier))
1612 Str += nextTok.getIdentifier();
1613 Parser.Lex(); // Eat the identifier.
1614 if (getLexer().getKind() != AsmToken::LParen)
1619 if (getParser().parseParenExpression(IdVal, EndLoc))
1622 while (getLexer().getKind() == AsmToken::RParen)
1623 Parser.Lex(); // Eat the ')' token.
1626 return true; // Parenthesis must follow the relocation operand.
1628 Res = evaluateRelocExpr(IdVal, Str);
1632 bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1634 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands;
1635 OperandMatchResultTy ResTy = ParseAnyRegister(Operands);
1636 if (ResTy == MatchOperand_Success) {
1637 assert(Operands.size() == 1);
1638 MipsOperand &Operand = static_cast<MipsOperand &>(*Operands.front());
1639 StartLoc = Operand.getStartLoc();
1640 EndLoc = Operand.getEndLoc();
1642 // AFAIK, we only support numeric registers and named GPR's in CFI
1644 // Don't worry about eating tokens before failing. Using an unrecognised
1645 // register is a parse error.
1646 if (Operand.isGPRAsmReg()) {
1647 // Resolve to GPR32 or GPR64 appropriately.
1648 RegNo = isGP64() ? Operand.getGPR64Reg() : Operand.getGPR32Reg();
1651 return (RegNo == (unsigned)-1);
1654 assert(Operands.size() == 0);
1655 return (RegNo == (unsigned)-1);
1658 bool MipsAsmParser::parseMemOffset(const MCExpr *&Res, bool isParenExpr) {
1662 while (getLexer().getKind() == AsmToken::LParen)
1665 switch (getLexer().getKind()) {
1668 case AsmToken::Identifier:
1669 case AsmToken::LParen:
1670 case AsmToken::Integer:
1671 case AsmToken::Minus:
1672 case AsmToken::Plus:
1674 Result = getParser().parseParenExpression(Res, S);
1676 Result = (getParser().parseExpression(Res));
1677 while (getLexer().getKind() == AsmToken::RParen)
1680 case AsmToken::Percent:
1681 Result = parseRelocOperand(Res);
1686 MipsAsmParser::OperandMatchResultTy
1687 MipsAsmParser::parseMemOperand(OperandVector &Operands) {
1688 DEBUG(dbgs() << "parseMemOperand\n");
1689 const MCExpr *IdVal = nullptr;
1691 bool isParenExpr = false;
1692 MipsAsmParser::OperandMatchResultTy Res = MatchOperand_NoMatch;
1693 // First operand is the offset.
1694 S = Parser.getTok().getLoc();
1696 if (getLexer().getKind() == AsmToken::LParen) {
1701 if (getLexer().getKind() != AsmToken::Dollar) {
1702 if (parseMemOffset(IdVal, isParenExpr))
1703 return MatchOperand_ParseFail;
1705 const AsmToken &Tok = Parser.getTok(); // Get the next token.
1706 if (Tok.isNot(AsmToken::LParen)) {
1707 MipsOperand &Mnemonic = static_cast<MipsOperand &>(*Operands[0]);
1708 if (Mnemonic.getToken() == "la") {
1710 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1711 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E, *this));
1712 return MatchOperand_Success;
1714 if (Tok.is(AsmToken::EndOfStatement)) {
1716 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1718 // Zero register assumed, add a memory operand with ZERO as its base.
1719 // "Base" will be managed by k_Memory.
1720 auto Base = MipsOperand::CreateGPRReg(0, getContext().getRegisterInfo(),
1723 MipsOperand::CreateMem(std::move(Base), IdVal, S, E, *this));
1724 return MatchOperand_Success;
1726 Error(Parser.getTok().getLoc(), "'(' expected");
1727 return MatchOperand_ParseFail;
1730 Parser.Lex(); // Eat the '(' token.
1733 Res = ParseAnyRegister(Operands);
1734 if (Res != MatchOperand_Success)
1737 if (Parser.getTok().isNot(AsmToken::RParen)) {
1738 Error(Parser.getTok().getLoc(), "')' expected");
1739 return MatchOperand_ParseFail;
1742 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1744 Parser.Lex(); // Eat the ')' token.
1747 IdVal = MCConstantExpr::Create(0, getContext());
1749 // Replace the register operand with the memory operand.
1750 std::unique_ptr<MipsOperand> op(
1751 static_cast<MipsOperand *>(Operands.back().release()));
1752 // Remove the register from the operands.
1753 // "op" will be managed by k_Memory.
1754 Operands.pop_back();
1755 // Add the memory operand.
1756 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(IdVal)) {
1758 if (IdVal->EvaluateAsAbsolute(Imm))
1759 IdVal = MCConstantExpr::Create(Imm, getContext());
1760 else if (BE->getLHS()->getKind() != MCExpr::SymbolRef)
1761 IdVal = MCBinaryExpr::Create(BE->getOpcode(), BE->getRHS(), BE->getLHS(),
1765 Operands.push_back(MipsOperand::CreateMem(std::move(op), IdVal, S, E, *this));
1766 return MatchOperand_Success;
1769 bool MipsAsmParser::searchSymbolAlias(OperandVector &Operands) {
1771 MCSymbol *Sym = getContext().LookupSymbol(Parser.getTok().getIdentifier());
1773 SMLoc S = Parser.getTok().getLoc();
1775 if (Sym->isVariable())
1776 Expr = Sym->getVariableValue();
1779 if (Expr->getKind() == MCExpr::SymbolRef) {
1780 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr *>(Expr);
1781 const StringRef DefSymbol = Ref->getSymbol().getName();
1782 if (DefSymbol.startswith("$")) {
1783 OperandMatchResultTy ResTy =
1784 MatchAnyRegisterNameWithoutDollar(Operands, DefSymbol.substr(1), S);
1785 if (ResTy == MatchOperand_Success) {
1788 } else if (ResTy == MatchOperand_ParseFail)
1789 llvm_unreachable("Should never ParseFail");
1792 } else if (Expr->getKind() == MCExpr::Constant) {
1794 const MCConstantExpr *Const = static_cast<const MCConstantExpr *>(Expr);
1796 MipsOperand::CreateImm(Const, S, Parser.getTok().getLoc(), *this));
1803 MipsAsmParser::OperandMatchResultTy
1804 MipsAsmParser::MatchAnyRegisterNameWithoutDollar(OperandVector &Operands,
1805 StringRef Identifier,
1807 int Index = matchCPURegisterName(Identifier);
1809 Operands.push_back(MipsOperand::CreateGPRReg(
1810 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1811 return MatchOperand_Success;
1814 Index = matchFPURegisterName(Identifier);
1816 Operands.push_back(MipsOperand::CreateFGRReg(
1817 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1818 return MatchOperand_Success;
1821 Index = matchFCCRegisterName(Identifier);
1823 Operands.push_back(MipsOperand::CreateFCCReg(
1824 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1825 return MatchOperand_Success;
1828 Index = matchACRegisterName(Identifier);
1830 Operands.push_back(MipsOperand::CreateACCReg(
1831 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1832 return MatchOperand_Success;
1835 Index = matchMSA128RegisterName(Identifier);
1837 Operands.push_back(MipsOperand::CreateMSA128Reg(
1838 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1839 return MatchOperand_Success;
1842 Index = matchMSA128CtrlRegisterName(Identifier);
1844 Operands.push_back(MipsOperand::CreateMSACtrlReg(
1845 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1846 return MatchOperand_Success;
1849 return MatchOperand_NoMatch;
1852 MipsAsmParser::OperandMatchResultTy
1853 MipsAsmParser::MatchAnyRegisterWithoutDollar(OperandVector &Operands, SMLoc S) {
1854 auto Token = Parser.getLexer().peekTok(false);
1856 if (Token.is(AsmToken::Identifier)) {
1857 DEBUG(dbgs() << ".. identifier\n");
1858 StringRef Identifier = Token.getIdentifier();
1859 OperandMatchResultTy ResTy =
1860 MatchAnyRegisterNameWithoutDollar(Operands, Identifier, S);
1862 } else if (Token.is(AsmToken::Integer)) {
1863 DEBUG(dbgs() << ".. integer\n");
1864 Operands.push_back(MipsOperand::CreateNumericReg(
1865 Token.getIntVal(), getContext().getRegisterInfo(), S, Token.getLoc(),
1867 return MatchOperand_Success;
1870 DEBUG(dbgs() << Parser.getTok().getKind() << "\n");
1872 return MatchOperand_NoMatch;
1875 MipsAsmParser::OperandMatchResultTy
1876 MipsAsmParser::ParseAnyRegister(OperandVector &Operands) {
1877 DEBUG(dbgs() << "ParseAnyRegister\n");
1879 auto Token = Parser.getTok();
1881 SMLoc S = Token.getLoc();
1883 if (Token.isNot(AsmToken::Dollar)) {
1884 DEBUG(dbgs() << ".. !$ -> try sym aliasing\n");
1885 if (Token.is(AsmToken::Identifier)) {
1886 if (searchSymbolAlias(Operands))
1887 return MatchOperand_Success;
1889 DEBUG(dbgs() << ".. !symalias -> NoMatch\n");
1890 return MatchOperand_NoMatch;
1892 DEBUG(dbgs() << ".. $\n");
1894 OperandMatchResultTy ResTy = MatchAnyRegisterWithoutDollar(Operands, S);
1895 if (ResTy == MatchOperand_Success) {
1897 Parser.Lex(); // identifier
1902 MipsAsmParser::OperandMatchResultTy
1903 MipsAsmParser::ParseImm(OperandVector &Operands) {
1904 switch (getLexer().getKind()) {
1906 return MatchOperand_NoMatch;
1907 case AsmToken::LParen:
1908 case AsmToken::Minus:
1909 case AsmToken::Plus:
1910 case AsmToken::Integer:
1911 case AsmToken::Tilde:
1912 case AsmToken::String:
1916 const MCExpr *IdVal;
1917 SMLoc S = Parser.getTok().getLoc();
1918 if (getParser().parseExpression(IdVal))
1919 return MatchOperand_ParseFail;
1921 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1922 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E, *this));
1923 return MatchOperand_Success;
1926 MipsAsmParser::OperandMatchResultTy
1927 MipsAsmParser::ParseJumpTarget(OperandVector &Operands) {
1928 DEBUG(dbgs() << "ParseJumpTarget\n");
1930 SMLoc S = getLexer().getLoc();
1932 // Integers and expressions are acceptable
1933 OperandMatchResultTy ResTy = ParseImm(Operands);
1934 if (ResTy != MatchOperand_NoMatch)
1937 // Registers are a valid target and have priority over symbols.
1938 ResTy = ParseAnyRegister(Operands);
1939 if (ResTy != MatchOperand_NoMatch)
1942 const MCExpr *Expr = nullptr;
1943 if (Parser.parseExpression(Expr)) {
1944 // We have no way of knowing if a symbol was consumed so we must ParseFail
1945 return MatchOperand_ParseFail;
1948 MipsOperand::CreateImm(Expr, S, getLexer().getLoc(), *this));
1949 return MatchOperand_Success;
1952 MipsAsmParser::OperandMatchResultTy
1953 MipsAsmParser::parseInvNum(OperandVector &Operands) {
1954 const MCExpr *IdVal;
1955 // If the first token is '$' we may have register operand.
1956 if (Parser.getTok().is(AsmToken::Dollar))
1957 return MatchOperand_NoMatch;
1958 SMLoc S = Parser.getTok().getLoc();
1959 if (getParser().parseExpression(IdVal))
1960 return MatchOperand_ParseFail;
1961 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(IdVal);
1962 assert(MCE && "Unexpected MCExpr type.");
1963 int64_t Val = MCE->getValue();
1964 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1965 Operands.push_back(MipsOperand::CreateImm(
1966 MCConstantExpr::Create(0 - Val, getContext()), S, E, *this));
1967 return MatchOperand_Success;
1970 MipsAsmParser::OperandMatchResultTy
1971 MipsAsmParser::ParseLSAImm(OperandVector &Operands) {
1972 switch (getLexer().getKind()) {
1974 return MatchOperand_NoMatch;
1975 case AsmToken::LParen:
1976 case AsmToken::Plus:
1977 case AsmToken::Minus:
1978 case AsmToken::Integer:
1983 SMLoc S = Parser.getTok().getLoc();
1985 if (getParser().parseExpression(Expr))
1986 return MatchOperand_ParseFail;
1989 if (!Expr->EvaluateAsAbsolute(Val)) {
1990 Error(S, "expected immediate value");
1991 return MatchOperand_ParseFail;
1994 // The LSA instruction allows a 2-bit unsigned immediate. For this reason
1995 // and because the CPU always adds one to the immediate field, the allowed
1996 // range becomes 1..4. We'll only check the range here and will deal
1997 // with the addition/subtraction when actually decoding/encoding
1999 if (Val < 1 || Val > 4) {
2000 Error(S, "immediate not in range (1..4)");
2001 return MatchOperand_ParseFail;
2005 MipsOperand::CreateImm(Expr, S, Parser.getTok().getLoc(), *this));
2006 return MatchOperand_Success;
2009 MCSymbolRefExpr::VariantKind MipsAsmParser::getVariantKind(StringRef Symbol) {
2011 MCSymbolRefExpr::VariantKind VK =
2012 StringSwitch<MCSymbolRefExpr::VariantKind>(Symbol)
2013 .Case("hi", MCSymbolRefExpr::VK_Mips_ABS_HI)
2014 .Case("lo", MCSymbolRefExpr::VK_Mips_ABS_LO)
2015 .Case("gp_rel", MCSymbolRefExpr::VK_Mips_GPREL)
2016 .Case("call16", MCSymbolRefExpr::VK_Mips_GOT_CALL)
2017 .Case("got", MCSymbolRefExpr::VK_Mips_GOT)
2018 .Case("tlsgd", MCSymbolRefExpr::VK_Mips_TLSGD)
2019 .Case("tlsldm", MCSymbolRefExpr::VK_Mips_TLSLDM)
2020 .Case("dtprel_hi", MCSymbolRefExpr::VK_Mips_DTPREL_HI)
2021 .Case("dtprel_lo", MCSymbolRefExpr::VK_Mips_DTPREL_LO)
2022 .Case("gottprel", MCSymbolRefExpr::VK_Mips_GOTTPREL)
2023 .Case("tprel_hi", MCSymbolRefExpr::VK_Mips_TPREL_HI)
2024 .Case("tprel_lo", MCSymbolRefExpr::VK_Mips_TPREL_LO)
2025 .Case("got_disp", MCSymbolRefExpr::VK_Mips_GOT_DISP)
2026 .Case("got_page", MCSymbolRefExpr::VK_Mips_GOT_PAGE)
2027 .Case("got_ofst", MCSymbolRefExpr::VK_Mips_GOT_OFST)
2028 .Case("hi(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_HI)
2029 .Case("lo(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_LO)
2030 .Case("got_hi", MCSymbolRefExpr::VK_Mips_GOT_HI16)
2031 .Case("got_lo", MCSymbolRefExpr::VK_Mips_GOT_LO16)
2032 .Case("call_hi", MCSymbolRefExpr::VK_Mips_CALL_HI16)
2033 .Case("call_lo", MCSymbolRefExpr::VK_Mips_CALL_LO16)
2034 .Case("higher", MCSymbolRefExpr::VK_Mips_HIGHER)
2035 .Case("highest", MCSymbolRefExpr::VK_Mips_HIGHEST)
2036 .Case("pcrel_hi", MCSymbolRefExpr::VK_Mips_PCREL_HI16)
2037 .Case("pcrel_lo", MCSymbolRefExpr::VK_Mips_PCREL_LO16)
2038 .Default(MCSymbolRefExpr::VK_None);
2040 assert(VK != MCSymbolRefExpr::VK_None);
2045 /// Sometimes (i.e. load/stores) the operand may be followed immediately by
2047 /// ::= '(', register, ')'
2048 /// handle it before we iterate so we don't get tripped up by the lack of
2050 bool MipsAsmParser::ParseParenSuffix(StringRef Name, OperandVector &Operands) {
2051 if (getLexer().is(AsmToken::LParen)) {
2053 MipsOperand::CreateToken("(", getLexer().getLoc(), *this));
2055 if (ParseOperand(Operands, Name)) {
2056 SMLoc Loc = getLexer().getLoc();
2057 Parser.eatToEndOfStatement();
2058 return Error(Loc, "unexpected token in argument list");
2060 if (Parser.getTok().isNot(AsmToken::RParen)) {
2061 SMLoc Loc = getLexer().getLoc();
2062 Parser.eatToEndOfStatement();
2063 return Error(Loc, "unexpected token, expected ')'");
2066 MipsOperand::CreateToken(")", getLexer().getLoc(), *this));
2072 /// Sometimes (i.e. in MSA) the operand may be followed immediately by
2073 /// either one of these.
2074 /// ::= '[', register, ']'
2075 /// ::= '[', integer, ']'
2076 /// handle it before we iterate so we don't get tripped up by the lack of
2078 bool MipsAsmParser::ParseBracketSuffix(StringRef Name,
2079 OperandVector &Operands) {
2080 if (getLexer().is(AsmToken::LBrac)) {
2082 MipsOperand::CreateToken("[", getLexer().getLoc(), *this));
2084 if (ParseOperand(Operands, Name)) {
2085 SMLoc Loc = getLexer().getLoc();
2086 Parser.eatToEndOfStatement();
2087 return Error(Loc, "unexpected token in argument list");
2089 if (Parser.getTok().isNot(AsmToken::RBrac)) {
2090 SMLoc Loc = getLexer().getLoc();
2091 Parser.eatToEndOfStatement();
2092 return Error(Loc, "unexpected token, expected ']'");
2095 MipsOperand::CreateToken("]", getLexer().getLoc(), *this));
2101 bool MipsAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
2102 SMLoc NameLoc, OperandVector &Operands) {
2103 DEBUG(dbgs() << "ParseInstruction\n");
2104 // Check if we have valid mnemonic
2105 if (!mnemonicIsValid(Name, 0)) {
2106 Parser.eatToEndOfStatement();
2107 return Error(NameLoc, "Unknown instruction");
2109 // First operand in MCInst is instruction mnemonic.
2110 Operands.push_back(MipsOperand::CreateToken(Name, NameLoc, *this));
2112 // Read the remaining operands.
2113 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2114 // Read the first operand.
2115 if (ParseOperand(Operands, Name)) {
2116 SMLoc Loc = getLexer().getLoc();
2117 Parser.eatToEndOfStatement();
2118 return Error(Loc, "unexpected token in argument list");
2120 if (getLexer().is(AsmToken::LBrac) && ParseBracketSuffix(Name, Operands))
2122 // AFAIK, parenthesis suffixes are never on the first operand
2124 while (getLexer().is(AsmToken::Comma)) {
2125 Parser.Lex(); // Eat the comma.
2126 // Parse and remember the operand.
2127 if (ParseOperand(Operands, Name)) {
2128 SMLoc Loc = getLexer().getLoc();
2129 Parser.eatToEndOfStatement();
2130 return Error(Loc, "unexpected token in argument list");
2132 // Parse bracket and parenthesis suffixes before we iterate
2133 if (getLexer().is(AsmToken::LBrac)) {
2134 if (ParseBracketSuffix(Name, Operands))
2136 } else if (getLexer().is(AsmToken::LParen) &&
2137 ParseParenSuffix(Name, Operands))
2141 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2142 SMLoc Loc = getLexer().getLoc();
2143 Parser.eatToEndOfStatement();
2144 return Error(Loc, "unexpected token in argument list");
2146 Parser.Lex(); // Consume the EndOfStatement.
2150 bool MipsAsmParser::reportParseError(StringRef ErrorMsg) {
2151 SMLoc Loc = getLexer().getLoc();
2152 Parser.eatToEndOfStatement();
2153 return Error(Loc, ErrorMsg);
2156 bool MipsAsmParser::reportParseError(SMLoc Loc, StringRef ErrorMsg) {
2157 return Error(Loc, ErrorMsg);
2160 bool MipsAsmParser::parseSetNoAtDirective() {
2161 // Line should look like: ".set noat".
2163 Options.setATReg(0);
2166 // If this is not the end of the statement, report an error.
2167 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2168 reportParseError("unexpected token in statement");
2171 Parser.Lex(); // Consume the EndOfStatement.
2175 bool MipsAsmParser::parseSetAtDirective() {
2176 // Line can be .set at - defaults to $1
2180 if (getLexer().is(AsmToken::EndOfStatement)) {
2181 Options.setATReg(1);
2182 Parser.Lex(); // Consume the EndOfStatement.
2184 } else if (getLexer().is(AsmToken::Equal)) {
2185 getParser().Lex(); // Eat the '='.
2186 if (getLexer().isNot(AsmToken::Dollar)) {
2187 reportParseError("unexpected token in statement");
2190 Parser.Lex(); // Eat the '$'.
2191 const AsmToken &Reg = Parser.getTok();
2192 if (Reg.is(AsmToken::Identifier)) {
2193 AtRegNo = matchCPURegisterName(Reg.getIdentifier());
2194 } else if (Reg.is(AsmToken::Integer)) {
2195 AtRegNo = Reg.getIntVal();
2197 reportParseError("unexpected token in statement");
2201 if (AtRegNo < 0 || AtRegNo > 31) {
2202 reportParseError("unexpected token in statement");
2206 if (!Options.setATReg(AtRegNo)) {
2207 reportParseError("unexpected token in statement");
2210 getParser().Lex(); // Eat the register.
2212 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2213 reportParseError("unexpected token in statement");
2216 Parser.Lex(); // Consume the EndOfStatement.
2219 reportParseError("unexpected token in statement");
2224 bool MipsAsmParser::parseSetReorderDirective() {
2226 // If this is not the end of the statement, report an error.
2227 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2228 reportParseError("unexpected token in statement");
2231 Options.setReorder();
2232 getTargetStreamer().emitDirectiveSetReorder();
2233 Parser.Lex(); // Consume the EndOfStatement.
2237 bool MipsAsmParser::parseSetNoReorderDirective() {
2239 // If this is not the end of the statement, report an error.
2240 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2241 reportParseError("unexpected token in statement");
2244 Options.setNoreorder();
2245 getTargetStreamer().emitDirectiveSetNoReorder();
2246 Parser.Lex(); // Consume the EndOfStatement.
2250 bool MipsAsmParser::parseSetMacroDirective() {
2252 // If this is not the end of the statement, report an error.
2253 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2254 reportParseError("unexpected token in statement");
2258 Parser.Lex(); // Consume the EndOfStatement.
2262 bool MipsAsmParser::parseSetNoMacroDirective() {
2264 // If this is not the end of the statement, report an error.
2265 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2266 reportParseError("`noreorder' must be set before `nomacro'");
2269 if (Options.isReorder()) {
2270 reportParseError("`noreorder' must be set before `nomacro'");
2273 Options.setNomacro();
2274 Parser.Lex(); // Consume the EndOfStatement.
2278 bool MipsAsmParser::parseSetNoMips16Directive() {
2280 // If this is not the end of the statement, report an error.
2281 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2282 reportParseError("unexpected token in statement");
2285 // For now do nothing.
2286 Parser.Lex(); // Consume the EndOfStatement.
2290 bool MipsAsmParser::parseSetAssignment() {
2292 const MCExpr *Value;
2294 if (Parser.parseIdentifier(Name))
2295 reportParseError("expected identifier after .set");
2297 if (getLexer().isNot(AsmToken::Comma))
2298 return reportParseError("unexpected token in .set directive");
2301 if (Parser.parseExpression(Value))
2302 return reportParseError("expected valid expression after comma");
2304 // Check if the Name already exists as a symbol.
2305 MCSymbol *Sym = getContext().LookupSymbol(Name);
2307 return reportParseError("symbol already defined");
2308 Sym = getContext().GetOrCreateSymbol(Name);
2309 Sym->setVariableValue(Value);
2314 bool MipsAsmParser::parseSetFeature(uint64_t Feature) {
2316 if (getLexer().isNot(AsmToken::EndOfStatement))
2317 return reportParseError("unexpected token in .set directive");
2321 llvm_unreachable("Unimplemented feature");
2322 case Mips::FeatureDSP:
2323 setFeatureBits(Mips::FeatureDSP, "dsp");
2324 getTargetStreamer().emitDirectiveSetDsp();
2326 case Mips::FeatureMicroMips:
2327 getTargetStreamer().emitDirectiveSetMicroMips();
2329 case Mips::FeatureMips16:
2330 getTargetStreamer().emitDirectiveSetMips16();
2332 case Mips::FeatureMips32r2:
2333 setFeatureBits(Mips::FeatureMips32r2, "mips32r2");
2334 getTargetStreamer().emitDirectiveSetMips32R2();
2336 case Mips::FeatureMips64:
2337 setFeatureBits(Mips::FeatureMips64, "mips64");
2338 getTargetStreamer().emitDirectiveSetMips64();
2340 case Mips::FeatureMips64r2:
2341 setFeatureBits(Mips::FeatureMips64r2, "mips64r2");
2342 getTargetStreamer().emitDirectiveSetMips64R2();
2348 bool MipsAsmParser::eatComma(StringRef ErrorStr) {
2349 if (getLexer().isNot(AsmToken::Comma)) {
2350 SMLoc Loc = getLexer().getLoc();
2351 Parser.eatToEndOfStatement();
2352 return Error(Loc, ErrorStr);
2355 Parser.Lex(); // Eat the comma.
2359 bool MipsAsmParser::parseDirectiveCPLoad(SMLoc Loc) {
2360 if (Options.isReorder())
2361 Warning(Loc, ".cpload in reorder section");
2363 // FIXME: Warn if cpload is used in Mips16 mode.
2365 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Reg;
2366 OperandMatchResultTy ResTy = ParseAnyRegister(Reg);
2367 if (ResTy == MatchOperand_NoMatch || ResTy == MatchOperand_ParseFail) {
2368 reportParseError("expected register containing function address");
2372 MipsOperand &RegOpnd = static_cast<MipsOperand &>(*Reg[0]);
2373 if (!RegOpnd.isGPRAsmReg()) {
2374 reportParseError(RegOpnd.getStartLoc(), "invalid register");
2378 getTargetStreamer().emitDirectiveCpload(RegOpnd.getGPR32Reg());
2382 bool MipsAsmParser::parseDirectiveCPSetup() {
2385 bool SaveIsReg = true;
2387 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> TmpReg;
2388 OperandMatchResultTy ResTy = ParseAnyRegister(TmpReg);
2389 if (ResTy == MatchOperand_NoMatch) {
2390 reportParseError("expected register containing function address");
2391 Parser.eatToEndOfStatement();
2395 MipsOperand &FuncRegOpnd = static_cast<MipsOperand &>(*TmpReg[0]);
2396 if (!FuncRegOpnd.isGPRAsmReg()) {
2397 reportParseError(FuncRegOpnd.getStartLoc(), "invalid register");
2398 Parser.eatToEndOfStatement();
2402 FuncReg = FuncRegOpnd.getGPR32Reg();
2405 if (!eatComma("expected comma parsing directive"))
2408 ResTy = ParseAnyRegister(TmpReg);
2409 if (ResTy == MatchOperand_NoMatch) {
2410 const AsmToken &Tok = Parser.getTok();
2411 if (Tok.is(AsmToken::Integer)) {
2412 Save = Tok.getIntVal();
2416 reportParseError("expected save register or stack offset");
2417 Parser.eatToEndOfStatement();
2421 MipsOperand &SaveOpnd = static_cast<MipsOperand &>(*TmpReg[0]);
2422 if (!SaveOpnd.isGPRAsmReg()) {
2423 reportParseError(SaveOpnd.getStartLoc(), "invalid register");
2424 Parser.eatToEndOfStatement();
2427 Save = SaveOpnd.getGPR32Reg();
2430 if (!eatComma("expected comma parsing directive"))
2434 if (Parser.parseIdentifier(Name))
2435 reportParseError("expected identifier");
2436 MCSymbol *Sym = getContext().GetOrCreateSymbol(Name);
2438 getTargetStreamer().emitDirectiveCpsetup(FuncReg, Save, *Sym, SaveIsReg);
2442 bool MipsAsmParser::parseDirectiveNaN() {
2443 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2444 const AsmToken &Tok = Parser.getTok();
2446 if (Tok.getString() == "2008") {
2448 getTargetStreamer().emitDirectiveNaN2008();
2450 } else if (Tok.getString() == "legacy") {
2452 getTargetStreamer().emitDirectiveNaNLegacy();
2456 // If we don't recognize the option passed to the .nan
2457 // directive (e.g. no option or unknown option), emit an error.
2458 reportParseError("invalid option in .nan directive");
2462 bool MipsAsmParser::parseDirectiveSet() {
2464 // Get the next token.
2465 const AsmToken &Tok = Parser.getTok();
2467 if (Tok.getString() == "noat") {
2468 return parseSetNoAtDirective();
2469 } else if (Tok.getString() == "at") {
2470 return parseSetAtDirective();
2471 } else if (Tok.getString() == "reorder") {
2472 return parseSetReorderDirective();
2473 } else if (Tok.getString() == "noreorder") {
2474 return parseSetNoReorderDirective();
2475 } else if (Tok.getString() == "macro") {
2476 return parseSetMacroDirective();
2477 } else if (Tok.getString() == "nomacro") {
2478 return parseSetNoMacroDirective();
2479 } else if (Tok.getString() == "mips16") {
2480 return parseSetFeature(Mips::FeatureMips16);
2481 } else if (Tok.getString() == "nomips16") {
2482 return parseSetNoMips16Directive();
2483 } else if (Tok.getString() == "nomicromips") {
2484 getTargetStreamer().emitDirectiveSetNoMicroMips();
2485 Parser.eatToEndOfStatement();
2487 } else if (Tok.getString() == "micromips") {
2488 return parseSetFeature(Mips::FeatureMicroMips);
2489 } else if (Tok.getString() == "mips32r2") {
2490 return parseSetFeature(Mips::FeatureMips32r2);
2491 } else if (Tok.getString() == "mips64") {
2492 return parseSetFeature(Mips::FeatureMips64);
2493 } else if (Tok.getString() == "mips64r2") {
2494 return parseSetFeature(Mips::FeatureMips64r2);
2495 } else if (Tok.getString() == "dsp") {
2496 return parseSetFeature(Mips::FeatureDSP);
2498 // It is just an identifier, look for an assignment.
2499 parseSetAssignment();
2506 /// parseDataDirective
2507 /// ::= .word [ expression (, expression)* ]
2508 bool MipsAsmParser::parseDataDirective(unsigned Size, SMLoc L) {
2509 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2511 const MCExpr *Value;
2512 if (getParser().parseExpression(Value))
2515 getParser().getStreamer().EmitValue(Value, Size);
2517 if (getLexer().is(AsmToken::EndOfStatement))
2520 // FIXME: Improve diagnostic.
2521 if (getLexer().isNot(AsmToken::Comma))
2522 return Error(L, "unexpected token in directive");
2531 /// parseDirectiveGpWord
2532 /// ::= .gpword local_sym
2533 bool MipsAsmParser::parseDirectiveGpWord() {
2534 const MCExpr *Value;
2535 // EmitGPRel32Value requires an expression, so we are using base class
2536 // method to evaluate the expression.
2537 if (getParser().parseExpression(Value))
2539 getParser().getStreamer().EmitGPRel32Value(Value);
2541 if (getLexer().isNot(AsmToken::EndOfStatement))
2542 return Error(getLexer().getLoc(), "unexpected token in directive");
2543 Parser.Lex(); // Eat EndOfStatement token.
2547 /// parseDirectiveGpDWord
2548 /// ::= .gpdword local_sym
2549 bool MipsAsmParser::parseDirectiveGpDWord() {
2550 const MCExpr *Value;
2551 // EmitGPRel64Value requires an expression, so we are using base class
2552 // method to evaluate the expression.
2553 if (getParser().parseExpression(Value))
2555 getParser().getStreamer().EmitGPRel64Value(Value);
2557 if (getLexer().isNot(AsmToken::EndOfStatement))
2558 return Error(getLexer().getLoc(), "unexpected token in directive");
2559 Parser.Lex(); // Eat EndOfStatement token.
2563 bool MipsAsmParser::parseDirectiveOption() {
2564 // Get the option token.
2565 AsmToken Tok = Parser.getTok();
2566 // At the moment only identifiers are supported.
2567 if (Tok.isNot(AsmToken::Identifier)) {
2568 Error(Parser.getTok().getLoc(), "unexpected token in .option directive");
2569 Parser.eatToEndOfStatement();
2573 StringRef Option = Tok.getIdentifier();
2575 if (Option == "pic0") {
2576 getTargetStreamer().emitDirectiveOptionPic0();
2578 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
2579 Error(Parser.getTok().getLoc(),
2580 "unexpected token in .option pic0 directive");
2581 Parser.eatToEndOfStatement();
2586 if (Option == "pic2") {
2587 getTargetStreamer().emitDirectiveOptionPic2();
2589 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
2590 Error(Parser.getTok().getLoc(),
2591 "unexpected token in .option pic2 directive");
2592 Parser.eatToEndOfStatement();
2598 Warning(Parser.getTok().getLoc(), "unknown option in .option directive");
2599 Parser.eatToEndOfStatement();
2603 bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) {
2604 StringRef IDVal = DirectiveID.getString();
2606 if (IDVal == ".cpload")
2607 return parseDirectiveCPLoad(DirectiveID.getLoc());
2608 if (IDVal == ".dword") {
2609 parseDataDirective(8, DirectiveID.getLoc());
2613 if (IDVal == ".ent") {
2614 // Ignore this directive for now.
2619 if (IDVal == ".end") {
2620 // Ignore this directive for now.
2625 if (IDVal == ".frame") {
2626 // Ignore this directive for now.
2627 Parser.eatToEndOfStatement();
2631 if (IDVal == ".set") {
2632 return parseDirectiveSet();
2635 if (IDVal == ".fmask") {
2636 // Ignore this directive for now.
2637 Parser.eatToEndOfStatement();
2641 if (IDVal == ".mask") {
2642 // Ignore this directive for now.
2643 Parser.eatToEndOfStatement();
2647 if (IDVal == ".nan")
2648 return parseDirectiveNaN();
2650 if (IDVal == ".gpword") {
2651 parseDirectiveGpWord();
2655 if (IDVal == ".gpdword") {
2656 parseDirectiveGpDWord();
2660 if (IDVal == ".word") {
2661 parseDataDirective(4, DirectiveID.getLoc());
2665 if (IDVal == ".option")
2666 return parseDirectiveOption();
2668 if (IDVal == ".abicalls") {
2669 getTargetStreamer().emitDirectiveAbiCalls();
2670 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
2671 Error(Parser.getTok().getLoc(), "unexpected token in directive");
2673 Parser.eatToEndOfStatement();
2678 if (IDVal == ".cpsetup")
2679 return parseDirectiveCPSetup();
2684 extern "C" void LLVMInitializeMipsAsmParser() {
2685 RegisterMCAsmParser<MipsAsmParser> X(TheMipsTarget);
2686 RegisterMCAsmParser<MipsAsmParser> Y(TheMipselTarget);
2687 RegisterMCAsmParser<MipsAsmParser> A(TheMips64Target);
2688 RegisterMCAsmParser<MipsAsmParser> B(TheMips64elTarget);
2691 #define GET_REGISTER_MATCHER
2692 #define GET_MATCHER_IMPLEMENTATION
2693 #include "MipsGenAsmMatcher.inc"