1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/MipsMCExpr.h"
11 #include "MCTargetDesc/MipsMCTargetDesc.h"
12 #include "MipsRegisterInfo.h"
13 #include "MipsTargetStreamer.h"
14 #include "llvm/ADT/APInt.h"
15 #include "llvm/ADT/StringSwitch.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstBuilder.h"
20 #include "llvm/MC/MCParser/MCAsmLexer.h"
21 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
22 #include "llvm/MC/MCStreamer.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCSymbol.h"
25 #include "llvm/MC/MCTargetAsmParser.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Support/TargetRegistry.h"
37 class MipsAssemblerOptions {
39 MipsAssemblerOptions() : aTReg(1), reorder(true), macro(true) {}
41 unsigned getATRegNum() { return aTReg; }
42 bool setATReg(unsigned Reg);
44 bool isReorder() { return reorder; }
45 void setReorder() { reorder = true; }
46 void setNoreorder() { reorder = false; }
48 bool isMacro() { return macro; }
49 void setMacro() { macro = true; }
50 void setNomacro() { macro = false; }
60 class MipsAsmParser : public MCTargetAsmParser {
61 MipsTargetStreamer &getTargetStreamer() {
62 MCTargetStreamer &TS = *Parser.getStreamer().getTargetStreamer();
63 return static_cast<MipsTargetStreamer &>(TS);
68 MipsAssemblerOptions Options;
70 #define GET_ASSEMBLER_HEADER
71 #include "MipsGenAsmMatcher.inc"
73 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
74 SmallVectorImpl<MCParsedAsmOperand *> &Operands,
75 MCStreamer &Out, unsigned &ErrorInfo,
76 bool MatchingInlineAsm);
78 /// Parse a register as used in CFI directives
79 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
81 bool ParseParenSuffix(StringRef Name,
82 SmallVectorImpl<MCParsedAsmOperand *> &Operands);
84 bool ParseBracketSuffix(StringRef Name,
85 SmallVectorImpl<MCParsedAsmOperand *> &Operands);
87 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
89 SmallVectorImpl<MCParsedAsmOperand *> &Operands);
91 bool ParseDirective(AsmToken DirectiveID);
93 MipsAsmParser::OperandMatchResultTy
94 parseMemOperand(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
96 MipsAsmParser::OperandMatchResultTy MatchAnyRegisterNameWithoutDollar(
97 SmallVectorImpl<MCParsedAsmOperand *> &Operands, StringRef Identifier,
100 MipsAsmParser::OperandMatchResultTy
101 ParseAnyRegisterWithoutDollar(SmallVectorImpl<MCParsedAsmOperand *> &Operands,
104 MipsAsmParser::OperandMatchResultTy
105 ParseAnyRegister(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
107 MipsAsmParser::OperandMatchResultTy
108 ParseImm(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
110 MipsAsmParser::OperandMatchResultTy
111 ParseJumpTarget(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
113 MipsAsmParser::OperandMatchResultTy
114 parseInvNum(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
116 MipsAsmParser::OperandMatchResultTy
117 ParseLSAImm(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
119 bool searchSymbolAlias(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
121 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand *> &,
124 bool needsExpansion(MCInst &Inst);
126 void expandInstruction(MCInst &Inst, SMLoc IDLoc,
127 SmallVectorImpl<MCInst> &Instructions);
128 void expandLoadImm(MCInst &Inst, SMLoc IDLoc,
129 SmallVectorImpl<MCInst> &Instructions);
130 void expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
131 SmallVectorImpl<MCInst> &Instructions);
132 void expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
133 SmallVectorImpl<MCInst> &Instructions);
134 void expandMemInst(MCInst &Inst, SMLoc IDLoc,
135 SmallVectorImpl<MCInst> &Instructions, bool isLoad,
137 bool reportParseError(StringRef ErrorMsg);
139 bool parseMemOffset(const MCExpr *&Res, bool isParenExpr);
140 bool parseRelocOperand(const MCExpr *&Res);
142 const MCExpr *evaluateRelocExpr(const MCExpr *Expr, StringRef RelocStr);
144 bool isEvaluated(const MCExpr *Expr);
145 bool parseSetFeature(uint64_t Feature);
146 bool parseDirectiveCPSetup();
147 bool parseDirectiveSet();
148 bool parseDirectiveOption();
150 bool parseSetAtDirective();
151 bool parseSetNoAtDirective();
152 bool parseSetMacroDirective();
153 bool parseSetNoMacroDirective();
154 bool parseSetReorderDirective();
155 bool parseSetNoReorderDirective();
156 bool parseSetNoMips16Directive();
158 bool parseSetAssignment();
160 bool parseDataDirective(unsigned Size, SMLoc L);
161 bool parseDirectiveGpWord();
162 bool parseDirectiveGpDWord();
164 MCSymbolRefExpr::VariantKind getVariantKind(StringRef Symbol);
166 bool isGP64() const {
167 return (STI.getFeatureBits() & Mips::FeatureGP64Bit) != 0;
170 bool isFP64() const {
171 return (STI.getFeatureBits() & Mips::FeatureFP64Bit) != 0;
174 bool isN32() const { return STI.getFeatureBits() & Mips::FeatureN32; }
175 bool isN64() const { return STI.getFeatureBits() & Mips::FeatureN64; }
177 bool isMicroMips() const {
178 return STI.getFeatureBits() & Mips::FeatureMicroMips;
181 bool parseRegister(unsigned &RegNum);
183 bool eatComma(StringRef ErrorStr);
185 int matchCPURegisterName(StringRef Symbol);
187 int matchRegisterByNumber(unsigned RegNum, unsigned RegClass);
189 int matchFPURegisterName(StringRef Name);
191 int matchFCCRegisterName(StringRef Name);
193 int matchACRegisterName(StringRef Name);
195 int matchMSA128RegisterName(StringRef Name);
197 int matchMSA128CtrlRegisterName(StringRef Name);
199 unsigned getReg(int RC, int RegNo);
201 unsigned getGPR(int RegNo);
205 bool processInstruction(MCInst &Inst, SMLoc IDLoc,
206 SmallVectorImpl<MCInst> &Instructions);
208 // Helper function that checks if the value of a vector index is within the
209 // boundaries of accepted values for each RegisterKind
210 // Example: INSERT.B $w0[n], $1 => 16 > n >= 0
211 bool validateMSAIndex(int Val, int RegKind);
213 void setFeatureBits(unsigned Feature, StringRef FeatureString) {
214 if (!(STI.getFeatureBits() & Feature)) {
215 setAvailableFeatures(ComputeAvailableFeatures(
216 STI.ToggleFeature(FeatureString)));
220 void clearFeatureBits(unsigned Feature, StringRef FeatureString) {
221 if (STI.getFeatureBits() & Feature) {
222 setAvailableFeatures(ComputeAvailableFeatures(
223 STI.ToggleFeature(FeatureString)));
228 MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
229 const MCInstrInfo &MII)
230 : MCTargetAsmParser(), STI(sti), Parser(parser) {
231 // Initialize the set of available features.
232 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
234 // Assert exactly one ABI was chosen.
235 assert((((STI.getFeatureBits() & Mips::FeatureO32) != 0) +
236 ((STI.getFeatureBits() & Mips::FeatureEABI) != 0) +
237 ((STI.getFeatureBits() & Mips::FeatureN32) != 0) +
238 ((STI.getFeatureBits() & Mips::FeatureN64) != 0)) == 1);
241 MCAsmParser &getParser() const { return Parser; }
242 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
244 /// Warn if RegNo is the current assembler temporary.
245 void WarnIfAssemblerTemporary(int RegNo, SMLoc Loc);
251 /// MipsOperand - Instances of this class represent a parsed Mips machine
253 class MipsOperand : public MCParsedAsmOperand {
255 /// Broad categories of register classes
256 /// The exact class is finalized by the render method.
258 RegKind_GPR = 1, /// GPR32 and GPR64 (depending on isGP64())
259 RegKind_FGR = 2, /// FGR32, FGR64, AFGR64 (depending on context and
261 RegKind_FCC = 4, /// FCC
262 RegKind_MSA128 = 8, /// MSA128[BHWD] (makes no difference which)
263 RegKind_MSACtrl = 16, /// MSA control registers
264 RegKind_COP2 = 32, /// COP2
265 RegKind_ACC = 64, /// HI32DSP, LO32DSP, and ACC64DSP (depending on
267 RegKind_CCR = 128, /// CCR
268 RegKind_HWRegs = 256, /// HWRegs
270 /// Potentially any (e.g. $1)
271 RegKind_Numeric = RegKind_GPR | RegKind_FGR | RegKind_FCC | RegKind_MSA128 |
272 RegKind_MSACtrl | RegKind_COP2 | RegKind_ACC |
273 RegKind_CCR | RegKind_HWRegs
285 MipsOperand(KindTy K, MipsAsmParser &Parser)
286 : MCParsedAsmOperand(), Kind(K), AsmParser(Parser) {}
288 /// For diagnostics, and checking the assembler temporary
289 MipsAsmParser &AsmParser;
297 unsigned Num; /// Register Number
301 unsigned Index; /// Index into the register class
302 RegKind Kind; /// Bitfield of the kinds it could possibly be
303 const MCRegisterInfo *RegInfo;
317 struct PhysRegOp PhysReg;
318 struct RegIdxOp RegIdx;
323 SMLoc StartLoc, EndLoc;
325 /// Internal constructor for register kinds
326 static MipsOperand *CreateReg(unsigned Index, RegKind RegKind,
327 const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E,
328 MipsAsmParser &Parser) {
329 MipsOperand *Op = new MipsOperand(k_RegisterIndex, Parser);
330 Op->RegIdx.Index = Index;
331 Op->RegIdx.RegInfo = RegInfo;
332 Op->RegIdx.Kind = RegKind;
339 /// Coerce the register to GPR32 and return the real register for the current
341 unsigned getGPR32Reg() const {
342 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
343 AsmParser.WarnIfAssemblerTemporary(RegIdx.Index, StartLoc);
344 unsigned ClassID = Mips::GPR32RegClassID;
345 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
348 /// Coerce the register to GPR64 and return the real register for the current
350 unsigned getGPR64Reg() const {
351 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
352 unsigned ClassID = Mips::GPR64RegClassID;
353 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
357 /// Coerce the register to AFGR64 and return the real register for the current
359 unsigned getAFGR64Reg() const {
360 assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
361 if (RegIdx.Index % 2 != 0)
362 AsmParser.Warning(StartLoc, "Float register should be even.");
363 return RegIdx.RegInfo->getRegClass(Mips::AFGR64RegClassID)
364 .getRegister(RegIdx.Index / 2);
367 /// Coerce the register to FGR64 and return the real register for the current
369 unsigned getFGR64Reg() const {
370 assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
371 return RegIdx.RegInfo->getRegClass(Mips::FGR64RegClassID)
372 .getRegister(RegIdx.Index);
375 /// Coerce the register to FGR32 and return the real register for the current
377 unsigned getFGR32Reg() const {
378 assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
379 return RegIdx.RegInfo->getRegClass(Mips::FGR32RegClassID)
380 .getRegister(RegIdx.Index);
383 /// Coerce the register to FGRH32 and return the real register for the current
385 unsigned getFGRH32Reg() const {
386 assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
387 return RegIdx.RegInfo->getRegClass(Mips::FGRH32RegClassID)
388 .getRegister(RegIdx.Index);
391 /// Coerce the register to FCC and return the real register for the current
393 unsigned getFCCReg() const {
394 assert(isRegIdx() && (RegIdx.Kind & RegKind_FCC) && "Invalid access!");
395 return RegIdx.RegInfo->getRegClass(Mips::FCCRegClassID)
396 .getRegister(RegIdx.Index);
399 /// Coerce the register to MSA128 and return the real register for the current
401 unsigned getMSA128Reg() const {
402 assert(isRegIdx() && (RegIdx.Kind & RegKind_MSA128) && "Invalid access!");
403 // It doesn't matter which of the MSA128[BHWD] classes we use. They are all
405 unsigned ClassID = Mips::MSA128BRegClassID;
406 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
409 /// Coerce the register to MSACtrl and return the real register for the
411 unsigned getMSACtrlReg() const {
412 assert(isRegIdx() && (RegIdx.Kind & RegKind_MSACtrl) && "Invalid access!");
413 unsigned ClassID = Mips::MSACtrlRegClassID;
414 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
417 /// Coerce the register to COP2 and return the real register for the
419 unsigned getCOP2Reg() const {
420 assert(isRegIdx() && (RegIdx.Kind & RegKind_COP2) && "Invalid access!");
421 unsigned ClassID = Mips::COP2RegClassID;
422 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
425 /// Coerce the register to ACC64DSP and return the real register for the
427 unsigned getACC64DSPReg() const {
428 assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");
429 unsigned ClassID = Mips::ACC64DSPRegClassID;
430 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
433 /// Coerce the register to HI32DSP and return the real register for the
435 unsigned getHI32DSPReg() const {
436 assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");
437 unsigned ClassID = Mips::HI32DSPRegClassID;
438 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
441 /// Coerce the register to LO32DSP and return the real register for the
443 unsigned getLO32DSPReg() const {
444 assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");
445 unsigned ClassID = Mips::LO32DSPRegClassID;
446 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
449 /// Coerce the register to CCR and return the real register for the
451 unsigned getCCRReg() const {
452 assert(isRegIdx() && (RegIdx.Kind & RegKind_CCR) && "Invalid access!");
453 unsigned ClassID = Mips::CCRRegClassID;
454 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
457 /// Coerce the register to HWRegs and return the real register for the
459 unsigned getHWRegsReg() const {
460 assert(isRegIdx() && (RegIdx.Kind & RegKind_HWRegs) && "Invalid access!");
461 unsigned ClassID = Mips::HWRegsRegClassID;
462 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
466 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
467 // Add as immediate when possible. Null MCExpr = 0.
469 Inst.addOperand(MCOperand::CreateImm(0));
470 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
471 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
473 Inst.addOperand(MCOperand::CreateExpr(Expr));
476 void addRegOperands(MCInst &Inst, unsigned N) const {
477 llvm_unreachable("Use a custom parser instead");
480 void addGPR32AsmRegOperands(MCInst &Inst, unsigned N) const {
481 assert(N == 1 && "Invalid number of operands!");
482 Inst.addOperand(MCOperand::CreateReg(getGPR32Reg()));
485 void addGPR64AsmRegOperands(MCInst &Inst, unsigned N) const {
486 assert(N == 1 && "Invalid number of operands!");
487 Inst.addOperand(MCOperand::CreateReg(getGPR64Reg()));
490 void addAFGR64AsmRegOperands(MCInst &Inst, unsigned N) const {
491 assert(N == 1 && "Invalid number of operands!");
492 Inst.addOperand(MCOperand::CreateReg(getAFGR64Reg()));
495 void addFGR64AsmRegOperands(MCInst &Inst, unsigned N) const {
496 assert(N == 1 && "Invalid number of operands!");
497 Inst.addOperand(MCOperand::CreateReg(getFGR64Reg()));
500 void addFGR32AsmRegOperands(MCInst &Inst, unsigned N) const {
501 assert(N == 1 && "Invalid number of operands!");
502 Inst.addOperand(MCOperand::CreateReg(getFGR32Reg()));
505 void addFGRH32AsmRegOperands(MCInst &Inst, unsigned N) const {
506 assert(N == 1 && "Invalid number of operands!");
507 Inst.addOperand(MCOperand::CreateReg(getFGRH32Reg()));
510 void addFCCAsmRegOperands(MCInst &Inst, unsigned N) const {
511 assert(N == 1 && "Invalid number of operands!");
512 Inst.addOperand(MCOperand::CreateReg(getFCCReg()));
515 void addMSA128AsmRegOperands(MCInst &Inst, unsigned N) const {
516 assert(N == 1 && "Invalid number of operands!");
517 Inst.addOperand(MCOperand::CreateReg(getMSA128Reg()));
520 void addMSACtrlAsmRegOperands(MCInst &Inst, unsigned N) const {
521 assert(N == 1 && "Invalid number of operands!");
522 Inst.addOperand(MCOperand::CreateReg(getMSACtrlReg()));
525 void addCOP2AsmRegOperands(MCInst &Inst, unsigned N) const {
526 assert(N == 1 && "Invalid number of operands!");
527 Inst.addOperand(MCOperand::CreateReg(getCOP2Reg()));
530 void addACC64DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
531 assert(N == 1 && "Invalid number of operands!");
532 Inst.addOperand(MCOperand::CreateReg(getACC64DSPReg()));
535 void addHI32DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
536 assert(N == 1 && "Invalid number of operands!");
537 Inst.addOperand(MCOperand::CreateReg(getHI32DSPReg()));
540 void addLO32DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
541 assert(N == 1 && "Invalid number of operands!");
542 Inst.addOperand(MCOperand::CreateReg(getLO32DSPReg()));
545 void addCCRAsmRegOperands(MCInst &Inst, unsigned N) const {
546 assert(N == 1 && "Invalid number of operands!");
547 Inst.addOperand(MCOperand::CreateReg(getCCRReg()));
550 void addHWRegsAsmRegOperands(MCInst &Inst, unsigned N) const {
551 assert(N == 1 && "Invalid number of operands!");
552 Inst.addOperand(MCOperand::CreateReg(getHWRegsReg()));
555 void addImmOperands(MCInst &Inst, unsigned N) const {
556 assert(N == 1 && "Invalid number of operands!");
557 const MCExpr *Expr = getImm();
561 void addMemOperands(MCInst &Inst, unsigned N) const {
562 assert(N == 2 && "Invalid number of operands!");
564 Inst.addOperand(MCOperand::CreateReg(getMemBase()->getGPR32Reg()));
566 const MCExpr *Expr = getMemOff();
571 // As a special case until we sort out the definition of div/divu, pretend
572 // that $0/$zero are k_PhysRegister so that MCK_ZERO works correctly.
573 if (isGPRAsmReg() && RegIdx.Index == 0)
576 return Kind == k_PhysRegister;
578 bool isRegIdx() const { return Kind == k_RegisterIndex; }
579 bool isImm() const { return Kind == k_Immediate; }
580 bool isConstantImm() const {
581 return isImm() && dyn_cast<MCConstantExpr>(getImm());
583 bool isToken() const {
584 // Note: It's not possible to pretend that other operand kinds are tokens.
585 // The matcher emitter checks tokens first.
586 return Kind == k_Token;
588 bool isMem() const { return Kind == k_Memory; }
589 bool isInvNum() const { return Kind == k_Immediate; }
590 bool isLSAImm() const {
591 if (!isConstantImm())
593 int64_t Val = getConstantImm();
594 return 1 <= Val && Val <= 4;
597 StringRef getToken() const {
598 assert(Kind == k_Token && "Invalid access!");
599 return StringRef(Tok.Data, Tok.Length);
602 unsigned getReg() const {
603 // As a special case until we sort out the definition of div/divu, pretend
604 // that $0/$zero are k_PhysRegister so that MCK_ZERO works correctly.
605 if (Kind == k_RegisterIndex && RegIdx.Index == 0 &&
606 RegIdx.Kind & RegKind_GPR)
607 return getGPR32Reg(); // FIXME: GPR64 too
609 assert(Kind == k_PhysRegister && "Invalid access!");
613 const MCExpr *getImm() const {
614 assert((Kind == k_Immediate) && "Invalid access!");
618 int64_t getConstantImm() const {
619 const MCExpr *Val = getImm();
620 return static_cast<const MCConstantExpr *>(Val)->getValue();
623 MipsOperand *getMemBase() const {
624 assert((Kind == k_Memory) && "Invalid access!");
628 const MCExpr *getMemOff() const {
629 assert((Kind == k_Memory) && "Invalid access!");
633 static MipsOperand *CreateToken(StringRef Str, SMLoc S,
634 MipsAsmParser &Parser) {
635 MipsOperand *Op = new MipsOperand(k_Token, Parser);
636 Op->Tok.Data = Str.data();
637 Op->Tok.Length = Str.size();
643 /// Create a numeric register (e.g. $1). The exact register remains
644 /// unresolved until an instruction successfully matches
645 static MipsOperand *CreateNumericReg(unsigned Index,
646 const MCRegisterInfo *RegInfo, SMLoc S,
647 SMLoc E, MipsAsmParser &Parser) {
648 DEBUG(dbgs() << "CreateNumericReg(" << Index << ", ...)\n");
649 return CreateReg(Index, RegKind_Numeric, RegInfo, S, E, Parser);
652 /// Create a register that is definitely a GPR.
653 /// This is typically only used for named registers such as $gp.
654 static MipsOperand *CreateGPRReg(unsigned Index,
655 const MCRegisterInfo *RegInfo, SMLoc S,
656 SMLoc E, MipsAsmParser &Parser) {
657 return CreateReg(Index, RegKind_GPR, RegInfo, S, E, Parser);
660 /// Create a register that is definitely a FGR.
661 /// This is typically only used for named registers such as $f0.
662 static MipsOperand *CreateFGRReg(unsigned Index,
663 const MCRegisterInfo *RegInfo, SMLoc S,
664 SMLoc E, MipsAsmParser &Parser) {
665 return CreateReg(Index, RegKind_FGR, RegInfo, S, E, Parser);
668 /// Create a register that is definitely an FCC.
669 /// This is typically only used for named registers such as $fcc0.
670 static MipsOperand *CreateFCCReg(unsigned Index,
671 const MCRegisterInfo *RegInfo, SMLoc S,
672 SMLoc E, MipsAsmParser &Parser) {
673 return CreateReg(Index, RegKind_FCC, RegInfo, S, E, Parser);
676 /// Create a register that is definitely an ACC.
677 /// This is typically only used for named registers such as $ac0.
678 static MipsOperand *CreateACCReg(unsigned Index,
679 const MCRegisterInfo *RegInfo, SMLoc S,
680 SMLoc E, MipsAsmParser &Parser) {
681 return CreateReg(Index, RegKind_ACC, RegInfo, S, E, Parser);
684 /// Create a register that is definitely an MSA128.
685 /// This is typically only used for named registers such as $w0.
686 static MipsOperand *CreateMSA128Reg(unsigned Index,
687 const MCRegisterInfo *RegInfo, SMLoc S,
688 SMLoc E, MipsAsmParser &Parser) {
689 return CreateReg(Index, RegKind_MSA128, RegInfo, S, E, Parser);
692 /// Create a register that is definitely an MSACtrl.
693 /// This is typically only used for named registers such as $msaaccess.
694 static MipsOperand *CreateMSACtrlReg(unsigned Index,
695 const MCRegisterInfo *RegInfo, SMLoc S,
696 SMLoc E, MipsAsmParser &Parser) {
697 return CreateReg(Index, RegKind_MSACtrl, RegInfo, S, E, Parser);
700 static MipsOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E,
701 MipsAsmParser &Parser) {
702 MipsOperand *Op = new MipsOperand(k_Immediate, Parser);
709 static MipsOperand *CreateMem(MipsOperand *Base, const MCExpr *Off, SMLoc S,
710 SMLoc E, MipsAsmParser &Parser) {
711 MipsOperand *Op = new MipsOperand(k_Memory, Parser);
719 bool isGPRAsmReg() const {
720 return isRegIdx() && RegIdx.Kind & RegKind_GPR && RegIdx.Index <= 31;
722 bool isFGRAsmReg() const {
723 // AFGR64 is $0-$15 but we handle this in getAFGR64()
724 return isRegIdx() && RegIdx.Kind & RegKind_FGR && RegIdx.Index <= 31;
726 bool isHWRegsAsmReg() const {
727 return isRegIdx() && RegIdx.Kind & RegKind_HWRegs && RegIdx.Index <= 31;
729 bool isCCRAsmReg() const {
730 return isRegIdx() && RegIdx.Kind & RegKind_CCR && RegIdx.Index <= 31;
732 bool isFCCAsmReg() const {
733 return isRegIdx() && RegIdx.Kind & RegKind_FCC && RegIdx.Index <= 7;
735 bool isACCAsmReg() const {
736 return isRegIdx() && RegIdx.Kind & RegKind_ACC && RegIdx.Index <= 3;
738 bool isCOP2AsmReg() const {
739 return isRegIdx() && RegIdx.Kind & RegKind_COP2 && RegIdx.Index <= 31;
741 bool isMSA128AsmReg() const {
742 return isRegIdx() && RegIdx.Kind & RegKind_MSA128 && RegIdx.Index <= 31;
744 bool isMSACtrlAsmReg() const {
745 return isRegIdx() && RegIdx.Kind & RegKind_MSACtrl && RegIdx.Index <= 7;
748 /// getStartLoc - Get the location of the first token of this operand.
749 SMLoc getStartLoc() const { return StartLoc; }
750 /// getEndLoc - Get the location of the last token of this operand.
751 SMLoc getEndLoc() const { return EndLoc; }
753 virtual void print(raw_ostream &OS) const {
768 OS << "PhysReg<" << PhysReg.Num << ">";
770 case k_RegisterIndex:
771 OS << "RegIdx<" << RegIdx.Index << ":" << RegIdx.Kind << ">";
778 }; // class MipsOperand
782 extern const MCInstrDesc MipsInsts[];
784 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
785 return MipsInsts[Opcode];
788 bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
789 SmallVectorImpl<MCInst> &Instructions) {
790 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
794 if (MCID.isBranch() || MCID.isCall()) {
795 const unsigned Opcode = Inst.getOpcode();
805 assert(MCID.getNumOperands() == 3 && "unexpected number of operands");
806 Offset = Inst.getOperand(2);
808 break; // We'll deal with this situation later on when applying fixups.
809 if (!isIntN(isMicroMips() ? 17 : 18, Offset.getImm()))
810 return Error(IDLoc, "branch target out of range");
811 if (OffsetToAlignment(Offset.getImm(), 1LL << (isMicroMips() ? 1 : 2)))
812 return Error(IDLoc, "branch to misaligned address");
826 case Mips::BGEZAL_MM:
827 case Mips::BLTZAL_MM:
830 assert(MCID.getNumOperands() == 2 && "unexpected number of operands");
831 Offset = Inst.getOperand(1);
833 break; // We'll deal with this situation later on when applying fixups.
834 if (!isIntN(isMicroMips() ? 17 : 18, Offset.getImm()))
835 return Error(IDLoc, "branch target out of range");
836 if (OffsetToAlignment(Offset.getImm(), 1LL << (isMicroMips() ? 1 : 2)))
837 return Error(IDLoc, "branch to misaligned address");
842 if (MCID.hasDelaySlot() && Options.isReorder()) {
843 // If this instruction has a delay slot and .set reorder is active,
844 // emit a NOP after it.
845 Instructions.push_back(Inst);
847 NopInst.setOpcode(Mips::SLL);
848 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
849 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
850 NopInst.addOperand(MCOperand::CreateImm(0));
851 Instructions.push_back(NopInst);
855 if (MCID.mayLoad() || MCID.mayStore()) {
856 // Check the offset of memory operand, if it is a symbol
857 // reference or immediate we may have to expand instructions.
858 for (unsigned i = 0; i < MCID.getNumOperands(); i++) {
859 const MCOperandInfo &OpInfo = MCID.OpInfo[i];
860 if ((OpInfo.OperandType == MCOI::OPERAND_MEMORY) ||
861 (OpInfo.OperandType == MCOI::OPERAND_UNKNOWN)) {
862 MCOperand &Op = Inst.getOperand(i);
864 int MemOffset = Op.getImm();
865 if (MemOffset < -32768 || MemOffset > 32767) {
866 // Offset can't exceed 16bit value.
867 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), true);
870 } else if (Op.isExpr()) {
871 const MCExpr *Expr = Op.getExpr();
872 if (Expr->getKind() == MCExpr::SymbolRef) {
873 const MCSymbolRefExpr *SR =
874 static_cast<const MCSymbolRefExpr *>(Expr);
875 if (SR->getKind() == MCSymbolRefExpr::VK_None) {
877 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false);
880 } else if (!isEvaluated(Expr)) {
881 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false);
889 if (needsExpansion(Inst))
890 expandInstruction(Inst, IDLoc, Instructions);
892 Instructions.push_back(Inst);
897 bool MipsAsmParser::needsExpansion(MCInst &Inst) {
899 switch (Inst.getOpcode()) {
900 case Mips::LoadImm32Reg:
901 case Mips::LoadAddr32Imm:
902 case Mips::LoadAddr32Reg:
913 void MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
914 SmallVectorImpl<MCInst> &Instructions) {
915 switch (Inst.getOpcode()) {
916 case Mips::LoadImm32Reg:
917 return expandLoadImm(Inst, IDLoc, Instructions);
918 case Mips::LoadAddr32Imm:
919 return expandLoadAddressImm(Inst, IDLoc, Instructions);
920 case Mips::LoadAddr32Reg:
921 return expandLoadAddressReg(Inst, IDLoc, Instructions);
923 Instructions.push_back(MCInstBuilder(Mips::ADDi)
924 .addReg(Inst.getOperand(0).getReg())
925 .addReg(Inst.getOperand(1).getReg())
926 .addImm(-Inst.getOperand(2).getImm()));
929 Instructions.push_back(MCInstBuilder(Mips::ADDiu)
930 .addReg(Inst.getOperand(0).getReg())
931 .addReg(Inst.getOperand(1).getReg())
932 .addImm(-Inst.getOperand(2).getImm()));
935 Instructions.push_back(MCInstBuilder(Mips::DADDi)
936 .addReg(Inst.getOperand(0).getReg())
937 .addReg(Inst.getOperand(1).getReg())
938 .addImm(-Inst.getOperand(2).getImm()));
941 Instructions.push_back(MCInstBuilder(Mips::DADDiu)
942 .addReg(Inst.getOperand(0).getReg())
943 .addReg(Inst.getOperand(1).getReg())
944 .addImm(-Inst.getOperand(2).getImm()));
949 void MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
950 SmallVectorImpl<MCInst> &Instructions) {
952 const MCOperand &ImmOp = Inst.getOperand(1);
953 assert(ImmOp.isImm() && "expected immediate operand kind");
954 const MCOperand &RegOp = Inst.getOperand(0);
955 assert(RegOp.isReg() && "expected register operand kind");
957 int ImmValue = ImmOp.getImm();
958 tmpInst.setLoc(IDLoc);
959 if (0 <= ImmValue && ImmValue <= 65535) {
960 // For 0 <= j <= 65535.
961 // li d,j => ori d,$zero,j
962 tmpInst.setOpcode(Mips::ORi);
963 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
964 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
965 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
966 Instructions.push_back(tmpInst);
967 } else if (ImmValue < 0 && ImmValue >= -32768) {
968 // For -32768 <= j < 0.
969 // li d,j => addiu d,$zero,j
970 tmpInst.setOpcode(Mips::ADDiu);
971 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
972 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
973 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
974 Instructions.push_back(tmpInst);
976 // For any other value of j that is representable as a 32-bit integer.
977 // li d,j => lui d,hi16(j)
979 tmpInst.setOpcode(Mips::LUi);
980 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
981 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
982 Instructions.push_back(tmpInst);
984 tmpInst.setOpcode(Mips::ORi);
985 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
986 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
987 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
988 tmpInst.setLoc(IDLoc);
989 Instructions.push_back(tmpInst);
994 MipsAsmParser::expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
995 SmallVectorImpl<MCInst> &Instructions) {
997 const MCOperand &ImmOp = Inst.getOperand(2);
998 assert(ImmOp.isImm() && "expected immediate operand kind");
999 const MCOperand &SrcRegOp = Inst.getOperand(1);
1000 assert(SrcRegOp.isReg() && "expected register operand kind");
1001 const MCOperand &DstRegOp = Inst.getOperand(0);
1002 assert(DstRegOp.isReg() && "expected register operand kind");
1003 int ImmValue = ImmOp.getImm();
1004 if (-32768 <= ImmValue && ImmValue <= 65535) {
1005 // For -32768 <= j <= 65535.
1006 // la d,j(s) => addiu d,s,j
1007 tmpInst.setOpcode(Mips::ADDiu);
1008 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1009 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
1010 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
1011 Instructions.push_back(tmpInst);
1013 // For any other value of j that is representable as a 32-bit integer.
1014 // la d,j(s) => lui d,hi16(j)
1017 tmpInst.setOpcode(Mips::LUi);
1018 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1019 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
1020 Instructions.push_back(tmpInst);
1022 tmpInst.setOpcode(Mips::ORi);
1023 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1024 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1025 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
1026 Instructions.push_back(tmpInst);
1028 tmpInst.setOpcode(Mips::ADDu);
1029 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1030 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1031 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
1032 Instructions.push_back(tmpInst);
1037 MipsAsmParser::expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
1038 SmallVectorImpl<MCInst> &Instructions) {
1040 const MCOperand &ImmOp = Inst.getOperand(1);
1041 assert(ImmOp.isImm() && "expected immediate operand kind");
1042 const MCOperand &RegOp = Inst.getOperand(0);
1043 assert(RegOp.isReg() && "expected register operand kind");
1044 int ImmValue = ImmOp.getImm();
1045 if (-32768 <= ImmValue && ImmValue <= 65535) {
1046 // For -32768 <= j <= 65535.
1047 // la d,j => addiu d,$zero,j
1048 tmpInst.setOpcode(Mips::ADDiu);
1049 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1050 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
1051 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
1052 Instructions.push_back(tmpInst);
1054 // For any other value of j that is representable as a 32-bit integer.
1055 // la d,j => lui d,hi16(j)
1057 tmpInst.setOpcode(Mips::LUi);
1058 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1059 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
1060 Instructions.push_back(tmpInst);
1062 tmpInst.setOpcode(Mips::ORi);
1063 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1064 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1065 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
1066 Instructions.push_back(tmpInst);
1070 void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc,
1071 SmallVectorImpl<MCInst> &Instructions,
1072 bool isLoad, bool isImmOpnd) {
1073 const MCSymbolRefExpr *SR;
1075 unsigned ImmOffset, HiOffset, LoOffset;
1076 const MCExpr *ExprOffset;
1078 unsigned AtRegNum = getReg(
1079 (isGP64()) ? Mips::GPR64RegClassID : Mips::GPR32RegClassID, getATReg());
1080 // 1st operand is either the source or destination register.
1081 assert(Inst.getOperand(0).isReg() && "expected register operand kind");
1082 unsigned RegOpNum = Inst.getOperand(0).getReg();
1083 // 2nd operand is the base register.
1084 assert(Inst.getOperand(1).isReg() && "expected register operand kind");
1085 unsigned BaseRegNum = Inst.getOperand(1).getReg();
1086 // 3rd operand is either an immediate or expression.
1088 assert(Inst.getOperand(2).isImm() && "expected immediate operand kind");
1089 ImmOffset = Inst.getOperand(2).getImm();
1090 LoOffset = ImmOffset & 0x0000ffff;
1091 HiOffset = (ImmOffset & 0xffff0000) >> 16;
1092 // If msb of LoOffset is 1(negative number) we must increment HiOffset.
1093 if (LoOffset & 0x8000)
1096 ExprOffset = Inst.getOperand(2).getExpr();
1097 // All instructions will have the same location.
1098 TempInst.setLoc(IDLoc);
1099 // 1st instruction in expansion is LUi. For load instruction we can use
1100 // the dst register as a temporary if base and dst are different,
1101 // but for stores we must use $at.
1102 TmpRegNum = (isLoad && (BaseRegNum != RegOpNum)) ? RegOpNum : AtRegNum;
1103 TempInst.setOpcode(Mips::LUi);
1104 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
1106 TempInst.addOperand(MCOperand::CreateImm(HiOffset));
1108 if (ExprOffset->getKind() == MCExpr::SymbolRef) {
1109 SR = static_cast<const MCSymbolRefExpr *>(ExprOffset);
1110 const MCSymbolRefExpr *HiExpr = MCSymbolRefExpr::Create(
1111 SR->getSymbol().getName(), MCSymbolRefExpr::VK_Mips_ABS_HI,
1113 TempInst.addOperand(MCOperand::CreateExpr(HiExpr));
1115 const MCExpr *HiExpr = evaluateRelocExpr(ExprOffset, "hi");
1116 TempInst.addOperand(MCOperand::CreateExpr(HiExpr));
1119 // Add the instruction to the list.
1120 Instructions.push_back(TempInst);
1121 // Prepare TempInst for next instruction.
1123 // Add temp register to base.
1124 TempInst.setOpcode(Mips::ADDu);
1125 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
1126 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
1127 TempInst.addOperand(MCOperand::CreateReg(BaseRegNum));
1128 Instructions.push_back(TempInst);
1130 // And finally, create original instruction with low part
1131 // of offset and new base.
1132 TempInst.setOpcode(Inst.getOpcode());
1133 TempInst.addOperand(MCOperand::CreateReg(RegOpNum));
1134 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
1136 TempInst.addOperand(MCOperand::CreateImm(LoOffset));
1138 if (ExprOffset->getKind() == MCExpr::SymbolRef) {
1139 const MCSymbolRefExpr *LoExpr = MCSymbolRefExpr::Create(
1140 SR->getSymbol().getName(), MCSymbolRefExpr::VK_Mips_ABS_LO,
1142 TempInst.addOperand(MCOperand::CreateExpr(LoExpr));
1144 const MCExpr *LoExpr = evaluateRelocExpr(ExprOffset, "lo");
1145 TempInst.addOperand(MCOperand::CreateExpr(LoExpr));
1148 Instructions.push_back(TempInst);
1152 bool MipsAsmParser::MatchAndEmitInstruction(
1153 SMLoc IDLoc, unsigned &Opcode,
1154 SmallVectorImpl<MCParsedAsmOperand *> &Operands, MCStreamer &Out,
1155 unsigned &ErrorInfo, bool MatchingInlineAsm) {
1157 SmallVector<MCInst, 8> Instructions;
1158 unsigned MatchResult =
1159 MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
1161 switch (MatchResult) {
1164 case Match_Success: {
1165 if (processInstruction(Inst, IDLoc, Instructions))
1167 for (unsigned i = 0; i < Instructions.size(); i++)
1168 Out.EmitInstruction(Instructions[i], STI);
1171 case Match_MissingFeature:
1172 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
1174 case Match_InvalidOperand: {
1175 SMLoc ErrorLoc = IDLoc;
1176 if (ErrorInfo != ~0U) {
1177 if (ErrorInfo >= Operands.size())
1178 return Error(IDLoc, "too few operands for instruction");
1180 ErrorLoc = ((MipsOperand *)Operands[ErrorInfo])->getStartLoc();
1181 if (ErrorLoc == SMLoc())
1185 return Error(ErrorLoc, "invalid operand for instruction");
1187 case Match_MnemonicFail:
1188 return Error(IDLoc, "invalid instruction");
1193 void MipsAsmParser::WarnIfAssemblerTemporary(int RegIndex, SMLoc Loc) {
1194 if ((RegIndex != 0) && ((int)Options.getATRegNum() == RegIndex)) {
1196 Warning(Loc, "Used $at without \".set noat\"");
1198 Warning(Loc, Twine("Used $") + Twine(RegIndex) + " with \".set at=$" +
1199 Twine(RegIndex) + "\"");
1203 int MipsAsmParser::matchCPURegisterName(StringRef Name) {
1206 CC = StringSwitch<unsigned>(Name)
1242 if (isN32() || isN64()) {
1243 // Although SGI documentation just cuts out t0-t3 for n32/n64,
1244 // GNU pushes the values of t0-t3 to override the o32/o64 values for t4-t7
1245 // We are supporting both cases, so for t0-t3 we'll just push them to t4-t7.
1246 if (8 <= CC && CC <= 11)
1250 CC = StringSwitch<unsigned>(Name)
1263 int MipsAsmParser::matchFPURegisterName(StringRef Name) {
1265 if (Name[0] == 'f') {
1266 StringRef NumString = Name.substr(1);
1268 if (NumString.getAsInteger(10, IntVal))
1269 return -1; // This is not an integer.
1270 if (IntVal > 31) // Maximum index for fpu register.
1277 int MipsAsmParser::matchFCCRegisterName(StringRef Name) {
1279 if (Name.startswith("fcc")) {
1280 StringRef NumString = Name.substr(3);
1282 if (NumString.getAsInteger(10, IntVal))
1283 return -1; // This is not an integer.
1284 if (IntVal > 7) // There are only 8 fcc registers.
1291 int MipsAsmParser::matchACRegisterName(StringRef Name) {
1293 if (Name.startswith("ac")) {
1294 StringRef NumString = Name.substr(2);
1296 if (NumString.getAsInteger(10, IntVal))
1297 return -1; // This is not an integer.
1298 if (IntVal > 3) // There are only 3 acc registers.
1305 int MipsAsmParser::matchMSA128RegisterName(StringRef Name) {
1308 if (Name.front() != 'w' || Name.drop_front(1).getAsInteger(10, IntVal))
1317 int MipsAsmParser::matchMSA128CtrlRegisterName(StringRef Name) {
1320 CC = StringSwitch<unsigned>(Name)
1323 .Case("msaaccess", 2)
1325 .Case("msamodify", 4)
1326 .Case("msarequest", 5)
1328 .Case("msaunmap", 7)
1334 bool MipsAssemblerOptions::setATReg(unsigned Reg) {
1342 int MipsAsmParser::getATReg() {
1343 int AT = Options.getATRegNum();
1345 TokError("Pseudo instruction requires $at, which is not available");
1349 unsigned MipsAsmParser::getReg(int RC, int RegNo) {
1350 return *(getContext().getRegisterInfo()->getRegClass(RC).begin() + RegNo);
1353 unsigned MipsAsmParser::getGPR(int RegNo) {
1354 return getReg(isGP64() ? Mips::GPR64RegClassID : Mips::GPR32RegClassID,
1358 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) {
1360 getContext().getRegisterInfo()->getRegClass(RegClass).getNumRegs() - 1)
1363 return getReg(RegClass, RegNum);
1367 MipsAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand *> &Operands,
1368 StringRef Mnemonic) {
1369 DEBUG(dbgs() << "ParseOperand\n");
1371 // Check if the current operand has a custom associated parser, if so, try to
1372 // custom parse the operand, or fallback to the general approach.
1373 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1374 if (ResTy == MatchOperand_Success)
1376 // If there wasn't a custom match, try the generic matcher below. Otherwise,
1377 // there was a match, but an error occurred, in which case, just return that
1378 // the operand parsing failed.
1379 if (ResTy == MatchOperand_ParseFail)
1382 DEBUG(dbgs() << ".. Generic Parser\n");
1384 switch (getLexer().getKind()) {
1386 Error(Parser.getTok().getLoc(), "unexpected token in operand");
1388 case AsmToken::Dollar: {
1389 // Parse the register.
1390 SMLoc S = Parser.getTok().getLoc();
1392 // Almost all registers have been parsed by custom parsers. There is only
1393 // one exception to this. $zero (and it's alias $0) will reach this point
1394 // for div, divu, and similar instructions because it is not an operand
1395 // to the instruction definition but an explicit register. Special case
1396 // this situation for now.
1397 if (ParseAnyRegister(Operands) != MatchOperand_NoMatch)
1400 // Maybe it is a symbol reference.
1401 StringRef Identifier;
1402 if (Parser.parseIdentifier(Identifier))
1405 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1406 MCSymbol *Sym = getContext().GetOrCreateSymbol("$" + Identifier);
1407 // Otherwise create a symbol reference.
1409 MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None, getContext());
1411 Operands.push_back(MipsOperand::CreateImm(Res, S, E, *this));
1414 // Else drop to expression parsing.
1415 case AsmToken::LParen:
1416 case AsmToken::Minus:
1417 case AsmToken::Plus:
1418 case AsmToken::Integer:
1419 case AsmToken::String: {
1420 DEBUG(dbgs() << ".. generic integer\n");
1421 OperandMatchResultTy ResTy = ParseImm(Operands);
1422 return ResTy != MatchOperand_Success;
1424 case AsmToken::Percent: {
1425 // It is a symbol reference or constant expression.
1426 const MCExpr *IdVal;
1427 SMLoc S = Parser.getTok().getLoc(); // Start location of the operand.
1428 if (parseRelocOperand(IdVal))
1431 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1433 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E, *this));
1435 } // case AsmToken::Percent
1436 } // switch(getLexer().getKind())
1440 const MCExpr *MipsAsmParser::evaluateRelocExpr(const MCExpr *Expr,
1441 StringRef RelocStr) {
1443 // Check the type of the expression.
1444 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(Expr)) {
1445 // It's a constant, evaluate lo or hi value.
1446 if (RelocStr == "lo") {
1447 short Val = MCE->getValue();
1448 Res = MCConstantExpr::Create(Val, getContext());
1449 } else if (RelocStr == "hi") {
1450 int Val = MCE->getValue();
1451 int LoSign = Val & 0x8000;
1452 Val = (Val & 0xffff0000) >> 16;
1453 // Lower part is treated as a signed int, so if it is negative
1454 // we must add 1 to the hi part to compensate.
1457 Res = MCConstantExpr::Create(Val, getContext());
1459 llvm_unreachable("Invalid RelocStr value");
1464 if (const MCSymbolRefExpr *MSRE = dyn_cast<MCSymbolRefExpr>(Expr)) {
1465 // It's a symbol, create a symbolic expression from the symbol.
1466 StringRef Symbol = MSRE->getSymbol().getName();
1467 MCSymbolRefExpr::VariantKind VK = getVariantKind(RelocStr);
1468 Res = MCSymbolRefExpr::Create(Symbol, VK, getContext());
1472 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
1473 MCSymbolRefExpr::VariantKind VK = getVariantKind(RelocStr);
1475 // Check for %hi(sym1-sym2) and %lo(sym1-sym2) expressions.
1476 if (isa<MCSymbolRefExpr>(BE->getLHS()) && isa<MCSymbolRefExpr>(BE->getRHS())
1477 && (VK == MCSymbolRefExpr::VK_Mips_ABS_HI
1478 || VK == MCSymbolRefExpr::VK_Mips_ABS_LO)) {
1479 // Create target expression for %hi(sym1-sym2) and %lo(sym1-sym2).
1480 if (VK == MCSymbolRefExpr::VK_Mips_ABS_HI)
1481 return MipsMCExpr::CreateHi(Expr, getContext());
1482 return MipsMCExpr::CreateLo(Expr, getContext());
1485 const MCExpr *LExp = evaluateRelocExpr(BE->getLHS(), RelocStr);
1486 const MCExpr *RExp = evaluateRelocExpr(BE->getRHS(), RelocStr);
1487 Res = MCBinaryExpr::Create(BE->getOpcode(), LExp, RExp, getContext());
1491 if (const MCUnaryExpr *UN = dyn_cast<MCUnaryExpr>(Expr)) {
1492 const MCExpr *UnExp = evaluateRelocExpr(UN->getSubExpr(), RelocStr);
1493 Res = MCUnaryExpr::Create(UN->getOpcode(), UnExp, getContext());
1496 // Just return the original expression.
1500 bool MipsAsmParser::isEvaluated(const MCExpr *Expr) {
1502 switch (Expr->getKind()) {
1503 case MCExpr::Constant:
1505 case MCExpr::SymbolRef:
1506 return (cast<MCSymbolRefExpr>(Expr)->getKind() != MCSymbolRefExpr::VK_None);
1507 case MCExpr::Binary:
1508 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
1509 if (!isEvaluated(BE->getLHS()))
1511 return isEvaluated(BE->getRHS());
1514 return isEvaluated(cast<MCUnaryExpr>(Expr)->getSubExpr());
1515 case MCExpr::Target:
1521 bool MipsAsmParser::parseRelocOperand(const MCExpr *&Res) {
1522 Parser.Lex(); // Eat the % token.
1523 const AsmToken &Tok = Parser.getTok(); // Get next token, operation.
1524 if (Tok.isNot(AsmToken::Identifier))
1527 std::string Str = Tok.getIdentifier().str();
1529 Parser.Lex(); // Eat the identifier.
1530 // Now make an expression from the rest of the operand.
1531 const MCExpr *IdVal;
1534 if (getLexer().getKind() == AsmToken::LParen) {
1536 Parser.Lex(); // Eat the '(' token.
1537 if (getLexer().getKind() == AsmToken::Percent) {
1538 Parser.Lex(); // Eat the % token.
1539 const AsmToken &nextTok = Parser.getTok();
1540 if (nextTok.isNot(AsmToken::Identifier))
1543 Str += nextTok.getIdentifier();
1544 Parser.Lex(); // Eat the identifier.
1545 if (getLexer().getKind() != AsmToken::LParen)
1550 if (getParser().parseParenExpression(IdVal, EndLoc))
1553 while (getLexer().getKind() == AsmToken::RParen)
1554 Parser.Lex(); // Eat the ')' token.
1557 return true; // Parenthesis must follow the relocation operand.
1559 Res = evaluateRelocExpr(IdVal, Str);
1563 bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1565 SmallVector<MCParsedAsmOperand *, 1> Operands;
1566 OperandMatchResultTy ResTy = ParseAnyRegister(Operands);
1567 if (ResTy == MatchOperand_Success) {
1568 assert(Operands.size() == 1);
1569 MipsOperand &Operand = *static_cast<MipsOperand *>(Operands.front());
1570 StartLoc = Operand.getStartLoc();
1571 EndLoc = Operand.getEndLoc();
1573 // AFAIK, we only support numeric registers and named GPR's in CFI
1575 // Don't worry about eating tokens before failing. Using an unrecognised
1576 // register is a parse error.
1577 if (Operand.isGPRAsmReg()) {
1578 // Resolve to GPR32 or GPR64 appropriately.
1579 RegNo = isGP64() ? Operand.getGPR64Reg() : Operand.getGPR32Reg();
1582 return (RegNo == (unsigned)-1);
1585 assert(Operands.size() == 0);
1586 return (RegNo == (unsigned)-1);
1589 bool MipsAsmParser::parseMemOffset(const MCExpr *&Res, bool isParenExpr) {
1593 while (getLexer().getKind() == AsmToken::LParen)
1596 switch (getLexer().getKind()) {
1599 case AsmToken::Identifier:
1600 case AsmToken::LParen:
1601 case AsmToken::Integer:
1602 case AsmToken::Minus:
1603 case AsmToken::Plus:
1605 Result = getParser().parseParenExpression(Res, S);
1607 Result = (getParser().parseExpression(Res));
1608 while (getLexer().getKind() == AsmToken::RParen)
1611 case AsmToken::Percent:
1612 Result = parseRelocOperand(Res);
1617 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMemOperand(
1618 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1619 DEBUG(dbgs() << "parseMemOperand\n");
1620 const MCExpr *IdVal = 0;
1622 bool isParenExpr = false;
1623 MipsAsmParser::OperandMatchResultTy Res = MatchOperand_NoMatch;
1624 // First operand is the offset.
1625 S = Parser.getTok().getLoc();
1627 if (getLexer().getKind() == AsmToken::LParen) {
1632 if (getLexer().getKind() != AsmToken::Dollar) {
1633 if (parseMemOffset(IdVal, isParenExpr))
1634 return MatchOperand_ParseFail;
1636 const AsmToken &Tok = Parser.getTok(); // Get the next token.
1637 if (Tok.isNot(AsmToken::LParen)) {
1638 MipsOperand *Mnemonic = static_cast<MipsOperand *>(Operands[0]);
1639 if (Mnemonic->getToken() == "la") {
1641 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1642 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E, *this));
1643 return MatchOperand_Success;
1645 if (Tok.is(AsmToken::EndOfStatement)) {
1647 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1649 // Zero register assumed, add a memory operand with ZERO as its base.
1650 MipsOperand *Base = MipsOperand::CreateGPRReg(
1651 0, getContext().getRegisterInfo(), S, E, *this);
1652 Operands.push_back(MipsOperand::CreateMem(Base, IdVal, S, E, *this));
1653 return MatchOperand_Success;
1655 Error(Parser.getTok().getLoc(), "'(' expected");
1656 return MatchOperand_ParseFail;
1659 Parser.Lex(); // Eat the '(' token.
1662 Res = ParseAnyRegister(Operands);
1663 if (Res != MatchOperand_Success)
1666 if (Parser.getTok().isNot(AsmToken::RParen)) {
1667 Error(Parser.getTok().getLoc(), "')' expected");
1668 return MatchOperand_ParseFail;
1671 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1673 Parser.Lex(); // Eat the ')' token.
1676 IdVal = MCConstantExpr::Create(0, getContext());
1678 // Replace the register operand with the memory operand.
1679 MipsOperand *op = static_cast<MipsOperand *>(Operands.back());
1680 // Remove the register from the operands.
1681 Operands.pop_back();
1682 // Add the memory operand.
1683 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(IdVal)) {
1685 if (IdVal->EvaluateAsAbsolute(Imm))
1686 IdVal = MCConstantExpr::Create(Imm, getContext());
1687 else if (BE->getLHS()->getKind() != MCExpr::SymbolRef)
1688 IdVal = MCBinaryExpr::Create(BE->getOpcode(), BE->getRHS(), BE->getLHS(),
1692 Operands.push_back(MipsOperand::CreateMem(op, IdVal, S, E, *this));
1693 return MatchOperand_Success;
1696 bool MipsAsmParser::searchSymbolAlias(
1697 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1699 MCSymbol *Sym = getContext().LookupSymbol(Parser.getTok().getIdentifier());
1701 SMLoc S = Parser.getTok().getLoc();
1703 if (Sym->isVariable())
1704 Expr = Sym->getVariableValue();
1707 if (Expr->getKind() == MCExpr::SymbolRef) {
1708 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr *>(Expr);
1709 const StringRef DefSymbol = Ref->getSymbol().getName();
1710 if (DefSymbol.startswith("$")) {
1711 OperandMatchResultTy ResTy =
1712 MatchAnyRegisterNameWithoutDollar(Operands, DefSymbol.substr(1), S);
1713 if (ResTy == MatchOperand_Success) {
1716 } else if (ResTy == MatchOperand_ParseFail)
1717 llvm_unreachable("Should never ParseFail");
1720 } else if (Expr->getKind() == MCExpr::Constant) {
1722 const MCConstantExpr *Const = static_cast<const MCConstantExpr *>(Expr);
1724 MipsOperand::CreateImm(Const, S, Parser.getTok().getLoc(), *this);
1725 Operands.push_back(op);
1732 MipsAsmParser::OperandMatchResultTy
1733 MipsAsmParser::MatchAnyRegisterNameWithoutDollar(
1734 SmallVectorImpl<MCParsedAsmOperand *> &Operands, StringRef Identifier,
1736 int Index = matchCPURegisterName(Identifier);
1738 Operands.push_back(MipsOperand::CreateGPRReg(
1739 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1740 return MatchOperand_Success;
1743 Index = matchFPURegisterName(Identifier);
1745 Operands.push_back(MipsOperand::CreateFGRReg(
1746 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1747 return MatchOperand_Success;
1750 Index = matchFCCRegisterName(Identifier);
1752 Operands.push_back(MipsOperand::CreateFCCReg(
1753 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1754 return MatchOperand_Success;
1757 Index = matchACRegisterName(Identifier);
1759 Operands.push_back(MipsOperand::CreateACCReg(
1760 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1761 return MatchOperand_Success;
1764 Index = matchMSA128RegisterName(Identifier);
1766 Operands.push_back(MipsOperand::CreateMSA128Reg(
1767 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1768 return MatchOperand_Success;
1771 Index = matchMSA128CtrlRegisterName(Identifier);
1773 Operands.push_back(MipsOperand::CreateMSACtrlReg(
1774 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1775 return MatchOperand_Success;
1778 return MatchOperand_NoMatch;
1781 MipsAsmParser::OperandMatchResultTy
1782 MipsAsmParser::ParseAnyRegisterWithoutDollar(
1783 SmallVectorImpl<MCParsedAsmOperand *> &Operands, SMLoc S) {
1784 auto Token = Parser.getLexer().peekTok(false);
1786 if (Token.is(AsmToken::Identifier)) {
1787 DEBUG(dbgs() << ".. identifier\n");
1788 StringRef Identifier = Token.getIdentifier();
1789 OperandMatchResultTy ResTy =
1790 MatchAnyRegisterNameWithoutDollar(Operands, Identifier, S);
1792 } else if (Token.is(AsmToken::Integer)) {
1793 DEBUG(dbgs() << ".. integer\n");
1794 Operands.push_back(MipsOperand::CreateNumericReg(
1795 Token.getIntVal(), getContext().getRegisterInfo(), S, Token.getLoc(),
1797 return MatchOperand_Success;
1800 DEBUG(dbgs() << Parser.getTok().getKind() << "\n");
1802 return MatchOperand_NoMatch;
1805 MipsAsmParser::OperandMatchResultTy MipsAsmParser::ParseAnyRegister(
1806 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1807 DEBUG(dbgs() << "ParseAnyRegister\n");
1809 auto Token = Parser.getTok();
1811 SMLoc S = Token.getLoc();
1813 if (Token.isNot(AsmToken::Dollar)) {
1814 DEBUG(dbgs() << ".. !$ -> try sym aliasing\n");
1815 if (Token.is(AsmToken::Identifier)) {
1816 if (searchSymbolAlias(Operands))
1817 return MatchOperand_Success;
1819 DEBUG(dbgs() << ".. !symalias -> NoMatch\n");
1820 return MatchOperand_NoMatch;
1822 DEBUG(dbgs() << ".. $\n");
1824 OperandMatchResultTy ResTy = ParseAnyRegisterWithoutDollar(Operands, S);
1825 if (ResTy == MatchOperand_Success) {
1827 Parser.Lex(); // identifier
1832 MipsAsmParser::OperandMatchResultTy
1833 MipsAsmParser::ParseImm(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1834 switch (getLexer().getKind()) {
1836 return MatchOperand_NoMatch;
1837 case AsmToken::LParen:
1838 case AsmToken::Minus:
1839 case AsmToken::Plus:
1840 case AsmToken::Integer:
1841 case AsmToken::String:
1845 const MCExpr *IdVal;
1846 SMLoc S = Parser.getTok().getLoc();
1847 if (getParser().parseExpression(IdVal))
1848 return MatchOperand_ParseFail;
1850 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1851 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E, *this));
1852 return MatchOperand_Success;
1855 MipsAsmParser::OperandMatchResultTy MipsAsmParser::ParseJumpTarget(
1856 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1857 DEBUG(dbgs() << "ParseJumpTarget\n");
1859 SMLoc S = getLexer().getLoc();
1861 // Integers and expressions are acceptable
1862 OperandMatchResultTy ResTy = ParseImm(Operands);
1863 if (ResTy != MatchOperand_NoMatch)
1866 // Registers are a valid target and have priority over symbols.
1867 ResTy = ParseAnyRegister(Operands);
1868 if (ResTy != MatchOperand_NoMatch)
1871 // Consume the $ if there is one. We'll add it to the symbol below.
1872 bool hasConsumedDollar = false;
1873 if (getLexer().is(AsmToken::Dollar)) {
1875 hasConsumedDollar = true;
1878 StringRef Identifier;
1879 if (Parser.parseIdentifier(Identifier))
1880 return hasConsumedDollar ? MatchOperand_ParseFail : MatchOperand_NoMatch;
1882 if (hasConsumedDollar)
1883 Identifier = StringRef("$" + Identifier.str());
1885 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1886 MCSymbol *Sym = getContext().GetOrCreateSymbol(Identifier);
1888 // Create a symbol reference.
1890 MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None, getContext());
1892 Operands.push_back(MipsOperand::CreateImm(Res, S, E, *this));
1893 return MatchOperand_Success;
1894 // // Look for the existing symbol, we should check if
1895 // // we need to assign the proper RegisterKind.
1896 // if (searchSymbolAlias(Operands))
1899 return MatchOperand_NoMatch;
1902 MipsAsmParser::OperandMatchResultTy
1903 MipsAsmParser::parseInvNum(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1904 const MCExpr *IdVal;
1905 // If the first token is '$' we may have register operand.
1906 if (Parser.getTok().is(AsmToken::Dollar))
1907 return MatchOperand_NoMatch;
1908 SMLoc S = Parser.getTok().getLoc();
1909 if (getParser().parseExpression(IdVal))
1910 return MatchOperand_ParseFail;
1911 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(IdVal);
1912 assert(MCE && "Unexpected MCExpr type.");
1913 int64_t Val = MCE->getValue();
1914 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1915 Operands.push_back(MipsOperand::CreateImm(
1916 MCConstantExpr::Create(0 - Val, getContext()), S, E, *this));
1917 return MatchOperand_Success;
1920 MipsAsmParser::OperandMatchResultTy
1921 MipsAsmParser::ParseLSAImm(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1922 switch (getLexer().getKind()) {
1924 return MatchOperand_NoMatch;
1925 case AsmToken::LParen:
1926 case AsmToken::Plus:
1927 case AsmToken::Minus:
1928 case AsmToken::Integer:
1933 SMLoc S = Parser.getTok().getLoc();
1935 if (getParser().parseExpression(Expr))
1936 return MatchOperand_ParseFail;
1939 if (!Expr->EvaluateAsAbsolute(Val)) {
1940 Error(S, "expected immediate value");
1941 return MatchOperand_ParseFail;
1944 // The LSA instruction allows a 2-bit unsigned immediate. For this reason
1945 // and because the CPU always adds one to the immediate field, the allowed
1946 // range becomes 1..4. We'll only check the range here and will deal
1947 // with the addition/subtraction when actually decoding/encoding
1949 if (Val < 1 || Val > 4) {
1950 Error(S, "immediate not in range (1..4)");
1951 return MatchOperand_ParseFail;
1955 MipsOperand::CreateImm(Expr, S, Parser.getTok().getLoc(), *this));
1956 return MatchOperand_Success;
1959 MCSymbolRefExpr::VariantKind MipsAsmParser::getVariantKind(StringRef Symbol) {
1961 MCSymbolRefExpr::VariantKind VK =
1962 StringSwitch<MCSymbolRefExpr::VariantKind>(Symbol)
1963 .Case("hi", MCSymbolRefExpr::VK_Mips_ABS_HI)
1964 .Case("lo", MCSymbolRefExpr::VK_Mips_ABS_LO)
1965 .Case("gp_rel", MCSymbolRefExpr::VK_Mips_GPREL)
1966 .Case("call16", MCSymbolRefExpr::VK_Mips_GOT_CALL)
1967 .Case("got", MCSymbolRefExpr::VK_Mips_GOT)
1968 .Case("tlsgd", MCSymbolRefExpr::VK_Mips_TLSGD)
1969 .Case("tlsldm", MCSymbolRefExpr::VK_Mips_TLSLDM)
1970 .Case("dtprel_hi", MCSymbolRefExpr::VK_Mips_DTPREL_HI)
1971 .Case("dtprel_lo", MCSymbolRefExpr::VK_Mips_DTPREL_LO)
1972 .Case("gottprel", MCSymbolRefExpr::VK_Mips_GOTTPREL)
1973 .Case("tprel_hi", MCSymbolRefExpr::VK_Mips_TPREL_HI)
1974 .Case("tprel_lo", MCSymbolRefExpr::VK_Mips_TPREL_LO)
1975 .Case("got_disp", MCSymbolRefExpr::VK_Mips_GOT_DISP)
1976 .Case("got_page", MCSymbolRefExpr::VK_Mips_GOT_PAGE)
1977 .Case("got_ofst", MCSymbolRefExpr::VK_Mips_GOT_OFST)
1978 .Case("hi(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_HI)
1979 .Case("lo(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_LO)
1980 .Case("got_hi", MCSymbolRefExpr::VK_Mips_GOT_HI16)
1981 .Case("got_lo", MCSymbolRefExpr::VK_Mips_GOT_LO16)
1982 .Case("call_hi", MCSymbolRefExpr::VK_Mips_CALL_HI16)
1983 .Case("call_lo", MCSymbolRefExpr::VK_Mips_CALL_LO16)
1984 .Case("higher", MCSymbolRefExpr::VK_Mips_HIGHER)
1985 .Case("highest", MCSymbolRefExpr::VK_Mips_HIGHEST)
1986 .Default(MCSymbolRefExpr::VK_None);
1988 assert (VK != MCSymbolRefExpr::VK_None);
1993 /// Sometimes (i.e. load/stores) the operand may be followed immediately by
1995 /// ::= '(', register, ')'
1996 /// handle it before we iterate so we don't get tripped up by the lack of
1998 bool MipsAsmParser::ParseParenSuffix(
1999 StringRef Name, SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2000 if (getLexer().is(AsmToken::LParen)) {
2002 MipsOperand::CreateToken("(", getLexer().getLoc(), *this));
2004 if (ParseOperand(Operands, Name)) {
2005 SMLoc Loc = getLexer().getLoc();
2006 Parser.eatToEndOfStatement();
2007 return Error(Loc, "unexpected token in argument list");
2009 if (Parser.getTok().isNot(AsmToken::RParen)) {
2010 SMLoc Loc = getLexer().getLoc();
2011 Parser.eatToEndOfStatement();
2012 return Error(Loc, "unexpected token, expected ')'");
2015 MipsOperand::CreateToken(")", getLexer().getLoc(), *this));
2021 /// Sometimes (i.e. in MSA) the operand may be followed immediately by
2022 /// either one of these.
2023 /// ::= '[', register, ']'
2024 /// ::= '[', integer, ']'
2025 /// handle it before we iterate so we don't get tripped up by the lack of
2027 bool MipsAsmParser::ParseBracketSuffix(
2028 StringRef Name, SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2029 if (getLexer().is(AsmToken::LBrac)) {
2031 MipsOperand::CreateToken("[", getLexer().getLoc(), *this));
2033 if (ParseOperand(Operands, Name)) {
2034 SMLoc Loc = getLexer().getLoc();
2035 Parser.eatToEndOfStatement();
2036 return Error(Loc, "unexpected token in argument list");
2038 if (Parser.getTok().isNot(AsmToken::RBrac)) {
2039 SMLoc Loc = getLexer().getLoc();
2040 Parser.eatToEndOfStatement();
2041 return Error(Loc, "unexpected token, expected ']'");
2044 MipsOperand::CreateToken("]", getLexer().getLoc(), *this));
2050 bool MipsAsmParser::ParseInstruction(
2051 ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
2052 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2053 DEBUG(dbgs() << "ParseInstruction\n");
2054 // Check if we have valid mnemonic
2055 if (!mnemonicIsValid(Name, 0)) {
2056 Parser.eatToEndOfStatement();
2057 return Error(NameLoc, "Unknown instruction");
2059 // First operand in MCInst is instruction mnemonic.
2060 Operands.push_back(MipsOperand::CreateToken(Name, NameLoc, *this));
2062 // Read the remaining operands.
2063 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2064 // Read the first operand.
2065 if (ParseOperand(Operands, Name)) {
2066 SMLoc Loc = getLexer().getLoc();
2067 Parser.eatToEndOfStatement();
2068 return Error(Loc, "unexpected token in argument list");
2070 if (getLexer().is(AsmToken::LBrac) && ParseBracketSuffix(Name, Operands))
2072 // AFAIK, parenthesis suffixes are never on the first operand
2074 while (getLexer().is(AsmToken::Comma)) {
2075 Parser.Lex(); // Eat the comma.
2076 // Parse and remember the operand.
2077 if (ParseOperand(Operands, Name)) {
2078 SMLoc Loc = getLexer().getLoc();
2079 Parser.eatToEndOfStatement();
2080 return Error(Loc, "unexpected token in argument list");
2082 // Parse bracket and parenthesis suffixes before we iterate
2083 if (getLexer().is(AsmToken::LBrac)) {
2084 if (ParseBracketSuffix(Name, Operands))
2086 } else if (getLexer().is(AsmToken::LParen) &&
2087 ParseParenSuffix(Name, Operands))
2091 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2092 SMLoc Loc = getLexer().getLoc();
2093 Parser.eatToEndOfStatement();
2094 return Error(Loc, "unexpected token in argument list");
2096 Parser.Lex(); // Consume the EndOfStatement.
2100 bool MipsAsmParser::reportParseError(StringRef ErrorMsg) {
2101 SMLoc Loc = getLexer().getLoc();
2102 Parser.eatToEndOfStatement();
2103 return Error(Loc, ErrorMsg);
2106 bool MipsAsmParser::parseSetNoAtDirective() {
2107 // Line should look like: ".set noat".
2109 Options.setATReg(0);
2112 // If this is not the end of the statement, report an error.
2113 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2114 reportParseError("unexpected token in statement");
2117 Parser.Lex(); // Consume the EndOfStatement.
2121 bool MipsAsmParser::parseSetAtDirective() {
2122 // Line can be .set at - defaults to $1
2126 if (getLexer().is(AsmToken::EndOfStatement)) {
2127 Options.setATReg(1);
2128 Parser.Lex(); // Consume the EndOfStatement.
2130 } else if (getLexer().is(AsmToken::Equal)) {
2131 getParser().Lex(); // Eat the '='.
2132 if (getLexer().isNot(AsmToken::Dollar)) {
2133 reportParseError("unexpected token in statement");
2136 Parser.Lex(); // Eat the '$'.
2137 const AsmToken &Reg = Parser.getTok();
2138 if (Reg.is(AsmToken::Identifier)) {
2139 AtRegNo = matchCPURegisterName(Reg.getIdentifier());
2140 } else if (Reg.is(AsmToken::Integer)) {
2141 AtRegNo = Reg.getIntVal();
2143 reportParseError("unexpected token in statement");
2147 if (AtRegNo < 0 || AtRegNo > 31) {
2148 reportParseError("unexpected token in statement");
2152 if (!Options.setATReg(AtRegNo)) {
2153 reportParseError("unexpected token in statement");
2156 getParser().Lex(); // Eat the register.
2158 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2159 reportParseError("unexpected token in statement");
2162 Parser.Lex(); // Consume the EndOfStatement.
2165 reportParseError("unexpected token in statement");
2170 bool MipsAsmParser::parseSetReorderDirective() {
2172 // If this is not the end of the statement, report an error.
2173 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2174 reportParseError("unexpected token in statement");
2177 Options.setReorder();
2178 getTargetStreamer().emitDirectiveSetReorder();
2179 Parser.Lex(); // Consume the EndOfStatement.
2183 bool MipsAsmParser::parseSetNoReorderDirective() {
2185 // If this is not the end of the statement, report an error.
2186 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2187 reportParseError("unexpected token in statement");
2190 Options.setNoreorder();
2191 getTargetStreamer().emitDirectiveSetNoReorder();
2192 Parser.Lex(); // Consume the EndOfStatement.
2196 bool MipsAsmParser::parseSetMacroDirective() {
2198 // If this is not the end of the statement, report an error.
2199 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2200 reportParseError("unexpected token in statement");
2204 Parser.Lex(); // Consume the EndOfStatement.
2208 bool MipsAsmParser::parseSetNoMacroDirective() {
2210 // If this is not the end of the statement, report an error.
2211 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2212 reportParseError("`noreorder' must be set before `nomacro'");
2215 if (Options.isReorder()) {
2216 reportParseError("`noreorder' must be set before `nomacro'");
2219 Options.setNomacro();
2220 Parser.Lex(); // Consume the EndOfStatement.
2224 bool MipsAsmParser::parseSetNoMips16Directive() {
2226 // If this is not the end of the statement, report an error.
2227 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2228 reportParseError("unexpected token in statement");
2231 // For now do nothing.
2232 Parser.Lex(); // Consume the EndOfStatement.
2236 bool MipsAsmParser::parseSetAssignment() {
2238 const MCExpr *Value;
2240 if (Parser.parseIdentifier(Name))
2241 reportParseError("expected identifier after .set");
2243 if (getLexer().isNot(AsmToken::Comma))
2244 return reportParseError("unexpected token in .set directive");
2247 if (Parser.parseExpression(Value))
2248 return reportParseError("expected valid expression after comma");
2250 // Check if the Name already exists as a symbol.
2251 MCSymbol *Sym = getContext().LookupSymbol(Name);
2253 return reportParseError("symbol already defined");
2254 Sym = getContext().GetOrCreateSymbol(Name);
2255 Sym->setVariableValue(Value);
2260 bool MipsAsmParser::parseSetFeature(uint64_t Feature) {
2262 if (getLexer().isNot(AsmToken::EndOfStatement))
2263 return reportParseError("unexpected token in .set directive");
2266 default: llvm_unreachable("Unimplemented feature");
2267 case Mips::FeatureDSP:
2268 setFeatureBits(Mips::FeatureDSP, "dsp");
2269 getTargetStreamer().emitDirectiveSetDsp();
2271 case Mips::FeatureMicroMips:
2272 getTargetStreamer().emitDirectiveSetMicroMips();
2274 case Mips::FeatureMips16:
2275 getTargetStreamer().emitDirectiveSetMips16();
2277 case Mips::FeatureMips32r2:
2278 setFeatureBits(Mips::FeatureMips32r2, "mips32r2");
2279 getTargetStreamer().emitDirectiveSetMips32R2();
2281 case Mips::FeatureMips64:
2282 setFeatureBits(Mips::FeatureMips64, "mips64");
2283 getTargetStreamer().emitDirectiveSetMips64();
2285 case Mips::FeatureMips64r2:
2286 setFeatureBits(Mips::FeatureMips64r2, "mips64r2");
2287 getTargetStreamer().emitDirectiveSetMips64R2();
2293 bool MipsAsmParser::parseRegister(unsigned &RegNum) {
2294 if (!getLexer().is(AsmToken::Dollar))
2299 const AsmToken &Reg = Parser.getTok();
2300 if (Reg.is(AsmToken::Identifier)) {
2301 RegNum = matchCPURegisterName(Reg.getIdentifier());
2302 } else if (Reg.is(AsmToken::Integer)) {
2303 RegNum = Reg.getIntVal();
2312 bool MipsAsmParser::eatComma(StringRef ErrorStr) {
2313 if (getLexer().isNot(AsmToken::Comma)) {
2314 SMLoc Loc = getLexer().getLoc();
2315 Parser.eatToEndOfStatement();
2316 return Error(Loc, ErrorStr);
2319 Parser.Lex(); // Eat the comma.
2323 bool MipsAsmParser::parseDirectiveCPSetup() {
2326 bool SaveIsReg = true;
2328 if (!parseRegister(FuncReg))
2329 return reportParseError("expected register containing function address");
2330 FuncReg = getGPR(FuncReg);
2332 if (!eatComma("expected comma parsing directive"))
2335 if (!parseRegister(Save)) {
2336 const AsmToken &Tok = Parser.getTok();
2337 if (Tok.is(AsmToken::Integer)) {
2338 Save = Tok.getIntVal();
2342 return reportParseError("expected save register or stack offset");
2344 Save = getGPR(Save);
2346 if (!eatComma("expected comma parsing directive"))
2350 if (Parser.parseIdentifier(Name))
2351 reportParseError("expected identifier");
2352 MCSymbol *Sym = getContext().GetOrCreateSymbol(Name);
2353 unsigned GPReg = getGPR(matchCPURegisterName("gp"));
2355 // FIXME: The code below this point should be in the TargetStreamers.
2356 // Only N32 and N64 emit anything for .cpsetup
2357 // FIXME: We should only emit something for PIC mode too.
2358 if (!isN32() && !isN64())
2361 MCStreamer &TS = getStreamer();
2363 // Either store the old $gp in a register or on the stack
2365 // move $save, $gpreg
2366 Inst.setOpcode(Mips::DADDu);
2367 Inst.addOperand(MCOperand::CreateReg(Save));
2368 Inst.addOperand(MCOperand::CreateReg(GPReg));
2369 Inst.addOperand(MCOperand::CreateReg(getGPR(0)));
2371 // sd $gpreg, offset($sp)
2372 Inst.setOpcode(Mips::SD);
2373 Inst.addOperand(MCOperand::CreateReg(GPReg));
2374 Inst.addOperand(MCOperand::CreateReg(getGPR(matchCPURegisterName("sp"))));
2375 Inst.addOperand(MCOperand::CreateImm(Save));
2377 TS.EmitInstruction(Inst, STI);
2380 const MCSymbolRefExpr *HiExpr = MCSymbolRefExpr::Create(
2381 Sym->getName(), MCSymbolRefExpr::VK_Mips_GPOFF_HI,
2383 const MCSymbolRefExpr *LoExpr = MCSymbolRefExpr::Create(
2384 Sym->getName(), MCSymbolRefExpr::VK_Mips_GPOFF_LO,
2386 // lui $gp, %hi(%neg(%gp_rel(funcSym)))
2387 Inst.setOpcode(Mips::LUi);
2388 Inst.addOperand(MCOperand::CreateReg(GPReg));
2389 Inst.addOperand(MCOperand::CreateExpr(HiExpr));
2390 TS.EmitInstruction(Inst, STI);
2393 // addiu $gp, $gp, %lo(%neg(%gp_rel(funcSym)))
2394 Inst.setOpcode(Mips::ADDiu);
2395 Inst.addOperand(MCOperand::CreateReg(GPReg));
2396 Inst.addOperand(MCOperand::CreateReg(GPReg));
2397 Inst.addOperand(MCOperand::CreateExpr(LoExpr));
2398 TS.EmitInstruction(Inst, STI);
2401 // daddu $gp, $gp, $funcreg
2402 Inst.setOpcode(Mips::DADDu);
2403 Inst.addOperand(MCOperand::CreateReg(GPReg));
2404 Inst.addOperand(MCOperand::CreateReg(GPReg));
2405 Inst.addOperand(MCOperand::CreateReg(FuncReg));
2406 TS.EmitInstruction(Inst, STI);
2410 bool MipsAsmParser::parseDirectiveSet() {
2412 // Get the next token.
2413 const AsmToken &Tok = Parser.getTok();
2415 if (Tok.getString() == "noat") {
2416 return parseSetNoAtDirective();
2417 } else if (Tok.getString() == "at") {
2418 return parseSetAtDirective();
2419 } else if (Tok.getString() == "reorder") {
2420 return parseSetReorderDirective();
2421 } else if (Tok.getString() == "noreorder") {
2422 return parseSetNoReorderDirective();
2423 } else if (Tok.getString() == "macro") {
2424 return parseSetMacroDirective();
2425 } else if (Tok.getString() == "nomacro") {
2426 return parseSetNoMacroDirective();
2427 } else if (Tok.getString() == "mips16") {
2428 return parseSetFeature(Mips::FeatureMips16);
2429 } else if (Tok.getString() == "nomips16") {
2430 return parseSetNoMips16Directive();
2431 } else if (Tok.getString() == "nomicromips") {
2432 getTargetStreamer().emitDirectiveSetNoMicroMips();
2433 Parser.eatToEndOfStatement();
2435 } else if (Tok.getString() == "micromips") {
2436 return parseSetFeature(Mips::FeatureMicroMips);
2437 } else if (Tok.getString() == "mips32r2") {
2438 return parseSetFeature(Mips::FeatureMips32r2);
2439 } else if (Tok.getString() == "mips64") {
2440 return parseSetFeature(Mips::FeatureMips64);
2441 } else if (Tok.getString() == "mips64r2") {
2442 return parseSetFeature(Mips::FeatureMips64r2);
2443 } else if (Tok.getString() == "dsp") {
2444 return parseSetFeature(Mips::FeatureDSP);
2446 // It is just an identifier, look for an assignment.
2447 parseSetAssignment();
2454 /// parseDataDirective
2455 /// ::= .word [ expression (, expression)* ]
2456 bool MipsAsmParser::parseDataDirective(unsigned Size, SMLoc L) {
2457 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2459 const MCExpr *Value;
2460 if (getParser().parseExpression(Value))
2463 getParser().getStreamer().EmitValue(Value, Size);
2465 if (getLexer().is(AsmToken::EndOfStatement))
2468 // FIXME: Improve diagnostic.
2469 if (getLexer().isNot(AsmToken::Comma))
2470 return Error(L, "unexpected token in directive");
2479 /// parseDirectiveGpWord
2480 /// ::= .gpword local_sym
2481 bool MipsAsmParser::parseDirectiveGpWord() {
2482 const MCExpr *Value;
2483 // EmitGPRel32Value requires an expression, so we are using base class
2484 // method to evaluate the expression.
2485 if (getParser().parseExpression(Value))
2487 getParser().getStreamer().EmitGPRel32Value(Value);
2489 if (getLexer().isNot(AsmToken::EndOfStatement))
2490 return Error(getLexer().getLoc(), "unexpected token in directive");
2491 Parser.Lex(); // Eat EndOfStatement token.
2495 /// parseDirectiveGpDWord
2496 /// ::= .gpdword local_sym
2497 bool MipsAsmParser::parseDirectiveGpDWord() {
2498 const MCExpr *Value;
2499 // EmitGPRel64Value requires an expression, so we are using base class
2500 // method to evaluate the expression.
2501 if (getParser().parseExpression(Value))
2503 getParser().getStreamer().EmitGPRel64Value(Value);
2505 if (getLexer().isNot(AsmToken::EndOfStatement))
2506 return Error(getLexer().getLoc(), "unexpected token in directive");
2507 Parser.Lex(); // Eat EndOfStatement token.
2511 bool MipsAsmParser::parseDirectiveOption() {
2512 // Get the option token.
2513 AsmToken Tok = Parser.getTok();
2514 // At the moment only identifiers are supported.
2515 if (Tok.isNot(AsmToken::Identifier)) {
2516 Error(Parser.getTok().getLoc(), "unexpected token in .option directive");
2517 Parser.eatToEndOfStatement();
2521 StringRef Option = Tok.getIdentifier();
2523 if (Option == "pic0") {
2524 getTargetStreamer().emitDirectiveOptionPic0();
2526 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
2527 Error(Parser.getTok().getLoc(),
2528 "unexpected token in .option pic0 directive");
2529 Parser.eatToEndOfStatement();
2534 if (Option == "pic2") {
2535 getTargetStreamer().emitDirectiveOptionPic2();
2537 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
2538 Error(Parser.getTok().getLoc(),
2539 "unexpected token in .option pic2 directive");
2540 Parser.eatToEndOfStatement();
2546 Warning(Parser.getTok().getLoc(), "unknown option in .option directive");
2547 Parser.eatToEndOfStatement();
2551 bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) {
2552 StringRef IDVal = DirectiveID.getString();
2554 if (IDVal == ".dword") {
2555 parseDataDirective(8, DirectiveID.getLoc());
2559 if (IDVal == ".ent") {
2560 // Ignore this directive for now.
2565 if (IDVal == ".end") {
2566 // Ignore this directive for now.
2571 if (IDVal == ".frame") {
2572 // Ignore this directive for now.
2573 Parser.eatToEndOfStatement();
2577 if (IDVal == ".set") {
2578 return parseDirectiveSet();
2581 if (IDVal == ".fmask") {
2582 // Ignore this directive for now.
2583 Parser.eatToEndOfStatement();
2587 if (IDVal == ".mask") {
2588 // Ignore this directive for now.
2589 Parser.eatToEndOfStatement();
2593 if (IDVal == ".gpword") {
2594 parseDirectiveGpWord();
2598 if (IDVal == ".gpdword") {
2599 parseDirectiveGpDWord();
2603 if (IDVal == ".word") {
2604 parseDataDirective(4, DirectiveID.getLoc());
2608 if (IDVal == ".option")
2609 return parseDirectiveOption();
2611 if (IDVal == ".abicalls") {
2612 getTargetStreamer().emitDirectiveAbiCalls();
2613 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
2614 Error(Parser.getTok().getLoc(), "unexpected token in directive");
2616 Parser.eatToEndOfStatement();
2621 if (IDVal == ".cpsetup")
2622 return parseDirectiveCPSetup();
2627 extern "C" void LLVMInitializeMipsAsmParser() {
2628 RegisterMCAsmParser<MipsAsmParser> X(TheMipsTarget);
2629 RegisterMCAsmParser<MipsAsmParser> Y(TheMipselTarget);
2630 RegisterMCAsmParser<MipsAsmParser> A(TheMips64Target);
2631 RegisterMCAsmParser<MipsAsmParser> B(TheMips64elTarget);
2634 #define GET_REGISTER_MATCHER
2635 #define GET_MATCHER_IMPLEMENTATION
2636 #include "MipsGenAsmMatcher.inc"