1 //===- MSP430RegisterInfo.cpp - MSP430 Register Information ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MSP430 implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "msp430-reg-info"
17 #include "MSP430MachineFunctionInfo.h"
18 #include "MSP430RegisterInfo.h"
19 #include "MSP430TargetMachine.h"
20 #include "llvm/Function.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/ADT/BitVector.h"
27 #include "llvm/Support/ErrorHandling.h"
31 // FIXME: Provide proper call frame setup / destroy opcodes.
32 MSP430RegisterInfo::MSP430RegisterInfo(MSP430TargetMachine &tm,
33 const TargetInstrInfo &tii)
34 : MSP430GenRegisterInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
36 StackAlign = TM.getFrameLowering()->getStackAlignment();
40 MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
41 const TargetFrameLowering *TFI = MF->getTarget().getFrameLowering();
42 const Function* F = MF->getFunction();
43 static const unsigned CalleeSavedRegs[] = {
44 MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W,
45 MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
48 static const unsigned CalleeSavedRegsFP[] = {
49 MSP430::R5W, MSP430::R6W, MSP430::R7W,
50 MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
53 static const unsigned CalleeSavedRegsIntr[] = {
54 MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W,
55 MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
56 MSP430::R12W, MSP430::R13W, MSP430::R14W, MSP430::R15W,
59 static const unsigned CalleeSavedRegsIntrFP[] = {
60 MSP430::R5W, MSP430::R6W, MSP430::R7W,
61 MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
62 MSP430::R12W, MSP430::R13W, MSP430::R14W, MSP430::R15W,
67 return (F->getCallingConv() == CallingConv::MSP430_INTR ?
68 CalleeSavedRegsIntrFP : CalleeSavedRegsFP);
70 return (F->getCallingConv() == CallingConv::MSP430_INTR ?
71 CalleeSavedRegsIntr : CalleeSavedRegs);
75 BitVector MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
76 BitVector Reserved(getNumRegs());
77 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
79 // Mark 4 special registers with subregisters as reserved.
80 Reserved.set(MSP430::PCB);
81 Reserved.set(MSP430::SPB);
82 Reserved.set(MSP430::SRB);
83 Reserved.set(MSP430::CGB);
84 Reserved.set(MSP430::PCW);
85 Reserved.set(MSP430::SPW);
86 Reserved.set(MSP430::SRW);
87 Reserved.set(MSP430::CGW);
89 // Mark frame pointer as reserved if needed.
91 Reserved.set(MSP430::FPW);
96 const TargetRegisterClass *
97 MSP430RegisterInfo::getPointerRegClass(unsigned Kind) const {
98 return &MSP430::GR16RegClass;
101 void MSP430RegisterInfo::
102 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
103 MachineBasicBlock::iterator I) const {
104 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
106 if (!TFI->hasReservedCallFrame(MF)) {
107 // If the stack pointer can be changed after prologue, turn the
108 // adjcallstackup instruction into a 'sub SPW, <amt>' and the
109 // adjcallstackdown instruction into 'add SPW, <amt>'
110 // TODO: consider using push / pop instead of sub + store / add
111 MachineInstr *Old = I;
112 uint64_t Amount = Old->getOperand(0).getImm();
114 // We need to keep the stack aligned properly. To do this, we round the
115 // amount of space needed for the outgoing arguments up to the next
116 // alignment boundary.
117 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
119 MachineInstr *New = 0;
120 if (Old->getOpcode() == getCallFrameSetupOpcode()) {
121 New = BuildMI(MF, Old->getDebugLoc(),
122 TII.get(MSP430::SUB16ri), MSP430::SPW)
123 .addReg(MSP430::SPW).addImm(Amount);
125 assert(Old->getOpcode() == getCallFrameDestroyOpcode());
126 // factor out the amount the callee already popped.
127 uint64_t CalleeAmt = Old->getOperand(1).getImm();
130 New = BuildMI(MF, Old->getDebugLoc(),
131 TII.get(MSP430::ADD16ri), MSP430::SPW)
132 .addReg(MSP430::SPW).addImm(Amount);
136 // The SRW implicit def is dead.
137 New->getOperand(3).setIsDead();
139 // Replace the pseudo instruction with a new instruction...
143 } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
144 // If we are performing frame pointer elimination and if the callee pops
145 // something off the stack pointer, add it back.
146 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
147 MachineInstr *Old = I;
149 BuildMI(MF, Old->getDebugLoc(), TII.get(MSP430::SUB16ri),
150 MSP430::SPW).addReg(MSP430::SPW).addImm(CalleeAmt);
151 // The SRW implicit def is dead.
152 New->getOperand(3).setIsDead();
162 MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
163 int SPAdj, RegScavenger *RS) const {
164 assert(SPAdj == 0 && "Unexpected");
167 MachineInstr &MI = *II;
168 MachineBasicBlock &MBB = *MI.getParent();
169 MachineFunction &MF = *MBB.getParent();
170 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
171 DebugLoc dl = MI.getDebugLoc();
172 while (!MI.getOperand(i).isFI()) {
174 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
177 int FrameIndex = MI.getOperand(i).getIndex();
179 unsigned BasePtr = (TFI->hasFP(MF) ? MSP430::FPW : MSP430::SPW);
180 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
186 Offset += MF.getFrameInfo()->getStackSize();
188 Offset += 2; // Skip the saved FPW
190 // Fold imm into offset
191 Offset += MI.getOperand(i+1).getImm();
193 if (MI.getOpcode() == MSP430::ADD16ri) {
194 // This is actually "load effective address" of the stack slot
195 // instruction. We have only two-address instructions, thus we need to
196 // expand it into mov + add
198 MI.setDesc(TII.get(MSP430::MOV16rr));
199 MI.getOperand(i).ChangeToRegister(BasePtr, false);
204 // We need to materialize the offset via add instruction.
205 unsigned DstReg = MI.getOperand(0).getReg();
207 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
208 .addReg(DstReg).addImm(-Offset);
210 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
211 .addReg(DstReg).addImm(Offset);
216 MI.getOperand(i).ChangeToRegister(BasePtr, false);
217 MI.getOperand(i+1).ChangeToImmediate(Offset);
221 MSP430RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
223 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
225 // Create a frame entry for the FPW register that must be saved.
226 if (TFI->hasFP(MF)) {
227 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(2, -4, true);
229 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
230 "Slot for FPW register must be last in order to be found!");
234 unsigned MSP430RegisterInfo::getRARegister() const {
238 unsigned MSP430RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
239 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
241 return TFI->hasFP(MF) ? MSP430::FPW : MSP430::SPW;
244 int MSP430RegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
245 llvm_unreachable("Not implemented yet!");
249 int MSP430RegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const {
250 llvm_unreachable("Not implemented yet!");
254 #include "MSP430GenRegisterInfo.inc"