1 //===- MSP430InstrInfo.td - MSP430 Instruction defs -----------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the MSP430 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "MSP430InstrFormats.td"
16 //===----------------------------------------------------------------------===//
18 //===----------------------------------------------------------------------===//
19 class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
20 class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
25 def SDT_MSP430Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
26 def SDT_MSP430CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>]>;
27 def SDT_MSP430CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
28 def SDT_MSP430Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
30 //===----------------------------------------------------------------------===//
31 // MSP430 Specific Node Definitions.
32 //===----------------------------------------------------------------------===//
33 def MSP430retflag : SDNode<"MSP430ISD::RET_FLAG", SDTNone,
34 [SDNPHasChain, SDNPOptInFlag]>;
36 def MSP430rra : SDNode<"MSP430ISD::RRA", SDTIntUnaryOp, []>;
38 def MSP430call : SDNode<"MSP430ISD::CALL", SDT_MSP430Call,
39 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
40 def MSP430callseq_start :
41 SDNode<"ISD::CALLSEQ_START", SDT_MSP430CallSeqStart,
42 [SDNPHasChain, SDNPOutFlag]>;
43 def MSP430callseq_end :
44 SDNode<"ISD::CALLSEQ_END", SDT_MSP430CallSeqEnd,
45 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
46 def MSP430Wrapper : SDNode<"MSP430ISD::Wrapper", SDT_MSP430Wrapper>;
48 //===----------------------------------------------------------------------===//
49 // MSP430 Operand Definitions.
50 //===----------------------------------------------------------------------===//
53 def memsrc : Operand<i16> {
54 let PrintMethod = "printSrcMemOperand";
55 let MIOperandInfo = (ops GR16, i16imm);
58 def memdst : Operand<i16> {
59 let PrintMethod = "printSrcMemOperand";
60 let MIOperandInfo = (ops GR16, i16imm);
63 //===----------------------------------------------------------------------===//
64 // MSP430 Complex Pattern Definitions.
65 //===----------------------------------------------------------------------===//
67 def addr : ComplexPattern<iPTR, 2, "SelectAddr", [], []>;
69 //===----------------------------------------------------------------------===//
71 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
72 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 ( extloadi8 node:$ptr))>;
74 //===----------------------------------------------------------------------===//
77 // ADJCALLSTACKDOWN/UP implicitly use/def SP because they may be expanded into
78 // a stack adjustment and the codegen must know that they may modify the stack
79 // pointer before prolog-epilog rewriting occurs.
80 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
81 // sub / add which can clobber SRW.
82 let Defs = [SPW, SRW], Uses = [SPW] in {
83 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i16imm:$amt),
85 [(MSP430callseq_start timm:$amt)]>;
86 def ADJCALLSTACKUP : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2),
88 [(MSP430callseq_end timm:$amt1, timm:$amt2)]>;
92 let neverHasSideEffects = 1 in
93 def NOP : Pseudo<(outs), (ins), "nop", []>;
95 // FIXME: Provide proper encoding!
96 let isReturn = 1, isTerminator = 1 in {
97 def RET : Pseudo<(outs), (ins), "ret", [(MSP430retflag)]>;
100 //===----------------------------------------------------------------------===//
101 // Call Instructions...
104 // All calls clobber the non-callee saved registers. SPW is marked as
105 // a use to prevent stack-pointer assignments that appear immediately
106 // before calls from potentially appearing dead. Uses for argument
107 // registers are added manually.
108 let Defs = [R12W, R13W, R14W, R15W, SRW],
110 def CALLi : Pseudo<(outs), (ins i16imm:$dst, variable_ops),
111 "call\t${dst:call}", [(MSP430call imm:$dst)]>;
112 def CALLr : Pseudo<(outs), (ins GR16:$dst, variable_ops),
113 "call\t$dst", [(MSP430call GR16:$dst)]>;
114 def CALLm : Pseudo<(outs), (ins memsrc:$dst, variable_ops),
115 "call\t${dst:mem}", [(MSP430call (load addr:$dst))]>;
119 //===----------------------------------------------------------------------===//
120 // Miscellaneous Instructions...
122 let Defs = [SPW], Uses = [SPW], neverHasSideEffects=1 in {
124 def POP16r : Pseudo<(outs GR16:$reg), (ins), "pop.w\t$reg", []>;
127 def PUSH16r : Pseudo<(outs), (ins GR16:$reg), "push.w\t$reg",[]>;
130 //===----------------------------------------------------------------------===//
133 // FIXME: Provide proper encoding!
134 let neverHasSideEffects = 1 in {
135 def MOV8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src),
136 "mov.b\t{$src, $dst|$dst, $src}",
138 def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src),
139 "mov.w\t{$src, $dst|$dst, $src}",
143 // FIXME: Provide proper encoding!
144 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
145 def MOV8ri : Pseudo<(outs GR8:$dst), (ins i8imm:$src),
146 "mov.b\t{$src, $dst|$dst, $src}",
147 [(set GR8:$dst, imm:$src)]>;
148 def MOV16ri : Pseudo<(outs GR16:$dst), (ins i16imm:$src),
149 "mov.w\t{$src, $dst|$dst, $src}",
150 [(set GR16:$dst, imm:$src)]>;
153 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
154 def MOV8rm : Pseudo<(outs GR8:$dst), (ins memsrc:$src),
155 "mov.b\t{$src, $dst|$dst, $src}",
156 [(set GR8:$dst, (load addr:$src))]>;
157 def MOV16rm : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
158 "mov.w\t{$src, $dst|$dst, $src}",
159 [(set GR16:$dst, (load addr:$src))]>;
162 def MOVZX16rr8 : Pseudo<(outs GR16:$dst), (ins GR8:$src),
163 "mov.b\t{$src, $dst|$dst, $src}",
164 [(set GR16:$dst, (zext GR8:$src))]>;
165 def MOVZX16rm8 : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
166 "mov.b\t{$src, $dst|$dst, $src}",
167 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>;
169 def MOV8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
170 "mov.b\t{$src, $dst|$dst, $src}",
171 [(store (i8 imm:$src), addr:$dst)]>;
172 def MOV16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
173 "mov.w\t{$src, $dst|$dst, $src}",
174 [(store (i16 imm:$src), addr:$dst)]>;
176 def MOV8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
177 "mov.b\t{$src, $dst|$dst, $src}",
178 [(store GR8:$src, addr:$dst)]>;
179 def MOV16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
180 "mov.w\t{$src, $dst|$dst, $src}",
181 [(store GR16:$src, addr:$dst)]>;
183 //===----------------------------------------------------------------------===//
184 // Arithmetic Instructions
186 let isTwoAddress = 1 in {
188 let Defs = [SRW] in {
190 let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y
191 // FIXME: Provide proper encoding!
192 def ADD8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
193 "add.b\t{$src2, $dst|$dst, $src2}",
194 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
196 def ADD16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
197 "add.w\t{$src2, $dst|$dst, $src2}",
198 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
202 def ADD8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
203 "add.b\t{$src2, $dst|$dst, $src2}",
204 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
206 def ADD16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
207 "add.w\t{$src2, $dst|$dst, $src2}",
208 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
211 def ADD8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
212 "add.b\t{$src2, $dst|$dst, $src2}",
213 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
215 def ADD16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
216 "add.w\t{$src2, $dst|$dst, $src2}",
217 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
220 let isTwoAddress = 0 in {
221 def ADD8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
222 "add.b\t{$src, $dst|$dst, $src}",
223 [(store (add (load addr:$dst), GR8:$src), addr:$dst),
225 def ADD16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
226 "add.w\t{$src, $dst|$dst, $src}",
227 [(store (add (load addr:$dst), GR16:$src), addr:$dst),
230 def ADD8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
231 "add.b\t{$src, $dst|$dst, $src}",
232 [(store (add (load addr:$dst), (i8 imm:$src)), addr:$dst),
234 def ADD16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
235 "add.w\t{$src, $dst|$dst, $src}",
236 [(store (add (load addr:$dst), (i16 imm:$src)), addr:$dst),
239 def ADD8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
240 "add.b\t{$src, $dst|$dst, $src}",
241 [(store (add (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
243 def ADD16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
244 "add.w\t{$src, $dst|$dst, $src}",
245 [(store (add (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
249 let Uses = [SRW] in {
251 let isCommutable = 1 in { // X = ADDC Y, Z == X = ADDC Z, Y
252 def ADC8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
253 "addc.b\t{$src2, $dst|$dst, $src2}",
254 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2)),
256 def ADC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
257 "addc.w\t{$src2, $dst|$dst, $src2}",
258 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2)),
262 def ADC8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
263 "addc.b\t{$src2, $dst|$dst, $src2}",
264 [(set GR8:$dst, (adde GR8:$src1, imm:$src2)),
266 def ADC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
267 "addc.w\t{$src2, $dst|$dst, $src2}",
268 [(set GR16:$dst, (adde GR16:$src1, imm:$src2)),
271 def ADC8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
272 "addc.b\t{$src2, $dst|$dst, $src2}",
273 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2))),
275 def ADC16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
276 "addc.w\t{$src2, $dst|$dst, $src2}",
277 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2))),
280 let isTwoAddress = 0 in {
281 def ADC8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
282 "addc.b\t{$src, $dst|$dst, $src}",
283 [(store (adde (load addr:$dst), GR8:$src), addr:$dst),
285 def ADC16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
286 "addc.w\t{$src, $dst|$dst, $src}",
287 [(store (adde (load addr:$dst), GR16:$src), addr:$dst),
290 def ADC8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
291 "addc.b\t{$src, $dst|$dst, $src}",
292 [(store (adde (load addr:$dst), (i8 imm:$src)), addr:$dst),
294 def ADC16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
295 "addc.w\t{$src, $dst|$dst, $src}",
296 [(store (adde (load addr:$dst), (i16 imm:$src)), addr:$dst),
299 def ADC8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
300 "addc.b\t{$src, $dst|$dst, $src}",
301 [(store (adde (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
303 def ADC16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
304 "addc.w\t{$src, $dst|$dst, $src}",
305 [(store (adde (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
311 let isCommutable = 1 in { // X = AND Y, Z == X = AND Z, Y
312 def AND8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
313 "and.b\t{$src2, $dst|$dst, $src2}",
314 [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
316 def AND16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
317 "and.w\t{$src2, $dst|$dst, $src2}",
318 [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
322 def AND8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
323 "and.b\t{$src2, $dst|$dst, $src2}",
324 [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
326 def AND16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
327 "and.w\t{$src2, $dst|$dst, $src2}",
328 [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
331 def AND8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
332 "and.b\t{$src2, $dst|$dst, $src2}",
333 [(set GR8:$dst, (and GR8:$src1, (load addr:$src2))),
335 def AND16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
336 "and.w\t{$src2, $dst|$dst, $src2}",
337 [(set GR16:$dst, (and GR16:$src1, (load addr:$src2))),
340 let isTwoAddress = 0 in {
341 def AND8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
342 "and.b\t{$src, $dst|$dst, $src}",
343 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
345 def AND16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
346 "and.w\t{$src, $dst|$dst, $src}",
347 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
350 def AND8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
351 "and.b\t{$src, $dst|$dst, $src}",
352 [(store (and (load addr:$dst), (i8 imm:$src)), addr:$dst),
354 def AND16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
355 "and.w\t{$src, $dst|$dst, $src}",
356 [(store (and (load addr:$dst), (i16 imm:$src)), addr:$dst),
359 def AND8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
360 "and.b\t{$src, $dst|$dst, $src}",
361 [(store (and (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
363 def AND16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
364 "and.w\t{$src, $dst|$dst, $src}",
365 [(store (and (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
370 let isCommutable = 1 in { // X = XOR Y, Z == X = XOR Z, Y
371 def XOR8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
372 "xor.b\t{$src2, $dst|$dst, $src2}",
373 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
375 def XOR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
376 "xor.w\t{$src2, $dst|$dst, $src2}",
377 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
381 def XOR8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
382 "xor.b\t{$src2, $dst|$dst, $src2}",
383 [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
385 def XOR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
386 "xor.w\t{$src2, $dst|$dst, $src2}",
387 [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
390 def XOR8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
391 "xor.b\t{$src2, $dst|$dst, $src2}",
392 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))),
394 def XOR16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
395 "xor.w\t{$src2, $dst|$dst, $src2}",
396 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
399 let isTwoAddress = 0 in {
400 def XOR8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
401 "xor.b\t{$src, $dst|$dst, $src}",
402 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
404 def XOR16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
405 "xor.w\t{$src, $dst|$dst, $src}",
406 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
409 def XOR8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
410 "xor.b\t{$src, $dst|$dst, $src}",
411 [(store (xor (load addr:$dst), (i8 imm:$src)), addr:$dst),
413 def XOR16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
414 "xor.w\t{$src, $dst|$dst, $src}",
415 [(store (xor (load addr:$dst), (i16 imm:$src)), addr:$dst),
418 def XOR8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
419 "xor.b\t{$src, $dst|$dst, $src}",
420 [(store (xor (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
422 def XOR16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
423 "xor.w\t{$src, $dst|$dst, $src}",
424 [(store (xor (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
429 def SUB8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
430 "sub.b\t{$src2, $dst|$dst, $src2}",
431 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
433 def SUB16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
434 "sub.w\t{$src2, $dst|$dst, $src2}",
435 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
438 def SUB8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
439 "sub.b\t{$src2, $dst|$dst, $src2}",
440 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
442 def SUB16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
443 "sub.w\t{$src2, $dst|$dst, $src2}",
444 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
447 def SUB8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
448 "sub.b\t{$src2, $dst|$dst, $src2}",
449 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
451 def SUB16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
452 "sub.w\t{$src2, $dst|$dst, $src2}",
453 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
456 let isTwoAddress = 0 in {
457 def SUB8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
458 "sub.b\t{$src, $dst|$dst, $src}",
459 [(store (sub (load addr:$dst), GR8:$src), addr:$dst),
461 def SUB16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
462 "sub.w\t{$src, $dst|$dst, $src}",
463 [(store (sub (load addr:$dst), GR16:$src), addr:$dst),
466 def SUB8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
467 "sub.b\t{$src, $dst|$dst, $src}",
468 [(store (sub (load addr:$dst), (i8 imm:$src)), addr:$dst),
470 def SUB16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
471 "sub.w\t{$src, $dst|$dst, $src}",
472 [(store (sub (load addr:$dst), (i16 imm:$src)), addr:$dst),
475 def SUB8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
476 "sub.b\t{$src, $dst|$dst, $src}",
477 [(store (sub (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
479 def SUB16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
480 "sub.w\t{$src, $dst|$dst, $src}",
481 [(store (sub (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
485 let Uses = [SRW] in {
486 def SBC8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
487 "subc.b\t{$src2, $dst|$dst, $src2}",
488 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2)),
490 def SBC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
491 "subc.w\t{$src2, $dst|$dst, $src2}",
492 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2)),
495 def SBC8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
496 "subc.b\t{$src2, $dst|$dst, $src2}",
497 [(set GR8:$dst, (sube GR8:$src1, imm:$src2)),
499 def SBC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
500 "subc.w\t{$src2, $dst|$dst, $src2}",
501 [(set GR16:$dst, (sube GR16:$src1, imm:$src2)),
504 def SBC8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
505 "subc.b\t{$src2, $dst|$dst, $src2}",
506 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2))),
508 def SBC16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
509 "subc.w\t{$src2, $dst|$dst, $src2}",
510 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2))),
513 let isTwoAddress = 0 in {
514 def SBC8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
515 "subc.b\t{$src, $dst|$dst, $src}",
516 [(store (sube (load addr:$dst), GR8:$src), addr:$dst),
518 def SBC16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
519 "subc.w\t{$src, $dst|$dst, $src}",
520 [(store (sube (load addr:$dst), GR16:$src), addr:$dst),
523 def SBC8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
524 "subc.b\t{$src, $dst|$dst, $src}",
525 [(store (sube (load addr:$dst), (i8 imm:$src)), addr:$dst),
527 def SBC16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
528 "subc.w\t{$src, $dst|$dst, $src}",
529 [(store (sube (load addr:$dst), (i16 imm:$src)), addr:$dst),
532 def SBC8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
533 "subc.b\t{$src, $dst|$dst, $src}",
534 [(store (sube (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
536 def SBC16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
537 "subc.w\t{$src, $dst|$dst, $src}",
538 [(store (sube (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
544 // FIXME: Provide proper encoding!
545 def SAR16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src),
547 [(set GR16:$dst, (MSP430rra GR16:$src)),
550 def SEXT16r : Pseudo<(outs GR16:$dst), (ins GR16:$src),
552 [(set GR16:$dst, (sext_inreg GR16:$src, i8)),
555 //def SEXT16r : Pseudo<(outs GR16:$dst), (ins GR16:$src),
557 // [(set GR16:$dst, (sext_inreg GR16:$src, i8)),
562 let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y
563 def OR8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
564 "bis.b\t{$src2, $dst|$dst, $src2}",
565 [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
566 def OR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
567 "bis.w\t{$src2, $dst|$dst, $src2}",
568 [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>;
571 def OR8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
572 "bis.b\t{$src2, $dst|$dst, $src2}",
573 [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
574 def OR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
575 "bis.w\t{$src2, $dst|$dst, $src2}",
576 [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>;
578 def OR8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
579 "bis.b\t{$src2, $dst|$dst, $src2}",
580 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>;
581 def OR16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
582 "bis.w\t{$src2, $dst|$dst, $src2}",
583 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>;
585 let isTwoAddress = 0 in {
586 def OR8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
587 "bis.b\t{$src, $dst|$dst, $src}",
588 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
590 def OR16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
591 "bis.w\t{$src, $dst|$dst, $src}",
592 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
595 def OR8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
596 "bis.b\t{$src, $dst|$dst, $src}",
597 [(store (or (load addr:$dst), (i8 imm:$src)), addr:$dst),
599 def OR16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
600 "bis.w\t{$src, $dst|$dst, $src}",
601 [(store (or (load addr:$dst), (i16 imm:$src)), addr:$dst),
604 def OR8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
605 "bis.b\t{$src, $dst|$dst, $src}",
606 [(store (or (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
608 def OR16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
609 "bis.w\t{$src, $dst|$dst, $src}",
610 [(store (or (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
614 } // isTwoAddress = 1
616 //===----------------------------------------------------------------------===//
617 // Non-Instruction Patterns
620 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
623 def : Pat<(i8 (trunc GR16:$src)),
624 (EXTRACT_SUBREG GR16:$src, subreg_8bit)>;
627 def : Pat<(i16 (MSP430Wrapper tglobaladdr:$dst)), (MOV16ri tglobaladdr:$dst)>;
629 def : Pat<(add GR16:$src1, (MSP430Wrapper tglobaladdr :$src2)),
630 (ADD16ri GR16:$src1, tglobaladdr:$src2)>;
633 def : Pat<(MSP430call (i16 tglobaladdr:$dst)),
634 (CALLi tglobaladdr:$dst)>;