1 //===- MSP430InstrInfo.td - MSP430 Instruction defs -----------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the MSP430 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "MSP430InstrFormats.td"
16 //===----------------------------------------------------------------------===//
18 //===----------------------------------------------------------------------===//
19 class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
20 class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
25 def SDT_MSP430Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
26 def SDT_MSP430CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>]>;
27 def SDT_MSP430CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
28 def SDT_MSP430Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
29 def SDT_MSP430SetCC : SDTypeProfile<1, 2, [SDTCisVT<0, i8>,
30 SDTCisVT<1, i8>, SDTCisVT<2, i16>]>;
31 def SDT_MSP430Cmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
32 def SDT_MSP430BrCond : SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>,
33 SDTCisVT<1, i8>, SDTCisVT<2, i16>]>;
34 def SDT_MSP430Select : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
35 SDTCisVT<3, i8>, SDTCisVT<4, i16>]>;
37 //===----------------------------------------------------------------------===//
38 // MSP430 Specific Node Definitions.
39 //===----------------------------------------------------------------------===//
40 def MSP430retflag : SDNode<"MSP430ISD::RET_FLAG", SDTNone,
41 [SDNPHasChain, SDNPOptInFlag]>;
43 def MSP430rra : SDNode<"MSP430ISD::RRA", SDTIntUnaryOp, []>;
45 def MSP430call : SDNode<"MSP430ISD::CALL", SDT_MSP430Call,
46 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
47 def MSP430callseq_start :
48 SDNode<"ISD::CALLSEQ_START", SDT_MSP430CallSeqStart,
49 [SDNPHasChain, SDNPOutFlag]>;
50 def MSP430callseq_end :
51 SDNode<"ISD::CALLSEQ_END", SDT_MSP430CallSeqEnd,
52 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
53 def MSP430Wrapper : SDNode<"MSP430ISD::Wrapper", SDT_MSP430Wrapper>;
54 def MSP430setcc : SDNode<"MSP430ISD::SETCC", SDT_MSP430SetCC>;
55 def MSP430cmp : SDNode<"MSP430ISD::CMP", SDT_MSP430Cmp>;
56 def MSP430brcond : SDNode<"MSP430ISD::BRCOND", SDT_MSP430BrCond, [SDNPHasChain]>;
57 def MSP430select : SDNode<"MSP430ISD::SELECT", SDT_MSP430Select>;
59 //===----------------------------------------------------------------------===//
60 // MSP430 Operand Definitions.
61 //===----------------------------------------------------------------------===//
64 def memsrc : Operand<i16> {
65 let PrintMethod = "printSrcMemOperand";
66 let MIOperandInfo = (ops GR16, i16imm);
69 def memdst : Operand<i16> {
70 let PrintMethod = "printSrcMemOperand";
71 let MIOperandInfo = (ops GR16, i16imm);
74 // Branch targets have OtherVT type.
75 def brtarget : Operand<OtherVT>;
77 // Operand for printing out a condition code.
78 def cc : Operand<i8> {
79 let PrintMethod = "printCCOperand";
82 //===----------------------------------------------------------------------===//
83 // MSP430 Complex Pattern Definitions.
84 //===----------------------------------------------------------------------===//
86 def addr : ComplexPattern<iPTR, 2, "SelectAddr", [], []>;
88 //===----------------------------------------------------------------------===//
90 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
91 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 ( extloadi8 node:$ptr))>;
93 //===----------------------------------------------------------------------===//
96 // ADJCALLSTACKDOWN/UP implicitly use/def SP because they may be expanded into
97 // a stack adjustment and the codegen must know that they may modify the stack
98 // pointer before prolog-epilog rewriting occurs.
99 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
100 // sub / add which can clobber SRW.
101 let Defs = [SPW, SRW], Uses = [SPW] in {
102 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i16imm:$amt),
104 [(MSP430callseq_start timm:$amt)]>;
105 def ADJCALLSTACKUP : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2),
107 [(MSP430callseq_end timm:$amt1, timm:$amt2)]>;
110 let usesCustomDAGSchedInserter = 1 in {
111 def Select16 : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cc),
114 (MSP430select GR16:$src1, GR16:$src2, imm:$cc, SRW))]>;
117 let neverHasSideEffects = 1 in
118 def NOP : Pseudo<(outs), (ins), "nop", []>;
120 //===----------------------------------------------------------------------===//
121 // Control Flow Instructions...
124 // FIXME: Provide proper encoding!
125 let isReturn = 1, isTerminator = 1 in {
126 def RET : Pseudo<(outs), (ins), "ret", [(MSP430retflag)]>;
129 // Conditional branches
130 let isBranch = 1, isTerminator = 1, Uses = [SRW] in {
131 def JCC : Pseudo<(outs), (ins brtarget:$dst, cc:$cc),
133 [(MSP430brcond bb:$dst, imm:$cc, SRW)]>;
136 //===----------------------------------------------------------------------===//
137 // Call Instructions...
140 // All calls clobber the non-callee saved registers. SPW is marked as
141 // a use to prevent stack-pointer assignments that appear immediately
142 // before calls from potentially appearing dead. Uses for argument
143 // registers are added manually.
144 let Defs = [R12W, R13W, R14W, R15W, SRW],
146 def CALLi : Pseudo<(outs), (ins i16imm:$dst, variable_ops),
147 "call\t${dst:call}", [(MSP430call imm:$dst)]>;
148 def CALLr : Pseudo<(outs), (ins GR16:$dst, variable_ops),
149 "call\t$dst", [(MSP430call GR16:$dst)]>;
150 def CALLm : Pseudo<(outs), (ins memsrc:$dst, variable_ops),
151 "call\t${dst:mem}", [(MSP430call (load addr:$dst))]>;
155 //===----------------------------------------------------------------------===//
156 // Miscellaneous Instructions...
158 let Defs = [SPW], Uses = [SPW], neverHasSideEffects=1 in {
160 def POP16r : Pseudo<(outs GR16:$reg), (ins), "pop.w\t$reg", []>;
163 def PUSH16r : Pseudo<(outs), (ins GR16:$reg), "push.w\t$reg",[]>;
166 //===----------------------------------------------------------------------===//
169 // FIXME: Provide proper encoding!
170 let neverHasSideEffects = 1 in {
171 def MOV8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src),
172 "mov.b\t{$src, $dst|$dst, $src}",
174 def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src),
175 "mov.w\t{$src, $dst|$dst, $src}",
179 // FIXME: Provide proper encoding!
180 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
181 def MOV8ri : Pseudo<(outs GR8:$dst), (ins i8imm:$src),
182 "mov.b\t{$src, $dst|$dst, $src}",
183 [(set GR8:$dst, imm:$src)]>;
184 def MOV16ri : Pseudo<(outs GR16:$dst), (ins i16imm:$src),
185 "mov.w\t{$src, $dst|$dst, $src}",
186 [(set GR16:$dst, imm:$src)]>;
189 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
190 def MOV8rm : Pseudo<(outs GR8:$dst), (ins memsrc:$src),
191 "mov.b\t{$src, $dst|$dst, $src}",
192 [(set GR8:$dst, (load addr:$src))]>;
193 def MOV16rm : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
194 "mov.w\t{$src, $dst|$dst, $src}",
195 [(set GR16:$dst, (load addr:$src))]>;
198 def MOVZX16rr8 : Pseudo<(outs GR16:$dst), (ins GR8:$src),
199 "mov.b\t{$src, $dst|$dst, $src}",
200 [(set GR16:$dst, (zext GR8:$src))]>;
201 def MOVZX16rm8 : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
202 "mov.b\t{$src, $dst|$dst, $src}",
203 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>;
205 def MOV8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
206 "mov.b\t{$src, $dst|$dst, $src}",
207 [(store (i8 imm:$src), addr:$dst)]>;
208 def MOV16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
209 "mov.w\t{$src, $dst|$dst, $src}",
210 [(store (i16 imm:$src), addr:$dst)]>;
212 def MOV8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
213 "mov.b\t{$src, $dst|$dst, $src}",
214 [(store GR8:$src, addr:$dst)]>;
215 def MOV16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
216 "mov.w\t{$src, $dst|$dst, $src}",
217 [(store GR16:$src, addr:$dst)]>;
219 //===----------------------------------------------------------------------===//
220 // Arithmetic Instructions
222 let isTwoAddress = 1 in {
224 let Defs = [SRW] in {
226 let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y
227 // FIXME: Provide proper encoding!
228 def ADD8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
229 "add.b\t{$src2, $dst|$dst, $src2}",
230 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
232 def ADD16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
233 "add.w\t{$src2, $dst|$dst, $src2}",
234 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
238 def ADD8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
239 "add.b\t{$src2, $dst|$dst, $src2}",
240 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
242 def ADD16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
243 "add.w\t{$src2, $dst|$dst, $src2}",
244 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
247 def ADD8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
248 "add.b\t{$src2, $dst|$dst, $src2}",
249 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
251 def ADD16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
252 "add.w\t{$src2, $dst|$dst, $src2}",
253 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
256 let isTwoAddress = 0 in {
257 def ADD8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
258 "add.b\t{$src, $dst|$dst, $src}",
259 [(store (add (load addr:$dst), GR8:$src), addr:$dst),
261 def ADD16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
262 "add.w\t{$src, $dst|$dst, $src}",
263 [(store (add (load addr:$dst), GR16:$src), addr:$dst),
266 def ADD8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
267 "add.b\t{$src, $dst|$dst, $src}",
268 [(store (add (load addr:$dst), (i8 imm:$src)), addr:$dst),
270 def ADD16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
271 "add.w\t{$src, $dst|$dst, $src}",
272 [(store (add (load addr:$dst), (i16 imm:$src)), addr:$dst),
275 def ADD8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
276 "add.b\t{$src, $dst|$dst, $src}",
277 [(store (add (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
279 def ADD16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
280 "add.w\t{$src, $dst|$dst, $src}",
281 [(store (add (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
285 let Uses = [SRW] in {
287 let isCommutable = 1 in { // X = ADDC Y, Z == X = ADDC Z, Y
288 def ADC8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
289 "addc.b\t{$src2, $dst|$dst, $src2}",
290 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2)),
292 def ADC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
293 "addc.w\t{$src2, $dst|$dst, $src2}",
294 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2)),
298 def ADC8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
299 "addc.b\t{$src2, $dst|$dst, $src2}",
300 [(set GR8:$dst, (adde GR8:$src1, imm:$src2)),
302 def ADC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
303 "addc.w\t{$src2, $dst|$dst, $src2}",
304 [(set GR16:$dst, (adde GR16:$src1, imm:$src2)),
307 def ADC8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
308 "addc.b\t{$src2, $dst|$dst, $src2}",
309 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2))),
311 def ADC16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
312 "addc.w\t{$src2, $dst|$dst, $src2}",
313 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2))),
316 let isTwoAddress = 0 in {
317 def ADC8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
318 "addc.b\t{$src, $dst|$dst, $src}",
319 [(store (adde (load addr:$dst), GR8:$src), addr:$dst),
321 def ADC16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
322 "addc.w\t{$src, $dst|$dst, $src}",
323 [(store (adde (load addr:$dst), GR16:$src), addr:$dst),
326 def ADC8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
327 "addc.b\t{$src, $dst|$dst, $src}",
328 [(store (adde (load addr:$dst), (i8 imm:$src)), addr:$dst),
330 def ADC16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
331 "addc.w\t{$src, $dst|$dst, $src}",
332 [(store (adde (load addr:$dst), (i16 imm:$src)), addr:$dst),
335 def ADC8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
336 "addc.b\t{$src, $dst|$dst, $src}",
337 [(store (adde (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
339 def ADC16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
340 "addc.w\t{$src, $dst|$dst, $src}",
341 [(store (adde (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
347 let isCommutable = 1 in { // X = AND Y, Z == X = AND Z, Y
348 def AND8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
349 "and.b\t{$src2, $dst|$dst, $src2}",
350 [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
352 def AND16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
353 "and.w\t{$src2, $dst|$dst, $src2}",
354 [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
358 def AND8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
359 "and.b\t{$src2, $dst|$dst, $src2}",
360 [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
362 def AND16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
363 "and.w\t{$src2, $dst|$dst, $src2}",
364 [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
367 def AND8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
368 "and.b\t{$src2, $dst|$dst, $src2}",
369 [(set GR8:$dst, (and GR8:$src1, (load addr:$src2))),
371 def AND16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
372 "and.w\t{$src2, $dst|$dst, $src2}",
373 [(set GR16:$dst, (and GR16:$src1, (load addr:$src2))),
376 let isTwoAddress = 0 in {
377 def AND8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
378 "and.b\t{$src, $dst|$dst, $src}",
379 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
381 def AND16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
382 "and.w\t{$src, $dst|$dst, $src}",
383 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
386 def AND8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
387 "and.b\t{$src, $dst|$dst, $src}",
388 [(store (and (load addr:$dst), (i8 imm:$src)), addr:$dst),
390 def AND16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
391 "and.w\t{$src, $dst|$dst, $src}",
392 [(store (and (load addr:$dst), (i16 imm:$src)), addr:$dst),
395 def AND8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
396 "and.b\t{$src, $dst|$dst, $src}",
397 [(store (and (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
399 def AND16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
400 "and.w\t{$src, $dst|$dst, $src}",
401 [(store (and (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
406 let isCommutable = 1 in { // X = XOR Y, Z == X = XOR Z, Y
407 def XOR8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
408 "xor.b\t{$src2, $dst|$dst, $src2}",
409 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
411 def XOR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
412 "xor.w\t{$src2, $dst|$dst, $src2}",
413 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
417 def XOR8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
418 "xor.b\t{$src2, $dst|$dst, $src2}",
419 [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
421 def XOR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
422 "xor.w\t{$src2, $dst|$dst, $src2}",
423 [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
426 def XOR8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
427 "xor.b\t{$src2, $dst|$dst, $src2}",
428 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))),
430 def XOR16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
431 "xor.w\t{$src2, $dst|$dst, $src2}",
432 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
435 let isTwoAddress = 0 in {
436 def XOR8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
437 "xor.b\t{$src, $dst|$dst, $src}",
438 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
440 def XOR16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
441 "xor.w\t{$src, $dst|$dst, $src}",
442 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
445 def XOR8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
446 "xor.b\t{$src, $dst|$dst, $src}",
447 [(store (xor (load addr:$dst), (i8 imm:$src)), addr:$dst),
449 def XOR16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
450 "xor.w\t{$src, $dst|$dst, $src}",
451 [(store (xor (load addr:$dst), (i16 imm:$src)), addr:$dst),
454 def XOR8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
455 "xor.b\t{$src, $dst|$dst, $src}",
456 [(store (xor (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
458 def XOR16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
459 "xor.w\t{$src, $dst|$dst, $src}",
460 [(store (xor (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
465 def SUB8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
466 "sub.b\t{$src2, $dst|$dst, $src2}",
467 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
469 def SUB16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
470 "sub.w\t{$src2, $dst|$dst, $src2}",
471 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
474 def SUB8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
475 "sub.b\t{$src2, $dst|$dst, $src2}",
476 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
478 def SUB16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
479 "sub.w\t{$src2, $dst|$dst, $src2}",
480 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
483 def SUB8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
484 "sub.b\t{$src2, $dst|$dst, $src2}",
485 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
487 def SUB16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
488 "sub.w\t{$src2, $dst|$dst, $src2}",
489 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
492 let isTwoAddress = 0 in {
493 def SUB8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
494 "sub.b\t{$src, $dst|$dst, $src}",
495 [(store (sub (load addr:$dst), GR8:$src), addr:$dst),
497 def SUB16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
498 "sub.w\t{$src, $dst|$dst, $src}",
499 [(store (sub (load addr:$dst), GR16:$src), addr:$dst),
502 def SUB8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
503 "sub.b\t{$src, $dst|$dst, $src}",
504 [(store (sub (load addr:$dst), (i8 imm:$src)), addr:$dst),
506 def SUB16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
507 "sub.w\t{$src, $dst|$dst, $src}",
508 [(store (sub (load addr:$dst), (i16 imm:$src)), addr:$dst),
511 def SUB8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
512 "sub.b\t{$src, $dst|$dst, $src}",
513 [(store (sub (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
515 def SUB16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
516 "sub.w\t{$src, $dst|$dst, $src}",
517 [(store (sub (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
521 let Uses = [SRW] in {
522 def SBC8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
523 "subc.b\t{$src2, $dst|$dst, $src2}",
524 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2)),
526 def SBC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
527 "subc.w\t{$src2, $dst|$dst, $src2}",
528 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2)),
531 def SBC8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
532 "subc.b\t{$src2, $dst|$dst, $src2}",
533 [(set GR8:$dst, (sube GR8:$src1, imm:$src2)),
535 def SBC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
536 "subc.w\t{$src2, $dst|$dst, $src2}",
537 [(set GR16:$dst, (sube GR16:$src1, imm:$src2)),
540 def SBC8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
541 "subc.b\t{$src2, $dst|$dst, $src2}",
542 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2))),
544 def SBC16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
545 "subc.w\t{$src2, $dst|$dst, $src2}",
546 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2))),
549 let isTwoAddress = 0 in {
550 def SBC8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
551 "subc.b\t{$src, $dst|$dst, $src}",
552 [(store (sube (load addr:$dst), GR8:$src), addr:$dst),
554 def SBC16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
555 "subc.w\t{$src, $dst|$dst, $src}",
556 [(store (sube (load addr:$dst), GR16:$src), addr:$dst),
559 def SBC8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
560 "subc.b\t{$src, $dst|$dst, $src}",
561 [(store (sube (load addr:$dst), (i8 imm:$src)), addr:$dst),
563 def SBC16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
564 "subc.w\t{$src, $dst|$dst, $src}",
565 [(store (sube (load addr:$dst), (i16 imm:$src)), addr:$dst),
568 def SBC8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
569 "subc.b\t{$src, $dst|$dst, $src}",
570 [(store (sube (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
572 def SBC16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
573 "subc.w\t{$src, $dst|$dst, $src}",
574 [(store (sube (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
580 // FIXME: Provide proper encoding!
581 def SAR16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src),
583 [(set GR16:$dst, (MSP430rra GR16:$src)),
586 def SEXT16r : Pseudo<(outs GR16:$dst), (ins GR16:$src),
588 [(set GR16:$dst, (sext_inreg GR16:$src, i8)),
591 //def SEXT16r : Pseudo<(outs GR16:$dst), (ins GR16:$src),
593 // [(set GR16:$dst, (sext_inreg GR16:$src, i8)),
598 let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y
599 def OR8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
600 "bis.b\t{$src2, $dst|$dst, $src2}",
601 [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
602 def OR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
603 "bis.w\t{$src2, $dst|$dst, $src2}",
604 [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>;
607 def OR8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
608 "bis.b\t{$src2, $dst|$dst, $src2}",
609 [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
610 def OR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
611 "bis.w\t{$src2, $dst|$dst, $src2}",
612 [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>;
614 def OR8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
615 "bis.b\t{$src2, $dst|$dst, $src2}",
616 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>;
617 def OR16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
618 "bis.w\t{$src2, $dst|$dst, $src2}",
619 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>;
621 let isTwoAddress = 0 in {
622 def OR8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
623 "bis.b\t{$src, $dst|$dst, $src}",
624 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
626 def OR16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
627 "bis.w\t{$src, $dst|$dst, $src}",
628 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
631 def OR8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
632 "bis.b\t{$src, $dst|$dst, $src}",
633 [(store (or (load addr:$dst), (i8 imm:$src)), addr:$dst),
635 def OR16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
636 "bis.w\t{$src, $dst|$dst, $src}",
637 [(store (or (load addr:$dst), (i16 imm:$src)), addr:$dst),
640 def OR8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
641 "bis.b\t{$src, $dst|$dst, $src}",
642 [(store (or (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
644 def OR16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
645 "bis.w\t{$src, $dst|$dst, $src}",
646 [(store (or (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
650 } // isTwoAddress = 1
652 // Integer comparisons
653 let Defs = [SRW] in {
654 def CMP8rr : Pseudo<(outs), (ins GR8:$src1, GR8:$src2),
655 "cmp.b\t{$src1, $src2}",
656 [(MSP430cmp GR8:$src1, GR8:$src2), (implicit SRW)]>;
657 def CMP16rr : Pseudo<(outs), (ins GR16:$src1, GR16:$src2),
658 "cmp.w\t{$src1, $src2}",
659 [(MSP430cmp GR16:$src1, GR16:$src2), (implicit SRW)]>;
661 def CMP8ri : Pseudo<(outs), (ins GR8:$src1, i8imm:$src2),
662 "cmp.b\t{$src1, $src2}",
663 [(MSP430cmp GR8:$src1, imm:$src2), (implicit SRW)]>;
664 def CMP16ri : Pseudo<(outs), (ins GR16:$src1, i16imm:$src2),
665 "cmp.w\t{$src1, $src2}",
666 [(MSP430cmp GR16:$src1, imm:$src2), (implicit SRW)]>;
668 def CMP8rm : Pseudo<(outs), (ins GR8:$src1, memsrc:$src2),
669 "cmp.b\t{$src2, $src1|$src1, $src2}",
670 [(MSP430cmp GR8:$src1, (load addr:$src2)), (implicit SRW)]>;
671 def CMP16rm : Pseudo<(outs), (ins GR16:$src1, memsrc:$src2),
672 "cmp.w\t{$src2, $src1|$src1, $src2}",
673 [(MSP430cmp GR16:$src1, (load addr:$src2)), (implicit SRW)]>;
675 def CMP8mr : Pseudo<(outs), (ins memsrc:$src1, GR8:$src2),
676 "cmp.b\t{$src2, $src1|$src1, $src2}",
677 [(MSP430cmp (load addr:$src1), GR8:$src2), (implicit SRW)]>;
678 def CMP16mr : Pseudo<(outs), (ins memsrc:$src1, GR16:$src2),
679 "cmp.w\t{$src2, $src1|$src1, $src2}",
680 [(MSP430cmp (load addr:$src1), GR16:$src2), (implicit SRW)]>;
682 def CMP8mi : Pseudo<(outs), (ins memsrc:$src1, i8imm:$src2),
683 "cmp.b\t{$src2, $src1|$src1, $src2}",
684 [(MSP430cmp (load addr:$src1), (i8 imm:$src2)), (implicit SRW)]>;
685 def CMP16mi : Pseudo<(outs), (ins memsrc:$src1, i16imm:$src2),
686 "cmp.w\t{$src2, $src1|$src1, $src2}",
687 [(MSP430cmp (load addr:$src1), (i16 imm:$src2)), (implicit SRW)]>;
689 def CMP8mm : Pseudo<(outs), (ins memsrc:$src1, memsrc:$src2),
690 "cmp.b\t{$src2, $src1|$src1, $src2}",
691 [(MSP430cmp (load addr:$src1), (i8 (load addr:$src2))), (implicit SRW)]>;
692 def CMP16mm : Pseudo<(outs), (ins memsrc:$src1, memsrc:$src2),
693 "cmp.w\t{$src2, $src1|$src1, $src2}",
694 [(MSP430cmp (load addr:$src1), (i16 (load addr:$src2))), (implicit SRW)]>;
697 //===----------------------------------------------------------------------===//
698 // Non-Instruction Patterns
701 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
704 def : Pat<(i8 (trunc GR16:$src)),
705 (EXTRACT_SUBREG GR16:$src, subreg_8bit)>;
708 def : Pat<(i16 (MSP430Wrapper tglobaladdr:$dst)), (MOV16ri tglobaladdr:$dst)>;
710 def : Pat<(add GR16:$src1, (MSP430Wrapper tglobaladdr :$src2)),
711 (ADD16ri GR16:$src1, tglobaladdr:$src2)>;
714 def : Pat<(MSP430call (i16 tglobaladdr:$dst)),
715 (CALLi tglobaladdr:$dst)>;