1 //===- MSP430InstrInfo.td - MSP430 Instruction defs -----------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the MSP430 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "MSP430InstrFormats.td"
16 //===----------------------------------------------------------------------===//
18 //===----------------------------------------------------------------------===//
19 class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
20 class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
26 //===----------------------------------------------------------------------===//
27 // MSP430 Specific Node Definitions.
28 //===----------------------------------------------------------------------===//
29 def MSP430retflag : SDNode<"MSP430ISD::RET_FLAG", SDTNone,
30 [SDNPHasChain, SDNPOptInFlag]>;
32 def MSP430rra : SDNode<"MSP430ISD::RRA", SDTIntUnaryOp, []>;
34 //===----------------------------------------------------------------------===//
35 // MSP430 Operand Definitions.
36 //===----------------------------------------------------------------------===//
39 def memsrc : Operand<i16> {
40 let PrintMethod = "printSrcMemOperand";
41 let MIOperandInfo = (ops i16imm, GR16);
45 //===----------------------------------------------------------------------===//
46 // MSP430 Complex Pattern Definitions.
47 //===----------------------------------------------------------------------===//
49 def addr : ComplexPattern<iPTR, 2, "SelectAddr", [], []>;
51 //===----------------------------------------------------------------------===//
53 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
54 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 ( extloadi8 node:$ptr))>;
56 //===----------------------------------------------------------------------===//
57 // Pseudo Instructions
59 let neverHasSideEffects = 1 in
60 def NOP : Pseudo<(outs), (ins), "nop", []>;
62 //===----------------------------------------------------------------------===//
65 // FIXME: Provide proper encoding!
66 let isReturn = 1, isTerminator = 1 in {
67 def RETI : Pseudo<(outs), (ins), "ret", [(MSP430retflag)]>;
70 //===----------------------------------------------------------------------===//
73 // FIXME: Provide proper encoding!
74 let neverHasSideEffects = 1 in {
75 def MOV8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src),
76 "mov.b\t{$src, $dst|$dst, $src}",
78 def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src),
79 "mov.w\t{$src, $dst|$dst, $src}",
83 // FIXME: Provide proper encoding!
84 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
85 def MOV8ri : Pseudo<(outs GR8:$dst), (ins i8imm:$src),
86 "mov.b\t{$src, $dst|$dst, $src}",
87 [(set GR8:$dst, imm:$src)]>;
88 def MOV16ri : Pseudo<(outs GR16:$dst), (ins i16imm:$src),
89 "mov.w\t{$src, $dst|$dst, $src}",
90 [(set GR16:$dst, imm:$src)]>;
93 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
94 def MOV8rm : Pseudo<(outs GR8:$dst), (ins memsrc:$src),
95 "mov.b\t{$src, $dst|$dst, $src}",
96 [(set GR8:$dst, (load addr:$src))]>;
97 def MOV16rm : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
98 "mov.w\t{$src, $dst|$dst, $src}",
99 [(set GR16:$dst, (load addr:$src))]>;
102 def MOVZX16rr8 : Pseudo<(outs GR16:$dst), (ins GR8:$src),
103 "mov.b\t{$src, $dst|$dst, $src}",
104 [(set GR16:$dst, (zext GR8:$src))]>;
105 def MOVZX16rm8 : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
106 "mov.b\t{$src, $dst|$dst, $src}",
107 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>;
109 //===----------------------------------------------------------------------===//
110 // Arithmetic Instructions
112 let isTwoAddress = 1 in {
114 let Defs = [SRW] in {
116 let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y
117 // FIXME: Provide proper encoding!
118 def ADD16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
119 "add.w\t{$src2, $dst|$dst, $src2}",
120 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
123 def ADD8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
124 "add.b\t{$src2, $dst|$dst, $src2}",
125 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
129 def ADD16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
130 "add.w\t{$src2, $dst|$dst, $src2}",
131 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
133 def ADD8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
134 "add.b\t{$src2, $dst|$dst, $src2}",
135 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
138 let Uses = [SRW] in {
140 let isCommutable = 1 in { // X = ADDC Y, Z == X = ADDC Z, Y
141 def ADC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
142 "addc.w\t{$src2, $dst|$dst, $src2}",
143 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2)),
145 def ADC8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
146 "addc.b\t{$src2, $dst|$dst, $src2}",
147 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2)),
151 def ADC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
152 "addc.w\t{$src2, $dst|$dst, $src2}",
153 [(set GR16:$dst, (adde GR16:$src1, imm:$src2)),
155 def ADC8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
156 "addc.b\t{$src2, $dst|$dst, $src2}",
157 [(set GR8:$dst, (adde GR8:$src1, imm:$src2)),
161 let isCommutable = 1 in { // X = AND Y, Z == X = AND Z, Y
162 def AND16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
163 "and.w\t{$src2, $dst|$dst, $src2}",
164 [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
166 def AND8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
167 "and.b\t{$src2, $dst|$dst, $src2}",
168 [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
172 def AND16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
173 "and.w\t{$src2, $dst|$dst, $src2}",
174 [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
176 def AND8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
177 "and.b\t{$src2, $dst|$dst, $src2}",
178 [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
181 let isCommutable = 1 in { // X = XOR Y, Z == X = XOR Z, Y
182 def XOR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
183 "xor.w\t{$src2, $dst|$dst, $src2}",
184 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
186 def XOR8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
187 "xor.b\t{$src2, $dst|$dst, $src2}",
188 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
192 def XOR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
193 "xor.w\t{$src2, $dst|$dst, $src2}",
194 [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
196 def XOR8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
197 "xor.b\t{$src2, $dst|$dst, $src2}",
198 [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
202 def SUB16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
203 "sub.w\t{$src2, $dst|$dst, $src2}",
204 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
206 def SUB8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
207 "sub.b\t{$src2, $dst|$dst, $src2}",
208 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
211 def SUB16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
212 "sub.w\t{$src2, $dst|$dst, $src2}",
213 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
215 def SUB8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
216 "sub.b\t{$src2, $dst|$dst, $src2}",
217 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
220 let Uses = [SRW] in {
221 def SBC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
222 "subc.w\t{$src2, $dst|$dst, $src2}",
223 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2)),
225 def SBC8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
226 "subc.b\t{$src2, $dst|$dst, $src2}",
227 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2)),
230 def SBC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
231 "subc.w\t{$src2, $dst|$dst, $src2}",
232 [(set GR16:$dst, (sube GR16:$src1, imm:$src2)),
234 def SBC8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
235 "subc.b\t{$src2, $dst|$dst, $src2}",
236 [(set GR8:$dst, (sube GR8:$src1, imm:$src2)),
240 // FIXME: Provide proper encoding!
241 def SAR16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src),
243 [(set GR16:$dst, (MSP430rra GR16:$src)),
246 def SEXT16r : Pseudo<(outs GR16:$dst), (ins GR16:$src),
248 [(set GR16:$dst, (sext_inreg GR16:$src, i8)),
253 let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y
254 def OR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
255 "bis.w\t{$src2, $dst|$dst, $src2}",
256 [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>;
257 def OR8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
258 "bis.b\t{$src2, $dst|$dst, $src2}",
259 [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
262 def OR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
263 "bis.w\t{$src2, $dst|$dst, $src2}",
264 [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>;
265 def OR8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
266 "bis.b\t{$src2, $dst|$dst, $src2}",
267 [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
269 } // isTwoAddress = 1
271 //===----------------------------------------------------------------------===//
272 // Non-Instruction Patterns
275 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;