1 //===- MSP430InstrInfo.cpp - MSP430 Instruction Information ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MSP430 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "MSP430InstrInfo.h"
16 #include "MSP430MachineFunctionInfo.h"
17 #include "MSP430TargetMachine.h"
18 #include "llvm/Function.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/TargetRegistry.h"
25 #define GET_INSTRINFO_CTOR
26 #include "MSP430GenInstrInfo.inc"
30 MSP430InstrInfo::MSP430InstrInfo(MSP430TargetMachine &tm)
31 : MSP430GenInstrInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
32 RI(tm, *this), TM(tm) {}
34 void MSP430InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
35 MachineBasicBlock::iterator MI,
36 unsigned SrcReg, bool isKill, int FrameIdx,
37 const TargetRegisterClass *RC,
38 const TargetRegisterInfo *TRI) const {
40 if (MI != MBB.end()) DL = MI->getDebugLoc();
41 MachineFunction &MF = *MBB.getParent();
42 MachineFrameInfo &MFI = *MF.getFrameInfo();
44 MachineMemOperand *MMO =
45 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
46 MachineMemOperand::MOStore,
47 MFI.getObjectSize(FrameIdx),
48 MFI.getObjectAlignment(FrameIdx));
50 if (RC == &MSP430::GR16RegClass)
51 BuildMI(MBB, MI, DL, get(MSP430::MOV16mr))
52 .addFrameIndex(FrameIdx).addImm(0)
53 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
54 else if (RC == &MSP430::GR8RegClass)
55 BuildMI(MBB, MI, DL, get(MSP430::MOV8mr))
56 .addFrameIndex(FrameIdx).addImm(0)
57 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
59 llvm_unreachable("Cannot store this register to stack slot!");
62 void MSP430InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
63 MachineBasicBlock::iterator MI,
64 unsigned DestReg, int FrameIdx,
65 const TargetRegisterClass *RC,
66 const TargetRegisterInfo *TRI) const{
68 if (MI != MBB.end()) DL = MI->getDebugLoc();
69 MachineFunction &MF = *MBB.getParent();
70 MachineFrameInfo &MFI = *MF.getFrameInfo();
72 MachineMemOperand *MMO =
73 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
74 MachineMemOperand::MOLoad,
75 MFI.getObjectSize(FrameIdx),
76 MFI.getObjectAlignment(FrameIdx));
78 if (RC == &MSP430::GR16RegClass)
79 BuildMI(MBB, MI, DL, get(MSP430::MOV16rm))
80 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
81 else if (RC == &MSP430::GR8RegClass)
82 BuildMI(MBB, MI, DL, get(MSP430::MOV8rm))
83 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
85 llvm_unreachable("Cannot store this register to stack slot!");
88 void MSP430InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
89 MachineBasicBlock::iterator I, DebugLoc DL,
90 unsigned DestReg, unsigned SrcReg,
93 if (MSP430::GR16RegClass.contains(DestReg, SrcReg))
94 Opc = MSP430::MOV16rr;
95 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg))
98 llvm_unreachable("Impossible reg-to-reg copy");
100 BuildMI(MBB, I, DL, get(Opc), DestReg)
101 .addReg(SrcReg, getKillRegState(KillSrc));
104 unsigned MSP430InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
105 MachineBasicBlock::iterator I = MBB.end();
108 while (I != MBB.begin()) {
110 if (I->isDebugValue())
112 if (I->getOpcode() != MSP430::JMP &&
113 I->getOpcode() != MSP430::JCC &&
114 I->getOpcode() != MSP430::Br &&
115 I->getOpcode() != MSP430::Bm)
117 // Remove the branch.
118 I->eraseFromParent();
126 bool MSP430InstrInfo::
127 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
128 assert(Cond.size() == 1 && "Invalid Xbranch condition!");
130 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm());
134 assert(0 && "Invalid branch condition!");
136 case MSP430CC::COND_E:
137 CC = MSP430CC::COND_NE;
139 case MSP430CC::COND_NE:
140 CC = MSP430CC::COND_E;
142 case MSP430CC::COND_L:
143 CC = MSP430CC::COND_GE;
145 case MSP430CC::COND_GE:
146 CC = MSP430CC::COND_L;
148 case MSP430CC::COND_HS:
149 CC = MSP430CC::COND_LO;
151 case MSP430CC::COND_LO:
152 CC = MSP430CC::COND_HS;
160 bool MSP430InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
161 if (!MI->isTerminator()) return false;
163 // Conditional branch is a special case.
164 if (MI->isBranch() && !MI->isBarrier())
166 if (!MI->isPredicable())
168 return !isPredicated(MI);
171 bool MSP430InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
172 MachineBasicBlock *&TBB,
173 MachineBasicBlock *&FBB,
174 SmallVectorImpl<MachineOperand> &Cond,
175 bool AllowModify) const {
176 // Start from the bottom of the block and work up, examining the
177 // terminator instructions.
178 MachineBasicBlock::iterator I = MBB.end();
179 while (I != MBB.begin()) {
181 if (I->isDebugValue())
184 // Working from the bottom, when we see a non-terminator
185 // instruction, we're done.
186 if (!isUnpredicatedTerminator(I))
189 // A terminator that isn't a branch can't easily be handled
194 // Cannot handle indirect branches.
195 if (I->getOpcode() == MSP430::Br ||
196 I->getOpcode() == MSP430::Bm)
199 // Handle unconditional branches.
200 if (I->getOpcode() == MSP430::JMP) {
202 TBB = I->getOperand(0).getMBB();
206 // If the block has any instructions after a JMP, delete them.
207 while (llvm::next(I) != MBB.end())
208 llvm::next(I)->eraseFromParent();
212 // Delete the JMP if it's equivalent to a fall-through.
213 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
215 I->eraseFromParent();
220 // TBB is used to indicate the unconditinal destination.
221 TBB = I->getOperand(0).getMBB();
225 // Handle conditional branches.
226 assert(I->getOpcode() == MSP430::JCC && "Invalid conditional branch");
227 MSP430CC::CondCodes BranchCode =
228 static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm());
229 if (BranchCode == MSP430CC::COND_INVALID)
230 return true; // Can't handle weird stuff.
232 // Working from the bottom, handle the first conditional branch.
235 TBB = I->getOperand(0).getMBB();
236 Cond.push_back(MachineOperand::CreateImm(BranchCode));
240 // Handle subsequent conditional branches. Only handle the case where all
241 // conditional branches branch to the same destination.
242 assert(Cond.size() == 1);
245 // Only handle the case where all conditional branches branch to
246 // the same destination.
247 if (TBB != I->getOperand(0).getMBB())
250 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm();
251 // If the conditions are the same, we can leave them alone.
252 if (OldBranchCode == BranchCode)
262 MSP430InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
263 MachineBasicBlock *FBB,
264 const SmallVectorImpl<MachineOperand> &Cond,
266 // Shouldn't be a fall through.
267 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
268 assert((Cond.size() == 1 || Cond.size() == 0) &&
269 "MSP430 branch conditions have one component!");
272 // Unconditional branch?
273 assert(!FBB && "Unconditional branch with multiple successors!");
274 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(TBB);
278 // Conditional branch.
280 BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm());
284 // Two-way Conditional branch. Insert the second branch.
285 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(FBB);
291 /// GetInstSize - Return the number of bytes of code the specified
292 /// instruction may be. This returns the maximum number of bytes.
294 unsigned MSP430InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
295 const MCInstrDesc &Desc = MI->getDesc();
297 switch (Desc.TSFlags & MSP430II::SizeMask) {
299 switch (Desc.getOpcode()) {
301 assert(0 && "Unknown instruction size!");
302 case TargetOpcode::PROLOG_LABEL:
303 case TargetOpcode::EH_LABEL:
304 case TargetOpcode::IMPLICIT_DEF:
305 case TargetOpcode::KILL:
306 case TargetOpcode::DBG_VALUE:
308 case TargetOpcode::INLINEASM: {
309 const MachineFunction *MF = MI->getParent()->getParent();
310 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
311 return TII.getInlineAsmLength(MI->getOperand(0).getSymbolName(),
312 *MF->getTarget().getMCAsmInfo());
315 case MSP430II::SizeSpecial:
316 switch (MI->getOpcode()) {
318 assert(0 && "Unknown instruction size!");
319 case MSP430::SAR8r1c:
320 case MSP430::SAR16r1c:
323 case MSP430II::Size2Bytes:
325 case MSP430II::Size4Bytes:
327 case MSP430II::Size6Bytes: