1 //===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the MSP430TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "msp430-lower"
16 #include "MSP430ISelLowering.h"
18 #include "MSP430TargetMachine.h"
19 #include "MSP430Subtarget.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/PseudoSourceValue.h"
32 #include "llvm/CodeGen/SelectionDAGISel.h"
33 #include "llvm/CodeGen/ValueTypes.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/ADT/VectorExtras.h"
38 MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
39 TargetLowering(tm), Subtarget(*tm.getSubtargetImpl()), TM(tm) {
41 // Set up the register classes.
42 addRegisterClass(MVT::i8, MSP430::GR8RegisterClass);
43 addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
45 // Compute derived properties from the register classes
46 computeRegisterProperties();
48 // Provide all sorts of operation actions
50 // Division is expensive
51 setIntDivIsCheap(false);
53 // Even if we have only 1 bit shift here, we can perform
54 // shifts of the whole bitwidth 1 bit per step.
55 setShiftAmountType(MVT::i8);
57 setStackPointerRegisterToSaveRestore(MSP430::SPW);
58 setBooleanContents(ZeroOrOneBooleanContent);
59 setSchedulingPreference(SchedulingForLatency);
61 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
62 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
63 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
64 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
65 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
67 // We don't have any truncstores
68 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
70 setOperationAction(ISD::SRA, MVT::i16, Custom);
71 setOperationAction(ISD::SHL, MVT::i16, Custom);
72 setOperationAction(ISD::RET, MVT::Other, Custom);
73 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
74 setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom);
75 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
76 setOperationAction(ISD::BRIND, MVT::Other, Expand);
77 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
78 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
79 setOperationAction(ISD::SETCC, MVT::i8, Custom);
80 setOperationAction(ISD::SETCC, MVT::i16, Custom);
81 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
82 setOperationAction(ISD::SELECT, MVT::i8, Custom);
83 setOperationAction(ISD::SELECT, MVT::i16, Custom);
85 // FIXME: Implement efficiently multiplication by a constant
86 setOperationAction(ISD::MUL, MVT::i16, Expand);
87 setOperationAction(ISD::MULHS, MVT::i16, Expand);
88 setOperationAction(ISD::MULHU, MVT::i16, Expand);
89 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
90 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
93 SDValue MSP430TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
94 switch (Op.getOpcode()) {
95 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
96 case ISD::SHL: // FALLTHROUGH
97 case ISD::SRA: return LowerShifts(Op, DAG);
98 case ISD::RET: return LowerRET(Op, DAG);
99 case ISD::CALL: return LowerCALL(Op, DAG);
100 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
101 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
102 case ISD::SETCC: return LowerSETCC(Op, DAG);
103 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
104 case ISD::SELECT: return LowerSELECT(Op, DAG);
106 assert(0 && "unimplemented operand");
111 //===----------------------------------------------------------------------===//
112 // Calling Convention Implementation
113 //===----------------------------------------------------------------------===//
115 #include "MSP430GenCallingConv.inc"
117 SDValue MSP430TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
119 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
122 assert(0 && "Unsupported calling convention");
124 case CallingConv::Fast:
125 return LowerCCCArguments(Op, DAG);
129 SDValue MSP430TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
130 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
131 unsigned CallingConv = TheCall->getCallingConv();
132 switch (CallingConv) {
134 assert(0 && "Unsupported calling convention");
135 case CallingConv::Fast:
137 return LowerCCCCallTo(Op, DAG, CallingConv);
141 /// LowerCCCArguments - transform physical registers into virtual registers and
142 /// generate load operations for arguments places on the stack.
143 // FIXME: struct return stuff
145 SDValue MSP430TargetLowering::LowerCCCArguments(SDValue Op,
147 MachineFunction &MF = DAG.getMachineFunction();
148 MachineFrameInfo *MFI = MF.getFrameInfo();
149 MachineRegisterInfo &RegInfo = MF.getRegInfo();
150 SDValue Root = Op.getOperand(0);
151 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
152 unsigned CC = MF.getFunction()->getCallingConv();
153 DebugLoc dl = Op.getDebugLoc();
155 // Assign locations to all of the incoming arguments.
156 SmallVector<CCValAssign, 16> ArgLocs;
157 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
158 CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_MSP430);
160 assert(!isVarArg && "Varargs not supported yet");
162 SmallVector<SDValue, 16> ArgValues;
163 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
164 CCValAssign &VA = ArgLocs[i];
166 // Arguments passed in registers
167 MVT RegVT = VA.getLocVT();
168 switch (RegVT.getSimpleVT()) {
170 cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
171 << RegVT.getSimpleVT()
176 RegInfo.createVirtualRegister(MSP430::GR16RegisterClass);
177 RegInfo.addLiveIn(VA.getLocReg(), VReg);
178 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, VReg, RegVT);
180 // If this is an 8-bit value, it is really passed promoted to 16
181 // bits. Insert an assert[sz]ext to capture this, then truncate to the
183 if (VA.getLocInfo() == CCValAssign::SExt)
184 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
185 DAG.getValueType(VA.getValVT()));
186 else if (VA.getLocInfo() == CCValAssign::ZExt)
187 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
188 DAG.getValueType(VA.getValVT()));
190 if (VA.getLocInfo() != CCValAssign::Full)
191 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
193 ArgValues.push_back(ArgValue);
197 assert(VA.isMemLoc());
198 // Load the argument to a virtual register
199 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
201 cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
202 << VA.getLocVT().getSimpleVT()
205 // Create the frame index object for this incoming parameter...
206 int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset());
208 // Create the SelectionDAG nodes corresponding to a load
209 //from this parameter
210 SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
211 ArgValues.push_back(DAG.getLoad(VA.getLocVT(), dl, Root, FIN,
212 PseudoSourceValue::getFixedStack(FI), 0));
216 ArgValues.push_back(Root);
218 // Return the new list of results.
219 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
220 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
223 SDValue MSP430TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
224 // CCValAssign - represent the assignment of the return value to a location
225 SmallVector<CCValAssign, 16> RVLocs;
226 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
227 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
228 DebugLoc dl = Op.getDebugLoc();
230 // CCState - Info about the registers and stack slot.
231 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
233 // Analize return values of ISD::RET
234 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_MSP430);
236 // If this is the first return lowered for this function, add the regs to the
237 // liveout set for the function.
238 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
239 for (unsigned i = 0; i != RVLocs.size(); ++i)
240 if (RVLocs[i].isRegLoc())
241 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
244 // The chain is always operand #0
245 SDValue Chain = Op.getOperand(0);
248 // Copy the result values into the output registers.
249 for (unsigned i = 0; i != RVLocs.size(); ++i) {
250 CCValAssign &VA = RVLocs[i];
251 assert(VA.isRegLoc() && "Can only return in registers!");
253 // ISD::RET => ret chain, (regnum1,val1), ...
254 // So i*2+1 index only the regnums
255 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
256 Op.getOperand(i*2+1), Flag);
258 // Guarantee that all emitted copies are stuck together,
259 // avoiding something bad.
260 Flag = Chain.getValue(1);
264 return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
267 return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain);
270 /// LowerCCCCallTo - functions arguments are copied from virtual regs to
271 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
273 SDValue MSP430TargetLowering::LowerCCCCallTo(SDValue Op, SelectionDAG &DAG,
275 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
276 SDValue Chain = TheCall->getChain();
277 SDValue Callee = TheCall->getCallee();
278 bool isVarArg = TheCall->isVarArg();
279 DebugLoc dl = Op.getDebugLoc();
281 // Analyze operands of the call, assigning locations to each operand.
282 SmallVector<CCValAssign, 16> ArgLocs;
283 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
285 CCInfo.AnalyzeCallOperands(TheCall, CC_MSP430);
287 // Get a count of how many bytes are to be pushed on the stack.
288 unsigned NumBytes = CCInfo.getNextStackOffset();
290 Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
291 getPointerTy(), true));
293 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
294 SmallVector<SDValue, 12> MemOpChains;
297 // Walk the register/memloc assignments, inserting copies/loads.
298 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
299 CCValAssign &VA = ArgLocs[i];
301 // Arguments start after the 5 first operands of ISD::CALL
302 SDValue Arg = TheCall->getArg(i);
304 // Promote the value if needed.
305 switch (VA.getLocInfo()) {
306 default: assert(0 && "Unknown loc info!");
307 case CCValAssign::Full: break;
308 case CCValAssign::SExt:
309 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
311 case CCValAssign::ZExt:
312 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
314 case CCValAssign::AExt:
315 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
319 // Arguments that can be passed on register must be kept at RegsToPass
322 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
324 assert(VA.isMemLoc());
326 if (StackPtr.getNode() == 0)
327 StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SPW, getPointerTy());
329 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
331 DAG.getIntPtrConstant(VA.getLocMemOffset()));
334 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
335 PseudoSourceValue::getStack(),
336 VA.getLocMemOffset()));
340 // Transform all store nodes into one single node because all store nodes are
341 // independent of each other.
342 if (!MemOpChains.empty())
343 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
344 &MemOpChains[0], MemOpChains.size());
346 // Build a sequence of copy-to-reg nodes chained together with token chain and
347 // flag operands which copy the outgoing args into registers. The InFlag in
348 // necessary since all emited instructions must be stuck together.
350 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
351 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
352 RegsToPass[i].second, InFlag);
353 InFlag = Chain.getValue(1);
356 // If the callee is a GlobalAddress node (quite common, every direct call is)
357 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
358 // Likewise ExternalSymbol -> TargetExternalSymbol.
359 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
360 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i16);
361 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
362 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
364 // Returns a chain & a flag for retval copy to use.
365 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
366 SmallVector<SDValue, 8> Ops;
367 Ops.push_back(Chain);
368 Ops.push_back(Callee);
370 // Add argument registers to the end of the list so that they are
371 // known live into the call.
372 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
373 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
374 RegsToPass[i].second.getValueType()));
376 if (InFlag.getNode())
377 Ops.push_back(InFlag);
379 Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
380 InFlag = Chain.getValue(1);
382 // Create the CALLSEQ_END node.
383 Chain = DAG.getCALLSEQ_END(Chain,
384 DAG.getConstant(NumBytes, getPointerTy(), true),
385 DAG.getConstant(0, getPointerTy(), true),
387 InFlag = Chain.getValue(1);
389 // Handle result values, copying them out of physregs into vregs that we
391 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
395 /// LowerCallResult - Lower the result values of an ISD::CALL into the
396 /// appropriate copies out of appropriate physical registers. This assumes that
397 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
398 /// being lowered. Returns a SDNode with the same number of values as the
401 MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
403 unsigned CallingConv,
405 bool isVarArg = TheCall->isVarArg();
406 DebugLoc dl = TheCall->getDebugLoc();
408 // Assign locations to each value returned by this call.
409 SmallVector<CCValAssign, 16> RVLocs;
410 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
412 CCInfo.AnalyzeCallResult(TheCall, RetCC_MSP430);
413 SmallVector<SDValue, 8> ResultVals;
415 // Copy all of the result registers out of their specified physreg.
416 for (unsigned i = 0; i != RVLocs.size(); ++i) {
417 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
418 RVLocs[i].getValVT(), InFlag).getValue(1);
419 InFlag = Chain.getValue(2);
420 ResultVals.push_back(Chain.getValue(0));
423 ResultVals.push_back(Chain);
425 // Merge everything together with a MERGE_VALUES node.
426 return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
427 &ResultVals[0], ResultVals.size()).getNode();
430 SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
432 unsigned Opc = Op.getOpcode();
433 assert((Opc == ISD::SRA || ISD::SHL) &&
434 "Only SRA and SHL are currently supported.");
435 SDNode* N = Op.getNode();
436 MVT VT = Op.getValueType();
437 DebugLoc dl = N->getDebugLoc();
439 // We currently only lower shifts of constant argument.
440 if (!isa<ConstantSDNode>(N->getOperand(1)))
443 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
445 // Expand the stuff into sequence of shifts.
446 // FIXME: for some shift amounts this might be done better!
447 // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
448 SDValue Victim = N->getOperand(0);
449 while (ShiftAmount--)
450 Victim = DAG.getNode((Opc == ISD::SRA ? MSP430ISD::RRA : MSP430ISD::RLA),
456 SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
457 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
458 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
460 // Create the TargetGlobalAddress node, folding in the constant offset.
461 SDValue Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
462 return DAG.getNode(MSP430ISD::Wrapper, Op.getDebugLoc(),
463 getPointerTy(), Result);
466 SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op,
468 DebugLoc dl = Op.getDebugLoc();
469 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
470 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
472 return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);;
476 MVT MSP430TargetLowering::getSetCCResultType(MVT VT) const {
480 SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
481 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
482 SDValue LHS = Op.getOperand(0);
483 SDValue RHS = Op.getOperand(1);
484 DebugLoc dl = Op.getDebugLoc();
485 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
487 // FIXME: Handle bittests someday
488 assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
490 // FIXME: Handle jump negative someday
491 unsigned TargetCC = 0;
493 default: assert(0 && "Invalid integer condition!");
495 TargetCC = MSP430::COND_E; // aka COND_Z
498 TargetCC = MSP430::COND_NE; // aka COND_NZ
501 std::swap(LHS, RHS); // FALLTHROUGH
503 TargetCC = MSP430::COND_HS; // aka COND_C
506 std::swap(LHS, RHS); // FALLTHROUGH
508 TargetCC = MSP430::COND_LO; // aka COND_NC
511 std::swap(LHS, RHS); // FALLTHROUGH
513 TargetCC = MSP430::COND_GE;
516 std::swap(LHS, RHS); // FALLTHROUGH
518 TargetCC = MSP430::COND_L;
522 SDValue Cond = DAG.getNode(MSP430ISD::CMP, dl, MVT::i16, LHS, RHS);
523 return DAG.getNode(MSP430ISD::SETCC, dl, MVT::i8,
524 DAG.getConstant(TargetCC, MVT::i8), Cond);
527 SDValue MSP430TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
528 SDValue Chain = Op.getOperand(0);
529 SDValue Cond = Op.getOperand(1);
530 SDValue Dest = Op.getOperand(2);
531 DebugLoc dl = Op.getDebugLoc();
534 // Lower condition if not lowered yet
535 if (Cond.getOpcode() == ISD::SETCC)
536 Cond = LowerSETCC(Cond, DAG);
538 // If condition flag is set by a MSP430ISD::CMP, then use it as the condition
539 // setting operand in place of the MSP430ISD::SETCC.
540 if (Cond.getOpcode() == MSP430ISD::SETCC) {
541 CC = Cond.getOperand(0);
542 Cond = Cond.getOperand(1);
544 assert(0 && "Unimplemented condition!");
546 return DAG.getNode(MSP430ISD::BRCOND, dl, Op.getValueType(),
547 Chain, Dest, CC, Cond);
550 SDValue MSP430TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
551 SDValue Cond = Op.getOperand(0);
552 SDValue TrueV = Op.getOperand(1);
553 SDValue FalseV = Op.getOperand(2);
554 DebugLoc dl = Op.getDebugLoc();
557 // Lower condition if not lowered yet
558 if (Cond.getOpcode() == ISD::SETCC)
559 Cond = LowerSETCC(Cond, DAG);
561 // If condition flag is set by a MSP430ISD::CMP, then use it as the condition
562 // setting operand in place of the MSP430ISD::SETCC.
563 if (Cond.getOpcode() == MSP430ISD::SETCC) {
564 CC = Cond.getOperand(0);
565 Cond = Cond.getOperand(1);
566 TrueV = Cond.getOperand(0);
567 FalseV = Cond.getOperand(1);
569 CC = DAG.getConstant(MSP430::COND_NE, MVT::i16);
570 Cond = DAG.getNode(MSP430ISD::CMP, dl, MVT::i16,
571 Cond, DAG.getConstant(0, MVT::i16));
574 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
575 SmallVector<SDValue, 4> Ops;
576 Ops.push_back(TrueV);
577 Ops.push_back(FalseV);
581 return DAG.getNode(MSP430ISD::SELECT, dl, VTs, &Ops[0], Ops.size());
584 const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
586 default: return NULL;
587 case MSP430ISD::RET_FLAG: return "MSP430ISD::RET_FLAG";
588 case MSP430ISD::RRA: return "MSP430ISD::RRA";
589 case MSP430ISD::RLA: return "MSP430ISD::RRA";
590 case MSP430ISD::CALL: return "MSP430ISD::CALL";
591 case MSP430ISD::Wrapper: return "MSP430ISD::Wrapper";
592 case MSP430ISD::BRCOND: return "MSP430ISD::BRCOND";
593 case MSP430ISD::CMP: return "MSP430ISD::CMP";
594 case MSP430ISD::SETCC: return "MSP430ISD::SETCC";
595 case MSP430ISD::SELECT: return "MSP430ISD::SELECT";
599 //===----------------------------------------------------------------------===//
600 // Other Lowering Code
601 //===----------------------------------------------------------------------===//
604 MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
605 MachineBasicBlock *BB) const {
606 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
607 DebugLoc dl = MI->getDebugLoc();
608 assert((MI->getOpcode() == MSP430::Select16) &&
609 "Unexpected instr type to insert");
611 // To "insert" a SELECT instruction, we actually have to insert the diamond
612 // control-flow pattern. The incoming instruction knows the destination vreg
613 // to set, the condition code register to branch on, the true/false values to
614 // select between, and a branch opcode to use.
615 const BasicBlock *LLVM_BB = BB->getBasicBlock();
616 MachineFunction::iterator I = BB;
624 // fallthrough --> copy0MBB
625 MachineBasicBlock *thisMBB = BB;
626 MachineFunction *F = BB->getParent();
627 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
628 MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
629 BuildMI(BB, dl, TII.get(MSP430::JCC))
631 .addImm(MI->getOperand(3).getImm());
632 F->insert(I, copy0MBB);
633 F->insert(I, copy1MBB);
634 // Update machine-CFG edges by transferring all successors of the current
635 // block to the new block which will contain the Phi node for the select.
636 copy1MBB->transferSuccessors(BB);
637 // Next, add the true and fallthrough blocks as its successors.
638 BB->addSuccessor(copy0MBB);
639 BB->addSuccessor(copy1MBB);
643 // # fallthrough to copy1MBB
646 // Update machine-CFG edges
647 BB->addSuccessor(copy1MBB);
650 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
653 BuildMI(BB, dl, TII.get(MSP430::PHI),
654 MI->getOperand(0).getReg())
655 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
656 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
658 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.