1 //===-- MSP430ISelDAGToDAG.cpp - A dag to dag inst selector for MSP430 ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the MSP430 target.
12 //===----------------------------------------------------------------------===//
15 #include "MSP430TargetMachine.h"
16 #include "llvm/DerivedTypes.h"
17 #include "llvm/Function.h"
18 #include "llvm/Intrinsics.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/Target/TargetLowering.h"
28 #include "llvm/Support/Compiler.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/raw_ostream.h"
35 struct MSP430ISelAddressMode {
41 struct { // This is really a union, discriminated by BaseType!
47 const GlobalValue *GV;
49 const BlockAddress *BlockAddr;
52 unsigned Align; // CP alignment.
54 MSP430ISelAddressMode()
55 : BaseType(RegBase), Disp(0), GV(0), CP(0), BlockAddr(0),
56 ES(0), JT(-1), Align(0) {
59 bool hasSymbolicDisplacement() const {
60 return GV != 0 || CP != 0 || ES != 0 || JT != -1;
63 bool hasBaseReg() const {
64 return Base.Reg.getNode() != 0;
67 void setBaseReg(SDValue Reg) {
73 errs() << "MSP430ISelAddressMode " << this << '\n';
74 if (BaseType == RegBase && Base.Reg.getNode() != 0) {
75 errs() << "Base.Reg ";
76 Base.Reg.getNode()->dump();
77 } else if (BaseType == FrameIndexBase) {
78 errs() << " Base.FrameIndex " << Base.FrameIndex << '\n';
80 errs() << " Disp " << Disp << '\n';
87 errs() << " Align" << Align << '\n';
92 errs() << " JT" << JT << " Align" << Align << '\n';
97 /// MSP430DAGToDAGISel - MSP430 specific code to select MSP430 machine
98 /// instructions for SelectionDAG operations.
101 class MSP430DAGToDAGISel : public SelectionDAGISel {
102 const MSP430TargetLowering &Lowering;
103 const MSP430Subtarget &Subtarget;
106 MSP430DAGToDAGISel(MSP430TargetMachine &TM, CodeGenOpt::Level OptLevel)
107 : SelectionDAGISel(TM, OptLevel),
108 Lowering(*TM.getTargetLowering()),
109 Subtarget(*TM.getSubtargetImpl()) { }
111 virtual const char *getPassName() const {
112 return "MSP430 DAG->DAG Pattern Instruction Selection";
115 bool MatchAddress(SDValue N, MSP430ISelAddressMode &AM);
116 bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM);
117 bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM);
120 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
121 std::vector<SDValue> &OutOps);
123 // Include the pieces autogenerated from the target description.
124 #include "MSP430GenDAGISel.inc"
127 SDNode *Select(SDNode *N);
128 SDNode *SelectIndexedLoad(SDNode *Op);
129 SDNode *SelectIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2,
130 unsigned Opc8, unsigned Opc16);
132 bool SelectAddr(SDNode *Op, SDValue Addr, SDValue &Base, SDValue &Disp);
134 } // end anonymous namespace
136 /// createMSP430ISelDag - This pass converts a legalized DAG into a
137 /// MSP430-specific DAG, ready for instruction scheduling.
139 FunctionPass *llvm::createMSP430ISelDag(MSP430TargetMachine &TM,
140 CodeGenOpt::Level OptLevel) {
141 return new MSP430DAGToDAGISel(TM, OptLevel);
145 /// MatchWrapper - Try to match MSP430ISD::Wrapper node into an addressing mode.
146 /// These wrap things that will resolve down into a symbol reference. If no
147 /// match is possible, this returns true, otherwise it returns false.
148 bool MSP430DAGToDAGISel::MatchWrapper(SDValue N, MSP430ISelAddressMode &AM) {
149 // If the addressing mode already has a symbol as the displacement, we can
150 // never match another symbol.
151 if (AM.hasSymbolicDisplacement())
154 SDValue N0 = N.getOperand(0);
156 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
157 AM.GV = G->getGlobal();
158 AM.Disp += G->getOffset();
159 //AM.SymbolFlags = G->getTargetFlags();
160 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
161 AM.CP = CP->getConstVal();
162 AM.Align = CP->getAlignment();
163 AM.Disp += CP->getOffset();
164 //AM.SymbolFlags = CP->getTargetFlags();
165 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
166 AM.ES = S->getSymbol();
167 //AM.SymbolFlags = S->getTargetFlags();
168 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
169 AM.JT = J->getIndex();
170 //AM.SymbolFlags = J->getTargetFlags();
172 AM.BlockAddr = cast<BlockAddressSDNode>(N0)->getBlockAddress();
173 //AM.SymbolFlags = cast<BlockAddressSDNode>(N0)->getTargetFlags();
178 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
179 /// specified addressing mode without any further recursion.
180 bool MSP430DAGToDAGISel::MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM) {
181 // Is the base register already occupied?
182 if (AM.BaseType != MSP430ISelAddressMode::RegBase || AM.Base.Reg.getNode()) {
183 // If so, we cannot select it.
187 // Default, generate it as a register.
188 AM.BaseType = MSP430ISelAddressMode::RegBase;
193 bool MSP430DAGToDAGISel::MatchAddress(SDValue N, MSP430ISelAddressMode &AM) {
194 DEBUG(errs() << "MatchAddress: "; AM.dump());
196 switch (N.getOpcode()) {
198 case ISD::Constant: {
199 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
204 case MSP430ISD::Wrapper:
205 if (!MatchWrapper(N, AM))
209 case ISD::FrameIndex:
210 if (AM.BaseType == MSP430ISelAddressMode::RegBase
211 && AM.Base.Reg.getNode() == 0) {
212 AM.BaseType = MSP430ISelAddressMode::FrameIndexBase;
213 AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
219 MSP430ISelAddressMode Backup = AM;
220 if (!MatchAddress(N.getNode()->getOperand(0), AM) &&
221 !MatchAddress(N.getNode()->getOperand(1), AM))
224 if (!MatchAddress(N.getNode()->getOperand(1), AM) &&
225 !MatchAddress(N.getNode()->getOperand(0), AM))
233 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
234 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
235 MSP430ISelAddressMode Backup = AM;
236 uint64_t Offset = CN->getSExtValue();
237 // Start with the LHS as an addr mode.
238 if (!MatchAddress(N.getOperand(0), AM) &&
239 // Address could not have picked a GV address for the displacement.
241 // Check to see if the LHS & C is zero.
242 CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
251 return MatchAddressBase(N, AM);
254 /// SelectAddr - returns true if it is able pattern match an addressing mode.
255 /// It returns the operands which make up the maximal addressing mode it can
256 /// match by reference.
257 bool MSP430DAGToDAGISel::SelectAddr(SDNode *Op, SDValue N,
258 SDValue &Base, SDValue &Disp) {
259 MSP430ISelAddressMode AM;
261 if (MatchAddress(N, AM))
264 EVT VT = N.getValueType();
265 if (AM.BaseType == MSP430ISelAddressMode::RegBase) {
266 if (!AM.Base.Reg.getNode())
267 AM.Base.Reg = CurDAG->getRegister(0, VT);
270 Base = (AM.BaseType == MSP430ISelAddressMode::FrameIndexBase) ?
271 CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy()) :
275 Disp = CurDAG->getTargetGlobalAddress(AM.GV, MVT::i16, AM.Disp,
276 0/*AM.SymbolFlags*/);
278 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i16,
279 AM.Align, AM.Disp, 0/*AM.SymbolFlags*/);
281 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i16, 0/*AM.SymbolFlags*/);
282 else if (AM.JT != -1)
283 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i16, 0/*AM.SymbolFlags*/);
284 else if (AM.BlockAddr)
285 Disp = CurDAG->getBlockAddress(AM.BlockAddr, MVT::i32,
286 true, 0/*AM.SymbolFlags*/);
288 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i16);
293 bool MSP430DAGToDAGISel::
294 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
295 std::vector<SDValue> &OutOps) {
297 switch (ConstraintCode) {
298 default: return true;
300 if (!SelectAddr(Op.getNode(), Op, Op0, Op1))
305 OutOps.push_back(Op0);
306 OutOps.push_back(Op1);
310 static bool isValidIndexedLoad(const LoadSDNode *LD) {
311 ISD::MemIndexedMode AM = LD->getAddressingMode();
312 if (AM != ISD::POST_INC || LD->getExtensionType() != ISD::NON_EXTLOAD)
315 EVT VT = LD->getMemoryVT();
317 switch (VT.getSimpleVT().SimpleTy) {
320 if (cast<ConstantSDNode>(LD->getOffset())->getZExtValue() != 1)
326 if (cast<ConstantSDNode>(LD->getOffset())->getZExtValue() != 2)
337 SDNode *MSP430DAGToDAGISel::SelectIndexedLoad(SDNode *N) {
338 LoadSDNode *LD = cast<LoadSDNode>(N);
339 if (!isValidIndexedLoad(LD))
342 MVT VT = LD->getMemoryVT().getSimpleVT();
345 switch (VT.SimpleTy) {
347 Opcode = MSP430::MOV8rm_POST;
350 Opcode = MSP430::MOV16rm_POST;
356 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(),
357 VT, MVT::i16, MVT::Other,
358 LD->getBasePtr(), LD->getChain());
361 SDNode *MSP430DAGToDAGISel::SelectIndexedBinOp(SDNode *Op,
362 SDValue N1, SDValue N2,
363 unsigned Opc8, unsigned Opc16) {
364 if (N1.getOpcode() == ISD::LOAD &&
366 IsLegalToFold(N1, Op, Op, OptLevel)) {
367 LoadSDNode *LD = cast<LoadSDNode>(N1);
368 if (!isValidIndexedLoad(LD))
371 MVT VT = LD->getMemoryVT().getSimpleVT();
372 unsigned Opc = (VT == MVT::i16 ? Opc16 : Opc8);
373 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
374 MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
375 SDValue Ops0[] = { N2, LD->getBasePtr(), LD->getChain() };
377 CurDAG->SelectNodeTo(Op, Opc,
378 VT, MVT::i16, MVT::Other,
380 cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
382 ReplaceUses(SDValue(N1.getNode(), 2), SDValue(ResNode, 2));
383 // Transfer writeback.
384 ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
392 SDNode *MSP430DAGToDAGISel::Select(SDNode *Node) {
393 DebugLoc dl = Node->getDebugLoc();
395 // Dump information about the Node being selected
396 DEBUG(errs() << "Selecting: ");
397 DEBUG(Node->dump(CurDAG));
398 DEBUG(errs() << "\n");
400 // If we have a custom node, we already have selected!
401 if (Node->isMachineOpcode()) {
402 DEBUG(errs() << "== ";
408 // Few custom selection stuff.
409 switch (Node->getOpcode()) {
411 case ISD::FrameIndex: {
412 assert(Node->getValueType(0) == MVT::i16);
413 int FI = cast<FrameIndexSDNode>(Node)->getIndex();
414 SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i16);
415 if (Node->hasOneUse())
416 return CurDAG->SelectNodeTo(Node, MSP430::ADD16ri, MVT::i16,
417 TFI, CurDAG->getTargetConstant(0, MVT::i16));
418 return CurDAG->getMachineNode(MSP430::ADD16ri, dl, MVT::i16,
419 TFI, CurDAG->getTargetConstant(0, MVT::i16));
422 if (SDNode *ResNode = SelectIndexedLoad(Node))
424 // Other cases are autogenerated.
427 if (SDNode *ResNode =
428 SelectIndexedBinOp(Node,
429 Node->getOperand(0), Node->getOperand(1),
430 MSP430::ADD8rm_POST, MSP430::ADD16rm_POST))
432 else if (SDNode *ResNode =
433 SelectIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
434 MSP430::ADD8rm_POST, MSP430::ADD16rm_POST))
437 // Other cases are autogenerated.
440 if (SDNode *ResNode =
441 SelectIndexedBinOp(Node,
442 Node->getOperand(0), Node->getOperand(1),
443 MSP430::SUB8rm_POST, MSP430::SUB16rm_POST))
446 // Other cases are autogenerated.
449 if (SDNode *ResNode =
450 SelectIndexedBinOp(Node,
451 Node->getOperand(0), Node->getOperand(1),
452 MSP430::AND8rm_POST, MSP430::AND16rm_POST))
454 else if (SDNode *ResNode =
455 SelectIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
456 MSP430::AND8rm_POST, MSP430::AND16rm_POST))
459 // Other cases are autogenerated.
462 if (SDNode *ResNode =
463 SelectIndexedBinOp(Node,
464 Node->getOperand(0), Node->getOperand(1),
465 MSP430::OR8rm_POST, MSP430::OR16rm_POST))
467 else if (SDNode *ResNode =
468 SelectIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
469 MSP430::OR8rm_POST, MSP430::OR16rm_POST))
472 // Other cases are autogenerated.
475 if (SDNode *ResNode =
476 SelectIndexedBinOp(Node,
477 Node->getOperand(0), Node->getOperand(1),
478 MSP430::XOR8rm_POST, MSP430::XOR16rm_POST))
480 else if (SDNode *ResNode =
481 SelectIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
482 MSP430::XOR8rm_POST, MSP430::XOR16rm_POST))
485 // Other cases are autogenerated.
489 // Select the default instruction
490 SDNode *ResNode = SelectCode(Node);
492 DEBUG(errs() << "=> ");
493 if (ResNode == NULL || ResNode == Node)
494 DEBUG(Node->dump(CurDAG));
496 DEBUG(ResNode->dump(CurDAG));
497 DEBUG(errs() << "\n");