1 //===- MBlazeInstrInfo.cpp - MBlaze Instruction Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MBlaze implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "MBlazeInstrInfo.h"
15 #include "MBlazeTargetMachine.h"
16 #include "MBlazeMachineFunction.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "MBlazeGenInstrInfo.inc"
27 MBlazeInstrInfo::MBlazeInstrInfo(MBlazeTargetMachine &tm)
28 : TargetInstrInfoImpl(MBlazeInsts, array_lengthof(MBlazeInsts)),
29 TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
31 static bool isZeroImm(const MachineOperand &op) {
32 return op.isImm() && op.getImm() == 0;
35 /// isLoadFromStackSlot - If the specified machine instruction is a direct
36 /// load from a stack slot, return the virtual or physical register number of
37 /// the destination along with the FrameIndex of the loaded stack slot. If
38 /// not, return 0. This predicate must return 0 if the instruction has
39 /// any side effects other than loading from the stack slot.
40 unsigned MBlazeInstrInfo::
41 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const {
42 if (MI->getOpcode() == MBlaze::LWI) {
43 if ((MI->getOperand(1).isFI()) && // is a stack slot
44 (MI->getOperand(2).isImm()) && // the imm is zero
45 (isZeroImm(MI->getOperand(2)))) {
46 FrameIndex = MI->getOperand(1).getIndex();
47 return MI->getOperand(0).getReg();
54 /// isStoreToStackSlot - If the specified machine instruction is a direct
55 /// store to a stack slot, return the virtual or physical register number of
56 /// the source reg along with the FrameIndex of the loaded stack slot. If
57 /// not, return 0. This predicate must return 0 if the instruction has
58 /// any side effects other than storing to the stack slot.
59 unsigned MBlazeInstrInfo::
60 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const {
61 if (MI->getOpcode() == MBlaze::SWI) {
62 if ((MI->getOperand(1).isFI()) && // is a stack slot
63 (MI->getOperand(2).isImm()) && // the imm is zero
64 (isZeroImm(MI->getOperand(2)))) {
65 FrameIndex = MI->getOperand(1).getIndex();
66 return MI->getOperand(0).getReg();
72 /// insertNoop - If data hazard condition is found insert the target nop
74 void MBlazeInstrInfo::
75 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const {
77 BuildMI(MBB, MI, DL, get(MBlaze::NOP));
80 void MBlazeInstrInfo::
81 copyPhysReg(MachineBasicBlock &MBB,
82 MachineBasicBlock::iterator I, DebugLoc DL,
83 unsigned DestReg, unsigned SrcReg,
85 llvm::BuildMI(MBB, I, DL, get(MBlaze::ADDK), DestReg)
86 .addReg(SrcReg, getKillRegState(KillSrc)).addReg(MBlaze::R0);
89 void MBlazeInstrInfo::
90 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
91 unsigned SrcReg, bool isKill, int FI,
92 const TargetRegisterClass *RC,
93 const TargetRegisterInfo *TRI) const {
95 BuildMI(MBB, I, DL, get(MBlaze::SWI)).addReg(SrcReg,getKillRegState(isKill))
96 .addFrameIndex(FI).addImm(0); //.addFrameIndex(FI);
99 void MBlazeInstrInfo::
100 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
101 unsigned DestReg, int FI,
102 const TargetRegisterClass *RC,
103 const TargetRegisterInfo *TRI) const {
105 BuildMI(MBB, I, DL, get(MBlaze::LWI), DestReg)
106 .addFrameIndex(FI).addImm(0); //.addFrameIndex(FI);
109 //===----------------------------------------------------------------------===//
111 //===----------------------------------------------------------------------===//
112 bool MBlazeInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
113 MachineBasicBlock *&TBB,
114 MachineBasicBlock *&FBB,
115 SmallVectorImpl<MachineOperand> &Cond,
116 bool AllowModify) const {
117 // If the block has no terminators, it just falls into the block after it.
118 MachineBasicBlock::iterator I = MBB.end();
119 if (I == MBB.begin())
122 while (I->isDebugValue()) {
123 if (I == MBB.begin())
127 if (!isUnpredicatedTerminator(I))
130 // Get the last instruction in the block.
131 MachineInstr *LastInst = I;
133 // If there is only one terminator instruction, process it.
134 unsigned LastOpc = LastInst->getOpcode();
135 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
136 if (MBlaze::isUncondBranchOpcode(LastOpc)) {
137 TBB = LastInst->getOperand(0).getMBB();
140 if (MBlaze::isCondBranchOpcode(LastOpc)) {
141 // Block ends with fall-through condbranch.
142 TBB = LastInst->getOperand(1).getMBB();
143 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
144 Cond.push_back(LastInst->getOperand(0));
147 // Otherwise, don't know what this is.
151 // Get the instruction before it if it's a terminator.
152 MachineInstr *SecondLastInst = I;
154 // If there are three terminators, we don't know what sort of block this is.
155 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
158 // If the block ends with something like BEQID then BRID, handle it.
159 if (MBlaze::isCondBranchOpcode(SecondLastInst->getOpcode()) &&
160 MBlaze::isUncondBranchOpcode(LastInst->getOpcode())) {
161 TBB = SecondLastInst->getOperand(1).getMBB();
162 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
163 Cond.push_back(SecondLastInst->getOperand(0));
164 FBB = LastInst->getOperand(0).getMBB();
168 // If the block ends with two unconditional branches, handle it.
169 // The second one is not executed, so remove it.
170 if (MBlaze::isUncondBranchOpcode(SecondLastInst->getOpcode()) &&
171 MBlaze::isUncondBranchOpcode(LastInst->getOpcode())) {
172 TBB = SecondLastInst->getOperand(0).getMBB();
175 I->eraseFromParent();
179 // Otherwise, can't handle this.
183 unsigned MBlazeInstrInfo::
184 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
185 MachineBasicBlock *FBB,
186 const SmallVectorImpl<MachineOperand> &Cond,
188 // Shouldn't be a fall through.
189 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
190 assert((Cond.size() == 2 || Cond.size() == 0) &&
191 "MBlaze branch conditions have two components!");
193 unsigned Opc = MBlaze::BRID;
195 Opc = (unsigned)Cond[0].getImm();
198 if (Cond.empty()) // Unconditional branch
199 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
200 else // Conditional branch
201 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB);
205 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB);
206 BuildMI(&MBB, DL, get(MBlaze::BRID)).addMBB(FBB);
210 unsigned MBlazeInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
211 MachineBasicBlock::iterator I = MBB.end();
212 if (I == MBB.begin()) return 0;
214 while (I->isDebugValue()) {
215 if (I == MBB.begin())
220 if (!MBlaze::isUncondBranchOpcode(I->getOpcode()) &&
221 !MBlaze::isCondBranchOpcode(I->getOpcode()))
224 // Remove the branch.
225 I->eraseFromParent();
229 if (I == MBB.begin()) return 1;
231 if (!MBlaze::isCondBranchOpcode(I->getOpcode()))
234 // Remove the branch.
235 I->eraseFromParent();
239 bool MBlazeInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
240 assert(Cond.size() == 2 && "Invalid MBlaze branch opcode!");
241 switch (Cond[0].getImm()) {
242 default: return true;
243 case MBlaze::BEQ: Cond[0].setImm(MBlaze::BNE); return false;
244 case MBlaze::BNE: Cond[0].setImm(MBlaze::BEQ); return false;
245 case MBlaze::BGT: Cond[0].setImm(MBlaze::BLE); return false;
246 case MBlaze::BGE: Cond[0].setImm(MBlaze::BLT); return false;
247 case MBlaze::BLT: Cond[0].setImm(MBlaze::BGE); return false;
248 case MBlaze::BLE: Cond[0].setImm(MBlaze::BGT); return false;
249 case MBlaze::BEQI: Cond[0].setImm(MBlaze::BNEI); return false;
250 case MBlaze::BNEI: Cond[0].setImm(MBlaze::BEQI); return false;
251 case MBlaze::BGTI: Cond[0].setImm(MBlaze::BLEI); return false;
252 case MBlaze::BGEI: Cond[0].setImm(MBlaze::BLTI); return false;
253 case MBlaze::BLTI: Cond[0].setImm(MBlaze::BGEI); return false;
254 case MBlaze::BLEI: Cond[0].setImm(MBlaze::BGTI); return false;
255 case MBlaze::BEQD: Cond[0].setImm(MBlaze::BNED); return false;
256 case MBlaze::BNED: Cond[0].setImm(MBlaze::BEQD); return false;
257 case MBlaze::BGTD: Cond[0].setImm(MBlaze::BLED); return false;
258 case MBlaze::BGED: Cond[0].setImm(MBlaze::BLTD); return false;
259 case MBlaze::BLTD: Cond[0].setImm(MBlaze::BGED); return false;
260 case MBlaze::BLED: Cond[0].setImm(MBlaze::BGTD); return false;
261 case MBlaze::BEQID: Cond[0].setImm(MBlaze::BNEID); return false;
262 case MBlaze::BNEID: Cond[0].setImm(MBlaze::BEQID); return false;
263 case MBlaze::BGTID: Cond[0].setImm(MBlaze::BLEID); return false;
264 case MBlaze::BGEID: Cond[0].setImm(MBlaze::BLTID); return false;
265 case MBlaze::BLTID: Cond[0].setImm(MBlaze::BGEID); return false;
266 case MBlaze::BLEID: Cond[0].setImm(MBlaze::BGTID); return false;
270 /// getGlobalBaseReg - Return a virtual register initialized with the
271 /// the global base register value. Output instructions required to
272 /// initialize the register in the function entry block, if necessary.
274 unsigned MBlazeInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
275 MBlazeFunctionInfo *MBlazeFI = MF->getInfo<MBlazeFunctionInfo>();
276 unsigned GlobalBaseReg = MBlazeFI->getGlobalBaseReg();
277 if (GlobalBaseReg != 0)
278 return GlobalBaseReg;
280 // Insert the set of GlobalBaseReg into the first MBB of the function
281 MachineBasicBlock &FirstMBB = MF->front();
282 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
283 MachineRegisterInfo &RegInfo = MF->getRegInfo();
284 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
286 GlobalBaseReg = RegInfo.createVirtualRegister(MBlaze::GPRRegisterClass);
287 BuildMI(FirstMBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY),
288 GlobalBaseReg).addReg(MBlaze::R20);
289 RegInfo.addLiveIn(MBlaze::R20);
291 MBlazeFI->setGlobalBaseReg(GlobalBaseReg);
292 return GlobalBaseReg;