1 //===- IA64RegisterInfo.cpp - IA64 Register Information ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Duraid Madina and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the IA64 implementation of the MRegisterInfo class. This
11 // file is responsible for the frame pointer elimination optimization on IA64.
13 //===----------------------------------------------------------------------===//
16 #include "IA64RegisterInfo.h"
17 #include "IA64InstrBuilder.h"
18 #include "IA64MachineFunctionInfo.h"
19 #include "llvm/Constants.h"
20 #include "llvm/Type.h"
21 #include "llvm/CodeGen/ValueTypes.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineLocation.h"
26 #include "llvm/Target/TargetFrameInfo.h"
27 #include "llvm/Target/TargetMachine.h"
28 #include "llvm/Target/TargetOptions.h"
29 #include "llvm/Target/TargetInstrInfo.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/ADT/BitVector.h"
32 #include "llvm/ADT/STLExtras.h"
35 IA64RegisterInfo::IA64RegisterInfo(const TargetInstrInfo &tii)
36 : IA64GenRegisterInfo(IA64::ADJUSTCALLSTACKDOWN, IA64::ADJUSTCALLSTACKUP),
39 void IA64RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
40 MachineBasicBlock::iterator MI,
41 unsigned SrcReg, int FrameIdx,
42 const TargetRegisterClass *RC) const{
44 if (RC == IA64::FPRegisterClass) {
45 BuildMI(MBB, MI, TII.get(IA64::STF_SPILL)).addFrameIndex(FrameIdx)
46 .addReg(SrcReg, false, false, true);
47 } else if (RC == IA64::GRRegisterClass) {
48 BuildMI(MBB, MI, TII.get(IA64::ST8)).addFrameIndex(FrameIdx)
49 .addReg(SrcReg, false, false, true);
50 } else if (RC == IA64::PRRegisterClass) {
51 /* we use IA64::r2 as a temporary register for doing this hackery. */
53 BuildMI(MBB, MI, TII.get(IA64::MOV), IA64::r2).addReg(IA64::r0);
54 // then conditionally add 1:
55 BuildMI(MBB, MI, TII.get(IA64::CADDIMM22), IA64::r2).addReg(IA64::r2)
56 .addImm(1).addReg(SrcReg, false, false, true);
57 // and then store it to the stack
58 BuildMI(MBB, MI, TII.get(IA64::ST8)).addFrameIndex(FrameIdx).addReg(IA64::r2);
60 "sorry, I don't know how to store this sort of reg in the stack\n");
63 void IA64RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
64 MachineBasicBlock::iterator MI,
65 unsigned DestReg, int FrameIdx,
66 const TargetRegisterClass *RC)const{
68 if (RC == IA64::FPRegisterClass) {
69 BuildMI(MBB, MI, TII.get(IA64::LDF_FILL), DestReg).addFrameIndex(FrameIdx);
70 } else if (RC == IA64::GRRegisterClass) {
71 BuildMI(MBB, MI, TII.get(IA64::LD8), DestReg).addFrameIndex(FrameIdx);
72 } else if (RC == IA64::PRRegisterClass) {
73 // first we load a byte from the stack into r2, our 'predicate hackery'
75 BuildMI(MBB, MI, TII.get(IA64::LD8), IA64::r2).addFrameIndex(FrameIdx);
76 // then we compare it to zero. If it _is_ zero, compare-not-equal to
77 // r0 gives us 0, which is what we want, so that's nice.
78 BuildMI(MBB, MI, TII.get(IA64::CMPNE), DestReg).addReg(IA64::r2).addReg(IA64::r0);
80 "sorry, I don't know how to load this sort of reg from the stack\n");
83 void IA64RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
84 MachineBasicBlock::iterator MI,
85 unsigned DestReg, unsigned SrcReg,
86 const TargetRegisterClass *RC) const {
88 if(RC == IA64::PRRegisterClass ) // if a bool, we use pseudocode
89 // (SrcReg) DestReg = cmp.eq.unc(r0, r0)
90 BuildMI(MBB, MI, TII.get(IA64::PCMPEQUNC), DestReg)
91 .addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg);
92 else // otherwise, MOV works (for both gen. regs and FP regs)
93 BuildMI(MBB, MI, TII.get(IA64::MOV), DestReg).addReg(SrcReg);
96 void IA64RegisterInfo::reMaterialize(MachineBasicBlock &MBB,
97 MachineBasicBlock::iterator I,
99 const MachineInstr *Orig) const {
100 MachineInstr *MI = Orig->clone();
101 MI->getOperand(0).setReg(DestReg);
105 const unsigned* IA64RegisterInfo::getCalleeSavedRegs() const {
106 static const unsigned CalleeSavedRegs[] = {
109 return CalleeSavedRegs;
112 const TargetRegisterClass* const*
113 IA64RegisterInfo::getCalleeSavedRegClasses() const {
114 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
117 return CalleeSavedRegClasses;
120 BitVector IA64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
121 BitVector Reserved(getNumRegs());
122 Reserved.set(IA64::r0);
123 Reserved.set(IA64::r1);
124 Reserved.set(IA64::r2);
125 Reserved.set(IA64::r5);
126 Reserved.set(IA64::r12);
127 Reserved.set(IA64::r13);
128 Reserved.set(IA64::r22);
129 Reserved.set(IA64::rp);
133 //===----------------------------------------------------------------------===//
134 // Stack Frame Processing methods
135 //===----------------------------------------------------------------------===//
137 // hasFP - Return true if the specified function should have a dedicated frame
138 // pointer register. This is true if the function has variable sized allocas or
139 // if frame pointer elimination is disabled.
141 bool IA64RegisterInfo::hasFP(const MachineFunction &MF) const {
142 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
145 void IA64RegisterInfo::
146 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
147 MachineBasicBlock::iterator I) const {
149 // If we have a frame pointer, turn the adjcallstackup instruction into a
150 // 'sub SP, <amt>' and the adjcallstackdown instruction into 'add SP,
152 MachineInstr *Old = I;
153 unsigned Amount = Old->getOperand(0).getImmedValue();
155 // We need to keep the stack aligned properly. To do this, we round the
156 // amount of space needed for the outgoing arguments up to the next
157 // alignment boundary.
158 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
159 Amount = (Amount+Align-1)/Align*Align;
162 if (Old->getOpcode() == IA64::ADJUSTCALLSTACKDOWN) {
163 New=BuildMI(TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12)
166 assert(Old->getOpcode() == IA64::ADJUSTCALLSTACKUP);
167 New=BuildMI(TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12)
171 // Replace the pseudo instruction with a new instruction...
179 void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
180 RegScavenger *RS)const{
182 MachineInstr &MI = *II;
183 MachineBasicBlock &MBB = *MI.getParent();
184 MachineFunction &MF = *MBB.getParent();
188 while (!MI.getOperand(i).isFrameIndex()) {
190 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
193 int FrameIndex = MI.getOperand(i).getFrameIndex();
195 // choose a base register: ( hasFP? framepointer : stack pointer )
196 unsigned BaseRegister = FP ? IA64::r5 : IA64::r12;
197 // Add the base register
198 MI.getOperand(i).ChangeToRegister(BaseRegister, false);
200 // Now add the frame object offset to the offset from r1.
201 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
203 // If we're not using a Frame Pointer that has been set to the value of the
204 // SP before having the stack size subtracted from it, then add the stack size
205 // to Offset to get the correct offset.
206 Offset += MF.getFrameInfo()->getStackSize();
208 // XXX: we use 'r22' as another hack+slash temporary register here :(
209 if (Offset <= 8191 && Offset >= -8192) { // smallish offset
211 MI.getOperand(i).ChangeToRegister(IA64::r22, false);
213 MachineInstr* nMI=BuildMI(TII.get(IA64::ADDIMM22), IA64::r22)
214 .addReg(BaseRegister).addImm(Offset);
218 MI.getOperand(i).ChangeToRegister(IA64::r22, false);
220 nMI=BuildMI(TII.get(IA64::MOVLIMM64), IA64::r22).addImm(Offset);
222 nMI=BuildMI(TII.get(IA64::ADD), IA64::r22).addReg(BaseRegister)
229 void IA64RegisterInfo::emitPrologue(MachineFunction &MF) const {
230 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
231 MachineBasicBlock::iterator MBBI = MBB.begin();
232 MachineFrameInfo *MFI = MF.getFrameInfo();
236 // first, we handle the 'alloc' instruction, that should be right up the
237 // top of any function
238 static const unsigned RegsInOrder[96] = { // there are 96 GPRs the
240 IA64::r32, IA64::r33, IA64::r34, IA64::r35,
241 IA64::r36, IA64::r37, IA64::r38, IA64::r39, IA64::r40, IA64::r41,
242 IA64::r42, IA64::r43, IA64::r44, IA64::r45, IA64::r46, IA64::r47,
243 IA64::r48, IA64::r49, IA64::r50, IA64::r51, IA64::r52, IA64::r53,
244 IA64::r54, IA64::r55, IA64::r56, IA64::r57, IA64::r58, IA64::r59,
245 IA64::r60, IA64::r61, IA64::r62, IA64::r63, IA64::r64, IA64::r65,
246 IA64::r66, IA64::r67, IA64::r68, IA64::r69, IA64::r70, IA64::r71,
247 IA64::r72, IA64::r73, IA64::r74, IA64::r75, IA64::r76, IA64::r77,
248 IA64::r78, IA64::r79, IA64::r80, IA64::r81, IA64::r82, IA64::r83,
249 IA64::r84, IA64::r85, IA64::r86, IA64::r87, IA64::r88, IA64::r89,
250 IA64::r90, IA64::r91, IA64::r92, IA64::r93, IA64::r94, IA64::r95,
251 IA64::r96, IA64::r97, IA64::r98, IA64::r99, IA64::r100, IA64::r101,
252 IA64::r102, IA64::r103, IA64::r104, IA64::r105, IA64::r106, IA64::r107,
253 IA64::r108, IA64::r109, IA64::r110, IA64::r111, IA64::r112, IA64::r113,
254 IA64::r114, IA64::r115, IA64::r116, IA64::r117, IA64::r118, IA64::r119,
255 IA64::r120, IA64::r121, IA64::r122, IA64::r123, IA64::r124, IA64::r125,
256 IA64::r126, IA64::r127 };
258 unsigned numStackedGPRsUsed=0;
259 for(int i=0; i<96; i++) {
260 if(MF.isPhysRegUsed(RegsInOrder[i]))
261 numStackedGPRsUsed=i+1; // (i+1 and not ++ - consider fn(fp, fp, int)
264 unsigned numOutRegsUsed=MF.getInfo<IA64FunctionInfo>()->outRegsUsed;
266 // XXX FIXME : this code should be a bit more reliable (in case there _isn't_
267 // a pseudo_alloc in the MBB)
268 unsigned dstRegOfPseudoAlloc;
269 for(MBBI = MBB.begin(); /*MBBI->getOpcode() != IA64::PSEUDO_ALLOC*/; ++MBBI) {
270 assert(MBBI != MBB.end());
271 if(MBBI->getOpcode() == IA64::PSEUDO_ALLOC) {
272 dstRegOfPseudoAlloc=MBBI->getOperand(0).getReg();
277 MI=BuildMI(TII.get(IA64::ALLOC)).addReg(dstRegOfPseudoAlloc).addImm(0). \
278 addImm(numStackedGPRsUsed).addImm(numOutRegsUsed).addImm(0);
279 MBB.insert(MBBI, MI);
281 // Get the number of bytes to allocate from the FrameInfo
282 unsigned NumBytes = MFI->getStackSize();
285 NumBytes += 8; // reserve space for the old FP
287 // Do we need to allocate space on the stack?
291 // Add 16 bytes at the bottom of the stack (scratch area)
292 // and round the size to a multiple of the alignment.
293 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
294 unsigned Size = 16 + (FP ? 8 : 0);
295 NumBytes = (NumBytes+Size+Align-1)/Align*Align;
297 // Update frame info to pretend that this is part of the stack...
298 MFI->setStackSize(NumBytes);
300 // adjust stack pointer: r12 -= numbytes
301 if (NumBytes <= 8191) {
302 MI=BuildMI(TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12).
304 MBB.insert(MBBI, MI);
305 } else { // we use r22 as a scratch register here
306 MI=BuildMI(TII.get(IA64::MOVLIMM64), IA64::r22).addImm(-NumBytes);
307 // FIXME: MOVLSI32 expects a _u_32imm
308 MBB.insert(MBBI, MI); // first load the decrement into r22
309 MI=BuildMI(TII.get(IA64::ADD), IA64::r12).addReg(IA64::r12).addReg(IA64::r22);
310 MBB.insert(MBBI, MI); // then add (subtract) it to r12 (stack ptr)
313 // now if we need to, save the old FP and set the new
315 MI = BuildMI(TII.get(IA64::ST8)).addReg(IA64::r12).addReg(IA64::r5);
316 MBB.insert(MBBI, MI);
317 // this must be the last instr in the prolog ? (XXX: why??)
318 MI = BuildMI(TII.get(IA64::MOV), IA64::r5).addReg(IA64::r12);
319 MBB.insert(MBBI, MI);
324 void IA64RegisterInfo::emitEpilogue(MachineFunction &MF,
325 MachineBasicBlock &MBB) const {
326 const MachineFrameInfo *MFI = MF.getFrameInfo();
327 MachineBasicBlock::iterator MBBI = prior(MBB.end());
329 assert(MBBI->getOpcode() == IA64::RET &&
330 "Can only insert epilog into returning blocks");
334 // Get the number of bytes allocated from the FrameInfo...
335 unsigned NumBytes = MFI->getStackSize();
337 //now if we need to, restore the old FP
340 //copy the FP into the SP (discards allocas)
341 MI=BuildMI(TII.get(IA64::MOV), IA64::r12).addReg(IA64::r5);
342 MBB.insert(MBBI, MI);
344 MI=BuildMI(TII.get(IA64::LD8), IA64::r5).addReg(IA64::r5);
345 MBB.insert(MBBI, MI);
350 if (NumBytes <= 8191) {
351 MI=BuildMI(TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12).
353 MBB.insert(MBBI, MI);
355 MI=BuildMI(TII.get(IA64::MOVLIMM64), IA64::r22).addImm(NumBytes);
356 MBB.insert(MBBI, MI);
357 MI=BuildMI(TII.get(IA64::ADD), IA64::r12).addReg(IA64::r12).
359 MBB.insert(MBBI, MI);
365 unsigned IA64RegisterInfo::getRARegister() const {
366 assert(0 && "What is the return address register");
370 unsigned IA64RegisterInfo::getFrameRegister(MachineFunction &MF) const {
371 return hasFP(MF) ? IA64::r5 : IA64::r12;
374 unsigned IA64RegisterInfo::getEHExceptionRegister() const {
375 assert(0 && "What is the exception register");
379 unsigned IA64RegisterInfo::getEHHandlerRegister() const {
380 assert(0 && "What is the exception handler register");
384 #include "IA64GenRegisterInfo.inc"