1 //===- IA64RegisterInfo.cpp - IA64 Register Information ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the IA64 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "IA64RegisterInfo.h"
18 #include "IA64InstrBuilder.h"
19 #include "IA64MachineFunctionInfo.h"
20 #include "llvm/Constants.h"
21 #include "llvm/Type.h"
22 #include "llvm/CodeGen/ValueTypes.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineLocation.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/Target/TargetFrameInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/ADT/BitVector.h"
33 #include "llvm/ADT/STLExtras.h"
36 IA64RegisterInfo::IA64RegisterInfo(const TargetInstrInfo &tii)
37 : IA64GenRegisterInfo(IA64::ADJUSTCALLSTACKDOWN, IA64::ADJUSTCALLSTACKUP),
40 const unsigned* IA64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
42 static const unsigned CalleeSavedRegs[] = {
45 return CalleeSavedRegs;
48 const TargetRegisterClass* const*
49 IA64RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
50 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
53 return CalleeSavedRegClasses;
56 BitVector IA64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
57 BitVector Reserved(getNumRegs());
58 Reserved.set(IA64::r0);
59 Reserved.set(IA64::r1);
60 Reserved.set(IA64::r2);
61 Reserved.set(IA64::r5);
62 Reserved.set(IA64::r12);
63 Reserved.set(IA64::r13);
64 Reserved.set(IA64::r22);
65 Reserved.set(IA64::rp);
69 //===----------------------------------------------------------------------===//
70 // Stack Frame Processing methods
71 //===----------------------------------------------------------------------===//
73 // hasFP - Return true if the specified function should have a dedicated frame
74 // pointer register. This is true if the function has variable sized allocas or
75 // if frame pointer elimination is disabled.
77 bool IA64RegisterInfo::hasFP(const MachineFunction &MF) const {
78 const MachineFrameInfo *MFI = MF.getFrameInfo();
79 return NoFramePointerElim || MFI->hasVarSizedObjects() ||
80 MFI->isFrameAddressTaken();
83 void IA64RegisterInfo::
84 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
85 MachineBasicBlock::iterator I) const {
87 // If we have a frame pointer, turn the adjcallstackup instruction into a
88 // 'sub SP, <amt>' and the adjcallstackdown instruction into 'add SP,
90 MachineInstr *Old = I;
91 unsigned Amount = Old->getOperand(0).getImm();
93 // We need to keep the stack aligned properly. To do this, we round the
94 // amount of space needed for the outgoing arguments up to the next
95 // alignment boundary.
96 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
97 Amount = (Amount+Align-1)/Align*Align;
99 // Replace the pseudo instruction with a new instruction...
100 if (Old->getOpcode() == IA64::ADJUSTCALLSTACKDOWN) {
101 BuildMI(MBB, I, TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12)
104 assert(Old->getOpcode() == IA64::ADJUSTCALLSTACKUP);
105 BuildMI(MBB, I, TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12)
114 void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
115 int SPAdj, RegScavenger *RS)const{
116 assert(SPAdj == 0 && "Unexpected");
119 MachineInstr &MI = *II;
120 MachineBasicBlock &MBB = *MI.getParent();
121 MachineFunction &MF = *MBB.getParent();
125 while (!MI.getOperand(i).isFrameIndex()) {
127 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
130 int FrameIndex = MI.getOperand(i).getIndex();
132 // choose a base register: ( hasFP? framepointer : stack pointer )
133 unsigned BaseRegister = FP ? IA64::r5 : IA64::r12;
134 // Add the base register
135 MI.getOperand(i).ChangeToRegister(BaseRegister, false);
137 // Now add the frame object offset to the offset from r1.
138 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
140 // If we're not using a Frame Pointer that has been set to the value of the
141 // SP before having the stack size subtracted from it, then add the stack size
142 // to Offset to get the correct offset.
143 Offset += MF.getFrameInfo()->getStackSize();
145 // XXX: we use 'r22' as another hack+slash temporary register here :(
146 if (Offset <= 8191 && Offset >= -8192) { // smallish offset
148 MI.getOperand(i).ChangeToRegister(IA64::r22, false);
150 BuildMI(MBB, II, TII.get(IA64::ADDIMM22), IA64::r22)
151 .addReg(BaseRegister).addImm(Offset);
154 MI.getOperand(i).ChangeToRegister(IA64::r22, false);
155 BuildMI(MBB, II, TII.get(IA64::MOVLIMM64), IA64::r22).addImm(Offset);
156 BuildMI(MBB, II, TII.get(IA64::ADD), IA64::r22).addReg(BaseRegister)
162 void IA64RegisterInfo::emitPrologue(MachineFunction &MF) const {
163 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
164 MachineBasicBlock::iterator MBBI = MBB.begin();
165 MachineFrameInfo *MFI = MF.getFrameInfo();
168 // first, we handle the 'alloc' instruction, that should be right up the
169 // top of any function
170 static const unsigned RegsInOrder[96] = { // there are 96 GPRs the
172 IA64::r32, IA64::r33, IA64::r34, IA64::r35,
173 IA64::r36, IA64::r37, IA64::r38, IA64::r39, IA64::r40, IA64::r41,
174 IA64::r42, IA64::r43, IA64::r44, IA64::r45, IA64::r46, IA64::r47,
175 IA64::r48, IA64::r49, IA64::r50, IA64::r51, IA64::r52, IA64::r53,
176 IA64::r54, IA64::r55, IA64::r56, IA64::r57, IA64::r58, IA64::r59,
177 IA64::r60, IA64::r61, IA64::r62, IA64::r63, IA64::r64, IA64::r65,
178 IA64::r66, IA64::r67, IA64::r68, IA64::r69, IA64::r70, IA64::r71,
179 IA64::r72, IA64::r73, IA64::r74, IA64::r75, IA64::r76, IA64::r77,
180 IA64::r78, IA64::r79, IA64::r80, IA64::r81, IA64::r82, IA64::r83,
181 IA64::r84, IA64::r85, IA64::r86, IA64::r87, IA64::r88, IA64::r89,
182 IA64::r90, IA64::r91, IA64::r92, IA64::r93, IA64::r94, IA64::r95,
183 IA64::r96, IA64::r97, IA64::r98, IA64::r99, IA64::r100, IA64::r101,
184 IA64::r102, IA64::r103, IA64::r104, IA64::r105, IA64::r106, IA64::r107,
185 IA64::r108, IA64::r109, IA64::r110, IA64::r111, IA64::r112, IA64::r113,
186 IA64::r114, IA64::r115, IA64::r116, IA64::r117, IA64::r118, IA64::r119,
187 IA64::r120, IA64::r121, IA64::r122, IA64::r123, IA64::r124, IA64::r125,
188 IA64::r126, IA64::r127 };
190 unsigned numStackedGPRsUsed=0;
191 for (int i=0; i != 96; i++) {
192 if (MF.getRegInfo().isPhysRegUsed(RegsInOrder[i]))
193 numStackedGPRsUsed=i+1; // (i+1 and not ++ - consider fn(fp, fp, int)
196 unsigned numOutRegsUsed=MF.getInfo<IA64FunctionInfo>()->outRegsUsed;
198 // XXX FIXME : this code should be a bit more reliable (in case there _isn't_
199 // a pseudo_alloc in the MBB)
200 unsigned dstRegOfPseudoAlloc;
201 for(MBBI = MBB.begin(); /*MBBI->getOpcode() != IA64::PSEUDO_ALLOC*/; ++MBBI) {
202 assert(MBBI != MBB.end());
203 if(MBBI->getOpcode() == IA64::PSEUDO_ALLOC) {
204 dstRegOfPseudoAlloc=MBBI->getOperand(0).getReg();
209 BuildMI(MBB, MBBI, TII.get(IA64::ALLOC)).
210 addReg(dstRegOfPseudoAlloc).addImm(0).
211 addImm(numStackedGPRsUsed).addImm(numOutRegsUsed).addImm(0);
213 // Get the number of bytes to allocate from the FrameInfo
214 unsigned NumBytes = MFI->getStackSize();
217 NumBytes += 8; // reserve space for the old FP
219 // Do we need to allocate space on the stack?
223 // Add 16 bytes at the bottom of the stack (scratch area)
224 // and round the size to a multiple of the alignment.
225 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
226 unsigned Size = 16 + (FP ? 8 : 0);
227 NumBytes = (NumBytes+Size+Align-1)/Align*Align;
229 // Update frame info to pretend that this is part of the stack...
230 MFI->setStackSize(NumBytes);
232 // adjust stack pointer: r12 -= numbytes
233 if (NumBytes <= 8191) {
234 BuildMI(MBB, MBBI, TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12).
236 } else { // we use r22 as a scratch register here
237 // first load the decrement into r22
238 BuildMI(MBB, MBBI, TII.get(IA64::MOVLIMM64), IA64::r22).addImm(-NumBytes);
239 // FIXME: MOVLSI32 expects a _u_32imm
240 // then add (subtract) it to r12 (stack ptr)
241 BuildMI(MBB, MBBI, TII.get(IA64::ADD), IA64::r12)
242 .addReg(IA64::r12).addReg(IA64::r22);
246 // now if we need to, save the old FP and set the new
248 BuildMI(MBB, MBBI, TII.get(IA64::ST8)).addReg(IA64::r12).addReg(IA64::r5);
249 // this must be the last instr in the prolog ? (XXX: why??)
250 BuildMI(MBB, MBBI, TII.get(IA64::MOV), IA64::r5).addReg(IA64::r12);
255 void IA64RegisterInfo::emitEpilogue(MachineFunction &MF,
256 MachineBasicBlock &MBB) const {
257 const MachineFrameInfo *MFI = MF.getFrameInfo();
258 MachineBasicBlock::iterator MBBI = prior(MBB.end());
259 assert(MBBI->getOpcode() == IA64::RET &&
260 "Can only insert epilog into returning blocks");
264 // Get the number of bytes allocated from the FrameInfo...
265 unsigned NumBytes = MFI->getStackSize();
267 //now if we need to, restore the old FP
270 //copy the FP into the SP (discards allocas)
271 BuildMI(MBB, MBBI, TII.get(IA64::MOV), IA64::r12).addReg(IA64::r5);
273 BuildMI(MBB, MBBI, TII.get(IA64::LD8), IA64::r5).addReg(IA64::r5);
278 if (NumBytes <= 8191) {
279 BuildMI(MBB, MBBI, TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12).
282 BuildMI(MBB, MBBI, TII.get(IA64::MOVLIMM64), IA64::r22).
284 BuildMI(MBB, MBBI, TII.get(IA64::ADD), IA64::r12).addReg(IA64::r12).
291 unsigned IA64RegisterInfo::getRARegister() const {
292 assert(0 && "What is the return address register");
296 unsigned IA64RegisterInfo::getFrameRegister(MachineFunction &MF) const {
297 return hasFP(MF) ? IA64::r5 : IA64::r12;
300 unsigned IA64RegisterInfo::getEHExceptionRegister() const {
301 assert(0 && "What is the exception register");
305 unsigned IA64RegisterInfo::getEHHandlerRegister() const {
306 assert(0 && "What is the exception handler register");
310 int IA64RegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
311 assert(0 && "What is the dwarf register number");
315 #include "IA64GenRegisterInfo.inc"