1 //===-- IA64ISelLowering.cpp - IA64 DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Duraid Madina and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the IA64ISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "IA64ISelLowering.h"
15 #include "IA64MachineFunctionInfo.h"
16 #include "IA64TargetMachine.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/SSARegMap.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
26 IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
27 : TargetLowering(TM) {
29 // register class for general registers
30 addRegisterClass(MVT::i64, IA64::GRRegisterClass);
32 // register class for FP registers
33 addRegisterClass(MVT::f64, IA64::FPRegisterClass);
35 // register class for predicate registers
36 addRegisterClass(MVT::i1, IA64::PRRegisterClass);
38 setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
39 setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand);
40 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
42 setSetCCResultType(MVT::i1);
43 setShiftAmountType(MVT::i64);
45 setOperationAction(ISD::EXTLOAD , MVT::i1 , Promote);
47 setOperationAction(ISD::ZEXTLOAD , MVT::i1 , Expand);
49 setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
50 setOperationAction(ISD::SEXTLOAD , MVT::i8 , Expand);
51 setOperationAction(ISD::SEXTLOAD , MVT::i16 , Expand);
52 setOperationAction(ISD::SEXTLOAD , MVT::i32 , Expand);
54 setOperationAction(ISD::FREM , MVT::f32 , Expand);
55 setOperationAction(ISD::FREM , MVT::f64 , Expand);
57 setOperationAction(ISD::UREM , MVT::f32 , Expand);
58 setOperationAction(ISD::UREM , MVT::f64 , Expand);
60 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
61 setOperationAction(ISD::MEMSET , MVT::Other, Expand);
62 setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
64 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
65 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
67 // We don't support sin/cos/sqrt
68 setOperationAction(ISD::FSIN , MVT::f64, Expand);
69 setOperationAction(ISD::FCOS , MVT::f64, Expand);
70 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
71 setOperationAction(ISD::FSIN , MVT::f32, Expand);
72 setOperationAction(ISD::FCOS , MVT::f32, Expand);
73 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
75 // We don't have line number support yet.
76 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
77 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
78 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
80 //IA64 has these, but they are not implemented
81 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
82 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
83 setOperationAction(ISD::ROTL , MVT::i64 , Expand);
84 setOperationAction(ISD::ROTR , MVT::i64 , Expand);
85 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); // mux @rev
87 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
88 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
89 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
91 setStackPointerRegisterToSaveRestore(IA64::r12);
93 computeRegisterProperties();
95 addLegalFPImmediate(+0.0);
96 addLegalFPImmediate(+1.0);
99 const char *IA64TargetLowering::getTargetNodeName(unsigned Opcode) const {
102 case IA64ISD::GETFD: return "IA64ISD::GETFD";
103 case IA64ISD::BRCALL: return "IA64ISD::BRCALL";
108 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
109 static bool isFloatingPointZero(SDOperand Op) {
110 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
111 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
112 else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) {
113 // Maybe this has already been legalized into the constant pool?
114 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
115 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get()))
116 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
121 std::vector<SDOperand>
122 IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
123 std::vector<SDOperand> ArgValues;
125 // add beautiful description of IA64 stack frame format
126 // here (from intel 24535803.pdf most likely)
128 MachineFunction &MF = DAG.getMachineFunction();
129 MachineFrameInfo *MFI = MF.getFrameInfo();
131 GP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
132 SP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
133 RP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
135 MachineBasicBlock& BB = MF.front();
137 unsigned args_int[] = {IA64::r32, IA64::r33, IA64::r34, IA64::r35,
138 IA64::r36, IA64::r37, IA64::r38, IA64::r39};
140 unsigned args_FP[] = {IA64::F8, IA64::F9, IA64::F10, IA64::F11,
141 IA64::F12,IA64::F13,IA64::F14, IA64::F15};
147 unsigned used_FPArgs = 0; // how many FP args have been used so far?
149 unsigned ArgOffset = 0;
152 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I)
154 SDOperand newroot, argt;
155 if(count < 8) { // need to fix this logic? maybe.
157 switch (getValueType(I->getType())) {
159 assert(0 && "ERROR in LowerArgs: can't lower this type of arg.\n");
161 // fixme? (well, will need to for weird FP structy stuff,
162 // see intel ABI docs)
164 //XXX BuildMI(&BB, IA64::IDEF, 0, args_FP[used_FPArgs]);
165 MF.addLiveIn(args_FP[used_FPArgs]); // mark this reg as liveIn
166 // floating point args go into f8..f15 as-needed, the increment
167 argVreg[count] = // is below..:
168 MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::f64));
169 // FP args go into f8..f15 as needed: (hence the ++)
170 argPreg[count] = args_FP[used_FPArgs++];
171 argOpc[count] = IA64::FMOV;
172 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), argVreg[count],
174 if (I->getType() == Type::FloatTy)
175 argt = DAG.getNode(ISD::FP_ROUND, MVT::f32, argt);
177 case MVT::i1: // NOTE: as far as C abi stuff goes,
178 // bools are just boring old ints
183 //XXX BuildMI(&BB, IA64::IDEF, 0, args_int[count]);
184 MF.addLiveIn(args_int[count]); // mark this register as liveIn
186 MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
187 argPreg[count] = args_int[count];
188 argOpc[count] = IA64::MOV;
190 DAG.getCopyFromReg(DAG.getRoot(), argVreg[count], MVT::i64);
191 if ( getValueType(I->getType()) != MVT::i64)
192 argt = DAG.getNode(ISD::TRUNCATE, getValueType(I->getType()),
196 } else { // more than 8 args go into the frame
197 // Create the frame index object for this incoming parameter...
198 ArgOffset = 16 + 8 * (count - 8);
199 int FI = MFI->CreateFixedObject(8, ArgOffset);
201 // Create the SelectionDAG nodes corresponding to a load
202 //from this parameter
203 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
204 argt = newroot = DAG.getLoad(getValueType(I->getType()),
205 DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL));
208 DAG.setRoot(newroot.getValue(1));
209 ArgValues.push_back(argt);
213 // Create a vreg to hold the output of (what will become)
214 // the "alloc" instruction
215 VirtGPR = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
216 BuildMI(&BB, IA64::PSEUDO_ALLOC, 0, VirtGPR);
217 // we create a PSEUDO_ALLOC (pseudo)instruction for now
219 BuildMI(&BB, IA64::IDEF, 0, IA64::r1);
222 BuildMI(&BB, IA64::IDEF, 0, IA64::r12);
223 BuildMI(&BB, IA64::IDEF, 0, IA64::rp);
226 BuildMI(&BB, IA64::MOV, 1, GP).addReg(IA64::r1);
229 BuildMI(&BB, IA64::MOV, 1, SP).addReg(IA64::r12);
230 BuildMI(&BB, IA64::MOV, 1, RP).addReg(IA64::rp);
234 unsigned tempOffset=0;
236 // if this is a varargs function, we simply lower llvm.va_start by
237 // pointing to the first entry
240 VarArgsFrameIndex = MFI->CreateFixedObject(8, tempOffset);
243 // here we actually do the moving of args, and store them to the stack
244 // too if this is a varargs function:
245 for (int i = 0; i < count && i < 8; ++i) {
246 BuildMI(&BB, argOpc[i], 1, argVreg[i]).addReg(argPreg[i]);
248 // if this is a varargs function, we copy the input registers to the stack
249 int FI = MFI->CreateFixedObject(8, tempOffset);
250 tempOffset+=8; //XXX: is it safe to use r22 like this?
251 BuildMI(&BB, IA64::MOV, 1, IA64::r22).addFrameIndex(FI);
252 // FIXME: we should use st8.spill here, one day
253 BuildMI(&BB, IA64::ST8, 1, IA64::r22).addReg(argPreg[i]);
257 // Finally, inform the code generator which regs we return values in.
258 // (see the ISD::RET: case in the instruction selector)
259 switch (getValueType(F.getReturnType())) {
260 default: assert(0 && "i have no idea where to return this type!");
261 case MVT::isVoid: break;
267 MF.addLiveOut(IA64::r8);
271 MF.addLiveOut(IA64::F8);
278 std::pair<SDOperand, SDOperand>
279 IA64TargetLowering::LowerCallTo(SDOperand Chain,
280 const Type *RetTy, bool isVarArg,
281 unsigned CallingConv, bool isTailCall,
282 SDOperand Callee, ArgListTy &Args,
285 MachineFunction &MF = DAG.getMachineFunction();
287 unsigned NumBytes = 16;
288 unsigned outRegsUsed = 0;
290 if (Args.size() > 8) {
291 NumBytes += (Args.size() - 8) * 8;
294 outRegsUsed = Args.size();
297 // FIXME? this WILL fail if we ever try to pass around an arg that
298 // consumes more than a single output slot (a 'real' double, int128
299 // some sort of aggregate etc.), as we'll underestimate how many 'outX'
300 // registers we use. Hopefully, the assembler will notice.
301 MF.getInfo<IA64FunctionInfo>()->outRegsUsed=
302 std::max(outRegsUsed, MF.getInfo<IA64FunctionInfo>()->outRegsUsed);
304 // keep stack frame 16-byte aligned
305 //assert(NumBytes==((NumBytes+15) & ~15) && "stack frame not 16-byte aligned!");
306 NumBytes = (NumBytes+15) & ~15;
308 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
309 DAG.getConstant(NumBytes, getPointerTy()));
311 SDOperand StackPtr, NullSV;
312 std::vector<SDOperand> Stores;
313 std::vector<SDOperand> Converts;
314 std::vector<SDOperand> RegValuesToPass;
315 unsigned ArgOffset = 16;
317 for (unsigned i = 0, e = Args.size(); i != e; ++i)
319 SDOperand Val = Args[i].first;
320 MVT::ValueType ObjectVT = Val.getValueType();
321 SDOperand ValToStore(0, 0), ValToConvert(0, 0);
324 default: assert(0 && "unexpected argument type!");
329 //promote to 64-bits, sign/zero extending based on type
331 if(Args[i].second->isSigned())
332 Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Val);
334 Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Val);
338 if(RegValuesToPass.size() >= 8) {
341 RegValuesToPass.push_back(Val);
346 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
349 if(RegValuesToPass.size() >= 8) {
352 RegValuesToPass.push_back(Val);
353 if(1 /* TODO: if(calling external or varadic function)*/ ) {
354 ValToConvert = Val; // additionally pass this FP value as an int
362 StackPtr = DAG.getRegister(IA64::r12, MVT::i64);
363 NullSV = DAG.getSrcValue(NULL);
365 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
366 PtrOff = DAG.getNode(ISD::ADD, MVT::i64, StackPtr, PtrOff);
367 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
368 ValToStore, PtrOff, NullSV));
369 ArgOffset += ObjSize;
372 if(ValToConvert.Val) {
373 Converts.push_back(DAG.getNode(IA64ISD::GETFD, MVT::i64, ValToConvert));
377 // Emit all stores, make sure they occur before any copies into physregs.
379 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
381 static const unsigned IntArgRegs[] = {
382 IA64::out0, IA64::out1, IA64::out2, IA64::out3,
383 IA64::out4, IA64::out5, IA64::out6, IA64::out7
386 static const unsigned FPArgRegs[] = {
387 IA64::F8, IA64::F9, IA64::F10, IA64::F11,
388 IA64::F12, IA64::F13, IA64::F14, IA64::F15
393 // save the current GP, SP and RP : FIXME: do we need to do all 3 always?
394 SDOperand GPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r1, MVT::i64, InFlag);
395 Chain = GPBeforeCall.getValue(1);
396 InFlag = Chain.getValue(2);
397 SDOperand SPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r12, MVT::i64, InFlag);
398 Chain = SPBeforeCall.getValue(1);
399 InFlag = Chain.getValue(2);
400 SDOperand RPBeforeCall = DAG.getCopyFromReg(Chain, IA64::rp, MVT::i64, InFlag);
401 Chain = RPBeforeCall.getValue(1);
402 InFlag = Chain.getValue(2);
404 // Build a sequence of copy-to-reg nodes chained together with token chain
405 // and flag operands which copy the outgoing integer args into regs out[0-7]
406 // mapped 1:1 and the FP args into regs F8-F15 "lazily"
407 // TODO: for performance, we should only copy FP args into int regs when we
408 // know this is required (i.e. for varardic or external (unknown) functions)
410 // first to the FP->(integer representation) conversions, these are
411 // flagged for now, but shouldn't have to be (TODO)
412 unsigned seenConverts = 0;
413 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
414 if(MVT::isFloatingPoint(RegValuesToPass[i].getValueType())) {
415 Chain = DAG.getCopyToReg(Chain, IntArgRegs[i], Converts[seenConverts++], InFlag);
416 InFlag = Chain.getValue(1);
420 // next copy args into the usual places, these are flagged
421 unsigned usedFPArgs = 0;
422 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
423 Chain = DAG.getCopyToReg(Chain,
424 MVT::isInteger(RegValuesToPass[i].getValueType()) ?
425 IntArgRegs[i] : FPArgRegs[usedFPArgs++],
426 RegValuesToPass[i], InFlag);
427 InFlag = Chain.getValue(1);
430 // If the callee is a GlobalAddress node (quite common, every direct call is)
431 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
433 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
434 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i64);
438 std::vector<MVT::ValueType> NodeTys;
439 std::vector<SDOperand> CallOperands;
440 NodeTys.push_back(MVT::Other); // Returns a chain
441 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
442 CallOperands.push_back(Chain);
443 CallOperands.push_back(Callee);
445 // emit the call itself
447 CallOperands.push_back(InFlag);
449 assert(0 && "this should never happen!\n");
451 /* out with the old...
452 Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee, InFlag), 0);
454 Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee), 0);
456 // to make way for a hack:
457 Chain = DAG.getNode(IA64ISD::BRCALL, NodeTys, CallOperands);
458 InFlag = Chain.getValue(1);
460 // restore the GP, SP and RP after the call
461 Chain = DAG.getCopyToReg(Chain, IA64::r1, GPBeforeCall, InFlag);
462 InFlag = Chain.getValue(1);
463 Chain = DAG.getCopyToReg(Chain, IA64::r12, SPBeforeCall, InFlag);
464 InFlag = Chain.getValue(1);
465 Chain = DAG.getCopyToReg(Chain, IA64::rp, RPBeforeCall, InFlag);
466 InFlag = Chain.getValue(1);
468 std::vector<MVT::ValueType> RetVals;
469 RetVals.push_back(MVT::Other);
470 RetVals.push_back(MVT::Flag);
472 MVT::ValueType RetTyVT = getValueType(RetTy);
474 if (RetTyVT != MVT::isVoid) {
476 default: assert(0 && "Unknown value type to return!");
477 case MVT::i1: { // bools are just like other integers (returned in r8)
478 // we *could* fall through to the truncate below, but this saves a
479 // few redundant predicate ops
480 SDOperand boolInR8 = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag);
481 InFlag = boolInR8.getValue(2);
482 Chain = boolInR8.getValue(1);
483 SDOperand zeroReg = DAG.getCopyFromReg(Chain, IA64::r0, MVT::i64, InFlag);
484 InFlag = zeroReg.getValue(2);
485 Chain = zeroReg.getValue(1);
487 RetVal = DAG.getSetCC(MVT::i1, boolInR8, zeroReg, ISD::SETNE);
493 RetVal = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag);
494 Chain = RetVal.getValue(1);
496 // keep track of whether it is sign or zero extended (todo: bools?)
498 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext,
499 MVT::i64, RetVal, DAG.getValueType(RetTyVT));
501 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
504 RetVal = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag);
505 Chain = RetVal.getValue(1);
506 InFlag = RetVal.getValue(2); // XXX dead
509 RetVal = DAG.getCopyFromReg(Chain, IA64::F8, MVT::f64, InFlag);
510 Chain = RetVal.getValue(1);
511 RetVal = DAG.getNode(ISD::TRUNCATE, MVT::f32, RetVal);
514 RetVal = DAG.getCopyFromReg(Chain, IA64::F8, MVT::f64, InFlag);
515 Chain = RetVal.getValue(1);
516 InFlag = RetVal.getValue(2); // XXX dead
521 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
522 DAG.getConstant(NumBytes, getPointerTy()));
524 return std::make_pair(RetVal, Chain);
528 IA64TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
529 Value *VAListV, SelectionDAG &DAG) {
530 // vastart just stores the address of the VarArgsFrameIndex slot.
531 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64);
532 return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR,
533 VAListP, DAG.getSrcValue(VAListV));
536 std::pair<SDOperand,SDOperand> IA64TargetLowering::
537 LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
538 const Type *ArgTy, SelectionDAG &DAG) {
540 MVT::ValueType ArgVT = getValueType(ArgTy);
541 SDOperand Val = DAG.getLoad(MVT::i64, Chain,
542 VAListP, DAG.getSrcValue(VAListV));
543 SDOperand Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), Val,
544 DAG.getSrcValue(NULL));
546 if (ArgVT == MVT::i32 || ArgVT == MVT::f32)
549 assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
550 "Other types should have been promoted for varargs!");
553 Val = DAG.getNode(ISD::ADD, Val.getValueType(), Val,
554 DAG.getConstant(Amt, Val.getValueType()));
555 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
556 Val, VAListP, DAG.getSrcValue(VAListV));
557 return std::make_pair(Result, Chain);
562 std::pair<SDOperand, SDOperand> IA64TargetLowering::
563 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
565 assert(0 && "LowerFrameReturnAddress unimplemented");