1 //===---- IA64ISelDAGToDAG.cpp - IA64 pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for IA64,
11 // converting a legalized dag to an IA64 dag.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "ia64-codegen"
17 #include "IA64TargetMachine.h"
18 #include "IA64ISelLowering.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/SelectionDAGISel.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/Constants.h"
25 #include "llvm/GlobalValue.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/Support/Compiler.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/Support/raw_ostream.h"
35 //===--------------------------------------------------------------------===//
36 /// IA64DAGToDAGISel - IA64 specific code to select IA64 machine
37 /// instructions for SelectionDAG operations.
39 class IA64DAGToDAGISel : public SelectionDAGISel {
40 unsigned GlobalBaseReg;
42 explicit IA64DAGToDAGISel(IA64TargetMachine &TM)
43 : SelectionDAGISel(TM) {}
45 virtual bool runOnFunction(Function &Fn) {
46 // Make sure we re-emit a set of the global base reg if necessary
48 return SelectionDAGISel::runOnFunction(Fn);
51 /// getI64Imm - Return a target constant with the specified value, of type
53 inline SDValue getI64Imm(uint64_t Imm) {
54 return CurDAG->getTargetConstant(Imm, MVT::i64);
57 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
58 /// base register. Return the virtual register that holds this value.
59 // SDValue getGlobalBaseReg(); TODO: hmm
61 // Select - Convert the specified operand from a target-independent to a
62 // target-specific node if it hasn't already been changed.
63 SDNode *Select(SDValue N);
65 SDNode *SelectIntImmediateExpr(SDValue LHS, SDValue RHS,
66 unsigned OCHi, unsigned OCLo,
67 bool IsArithmetic = false,
69 SDNode *SelectBitfieldInsert(SDNode *N);
71 /// SelectCC - Select a comparison of the specified values with the
72 /// specified condition code, returning the CR# of the expression.
73 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC);
75 /// SelectAddr - Given the specified address, return the two operands for a
76 /// load/store instruction, and return true if it should be an indexed [r+r]
78 bool SelectAddr(SDValue Addr, SDValue &Op1, SDValue &Op2);
80 /// InstructionSelect - This callback is invoked by
81 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
82 virtual void InstructionSelect();
84 virtual const char *getPassName() const {
85 return "IA64 (Itanium) DAG->DAG Instruction Selector";
88 // Include the pieces autogenerated from the target description.
89 #include "IA64GenDAGISel.inc"
92 SDNode *SelectDIV(SDValue Op);
96 /// InstructionSelect - This callback is invoked by
97 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
98 void IA64DAGToDAGISel::InstructionSelect() {
101 // Select target instructions for the DAG.
103 CurDAG->RemoveDeadNodes();
106 SDNode *IA64DAGToDAGISel::SelectDIV(SDValue Op) {
107 SDNode *N = Op.getNode();
108 SDValue Chain = N->getOperand(0);
109 SDValue Tmp1 = N->getOperand(0);
110 SDValue Tmp2 = N->getOperand(1);
111 DebugLoc dl = N->getDebugLoc();
115 if(Tmp1.getValueType().isFloatingPoint())
118 bool isModulus=false; // is it a division or a modulus?
121 switch(N->getOpcode()) {
123 case ISD::SDIV: isModulus=false; isSigned=true; break;
124 case ISD::UDIV: isModulus=false; isSigned=false; break;
126 case ISD::SREM: isModulus=true; isSigned=true; break;
127 case ISD::UREM: isModulus=true; isSigned=false; break;
130 // TODO: check for integer divides by powers of 2 (or other simple patterns?)
132 SDValue TmpPR, TmpPR2;
133 SDValue TmpF1, TmpF2, TmpF3, TmpF4, TmpF5, TmpF6, TmpF7, TmpF8;
134 SDValue TmpF9, TmpF10,TmpF11,TmpF12,TmpF13,TmpF14,TmpF15;
137 // we'll need copies of F0 and F1
138 SDValue F0 = CurDAG->getRegister(IA64::F0, MVT::f64);
139 SDValue F1 = CurDAG->getRegister(IA64::F1, MVT::f64);
141 // OK, emit some code:
144 // first, load the inputs into FP regs.
146 SDValue(CurDAG->getTargetNode(IA64::SETFSIG, dl, MVT::f64, Tmp1), 0);
147 Chain = TmpF1.getValue(1);
149 SDValue(CurDAG->getTargetNode(IA64::SETFSIG, dl, MVT::f64, Tmp2), 0);
150 Chain = TmpF2.getValue(1);
152 // next, convert the inputs to FP
155 SDValue(CurDAG->getTargetNode(IA64::FCVTXF, dl, MVT::f64, TmpF1), 0);
156 Chain = TmpF3.getValue(1);
158 SDValue(CurDAG->getTargetNode(IA64::FCVTXF, dl, MVT::f64, TmpF2), 0);
159 Chain = TmpF4.getValue(1);
160 } else { // is unsigned
162 SDValue(CurDAG->getTargetNode(IA64::FCVTXUFS1, dl, MVT::f64, TmpF1),
164 Chain = TmpF3.getValue(1);
166 SDValue(CurDAG->getTargetNode(IA64::FCVTXUFS1, dl, MVT::f64, TmpF2),
168 Chain = TmpF4.getValue(1);
171 } else { // this is an FP divide/remainder, so we 'leak' some temp
172 // regs and assign TmpF3=Tmp1, TmpF4=Tmp2
177 // we start by computing an approximate reciprocal (good to 9 bits?)
178 // note, this instruction writes _both_ TmpF5 (answer) and TmpPR (predicate)
180 TmpF5 = SDValue(CurDAG->getTargetNode(IA64::FRCPAS0, dl, MVT::f64,
181 MVT::i1, TmpF3, TmpF4), 0);
183 TmpF5 = SDValue(CurDAG->getTargetNode(IA64::FRCPAS1, dl, MVT::f64,
184 MVT::i1, TmpF3, TmpF4), 0);
186 TmpPR = TmpF5.getValue(1);
187 Chain = TmpF5.getValue(2);
190 if(isModulus) { // for remainders, it'll be handy to have
191 // copies of -input_b
192 minusB = SDValue(CurDAG->getTargetNode(IA64::SUB, dl, MVT::i64,
193 CurDAG->getRegister(IA64::r0, MVT::i64), Tmp2), 0);
194 Chain = minusB.getValue(1);
197 SDValue TmpE0, TmpY1, TmpE1, TmpY2;
199 SDValue OpsE0[] = { TmpF4, TmpF5, F1, TmpPR };
200 TmpE0 = SDValue(CurDAG->getTargetNode(IA64::CFNMAS1, dl, MVT::f64,
202 Chain = TmpE0.getValue(1);
203 SDValue OpsY1[] = { TmpF5, TmpE0, TmpF5, TmpPR };
204 TmpY1 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64,
206 Chain = TmpY1.getValue(1);
207 SDValue OpsE1[] = { TmpE0, TmpE0, F0, TmpPR };
208 TmpE1 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64,
210 Chain = TmpE1.getValue(1);
211 SDValue OpsY2[] = { TmpY1, TmpE1, TmpY1, TmpPR };
212 TmpY2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64,
214 Chain = TmpY2.getValue(1);
216 if(isFP) { // if this is an FP divide, we finish up here and exit early
218 assert(0 && "Sorry, try another FORTRAN compiler.");
220 SDValue TmpE2, TmpY3, TmpQ0, TmpR0;
222 SDValue OpsE2[] = { TmpE1, TmpE1, F0, TmpPR };
223 TmpE2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64,
225 Chain = TmpE2.getValue(1);
226 SDValue OpsY3[] = { TmpY2, TmpE2, TmpY2, TmpPR };
227 TmpY3 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64,
229 Chain = TmpY3.getValue(1);
230 SDValue OpsQ0[] = { Tmp1, TmpY3, F0, TmpPR };
232 SDValue(CurDAG->getTargetNode(IA64::CFMADS1, dl, // double prec!
233 MVT::f64, OpsQ0, 4), 0);
234 Chain = TmpQ0.getValue(1);
235 SDValue OpsR0[] = { Tmp2, TmpQ0, Tmp1, TmpPR };
237 SDValue(CurDAG->getTargetNode(IA64::CFNMADS1, dl, // double prec!
238 MVT::f64, OpsR0, 4), 0);
239 Chain = TmpR0.getValue(1);
241 // we want Result to have the same target register as the frcpa, so
242 // we two-address hack it. See the comment "for this to work..." on
243 // page 48 of Intel application note #245415
244 SDValue Ops[] = { TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR };
245 Result = CurDAG->getTargetNode(IA64::TCFMADS0, dl, // d.p. s0 rndg!
247 Chain = SDValue(Result, 1);
248 return Result; // XXX: early exit!
249 } else { // this is *not* an FP divide, so there's a bit left to do:
251 SDValue TmpQ2, TmpR2, TmpQ3, TmpQ;
253 SDValue OpsQ2[] = { TmpF3, TmpY2, F0, TmpPR };
254 TmpQ2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64,
256 Chain = TmpQ2.getValue(1);
257 SDValue OpsR2[] = { TmpF4, TmpQ2, TmpF3, TmpPR };
258 TmpR2 = SDValue(CurDAG->getTargetNode(IA64::CFNMAS1, dl, MVT::f64,
260 Chain = TmpR2.getValue(1);
262 // we want TmpQ3 to have the same target register as the frcpa? maybe we
263 // should two-address hack it. See the comment "for this to work..." on page
264 // 48 of Intel application note #245415
265 SDValue OpsQ3[] = { TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR };
266 TmpQ3 = SDValue(CurDAG->getTargetNode(IA64::TCFMAS1, dl, MVT::f64,
268 Chain = TmpQ3.getValue(1);
270 // STORY: without these two-address instructions (TCFMAS1 and TCFMADS0)
271 // the FPSWA won't be able to help out in the case of large/tiny
272 // arguments. Other fun bugs may also appear, e.g. 0/x = x, not 0.
275 TmpQ = SDValue(CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1, dl,
276 MVT::f64, TmpQ3), 0);
278 TmpQ = SDValue(CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1, dl,
279 MVT::f64, TmpQ3), 0);
281 Chain = TmpQ.getValue(1);
285 SDValue(CurDAG->getTargetNode(IA64::SETFSIG, dl, MVT::f64, minusB),
287 Chain = FPminusB.getValue(1);
289 SDValue(CurDAG->getTargetNode(IA64::XMAL, dl, MVT::f64,
290 TmpQ, FPminusB, TmpF1), 0);
291 Chain = Remainder.getValue(1);
292 Result = CurDAG->getTargetNode(IA64::GETFSIG, dl, MVT::i64, Remainder);
293 Chain = SDValue(Result, 1);
294 } else { // just an integer divide
295 Result = CurDAG->getTargetNode(IA64::GETFSIG, dl, MVT::i64, TmpQ);
296 Chain = SDValue(Result, 1);
300 } // wasn't an FP divide
303 // Select - Convert the specified operand from a target-independent to a
304 // target-specific node if it hasn't already been changed.
305 SDNode *IA64DAGToDAGISel::Select(SDValue Op) {
306 SDNode *N = Op.getNode();
307 if (N->isMachineOpcode())
308 return NULL; // Already selected.
309 DebugLoc dl = Op.getDebugLoc();
311 switch (N->getOpcode()) {
314 case IA64ISD::BRCALL: { // XXX: this is also a hack!
315 SDValue Chain = N->getOperand(0);
316 SDValue InFlag; // Null incoming flag value.
318 if(N->getNumOperands()==3) { // we have an incoming chain, callee and flag
319 InFlag = N->getOperand(2);
325 // if we can call directly, do so
326 if (GlobalAddressSDNode *GASD =
327 dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
328 CallOpcode = IA64::BRCALL_IPREL_GA;
329 CallOperand = CurDAG->getTargetGlobalAddress(GASD->getGlobal(), MVT::i64);
330 } else if (isa<ExternalSymbolSDNode>(N->getOperand(1))) {
331 // FIXME: we currently NEED this case for correctness, to avoid
332 // "non-pic code with imm reloc.n against dynamic symbol" errors
333 CallOpcode = IA64::BRCALL_IPREL_ES;
334 CallOperand = N->getOperand(1);
336 // otherwise we need to load the function descriptor,
337 // load the branch target (function)'s entry point and GP,
338 // branch (call) then restore the GP
339 SDValue FnDescriptor = N->getOperand(1);
341 // load the branch target's entry point [mem] and
343 SDValue targetEntryPoint=
344 SDValue(CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64, MVT::Other,
345 FnDescriptor, CurDAG->getEntryNode()), 0);
346 Chain = targetEntryPoint.getValue(1);
347 SDValue targetGPAddr=
348 SDValue(CurDAG->getTargetNode(IA64::ADDS, dl, MVT::i64,
350 CurDAG->getConstant(8, MVT::i64)), 0);
351 Chain = targetGPAddr.getValue(1);
353 SDValue(CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64,MVT::Other,
354 targetGPAddr, CurDAG->getEntryNode()), 0);
355 Chain = targetGP.getValue(1);
357 Chain = CurDAG->getCopyToReg(Chain, dl, IA64::r1, targetGP, InFlag);
358 InFlag = Chain.getValue(1);
359 Chain = CurDAG->getCopyToReg(Chain, dl, IA64::B6,
360 targetEntryPoint, InFlag); // FLAG these?
361 InFlag = Chain.getValue(1);
363 CallOperand = CurDAG->getRegister(IA64::B6, MVT::i64);
364 CallOpcode = IA64::BRCALL_INDIRECT;
367 // Finally, once everything is setup, emit the call itself
368 if (InFlag.getNode())
369 Chain = SDValue(CurDAG->getTargetNode(CallOpcode, dl, MVT::Other,
370 MVT::Flag, CallOperand, InFlag), 0);
371 else // there might be no arguments
372 Chain = SDValue(CurDAG->getTargetNode(CallOpcode, dl, MVT::Other,
373 MVT::Flag, CallOperand, Chain), 0);
374 InFlag = Chain.getValue(1);
376 std::vector<SDValue> CallResults;
378 CallResults.push_back(Chain);
379 CallResults.push_back(InFlag);
381 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
382 ReplaceUses(Op.getValue(i), CallResults[i]);
386 case IA64ISD::GETFD: {
387 SDValue Input = N->getOperand(0);
388 return CurDAG->getTargetNode(IA64::GETFD, dl, MVT::i64, Input);
396 return SelectDIV(Op);
398 case ISD::TargetConstantFP: {
399 SDValue Chain = CurDAG->getEntryNode(); // this is a constant, so..
402 ConstantFPSDNode* N2 = cast<ConstantFPSDNode>(N);
403 if (N2->getValueAPF().isPosZero()) {
404 V = CurDAG->getCopyFromReg(Chain, dl, IA64::F0, MVT::f64);
405 } else if (N2->isExactlyValue(N2->getValueType(0) == MVT::f32 ?
406 APFloat(+1.0f) : APFloat(+1.0))) {
407 V = CurDAG->getCopyFromReg(Chain, dl, IA64::F1, MVT::f64);
409 assert(0 && "Unexpected FP constant!");
411 ReplaceUses(SDValue(N, 0), V);
415 case ISD::FrameIndex: { // TODO: reduce creepyness
416 int FI = cast<FrameIndexSDNode>(N)->getIndex();
418 return CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
419 CurDAG->getTargetFrameIndex(FI, MVT::i64));
421 return CurDAG->getTargetNode(IA64::MOV, dl, MVT::i64,
422 CurDAG->getTargetFrameIndex(FI, MVT::i64));
425 case ISD::ConstantPool: { // TODO: nuke the constant pool
426 // (ia64 doesn't need one)
427 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N);
428 Constant *C = CP->getConstVal();
429 SDValue CPI = CurDAG->getTargetConstantPool(C, MVT::i64,
431 return CurDAG->getTargetNode(IA64::ADDL_GA, dl, MVT::i64, // ?
432 CurDAG->getRegister(IA64::r1, MVT::i64), CPI);
435 case ISD::GlobalAddress: {
436 GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
437 SDValue GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
439 SDValue(CurDAG->getTargetNode(IA64::ADDL_GA, dl, MVT::i64,
440 CurDAG->getRegister(IA64::r1,
442 return CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64, MVT::Other, Tmp,
443 CurDAG->getEntryNode());
447 case ISD::ExternalSymbol: {
448 SDValue EA = CurDAG->getTargetExternalSymbol(
449 cast<ExternalSymbolSDNode>(N)->getSymbol(),
451 SDValue Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, dl, MVT::i64,
452 CurDAG->getRegister(IA64::r1,
455 return CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64, Tmp);
459 case ISD::LOAD: { // FIXME: load -1, not 1, for bools?
460 LoadSDNode *LD = cast<LoadSDNode>(N);
461 SDValue Chain = LD->getChain();
462 SDValue Address = LD->getBasePtr();
464 MVT TypeBeingLoaded = LD->getMemoryVT();
466 switch (TypeBeingLoaded.getSimpleVT()) {
471 assert(0 && "Cannot load this type!");
472 case MVT::i1: { // this is a bool
473 Opc = IA64::LD1; // first we load a byte, then compare for != 0
474 if(N->getValueType(0) == MVT::i1) { // XXX: early exit!
475 return CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
476 SDValue(CurDAG->getTargetNode(Opc, dl,
479 CurDAG->getRegister(IA64::r0, MVT::i64),
482 /* otherwise, we want to load a bool into something bigger: LD1
483 will do that for us, so we just fall through */
485 case MVT::i8: Opc = IA64::LD1; break;
486 case MVT::i16: Opc = IA64::LD2; break;
487 case MVT::i32: Opc = IA64::LD4; break;
488 case MVT::i64: Opc = IA64::LD8; break;
490 case MVT::f32: Opc = IA64::LDF4; break;
491 case MVT::f64: Opc = IA64::LDF8; break;
494 // TODO: comment this
495 return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
500 StoreSDNode *ST = cast<StoreSDNode>(N);
501 SDValue Address = ST->getBasePtr();
502 SDValue Chain = ST->getChain();
505 if (ISD::isNON_TRUNCStore(N)) {
506 switch (N->getOperand(1).getValueType().getSimpleVT()) {
507 default: assert(0 && "unknown type in store");
508 case MVT::i1: { // this is a bool
509 Opc = IA64::ST1; // we store either 0 or 1 as a byte
511 SDValue Initial = CurDAG->getCopyFromReg(Chain, dl, IA64::r0, MVT::i64);
512 Chain = Initial.getValue(1);
513 // then load 1 into the same reg iff the predicate to store is 1
514 SDValue Tmp = ST->getValue();
516 SDValue(CurDAG->getTargetNode(IA64::TPCADDS, dl, MVT::i64, Initial,
517 CurDAG->getTargetConstant(1,
520 return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
522 case MVT::i64: Opc = IA64::ST8; break;
523 case MVT::f64: Opc = IA64::STF8; break;
525 } else { // Truncating store
526 switch(ST->getMemoryVT().getSimpleVT()) {
527 default: assert(0 && "unknown type in truncstore");
528 case MVT::i8: Opc = IA64::ST1; break;
529 case MVT::i16: Opc = IA64::ST2; break;
530 case MVT::i32: Opc = IA64::ST4; break;
531 case MVT::f32: Opc = IA64::STF4; break;
535 SDValue N1 = N->getOperand(1);
536 SDValue N2 = N->getOperand(2);
537 return CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain);
541 SDValue Chain = N->getOperand(0);
542 SDValue CC = N->getOperand(1);
543 MachineBasicBlock *Dest =
544 cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
545 //FIXME - we do NOT need long branches all the time
546 return CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC,
547 CurDAG->getBasicBlock(Dest), Chain);
550 case ISD::CALLSEQ_START:
551 case ISD::CALLSEQ_END: {
552 int64_t Amt = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
553 unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
554 IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
555 SDValue N0 = N->getOperand(0);
556 return CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0);
560 // FIXME: we don't need long branches all the time!
561 SDValue N0 = N->getOperand(0);
562 return CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other,
563 N->getOperand(1), N0);
566 return SelectCode(Op);
570 /// createIA64DAGToDAGInstructionSelector - This pass converts a legalized DAG
571 /// into an IA64-specific DAG, ready for instruction scheduling.
574 *llvm::createIA64DAGToDAGInstructionSelector(IA64TargetMachine &TM) {
575 return new IA64DAGToDAGISel(TM);