1 //===----- HexagonPacketizer.cpp - vliw packetizer ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements a simple VLIW packetizer using DFA. The packetizer works on
11 // machine basic blocks. For each instruction I in BB, the packetizer consults
12 // the DFA to see if machine resources are available to execute I. If so, the
13 // packetizer checks if I depends on any instruction J in the current packet.
14 // If no dependency is found, I is added to current packet and machine resource
15 // is marked as taken. If any dependency is found, a target API call is made to
16 // prune the dependence.
18 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "packets"
21 #include "HexagonMachineFunctionInfo.h"
22 #include "HexagonRegisterInfo.h"
23 #include "HexagonSubtarget.h"
24 #include "HexagonTargetMachine.h"
25 #include "llvm/ADT/DenseMap.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/CodeGen/DFAPacketizer.h"
28 #include "llvm/CodeGen/LatencyPriorityQueue.h"
29 #include "llvm/CodeGen/MachineDominators.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineLoopInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/Passes.h"
37 #include "llvm/CodeGen/ScheduleDAG.h"
38 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
39 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
40 #include "llvm/CodeGen/SchedulerRegistry.h"
41 #include "llvm/MC/MCInstrItineraries.h"
42 #include "llvm/Support/CommandLine.h"
43 #include "llvm/Support/Compiler.h"
44 #include "llvm/Support/Debug.h"
45 #include "llvm/Support/MathExtras.h"
46 #include "llvm/Target/TargetInstrInfo.h"
47 #include "llvm/Target/TargetMachine.h"
48 #include "llvm/Target/TargetRegisterInfo.h"
54 class HexagonPacketizer : public MachineFunctionPass {
58 HexagonPacketizer() : MachineFunctionPass(ID) {}
60 void getAnalysisUsage(AnalysisUsage &AU) const {
62 AU.addRequired<MachineDominatorTree>();
63 AU.addPreserved<MachineDominatorTree>();
64 AU.addRequired<MachineLoopInfo>();
65 AU.addPreserved<MachineLoopInfo>();
66 MachineFunctionPass::getAnalysisUsage(AU);
69 const char *getPassName() const {
70 return "Hexagon Packetizer";
73 bool runOnMachineFunction(MachineFunction &Fn);
75 char HexagonPacketizer::ID = 0;
77 class HexagonPacketizerList : public VLIWPacketizerList {
81 // Has the instruction been promoted to a dot-new instruction.
82 bool PromotedToDotNew;
84 // Has the instruction been glued to allocframe.
85 bool GlueAllocframeStore;
87 // Has the feeder instruction been glued to new value jump.
88 bool GlueToNewValueJump;
90 // Check if there is a dependence between some instruction already in this
91 // packet and this instruction.
94 // Only check for dependence if there are resources available to
95 // schedule this instruction.
96 bool FoundSequentialDependence;
100 HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
101 MachineDominatorTree &MDT);
103 // initPacketizerState - initialize some internal flags.
104 void initPacketizerState();
106 // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
107 bool ignorePseudoInstruction(MachineInstr *MI, MachineBasicBlock *MBB);
109 // isSoloInstruction - return true if instruction MI can not be packetized
110 // with any other instruction, which means that MI itself is a packet.
111 bool isSoloInstruction(MachineInstr *MI);
113 // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
115 bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ);
117 // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
119 bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ);
121 MachineBasicBlock::iterator addToPacket(MachineInstr *MI);
123 bool IsCallDependent(MachineInstr* MI, SDep::Kind DepType, unsigned DepReg);
124 bool PromoteToDotNew(MachineInstr* MI, SDep::Kind DepType,
125 MachineBasicBlock::iterator &MII,
126 const TargetRegisterClass* RC);
127 bool CanPromoteToDotNew(MachineInstr* MI, SUnit* PacketSU,
129 std::map <MachineInstr*, SUnit*> MIToSUnit,
130 MachineBasicBlock::iterator &MII,
131 const TargetRegisterClass* RC);
132 bool CanPromoteToNewValue(MachineInstr* MI, SUnit* PacketSU,
134 std::map <MachineInstr*, SUnit*> MIToSUnit,
135 MachineBasicBlock::iterator &MII);
136 bool CanPromoteToNewValueStore(MachineInstr* MI, MachineInstr* PacketMI,
138 std::map <MachineInstr*, SUnit*> MIToSUnit);
139 bool DemoteToDotOld(MachineInstr* MI);
140 bool ArePredicatesComplements(MachineInstr* MI1, MachineInstr* MI2,
141 std::map <MachineInstr*, SUnit*> MIToSUnit);
142 bool RestrictingDepExistInPacket(MachineInstr*,
143 unsigned, std::map <MachineInstr*, SUnit*>);
144 bool isNewifiable(MachineInstr* MI);
145 bool isCondInst(MachineInstr* MI);
146 bool IsNewifyStore (MachineInstr* MI);
147 bool tryAllocateResourcesForConstExt(MachineInstr* MI);
148 bool canReserveResourcesForConstExt(MachineInstr *MI);
149 void reserveResourcesForConstExt(MachineInstr* MI);
150 bool isNewValueInst(MachineInstr* MI);
151 bool isDotNewInst(MachineInstr* MI);
155 // HexagonPacketizerList Ctor.
156 HexagonPacketizerList::HexagonPacketizerList(
157 MachineFunction &MF, MachineLoopInfo &MLI,MachineDominatorTree &MDT)
158 : VLIWPacketizerList(MF, MLI, MDT, true){
161 bool HexagonPacketizer::runOnMachineFunction(MachineFunction &Fn) {
162 const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo();
163 MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
164 MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
166 // Instantiate the packetizer.
167 HexagonPacketizerList Packetizer(Fn, MLI, MDT);
169 // DFA state table should not be empty.
170 assert(Packetizer.getResourceTracker() && "Empty DFA table!");
173 // Loop over all basic blocks and remove KILL pseudo-instructions
174 // These instructions confuse the dependence analysis. Consider:
176 // R0 = KILL R0, D0 (Insn 1)
178 // Here, Insn 1 will result in the dependence graph not emitting an output
179 // dependence between Insn 0 and Insn 2. This can lead to incorrect
182 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
183 MBB != MBBe; ++MBB) {
184 MachineBasicBlock::iterator End = MBB->end();
185 MachineBasicBlock::iterator MI = MBB->begin();
188 MachineBasicBlock::iterator DeleteMI = MI;
190 MBB->erase(DeleteMI);
198 // Loop over all of the basic blocks.
199 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
200 MBB != MBBe; ++MBB) {
201 // Find scheduling regions and schedule / packetize each region.
202 unsigned RemainingCount = MBB->size();
203 for(MachineBasicBlock::iterator RegionEnd = MBB->end();
204 RegionEnd != MBB->begin();) {
205 // The next region starts above the previous region. Look backward in the
206 // instruction stream until we find the nearest boundary.
207 MachineBasicBlock::iterator I = RegionEnd;
208 for(;I != MBB->begin(); --I, --RemainingCount) {
209 if (TII->isSchedulingBoundary(llvm::prior(I), MBB, Fn))
214 // Skip empty scheduling regions.
215 if (I == RegionEnd) {
216 RegionEnd = llvm::prior(RegionEnd);
220 // Skip regions with one instruction.
221 if (I == llvm::prior(RegionEnd)) {
222 RegionEnd = llvm::prior(RegionEnd);
226 Packetizer.PacketizeMIs(MBB, I, RegionEnd);
235 static bool IsIndirectCall(MachineInstr* MI) {
236 return ((MI->getOpcode() == Hexagon::CALLR) ||
237 (MI->getOpcode() == Hexagon::CALLRv3));
240 // Reserve resources for constant extender. Trigure an assertion if
242 void HexagonPacketizerList::reserveResourcesForConstExt(MachineInstr* MI) {
243 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
244 MachineInstr *PseudoMI = MI->getParent()->getParent()->CreateMachineInstr(
245 QII->get(Hexagon::IMMEXT), MI->getDebugLoc());
247 if (ResourceTracker->canReserveResources(PseudoMI)) {
248 ResourceTracker->reserveResources(PseudoMI);
249 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
251 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
252 llvm_unreachable("can not reserve resources for constant extender.");
257 bool HexagonPacketizerList::canReserveResourcesForConstExt(MachineInstr *MI) {
258 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
259 assert(QII->isExtended(MI) &&
260 "Should only be called for constant extended instructions");
261 MachineFunction *MF = MI->getParent()->getParent();
262 MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT),
264 bool CanReserve = ResourceTracker->canReserveResources(PseudoMI);
265 MF->DeleteMachineInstr(PseudoMI);
269 // Allocate resources (i.e. 4 bytes) for constant extender. If succeed, return
270 // true, otherwise, return false.
271 bool HexagonPacketizerList::tryAllocateResourcesForConstExt(MachineInstr* MI) {
272 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
273 MachineInstr *PseudoMI = MI->getParent()->getParent()->CreateMachineInstr(
274 QII->get(Hexagon::IMMEXT), MI->getDebugLoc());
276 if (ResourceTracker->canReserveResources(PseudoMI)) {
277 ResourceTracker->reserveResources(PseudoMI);
278 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
281 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
287 bool HexagonPacketizerList::IsCallDependent(MachineInstr* MI,
291 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
292 const HexagonRegisterInfo* QRI =
293 (const HexagonRegisterInfo *) TM.getRegisterInfo();
295 // Check for lr dependence
296 if (DepReg == QRI->getRARegister()) {
300 if (QII->isDeallocRet(MI)) {
301 if (DepReg == QRI->getFrameRegister() ||
302 DepReg == QRI->getStackRegister())
306 // Check if this is a predicate dependence
307 const TargetRegisterClass* RC = QRI->getMinimalPhysRegClass(DepReg);
308 if (RC == &Hexagon::PredRegsRegClass) {
313 // Lastly check for an operand used in an indirect call
314 // If we had an attribute for checking if an instruction is an indirect call,
315 // then we could have avoided this relatively brittle implementation of
318 // Assumes that the first operand of the CALLr is the function address
320 if (IsIndirectCall(MI) && (DepType == SDep::Data)) {
321 MachineOperand MO = MI->getOperand(0);
322 if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg)) {
330 static bool IsRegDependence(const SDep::Kind DepType) {
331 return (DepType == SDep::Data || DepType == SDep::Anti ||
332 DepType == SDep::Output);
335 static bool IsDirectJump(MachineInstr* MI) {
336 return (MI->getOpcode() == Hexagon::JMP);
339 static bool IsSchedBarrier(MachineInstr* MI) {
340 switch (MI->getOpcode()) {
341 case Hexagon::BARRIER:
347 static bool IsControlFlow(MachineInstr* MI) {
348 return (MI->getDesc().isTerminator() || MI->getDesc().isCall());
351 bool HexagonPacketizerList::isNewValueInst(MachineInstr* MI) {
352 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
353 if (QII->isNewValueJump(MI))
356 if (QII->isNewValueStore(MI))
362 // Function returns true if an instruction can be promoted to the new-value
363 // store. It will always return false for v2 and v3.
364 // It lists all the conditional and unconditional stores that can be promoted
365 // to the new-value stores.
367 bool HexagonPacketizerList::IsNewifyStore (MachineInstr* MI) {
368 const HexagonRegisterInfo* QRI =
369 (const HexagonRegisterInfo *) TM.getRegisterInfo();
370 switch (MI->getOpcode())
374 case Hexagon::STrib_indexed:
375 case Hexagon::STrib_indexed_shl_V4:
376 case Hexagon::STrib_shl_V4:
377 case Hexagon::STrib_GP_V4:
378 case Hexagon::STb_GP_V4:
379 case Hexagon::POST_STbri:
380 case Hexagon::STrib_cPt:
381 case Hexagon::STrib_cdnPt_V4:
382 case Hexagon::STrib_cNotPt:
383 case Hexagon::STrib_cdnNotPt_V4:
384 case Hexagon::STrib_indexed_cPt:
385 case Hexagon::STrib_indexed_cdnPt_V4:
386 case Hexagon::STrib_indexed_cNotPt:
387 case Hexagon::STrib_indexed_cdnNotPt_V4:
388 case Hexagon::STrib_indexed_shl_cPt_V4:
389 case Hexagon::STrib_indexed_shl_cdnPt_V4:
390 case Hexagon::STrib_indexed_shl_cNotPt_V4:
391 case Hexagon::STrib_indexed_shl_cdnNotPt_V4:
392 case Hexagon::POST_STbri_cPt:
393 case Hexagon::POST_STbri_cdnPt_V4:
394 case Hexagon::POST_STbri_cNotPt:
395 case Hexagon::POST_STbri_cdnNotPt_V4:
396 case Hexagon::STb_GP_cPt_V4:
397 case Hexagon::STb_GP_cNotPt_V4:
398 case Hexagon::STb_GP_cdnPt_V4:
399 case Hexagon::STb_GP_cdnNotPt_V4:
400 case Hexagon::STrib_GP_cPt_V4:
401 case Hexagon::STrib_GP_cNotPt_V4:
402 case Hexagon::STrib_GP_cdnPt_V4:
403 case Hexagon::STrib_GP_cdnNotPt_V4:
407 case Hexagon::STrih_indexed:
408 case Hexagon::STrih_indexed_shl_V4:
409 case Hexagon::STrih_shl_V4:
410 case Hexagon::STrih_GP_V4:
411 case Hexagon::STh_GP_V4:
412 case Hexagon::POST_SThri:
413 case Hexagon::STrih_cPt:
414 case Hexagon::STrih_cdnPt_V4:
415 case Hexagon::STrih_cNotPt:
416 case Hexagon::STrih_cdnNotPt_V4:
417 case Hexagon::STrih_indexed_cPt:
418 case Hexagon::STrih_indexed_cdnPt_V4:
419 case Hexagon::STrih_indexed_cNotPt:
420 case Hexagon::STrih_indexed_cdnNotPt_V4:
421 case Hexagon::STrih_indexed_shl_cPt_V4:
422 case Hexagon::STrih_indexed_shl_cdnPt_V4:
423 case Hexagon::STrih_indexed_shl_cNotPt_V4:
424 case Hexagon::STrih_indexed_shl_cdnNotPt_V4:
425 case Hexagon::POST_SThri_cPt:
426 case Hexagon::POST_SThri_cdnPt_V4:
427 case Hexagon::POST_SThri_cNotPt:
428 case Hexagon::POST_SThri_cdnNotPt_V4:
429 case Hexagon::STh_GP_cPt_V4:
430 case Hexagon::STh_GP_cNotPt_V4:
431 case Hexagon::STh_GP_cdnPt_V4:
432 case Hexagon::STh_GP_cdnNotPt_V4:
433 case Hexagon::STrih_GP_cPt_V4:
434 case Hexagon::STrih_GP_cNotPt_V4:
435 case Hexagon::STrih_GP_cdnPt_V4:
436 case Hexagon::STrih_GP_cdnNotPt_V4:
440 case Hexagon::STriw_indexed:
441 case Hexagon::STriw_indexed_shl_V4:
442 case Hexagon::STriw_shl_V4:
443 case Hexagon::STriw_GP_V4:
444 case Hexagon::STw_GP_V4:
445 case Hexagon::POST_STwri:
446 case Hexagon::STriw_cPt:
447 case Hexagon::STriw_cdnPt_V4:
448 case Hexagon::STriw_cNotPt:
449 case Hexagon::STriw_cdnNotPt_V4:
450 case Hexagon::STriw_indexed_cPt:
451 case Hexagon::STriw_indexed_cdnPt_V4:
452 case Hexagon::STriw_indexed_cNotPt:
453 case Hexagon::STriw_indexed_cdnNotPt_V4:
454 case Hexagon::STriw_indexed_shl_cPt_V4:
455 case Hexagon::STriw_indexed_shl_cdnPt_V4:
456 case Hexagon::STriw_indexed_shl_cNotPt_V4:
457 case Hexagon::STriw_indexed_shl_cdnNotPt_V4:
458 case Hexagon::POST_STwri_cPt:
459 case Hexagon::POST_STwri_cdnPt_V4:
460 case Hexagon::POST_STwri_cNotPt:
461 case Hexagon::POST_STwri_cdnNotPt_V4:
462 case Hexagon::STw_GP_cPt_V4:
463 case Hexagon::STw_GP_cNotPt_V4:
464 case Hexagon::STw_GP_cdnPt_V4:
465 case Hexagon::STw_GP_cdnNotPt_V4:
466 case Hexagon::STriw_GP_cPt_V4:
467 case Hexagon::STriw_GP_cNotPt_V4:
468 case Hexagon::STriw_GP_cdnPt_V4:
469 case Hexagon::STriw_GP_cdnNotPt_V4:
470 return QRI->Subtarget.hasV4TOps();
475 static bool IsLoopN(MachineInstr *MI) {
476 return (MI->getOpcode() == Hexagon::LOOP0_i ||
477 MI->getOpcode() == Hexagon::LOOP0_r);
480 /// DoesModifyCalleeSavedReg - Returns true if the instruction modifies a
481 /// callee-saved register.
482 static bool DoesModifyCalleeSavedReg(MachineInstr *MI,
483 const TargetRegisterInfo *TRI) {
484 for (const uint16_t *CSR = TRI->getCalleeSavedRegs(); *CSR; ++CSR) {
485 unsigned CalleeSavedReg = *CSR;
486 if (MI->modifiesRegister(CalleeSavedReg, TRI))
492 // Return the new value instruction for a given store.
493 static int GetDotNewOp(const int opc) {
495 default: llvm_unreachable("Unknown .new type");
496 // store new value byte
498 return Hexagon::STrib_nv_V4;
500 case Hexagon::STrib_indexed:
501 return Hexagon::STrib_indexed_nv_V4;
503 case Hexagon::STrib_indexed_shl_V4:
504 return Hexagon::STrib_indexed_shl_nv_V4;
506 case Hexagon::STrib_shl_V4:
507 return Hexagon::STrib_shl_nv_V4;
509 case Hexagon::STrib_GP_V4:
510 return Hexagon::STrib_GP_nv_V4;
512 case Hexagon::STb_GP_V4:
513 return Hexagon::STb_GP_nv_V4;
515 case Hexagon::POST_STbri:
516 return Hexagon::POST_STbri_nv_V4;
518 case Hexagon::STrib_cPt:
519 return Hexagon::STrib_cPt_nv_V4;
521 case Hexagon::STrib_cdnPt_V4:
522 return Hexagon::STrib_cdnPt_nv_V4;
524 case Hexagon::STrib_cNotPt:
525 return Hexagon::STrib_cNotPt_nv_V4;
527 case Hexagon::STrib_cdnNotPt_V4:
528 return Hexagon::STrib_cdnNotPt_nv_V4;
530 case Hexagon::STrib_indexed_cPt:
531 return Hexagon::STrib_indexed_cPt_nv_V4;
533 case Hexagon::STrib_indexed_cdnPt_V4:
534 return Hexagon::STrib_indexed_cdnPt_nv_V4;
536 case Hexagon::STrib_indexed_cNotPt:
537 return Hexagon::STrib_indexed_cNotPt_nv_V4;
539 case Hexagon::STrib_indexed_cdnNotPt_V4:
540 return Hexagon::STrib_indexed_cdnNotPt_nv_V4;
542 case Hexagon::STrib_indexed_shl_cPt_V4:
543 return Hexagon::STrib_indexed_shl_cPt_nv_V4;
545 case Hexagon::STrib_indexed_shl_cdnPt_V4:
546 return Hexagon::STrib_indexed_shl_cdnPt_nv_V4;
548 case Hexagon::STrib_indexed_shl_cNotPt_V4:
549 return Hexagon::STrib_indexed_shl_cNotPt_nv_V4;
551 case Hexagon::STrib_indexed_shl_cdnNotPt_V4:
552 return Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4;
554 case Hexagon::POST_STbri_cPt:
555 return Hexagon::POST_STbri_cPt_nv_V4;
557 case Hexagon::POST_STbri_cdnPt_V4:
558 return Hexagon::POST_STbri_cdnPt_nv_V4;
560 case Hexagon::POST_STbri_cNotPt:
561 return Hexagon::POST_STbri_cNotPt_nv_V4;
563 case Hexagon::POST_STbri_cdnNotPt_V4:
564 return Hexagon::POST_STbri_cdnNotPt_nv_V4;
566 case Hexagon::STb_GP_cPt_V4:
567 return Hexagon::STb_GP_cPt_nv_V4;
569 case Hexagon::STb_GP_cNotPt_V4:
570 return Hexagon::STb_GP_cNotPt_nv_V4;
572 case Hexagon::STb_GP_cdnPt_V4:
573 return Hexagon::STb_GP_cdnPt_nv_V4;
575 case Hexagon::STb_GP_cdnNotPt_V4:
576 return Hexagon::STb_GP_cdnNotPt_nv_V4;
578 case Hexagon::STrib_GP_cPt_V4:
579 return Hexagon::STrib_GP_cPt_nv_V4;
581 case Hexagon::STrib_GP_cNotPt_V4:
582 return Hexagon::STrib_GP_cNotPt_nv_V4;
584 case Hexagon::STrib_GP_cdnPt_V4:
585 return Hexagon::STrib_GP_cdnPt_nv_V4;
587 case Hexagon::STrib_GP_cdnNotPt_V4:
588 return Hexagon::STrib_GP_cdnNotPt_nv_V4;
590 // store new value halfword
592 return Hexagon::STrih_nv_V4;
594 case Hexagon::STrih_indexed:
595 return Hexagon::STrih_indexed_nv_V4;
597 case Hexagon::STrih_indexed_shl_V4:
598 return Hexagon::STrih_indexed_shl_nv_V4;
600 case Hexagon::STrih_shl_V4:
601 return Hexagon::STrih_shl_nv_V4;
603 case Hexagon::STrih_GP_V4:
604 return Hexagon::STrih_GP_nv_V4;
606 case Hexagon::STh_GP_V4:
607 return Hexagon::STh_GP_nv_V4;
609 case Hexagon::POST_SThri:
610 return Hexagon::POST_SThri_nv_V4;
612 case Hexagon::STrih_cPt:
613 return Hexagon::STrih_cPt_nv_V4;
615 case Hexagon::STrih_cdnPt_V4:
616 return Hexagon::STrih_cdnPt_nv_V4;
618 case Hexagon::STrih_cNotPt:
619 return Hexagon::STrih_cNotPt_nv_V4;
621 case Hexagon::STrih_cdnNotPt_V4:
622 return Hexagon::STrih_cdnNotPt_nv_V4;
624 case Hexagon::STrih_indexed_cPt:
625 return Hexagon::STrih_indexed_cPt_nv_V4;
627 case Hexagon::STrih_indexed_cdnPt_V4:
628 return Hexagon::STrih_indexed_cdnPt_nv_V4;
630 case Hexagon::STrih_indexed_cNotPt:
631 return Hexagon::STrih_indexed_cNotPt_nv_V4;
633 case Hexagon::STrih_indexed_cdnNotPt_V4:
634 return Hexagon::STrih_indexed_cdnNotPt_nv_V4;
636 case Hexagon::STrih_indexed_shl_cPt_V4:
637 return Hexagon::STrih_indexed_shl_cPt_nv_V4;
639 case Hexagon::STrih_indexed_shl_cdnPt_V4:
640 return Hexagon::STrih_indexed_shl_cdnPt_nv_V4;
642 case Hexagon::STrih_indexed_shl_cNotPt_V4:
643 return Hexagon::STrih_indexed_shl_cNotPt_nv_V4;
645 case Hexagon::STrih_indexed_shl_cdnNotPt_V4:
646 return Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4;
648 case Hexagon::POST_SThri_cPt:
649 return Hexagon::POST_SThri_cPt_nv_V4;
651 case Hexagon::POST_SThri_cdnPt_V4:
652 return Hexagon::POST_SThri_cdnPt_nv_V4;
654 case Hexagon::POST_SThri_cNotPt:
655 return Hexagon::POST_SThri_cNotPt_nv_V4;
657 case Hexagon::POST_SThri_cdnNotPt_V4:
658 return Hexagon::POST_SThri_cdnNotPt_nv_V4;
660 case Hexagon::STh_GP_cPt_V4:
661 return Hexagon::STh_GP_cPt_nv_V4;
663 case Hexagon::STh_GP_cNotPt_V4:
664 return Hexagon::STh_GP_cNotPt_nv_V4;
666 case Hexagon::STh_GP_cdnPt_V4:
667 return Hexagon::STh_GP_cdnPt_nv_V4;
669 case Hexagon::STh_GP_cdnNotPt_V4:
670 return Hexagon::STh_GP_cdnNotPt_nv_V4;
672 case Hexagon::STrih_GP_cPt_V4:
673 return Hexagon::STrih_GP_cPt_nv_V4;
675 case Hexagon::STrih_GP_cNotPt_V4:
676 return Hexagon::STrih_GP_cNotPt_nv_V4;
678 case Hexagon::STrih_GP_cdnPt_V4:
679 return Hexagon::STrih_GP_cdnPt_nv_V4;
681 case Hexagon::STrih_GP_cdnNotPt_V4:
682 return Hexagon::STrih_GP_cdnNotPt_nv_V4;
684 // store new value word
686 return Hexagon::STriw_nv_V4;
688 case Hexagon::STriw_indexed:
689 return Hexagon::STriw_indexed_nv_V4;
691 case Hexagon::STriw_indexed_shl_V4:
692 return Hexagon::STriw_indexed_shl_nv_V4;
694 case Hexagon::STriw_shl_V4:
695 return Hexagon::STriw_shl_nv_V4;
697 case Hexagon::STriw_GP_V4:
698 return Hexagon::STriw_GP_nv_V4;
700 case Hexagon::STw_GP_V4:
701 return Hexagon::STw_GP_nv_V4;
703 case Hexagon::POST_STwri:
704 return Hexagon::POST_STwri_nv_V4;
706 case Hexagon::STriw_cPt:
707 return Hexagon::STriw_cPt_nv_V4;
709 case Hexagon::STriw_cdnPt_V4:
710 return Hexagon::STriw_cdnPt_nv_V4;
712 case Hexagon::STriw_cNotPt:
713 return Hexagon::STriw_cNotPt_nv_V4;
715 case Hexagon::STriw_cdnNotPt_V4:
716 return Hexagon::STriw_cdnNotPt_nv_V4;
718 case Hexagon::STriw_indexed_cPt:
719 return Hexagon::STriw_indexed_cPt_nv_V4;
721 case Hexagon::STriw_indexed_cdnPt_V4:
722 return Hexagon::STriw_indexed_cdnPt_nv_V4;
724 case Hexagon::STriw_indexed_cNotPt:
725 return Hexagon::STriw_indexed_cNotPt_nv_V4;
727 case Hexagon::STriw_indexed_cdnNotPt_V4:
728 return Hexagon::STriw_indexed_cdnNotPt_nv_V4;
730 case Hexagon::STriw_indexed_shl_cPt_V4:
731 return Hexagon::STriw_indexed_shl_cPt_nv_V4;
733 case Hexagon::STriw_indexed_shl_cdnPt_V4:
734 return Hexagon::STriw_indexed_shl_cdnPt_nv_V4;
736 case Hexagon::STriw_indexed_shl_cNotPt_V4:
737 return Hexagon::STriw_indexed_shl_cNotPt_nv_V4;
739 case Hexagon::STriw_indexed_shl_cdnNotPt_V4:
740 return Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4;
742 case Hexagon::POST_STwri_cPt:
743 return Hexagon::POST_STwri_cPt_nv_V4;
745 case Hexagon::POST_STwri_cdnPt_V4:
746 return Hexagon::POST_STwri_cdnPt_nv_V4;
748 case Hexagon::POST_STwri_cNotPt:
749 return Hexagon::POST_STwri_cNotPt_nv_V4;
751 case Hexagon::POST_STwri_cdnNotPt_V4:
752 return Hexagon::POST_STwri_cdnNotPt_nv_V4;
754 case Hexagon::STw_GP_cPt_V4:
755 return Hexagon::STw_GP_cPt_nv_V4;
757 case Hexagon::STw_GP_cNotPt_V4:
758 return Hexagon::STw_GP_cNotPt_nv_V4;
760 case Hexagon::STw_GP_cdnPt_V4:
761 return Hexagon::STw_GP_cdnPt_nv_V4;
763 case Hexagon::STw_GP_cdnNotPt_V4:
764 return Hexagon::STw_GP_cdnNotPt_nv_V4;
766 case Hexagon::STriw_GP_cPt_V4:
767 return Hexagon::STriw_GP_cPt_nv_V4;
769 case Hexagon::STriw_GP_cNotPt_V4:
770 return Hexagon::STriw_GP_cNotPt_nv_V4;
772 case Hexagon::STriw_GP_cdnPt_V4:
773 return Hexagon::STriw_GP_cdnPt_nv_V4;
775 case Hexagon::STriw_GP_cdnNotPt_V4:
776 return Hexagon::STriw_GP_cdnNotPt_nv_V4;
780 // Return .new predicate version for an instruction
781 static int GetDotNewPredOp(const int opc) {
783 default: llvm_unreachable("Unknown .new type");
784 // Conditional stores
785 // Store byte conditionally
786 case Hexagon::STrib_cPt :
787 return Hexagon::STrib_cdnPt_V4;
789 case Hexagon::STrib_cNotPt :
790 return Hexagon::STrib_cdnNotPt_V4;
792 case Hexagon::STrib_indexed_cPt :
793 return Hexagon::STrib_indexed_cdnPt_V4;
795 case Hexagon::STrib_indexed_cNotPt :
796 return Hexagon::STrib_indexed_cdnNotPt_V4;
798 case Hexagon::STrib_imm_cPt_V4 :
799 return Hexagon::STrib_imm_cdnPt_V4;
801 case Hexagon::STrib_imm_cNotPt_V4 :
802 return Hexagon::STrib_imm_cdnNotPt_V4;
804 case Hexagon::POST_STbri_cPt :
805 return Hexagon::POST_STbri_cdnPt_V4;
807 case Hexagon::POST_STbri_cNotPt :
808 return Hexagon::POST_STbri_cdnNotPt_V4;
810 case Hexagon::STrib_indexed_shl_cPt_V4 :
811 return Hexagon::STrib_indexed_shl_cdnPt_V4;
813 case Hexagon::STrib_indexed_shl_cNotPt_V4 :
814 return Hexagon::STrib_indexed_shl_cdnNotPt_V4;
816 case Hexagon::STb_GP_cPt_V4 :
817 return Hexagon::STb_GP_cdnPt_V4;
819 case Hexagon::STb_GP_cNotPt_V4 :
820 return Hexagon::STb_GP_cdnNotPt_V4;
822 case Hexagon::STrib_GP_cPt_V4 :
823 return Hexagon::STrib_GP_cdnPt_V4;
825 case Hexagon::STrib_GP_cNotPt_V4 :
826 return Hexagon::STrib_GP_cdnNotPt_V4;
828 // Store doubleword conditionally
829 case Hexagon::STrid_cPt :
830 return Hexagon::STrid_cdnPt_V4;
832 case Hexagon::STrid_cNotPt :
833 return Hexagon::STrid_cdnNotPt_V4;
835 case Hexagon::STrid_indexed_cPt :
836 return Hexagon::STrid_indexed_cdnPt_V4;
838 case Hexagon::STrid_indexed_cNotPt :
839 return Hexagon::STrid_indexed_cdnNotPt_V4;
841 case Hexagon::STrid_indexed_shl_cPt_V4 :
842 return Hexagon::STrid_indexed_shl_cdnPt_V4;
844 case Hexagon::STrid_indexed_shl_cNotPt_V4 :
845 return Hexagon::STrid_indexed_shl_cdnNotPt_V4;
847 case Hexagon::POST_STdri_cPt :
848 return Hexagon::POST_STdri_cdnPt_V4;
850 case Hexagon::POST_STdri_cNotPt :
851 return Hexagon::POST_STdri_cdnNotPt_V4;
853 case Hexagon::STd_GP_cPt_V4 :
854 return Hexagon::STd_GP_cdnPt_V4;
856 case Hexagon::STd_GP_cNotPt_V4 :
857 return Hexagon::STd_GP_cdnNotPt_V4;
859 case Hexagon::STrid_GP_cPt_V4 :
860 return Hexagon::STrid_GP_cdnPt_V4;
862 case Hexagon::STrid_GP_cNotPt_V4 :
863 return Hexagon::STrid_GP_cdnNotPt_V4;
865 // Store halfword conditionally
866 case Hexagon::STrih_cPt :
867 return Hexagon::STrih_cdnPt_V4;
869 case Hexagon::STrih_cNotPt :
870 return Hexagon::STrih_cdnNotPt_V4;
872 case Hexagon::STrih_indexed_cPt :
873 return Hexagon::STrih_indexed_cdnPt_V4;
875 case Hexagon::STrih_indexed_cNotPt :
876 return Hexagon::STrih_indexed_cdnNotPt_V4;
878 case Hexagon::STrih_imm_cPt_V4 :
879 return Hexagon::STrih_imm_cdnPt_V4;
881 case Hexagon::STrih_imm_cNotPt_V4 :
882 return Hexagon::STrih_imm_cdnNotPt_V4;
884 case Hexagon::STrih_indexed_shl_cPt_V4 :
885 return Hexagon::STrih_indexed_shl_cdnPt_V4;
887 case Hexagon::STrih_indexed_shl_cNotPt_V4 :
888 return Hexagon::STrih_indexed_shl_cdnNotPt_V4;
890 case Hexagon::POST_SThri_cPt :
891 return Hexagon::POST_SThri_cdnPt_V4;
893 case Hexagon::POST_SThri_cNotPt :
894 return Hexagon::POST_SThri_cdnNotPt_V4;
896 case Hexagon::STh_GP_cPt_V4 :
897 return Hexagon::STh_GP_cdnPt_V4;
899 case Hexagon::STh_GP_cNotPt_V4 :
900 return Hexagon::STh_GP_cdnNotPt_V4;
902 case Hexagon::STrih_GP_cPt_V4 :
903 return Hexagon::STrih_GP_cdnPt_V4;
905 case Hexagon::STrih_GP_cNotPt_V4 :
906 return Hexagon::STrih_GP_cdnNotPt_V4;
908 // Store word conditionally
909 case Hexagon::STriw_cPt :
910 return Hexagon::STriw_cdnPt_V4;
912 case Hexagon::STriw_cNotPt :
913 return Hexagon::STriw_cdnNotPt_V4;
915 case Hexagon::STriw_indexed_cPt :
916 return Hexagon::STriw_indexed_cdnPt_V4;
918 case Hexagon::STriw_indexed_cNotPt :
919 return Hexagon::STriw_indexed_cdnNotPt_V4;
921 case Hexagon::STriw_imm_cPt_V4 :
922 return Hexagon::STriw_imm_cdnPt_V4;
924 case Hexagon::STriw_imm_cNotPt_V4 :
925 return Hexagon::STriw_imm_cdnNotPt_V4;
927 case Hexagon::STriw_indexed_shl_cPt_V4 :
928 return Hexagon::STriw_indexed_shl_cdnPt_V4;
930 case Hexagon::STriw_indexed_shl_cNotPt_V4 :
931 return Hexagon::STriw_indexed_shl_cdnNotPt_V4;
933 case Hexagon::POST_STwri_cPt :
934 return Hexagon::POST_STwri_cdnPt_V4;
936 case Hexagon::POST_STwri_cNotPt :
937 return Hexagon::POST_STwri_cdnNotPt_V4;
939 case Hexagon::STw_GP_cPt_V4 :
940 return Hexagon::STw_GP_cdnPt_V4;
942 case Hexagon::STw_GP_cNotPt_V4 :
943 return Hexagon::STw_GP_cdnNotPt_V4;
945 case Hexagon::STriw_GP_cPt_V4 :
946 return Hexagon::STriw_GP_cdnPt_V4;
948 case Hexagon::STriw_GP_cNotPt_V4 :
949 return Hexagon::STriw_GP_cdnNotPt_V4;
953 return Hexagon::JMP_cdnPt;
955 case Hexagon::JMP_cNot:
956 return Hexagon::JMP_cdnNotPt;
958 case Hexagon::JMPR_cPt:
959 return Hexagon::JMPR_cdnPt_V3;
961 case Hexagon::JMPR_cNotPt:
962 return Hexagon::JMPR_cdnNotPt_V3;
964 // Conditional Transfers
965 case Hexagon::TFR_cPt:
966 return Hexagon::TFR_cdnPt;
968 case Hexagon::TFR_cNotPt:
969 return Hexagon::TFR_cdnNotPt;
971 case Hexagon::TFRI_cPt:
972 return Hexagon::TFRI_cdnPt;
974 case Hexagon::TFRI_cNotPt:
975 return Hexagon::TFRI_cdnNotPt;
978 case Hexagon::LDrid_cPt :
979 return Hexagon::LDrid_cdnPt;
981 case Hexagon::LDrid_cNotPt :
982 return Hexagon::LDrid_cdnNotPt;
984 case Hexagon::LDrid_indexed_cPt :
985 return Hexagon::LDrid_indexed_cdnPt;
987 case Hexagon::LDrid_indexed_cNotPt :
988 return Hexagon::LDrid_indexed_cdnNotPt;
990 case Hexagon::POST_LDrid_cPt :
991 return Hexagon::POST_LDrid_cdnPt_V4;
993 case Hexagon::POST_LDrid_cNotPt :
994 return Hexagon::POST_LDrid_cdnNotPt_V4;
997 case Hexagon::LDriw_cPt :
998 return Hexagon::LDriw_cdnPt;
1000 case Hexagon::LDriw_cNotPt :
1001 return Hexagon::LDriw_cdnNotPt;
1003 case Hexagon::LDriw_indexed_cPt :
1004 return Hexagon::LDriw_indexed_cdnPt;
1006 case Hexagon::LDriw_indexed_cNotPt :
1007 return Hexagon::LDriw_indexed_cdnNotPt;
1009 case Hexagon::POST_LDriw_cPt :
1010 return Hexagon::POST_LDriw_cdnPt_V4;
1012 case Hexagon::POST_LDriw_cNotPt :
1013 return Hexagon::POST_LDriw_cdnNotPt_V4;
1016 case Hexagon::LDrih_cPt :
1017 return Hexagon::LDrih_cdnPt;
1019 case Hexagon::LDrih_cNotPt :
1020 return Hexagon::LDrih_cdnNotPt;
1022 case Hexagon::LDrih_indexed_cPt :
1023 return Hexagon::LDrih_indexed_cdnPt;
1025 case Hexagon::LDrih_indexed_cNotPt :
1026 return Hexagon::LDrih_indexed_cdnNotPt;
1028 case Hexagon::POST_LDrih_cPt :
1029 return Hexagon::POST_LDrih_cdnPt_V4;
1031 case Hexagon::POST_LDrih_cNotPt :
1032 return Hexagon::POST_LDrih_cdnNotPt_V4;
1035 case Hexagon::LDrib_cPt :
1036 return Hexagon::LDrib_cdnPt;
1038 case Hexagon::LDrib_cNotPt :
1039 return Hexagon::LDrib_cdnNotPt;
1041 case Hexagon::LDrib_indexed_cPt :
1042 return Hexagon::LDrib_indexed_cdnPt;
1044 case Hexagon::LDrib_indexed_cNotPt :
1045 return Hexagon::LDrib_indexed_cdnNotPt;
1047 case Hexagon::POST_LDrib_cPt :
1048 return Hexagon::POST_LDrib_cdnPt_V4;
1050 case Hexagon::POST_LDrib_cNotPt :
1051 return Hexagon::POST_LDrib_cdnNotPt_V4;
1053 // Load unsigned halfword
1054 case Hexagon::LDriuh_cPt :
1055 return Hexagon::LDriuh_cdnPt;
1057 case Hexagon::LDriuh_cNotPt :
1058 return Hexagon::LDriuh_cdnNotPt;
1060 case Hexagon::LDriuh_indexed_cPt :
1061 return Hexagon::LDriuh_indexed_cdnPt;
1063 case Hexagon::LDriuh_indexed_cNotPt :
1064 return Hexagon::LDriuh_indexed_cdnNotPt;
1066 case Hexagon::POST_LDriuh_cPt :
1067 return Hexagon::POST_LDriuh_cdnPt_V4;
1069 case Hexagon::POST_LDriuh_cNotPt :
1070 return Hexagon::POST_LDriuh_cdnNotPt_V4;
1072 // Load unsigned byte
1073 case Hexagon::LDriub_cPt :
1074 return Hexagon::LDriub_cdnPt;
1076 case Hexagon::LDriub_cNotPt :
1077 return Hexagon::LDriub_cdnNotPt;
1079 case Hexagon::LDriub_indexed_cPt :
1080 return Hexagon::LDriub_indexed_cdnPt;
1082 case Hexagon::LDriub_indexed_cNotPt :
1083 return Hexagon::LDriub_indexed_cdnNotPt;
1085 case Hexagon::POST_LDriub_cPt :
1086 return Hexagon::POST_LDriub_cdnPt_V4;
1088 case Hexagon::POST_LDriub_cNotPt :
1089 return Hexagon::POST_LDriub_cdnNotPt_V4;
1091 // V4 indexed+scaled load
1093 case Hexagon::LDrid_indexed_cPt_V4 :
1094 return Hexagon::LDrid_indexed_cdnPt_V4;
1096 case Hexagon::LDrid_indexed_cNotPt_V4 :
1097 return Hexagon::LDrid_indexed_cdnNotPt_V4;
1099 case Hexagon::LDrid_indexed_shl_cPt_V4 :
1100 return Hexagon::LDrid_indexed_shl_cdnPt_V4;
1102 case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
1103 return Hexagon::LDrid_indexed_shl_cdnNotPt_V4;
1105 case Hexagon::LDrib_indexed_cPt_V4 :
1106 return Hexagon::LDrib_indexed_cdnPt_V4;
1108 case Hexagon::LDrib_indexed_cNotPt_V4 :
1109 return Hexagon::LDrib_indexed_cdnNotPt_V4;
1111 case Hexagon::LDrib_indexed_shl_cPt_V4 :
1112 return Hexagon::LDrib_indexed_shl_cdnPt_V4;
1114 case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
1115 return Hexagon::LDrib_indexed_shl_cdnNotPt_V4;
1117 case Hexagon::LDriub_indexed_cPt_V4 :
1118 return Hexagon::LDriub_indexed_cdnPt_V4;
1120 case Hexagon::LDriub_indexed_cNotPt_V4 :
1121 return Hexagon::LDriub_indexed_cdnNotPt_V4;
1123 case Hexagon::LDriub_indexed_shl_cPt_V4 :
1124 return Hexagon::LDriub_indexed_shl_cdnPt_V4;
1126 case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
1127 return Hexagon::LDriub_indexed_shl_cdnNotPt_V4;
1129 case Hexagon::LDrih_indexed_cPt_V4 :
1130 return Hexagon::LDrih_indexed_cdnPt_V4;
1132 case Hexagon::LDrih_indexed_cNotPt_V4 :
1133 return Hexagon::LDrih_indexed_cdnNotPt_V4;
1135 case Hexagon::LDrih_indexed_shl_cPt_V4 :
1136 return Hexagon::LDrih_indexed_shl_cdnPt_V4;
1138 case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
1139 return Hexagon::LDrih_indexed_shl_cdnNotPt_V4;
1141 case Hexagon::LDriuh_indexed_cPt_V4 :
1142 return Hexagon::LDriuh_indexed_cdnPt_V4;
1144 case Hexagon::LDriuh_indexed_cNotPt_V4 :
1145 return Hexagon::LDriuh_indexed_cdnNotPt_V4;
1147 case Hexagon::LDriuh_indexed_shl_cPt_V4 :
1148 return Hexagon::LDriuh_indexed_shl_cdnPt_V4;
1150 case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
1151 return Hexagon::LDriuh_indexed_shl_cdnNotPt_V4;
1153 case Hexagon::LDriw_indexed_cPt_V4 :
1154 return Hexagon::LDriw_indexed_cdnPt_V4;
1156 case Hexagon::LDriw_indexed_cNotPt_V4 :
1157 return Hexagon::LDriw_indexed_cdnNotPt_V4;
1159 case Hexagon::LDriw_indexed_shl_cPt_V4 :
1160 return Hexagon::LDriw_indexed_shl_cdnPt_V4;
1162 case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
1163 return Hexagon::LDriw_indexed_shl_cdnNotPt_V4;
1165 // V4 global address load
1167 case Hexagon::LDd_GP_cPt_V4:
1168 return Hexagon::LDd_GP_cdnPt_V4;
1170 case Hexagon::LDd_GP_cNotPt_V4:
1171 return Hexagon::LDd_GP_cdnNotPt_V4;
1173 case Hexagon::LDb_GP_cPt_V4:
1174 return Hexagon::LDb_GP_cdnPt_V4;
1176 case Hexagon::LDb_GP_cNotPt_V4:
1177 return Hexagon::LDb_GP_cdnNotPt_V4;
1179 case Hexagon::LDub_GP_cPt_V4:
1180 return Hexagon::LDub_GP_cdnPt_V4;
1182 case Hexagon::LDub_GP_cNotPt_V4:
1183 return Hexagon::LDub_GP_cdnNotPt_V4;
1185 case Hexagon::LDh_GP_cPt_V4:
1186 return Hexagon::LDh_GP_cdnPt_V4;
1188 case Hexagon::LDh_GP_cNotPt_V4:
1189 return Hexagon::LDh_GP_cdnNotPt_V4;
1191 case Hexagon::LDuh_GP_cPt_V4:
1192 return Hexagon::LDuh_GP_cdnPt_V4;
1194 case Hexagon::LDuh_GP_cNotPt_V4:
1195 return Hexagon::LDuh_GP_cdnNotPt_V4;
1197 case Hexagon::LDw_GP_cPt_V4:
1198 return Hexagon::LDw_GP_cdnPt_V4;
1200 case Hexagon::LDw_GP_cNotPt_V4:
1201 return Hexagon::LDw_GP_cdnNotPt_V4;
1203 case Hexagon::LDrid_GP_cPt_V4:
1204 return Hexagon::LDrid_GP_cdnPt_V4;
1206 case Hexagon::LDrid_GP_cNotPt_V4:
1207 return Hexagon::LDrid_GP_cdnNotPt_V4;
1209 case Hexagon::LDrib_GP_cPt_V4:
1210 return Hexagon::LDrib_GP_cdnPt_V4;
1212 case Hexagon::LDrib_GP_cNotPt_V4:
1213 return Hexagon::LDrib_GP_cdnNotPt_V4;
1215 case Hexagon::LDriub_GP_cPt_V4:
1216 return Hexagon::LDriub_GP_cdnPt_V4;
1218 case Hexagon::LDriub_GP_cNotPt_V4:
1219 return Hexagon::LDriub_GP_cdnNotPt_V4;
1221 case Hexagon::LDrih_GP_cPt_V4:
1222 return Hexagon::LDrih_GP_cdnPt_V4;
1224 case Hexagon::LDrih_GP_cNotPt_V4:
1225 return Hexagon::LDrih_GP_cdnNotPt_V4;
1227 case Hexagon::LDriuh_GP_cPt_V4:
1228 return Hexagon::LDriuh_GP_cdnPt_V4;
1230 case Hexagon::LDriuh_GP_cNotPt_V4:
1231 return Hexagon::LDriuh_GP_cdnNotPt_V4;
1233 case Hexagon::LDriw_GP_cPt_V4:
1234 return Hexagon::LDriw_GP_cdnPt_V4;
1236 case Hexagon::LDriw_GP_cNotPt_V4:
1237 return Hexagon::LDriw_GP_cdnNotPt_V4;
1239 // Conditional store new-value byte
1240 case Hexagon::STrib_cPt_nv_V4 :
1241 return Hexagon::STrib_cdnPt_nv_V4;
1242 case Hexagon::STrib_cNotPt_nv_V4 :
1243 return Hexagon::STrib_cdnNotPt_nv_V4;
1245 case Hexagon::STrib_indexed_cPt_nv_V4 :
1246 return Hexagon::STrib_indexed_cdnPt_nv_V4;
1247 case Hexagon::STrib_indexed_cNotPt_nv_V4 :
1248 return Hexagon::STrib_indexed_cdnNotPt_nv_V4;
1250 case Hexagon::STrib_indexed_shl_cPt_nv_V4 :
1251 return Hexagon::STrib_indexed_shl_cdnPt_nv_V4;
1252 case Hexagon::STrib_indexed_shl_cNotPt_nv_V4 :
1253 return Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4;
1255 case Hexagon::POST_STbri_cPt_nv_V4 :
1256 return Hexagon::POST_STbri_cdnPt_nv_V4;
1257 case Hexagon::POST_STbri_cNotPt_nv_V4 :
1258 return Hexagon::POST_STbri_cdnNotPt_nv_V4;
1260 case Hexagon::STb_GP_cPt_nv_V4 :
1261 return Hexagon::STb_GP_cdnPt_nv_V4;
1263 case Hexagon::STb_GP_cNotPt_nv_V4 :
1264 return Hexagon::STb_GP_cdnNotPt_nv_V4;
1266 case Hexagon::STrib_GP_cPt_nv_V4 :
1267 return Hexagon::STrib_GP_cdnPt_nv_V4;
1269 case Hexagon::STrib_GP_cNotPt_nv_V4 :
1270 return Hexagon::STrib_GP_cdnNotPt_nv_V4;
1272 // Conditional store new-value halfword
1273 case Hexagon::STrih_cPt_nv_V4 :
1274 return Hexagon::STrih_cdnPt_nv_V4;
1275 case Hexagon::STrih_cNotPt_nv_V4 :
1276 return Hexagon::STrih_cdnNotPt_nv_V4;
1278 case Hexagon::STrih_indexed_cPt_nv_V4 :
1279 return Hexagon::STrih_indexed_cdnPt_nv_V4;
1280 case Hexagon::STrih_indexed_cNotPt_nv_V4 :
1281 return Hexagon::STrih_indexed_cdnNotPt_nv_V4;
1283 case Hexagon::STrih_indexed_shl_cPt_nv_V4 :
1284 return Hexagon::STrih_indexed_shl_cdnPt_nv_V4;
1285 case Hexagon::STrih_indexed_shl_cNotPt_nv_V4 :
1286 return Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4;
1288 case Hexagon::POST_SThri_cPt_nv_V4 :
1289 return Hexagon::POST_SThri_cdnPt_nv_V4;
1290 case Hexagon::POST_SThri_cNotPt_nv_V4 :
1291 return Hexagon::POST_SThri_cdnNotPt_nv_V4;
1293 case Hexagon::STh_GP_cPt_nv_V4 :
1294 return Hexagon::STh_GP_cdnPt_nv_V4;
1296 case Hexagon::STh_GP_cNotPt_nv_V4 :
1297 return Hexagon::STh_GP_cdnNotPt_nv_V4;
1299 case Hexagon::STrih_GP_cPt_nv_V4 :
1300 return Hexagon::STrih_GP_cdnPt_nv_V4;
1302 case Hexagon::STrih_GP_cNotPt_nv_V4 :
1303 return Hexagon::STrih_GP_cdnNotPt_nv_V4;
1305 // Conditional store new-value word
1306 case Hexagon::STriw_cPt_nv_V4 :
1307 return Hexagon::STriw_cdnPt_nv_V4;
1308 case Hexagon::STriw_cNotPt_nv_V4 :
1309 return Hexagon::STriw_cdnNotPt_nv_V4;
1311 case Hexagon::STriw_indexed_cPt_nv_V4 :
1312 return Hexagon::STriw_indexed_cdnPt_nv_V4;
1313 case Hexagon::STriw_indexed_cNotPt_nv_V4 :
1314 return Hexagon::STriw_indexed_cdnNotPt_nv_V4;
1316 case Hexagon::STriw_indexed_shl_cPt_nv_V4 :
1317 return Hexagon::STriw_indexed_shl_cdnPt_nv_V4;
1318 case Hexagon::STriw_indexed_shl_cNotPt_nv_V4 :
1319 return Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4;
1321 case Hexagon::POST_STwri_cPt_nv_V4 :
1322 return Hexagon::POST_STwri_cdnPt_nv_V4;
1323 case Hexagon::POST_STwri_cNotPt_nv_V4:
1324 return Hexagon::POST_STwri_cdnNotPt_nv_V4;
1326 case Hexagon::STw_GP_cPt_nv_V4 :
1327 return Hexagon::STw_GP_cdnPt_nv_V4;
1329 case Hexagon::STw_GP_cNotPt_nv_V4 :
1330 return Hexagon::STw_GP_cdnNotPt_nv_V4;
1332 case Hexagon::STriw_GP_cPt_nv_V4 :
1333 return Hexagon::STriw_GP_cdnPt_nv_V4;
1335 case Hexagon::STriw_GP_cNotPt_nv_V4 :
1336 return Hexagon::STriw_GP_cdnNotPt_nv_V4;
1339 case Hexagon::ADD_ri_cPt :
1340 return Hexagon::ADD_ri_cdnPt;
1341 case Hexagon::ADD_ri_cNotPt :
1342 return Hexagon::ADD_ri_cdnNotPt;
1344 case Hexagon::ADD_rr_cPt :
1345 return Hexagon::ADD_rr_cdnPt;
1346 case Hexagon::ADD_rr_cNotPt :
1347 return Hexagon::ADD_rr_cdnNotPt;
1349 // Conditional logical Operations
1350 case Hexagon::XOR_rr_cPt :
1351 return Hexagon::XOR_rr_cdnPt;
1352 case Hexagon::XOR_rr_cNotPt :
1353 return Hexagon::XOR_rr_cdnNotPt;
1355 case Hexagon::AND_rr_cPt :
1356 return Hexagon::AND_rr_cdnPt;
1357 case Hexagon::AND_rr_cNotPt :
1358 return Hexagon::AND_rr_cdnNotPt;
1360 case Hexagon::OR_rr_cPt :
1361 return Hexagon::OR_rr_cdnPt;
1362 case Hexagon::OR_rr_cNotPt :
1363 return Hexagon::OR_rr_cdnNotPt;
1365 // Conditional Subtract
1366 case Hexagon::SUB_rr_cPt :
1367 return Hexagon::SUB_rr_cdnPt;
1368 case Hexagon::SUB_rr_cNotPt :
1369 return Hexagon::SUB_rr_cdnNotPt;
1371 // Conditional combine
1372 case Hexagon::COMBINE_rr_cPt :
1373 return Hexagon::COMBINE_rr_cdnPt;
1374 case Hexagon::COMBINE_rr_cNotPt :
1375 return Hexagon::COMBINE_rr_cdnNotPt;
1377 case Hexagon::ASLH_cPt_V4 :
1378 return Hexagon::ASLH_cdnPt_V4;
1379 case Hexagon::ASLH_cNotPt_V4 :
1380 return Hexagon::ASLH_cdnNotPt_V4;
1382 case Hexagon::ASRH_cPt_V4 :
1383 return Hexagon::ASRH_cdnPt_V4;
1384 case Hexagon::ASRH_cNotPt_V4 :
1385 return Hexagon::ASRH_cdnNotPt_V4;
1387 case Hexagon::SXTB_cPt_V4 :
1388 return Hexagon::SXTB_cdnPt_V4;
1389 case Hexagon::SXTB_cNotPt_V4 :
1390 return Hexagon::SXTB_cdnNotPt_V4;
1392 case Hexagon::SXTH_cPt_V4 :
1393 return Hexagon::SXTH_cdnPt_V4;
1394 case Hexagon::SXTH_cNotPt_V4 :
1395 return Hexagon::SXTH_cdnNotPt_V4;
1397 case Hexagon::ZXTB_cPt_V4 :
1398 return Hexagon::ZXTB_cdnPt_V4;
1399 case Hexagon::ZXTB_cNotPt_V4 :
1400 return Hexagon::ZXTB_cdnNotPt_V4;
1402 case Hexagon::ZXTH_cPt_V4 :
1403 return Hexagon::ZXTH_cdnPt_V4;
1404 case Hexagon::ZXTH_cNotPt_V4 :
1405 return Hexagon::ZXTH_cdnNotPt_V4;
1409 // Returns true if an instruction can be promoted to .new predicate
1410 // or new-value store.
1411 bool HexagonPacketizerList::isNewifiable(MachineInstr* MI) {
1412 if ( isCondInst(MI) || IsNewifyStore(MI))
1418 bool HexagonPacketizerList::isCondInst (MachineInstr* MI) {
1419 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1420 const MCInstrDesc& TID = MI->getDesc();
1421 // bug 5670: until that is fixed,
1422 // this portion is disabled.
1423 if ( TID.isConditionalBranch() // && !IsRegisterJump(MI)) ||
1424 || QII->isConditionalTransfer(MI)
1425 || QII->isConditionalALU32(MI)
1426 || QII->isConditionalLoad(MI)
1427 || QII->isConditionalStore(MI)) {
1434 // Promote an instructiont to its .new form.
1435 // At this time, we have already made a call to CanPromoteToDotNew
1436 // and made sure that it can *indeed* be promoted.
1437 bool HexagonPacketizerList::PromoteToDotNew(MachineInstr* MI,
1438 SDep::Kind DepType, MachineBasicBlock::iterator &MII,
1439 const TargetRegisterClass* RC) {
1441 assert (DepType == SDep::Data);
1442 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1445 if (RC == &Hexagon::PredRegsRegClass)
1446 NewOpcode = GetDotNewPredOp(MI->getOpcode());
1448 NewOpcode = GetDotNewOp(MI->getOpcode());
1449 MI->setDesc(QII->get(NewOpcode));
1454 // Returns the most basic instruction for the .new predicated instructions and
1455 // new-value stores.
1456 // For example, all of the following instructions will be converted back to the
1457 // same instruction:
1458 // 1) if (p0.new) memw(R0+#0) = R1.new --->
1459 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
1460 // 3) if (p0.new) memw(R0+#0) = R1 --->
1462 // To understand the translation of instruction 1 to its original form, consider
1463 // a packet with 3 instructions.
1464 // { p0 = cmp.eq(R0,R1)
1465 // if (p0.new) R2 = add(R3, R4)
1466 // R5 = add (R3, R1)
1468 // if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet
1470 // This instruction can be part of the previous packet only if both p0 and R2
1471 // are promoted to .new values. This promotion happens in steps, first
1472 // predicate register is promoted to .new and in the next iteration R2 is
1473 // promoted. Therefore, in case of dependence check failure (due to R5) during
1474 // next iteration, it should be converted back to its most basic form.
1476 static int GetDotOldOp(const int opc) {
1478 default: llvm_unreachable("Unknown .old type");
1479 case Hexagon::TFR_cdnPt:
1480 return Hexagon::TFR_cPt;
1482 case Hexagon::TFR_cdnNotPt:
1483 return Hexagon::TFR_cNotPt;
1485 case Hexagon::TFRI_cdnPt:
1486 return Hexagon::TFRI_cPt;
1488 case Hexagon::TFRI_cdnNotPt:
1489 return Hexagon::TFRI_cNotPt;
1491 case Hexagon::JMP_cdnPt:
1492 return Hexagon::JMP_c;
1494 case Hexagon::JMP_cdnNotPt:
1495 return Hexagon::JMP_cNot;
1497 case Hexagon::JMPR_cdnPt_V3:
1498 return Hexagon::JMPR_cPt;
1500 case Hexagon::JMPR_cdnNotPt_V3:
1501 return Hexagon::JMPR_cNotPt;
1505 case Hexagon::LDrid_cdnPt :
1506 return Hexagon::LDrid_cPt;
1508 case Hexagon::LDrid_cdnNotPt :
1509 return Hexagon::LDrid_cNotPt;
1511 case Hexagon::LDrid_indexed_cdnPt :
1512 return Hexagon::LDrid_indexed_cPt;
1514 case Hexagon::LDrid_indexed_cdnNotPt :
1515 return Hexagon::LDrid_indexed_cNotPt;
1517 case Hexagon::POST_LDrid_cdnPt_V4 :
1518 return Hexagon::POST_LDrid_cPt;
1520 case Hexagon::POST_LDrid_cdnNotPt_V4 :
1521 return Hexagon::POST_LDrid_cNotPt;
1525 case Hexagon::LDriw_cdnPt :
1526 return Hexagon::LDriw_cPt;
1528 case Hexagon::LDriw_cdnNotPt :
1529 return Hexagon::LDriw_cNotPt;
1531 case Hexagon::LDriw_indexed_cdnPt :
1532 return Hexagon::LDriw_indexed_cPt;
1534 case Hexagon::LDriw_indexed_cdnNotPt :
1535 return Hexagon::LDriw_indexed_cNotPt;
1537 case Hexagon::POST_LDriw_cdnPt_V4 :
1538 return Hexagon::POST_LDriw_cPt;
1540 case Hexagon::POST_LDriw_cdnNotPt_V4 :
1541 return Hexagon::POST_LDriw_cNotPt;
1545 case Hexagon::LDrih_cdnPt :
1546 return Hexagon::LDrih_cPt;
1548 case Hexagon::LDrih_cdnNotPt :
1549 return Hexagon::LDrih_cNotPt;
1551 case Hexagon::LDrih_indexed_cdnPt :
1552 return Hexagon::LDrih_indexed_cPt;
1554 case Hexagon::LDrih_indexed_cdnNotPt :
1555 return Hexagon::LDrih_indexed_cNotPt;
1557 case Hexagon::POST_LDrih_cdnPt_V4 :
1558 return Hexagon::POST_LDrih_cPt;
1560 case Hexagon::POST_LDrih_cdnNotPt_V4 :
1561 return Hexagon::POST_LDrih_cNotPt;
1565 case Hexagon::LDrib_cdnPt :
1566 return Hexagon::LDrib_cPt;
1568 case Hexagon::LDrib_cdnNotPt :
1569 return Hexagon::LDrib_cNotPt;
1571 case Hexagon::LDrib_indexed_cdnPt :
1572 return Hexagon::LDrib_indexed_cPt;
1574 case Hexagon::LDrib_indexed_cdnNotPt :
1575 return Hexagon::LDrib_indexed_cNotPt;
1577 case Hexagon::POST_LDrib_cdnPt_V4 :
1578 return Hexagon::POST_LDrib_cPt;
1580 case Hexagon::POST_LDrib_cdnNotPt_V4 :
1581 return Hexagon::POST_LDrib_cNotPt;
1583 // Load unsigned half
1585 case Hexagon::LDriuh_cdnPt :
1586 return Hexagon::LDriuh_cPt;
1588 case Hexagon::LDriuh_cdnNotPt :
1589 return Hexagon::LDriuh_cNotPt;
1591 case Hexagon::LDriuh_indexed_cdnPt :
1592 return Hexagon::LDriuh_indexed_cPt;
1594 case Hexagon::LDriuh_indexed_cdnNotPt :
1595 return Hexagon::LDriuh_indexed_cNotPt;
1597 case Hexagon::POST_LDriuh_cdnPt_V4 :
1598 return Hexagon::POST_LDriuh_cPt;
1600 case Hexagon::POST_LDriuh_cdnNotPt_V4 :
1601 return Hexagon::POST_LDriuh_cNotPt;
1603 // Load unsigned byte
1604 case Hexagon::LDriub_cdnPt :
1605 return Hexagon::LDriub_cPt;
1607 case Hexagon::LDriub_cdnNotPt :
1608 return Hexagon::LDriub_cNotPt;
1610 case Hexagon::LDriub_indexed_cdnPt :
1611 return Hexagon::LDriub_indexed_cPt;
1613 case Hexagon::LDriub_indexed_cdnNotPt :
1614 return Hexagon::LDriub_indexed_cNotPt;
1616 case Hexagon::POST_LDriub_cdnPt_V4 :
1617 return Hexagon::POST_LDriub_cPt;
1619 case Hexagon::POST_LDriub_cdnNotPt_V4 :
1620 return Hexagon::POST_LDriub_cNotPt;
1622 // V4 indexed+scaled Load
1624 case Hexagon::LDrid_indexed_cdnPt_V4 :
1625 return Hexagon::LDrid_indexed_cPt_V4;
1627 case Hexagon::LDrid_indexed_cdnNotPt_V4 :
1628 return Hexagon::LDrid_indexed_cNotPt_V4;
1630 case Hexagon::LDrid_indexed_shl_cdnPt_V4 :
1631 return Hexagon::LDrid_indexed_shl_cPt_V4;
1633 case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :
1634 return Hexagon::LDrid_indexed_shl_cNotPt_V4;
1636 case Hexagon::LDrib_indexed_cdnPt_V4 :
1637 return Hexagon::LDrib_indexed_cPt_V4;
1639 case Hexagon::LDrib_indexed_cdnNotPt_V4 :
1640 return Hexagon::LDrib_indexed_cNotPt_V4;
1642 case Hexagon::LDrib_indexed_shl_cdnPt_V4 :
1643 return Hexagon::LDrib_indexed_shl_cPt_V4;
1645 case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :
1646 return Hexagon::LDrib_indexed_shl_cNotPt_V4;
1648 case Hexagon::LDriub_indexed_cdnPt_V4 :
1649 return Hexagon::LDriub_indexed_cPt_V4;
1651 case Hexagon::LDriub_indexed_cdnNotPt_V4 :
1652 return Hexagon::LDriub_indexed_cNotPt_V4;
1654 case Hexagon::LDriub_indexed_shl_cdnPt_V4 :
1655 return Hexagon::LDriub_indexed_shl_cPt_V4;
1657 case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :
1658 return Hexagon::LDriub_indexed_shl_cNotPt_V4;
1660 case Hexagon::LDrih_indexed_cdnPt_V4 :
1661 return Hexagon::LDrih_indexed_cPt_V4;
1663 case Hexagon::LDrih_indexed_cdnNotPt_V4 :
1664 return Hexagon::LDrih_indexed_cNotPt_V4;
1666 case Hexagon::LDrih_indexed_shl_cdnPt_V4 :
1667 return Hexagon::LDrih_indexed_shl_cPt_V4;
1669 case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :
1670 return Hexagon::LDrih_indexed_shl_cNotPt_V4;
1672 case Hexagon::LDriuh_indexed_cdnPt_V4 :
1673 return Hexagon::LDriuh_indexed_cPt_V4;
1675 case Hexagon::LDriuh_indexed_cdnNotPt_V4 :
1676 return Hexagon::LDriuh_indexed_cNotPt_V4;
1678 case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :
1679 return Hexagon::LDriuh_indexed_shl_cPt_V4;
1681 case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :
1682 return Hexagon::LDriuh_indexed_shl_cNotPt_V4;
1684 case Hexagon::LDriw_indexed_cdnPt_V4 :
1685 return Hexagon::LDriw_indexed_cPt_V4;
1687 case Hexagon::LDriw_indexed_cdnNotPt_V4 :
1688 return Hexagon::LDriw_indexed_cNotPt_V4;
1690 case Hexagon::LDriw_indexed_shl_cdnPt_V4 :
1691 return Hexagon::LDriw_indexed_shl_cPt_V4;
1693 case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :
1694 return Hexagon::LDriw_indexed_shl_cNotPt_V4;
1696 // V4 global address load
1698 case Hexagon::LDd_GP_cdnPt_V4:
1699 return Hexagon::LDd_GP_cPt_V4;
1701 case Hexagon::LDd_GP_cdnNotPt_V4:
1702 return Hexagon::LDd_GP_cNotPt_V4;
1704 case Hexagon::LDb_GP_cdnPt_V4:
1705 return Hexagon::LDb_GP_cPt_V4;
1707 case Hexagon::LDb_GP_cdnNotPt_V4:
1708 return Hexagon::LDb_GP_cNotPt_V4;
1710 case Hexagon::LDub_GP_cdnPt_V4:
1711 return Hexagon::LDub_GP_cPt_V4;
1713 case Hexagon::LDub_GP_cdnNotPt_V4:
1714 return Hexagon::LDub_GP_cNotPt_V4;
1716 case Hexagon::LDh_GP_cdnPt_V4:
1717 return Hexagon::LDh_GP_cPt_V4;
1719 case Hexagon::LDh_GP_cdnNotPt_V4:
1720 return Hexagon::LDh_GP_cNotPt_V4;
1722 case Hexagon::LDuh_GP_cdnPt_V4:
1723 return Hexagon::LDuh_GP_cPt_V4;
1725 case Hexagon::LDuh_GP_cdnNotPt_V4:
1726 return Hexagon::LDuh_GP_cNotPt_V4;
1728 case Hexagon::LDw_GP_cdnPt_V4:
1729 return Hexagon::LDw_GP_cPt_V4;
1731 case Hexagon::LDw_GP_cdnNotPt_V4:
1732 return Hexagon::LDw_GP_cNotPt_V4;
1734 case Hexagon::LDrid_GP_cdnPt_V4:
1735 return Hexagon::LDrid_GP_cPt_V4;
1737 case Hexagon::LDrid_GP_cdnNotPt_V4:
1738 return Hexagon::LDrid_GP_cNotPt_V4;
1740 case Hexagon::LDrib_GP_cdnPt_V4:
1741 return Hexagon::LDrib_GP_cPt_V4;
1743 case Hexagon::LDrib_GP_cdnNotPt_V4:
1744 return Hexagon::LDrib_GP_cNotPt_V4;
1746 case Hexagon::LDriub_GP_cdnPt_V4:
1747 return Hexagon::LDriub_GP_cPt_V4;
1749 case Hexagon::LDriub_GP_cdnNotPt_V4:
1750 return Hexagon::LDriub_GP_cNotPt_V4;
1752 case Hexagon::LDrih_GP_cdnPt_V4:
1753 return Hexagon::LDrih_GP_cPt_V4;
1755 case Hexagon::LDrih_GP_cdnNotPt_V4:
1756 return Hexagon::LDrih_GP_cNotPt_V4;
1758 case Hexagon::LDriuh_GP_cdnPt_V4:
1759 return Hexagon::LDriuh_GP_cPt_V4;
1761 case Hexagon::LDriuh_GP_cdnNotPt_V4:
1762 return Hexagon::LDriuh_GP_cNotPt_V4;
1764 case Hexagon::LDriw_GP_cdnPt_V4:
1765 return Hexagon::LDriw_GP_cPt_V4;
1767 case Hexagon::LDriw_GP_cdnNotPt_V4:
1768 return Hexagon::LDriw_GP_cNotPt_V4;
1772 case Hexagon::ADD_ri_cdnPt :
1773 return Hexagon::ADD_ri_cPt;
1774 case Hexagon::ADD_ri_cdnNotPt :
1775 return Hexagon::ADD_ri_cNotPt;
1777 case Hexagon::ADD_rr_cdnPt :
1778 return Hexagon::ADD_rr_cPt;
1779 case Hexagon::ADD_rr_cdnNotPt:
1780 return Hexagon::ADD_rr_cNotPt;
1782 // Conditional logical Operations
1784 case Hexagon::XOR_rr_cdnPt :
1785 return Hexagon::XOR_rr_cPt;
1786 case Hexagon::XOR_rr_cdnNotPt :
1787 return Hexagon::XOR_rr_cNotPt;
1789 case Hexagon::AND_rr_cdnPt :
1790 return Hexagon::AND_rr_cPt;
1791 case Hexagon::AND_rr_cdnNotPt :
1792 return Hexagon::AND_rr_cNotPt;
1794 case Hexagon::OR_rr_cdnPt :
1795 return Hexagon::OR_rr_cPt;
1796 case Hexagon::OR_rr_cdnNotPt :
1797 return Hexagon::OR_rr_cNotPt;
1799 // Conditional Subtract
1801 case Hexagon::SUB_rr_cdnPt :
1802 return Hexagon::SUB_rr_cPt;
1803 case Hexagon::SUB_rr_cdnNotPt :
1804 return Hexagon::SUB_rr_cNotPt;
1806 // Conditional combine
1808 case Hexagon::COMBINE_rr_cdnPt :
1809 return Hexagon::COMBINE_rr_cPt;
1810 case Hexagon::COMBINE_rr_cdnNotPt :
1811 return Hexagon::COMBINE_rr_cNotPt;
1813 // Conditional shift operations
1815 case Hexagon::ASLH_cdnPt_V4 :
1816 return Hexagon::ASLH_cPt_V4;
1817 case Hexagon::ASLH_cdnNotPt_V4 :
1818 return Hexagon::ASLH_cNotPt_V4;
1820 case Hexagon::ASRH_cdnPt_V4 :
1821 return Hexagon::ASRH_cPt_V4;
1822 case Hexagon::ASRH_cdnNotPt_V4 :
1823 return Hexagon::ASRH_cNotPt_V4;
1825 case Hexagon::SXTB_cdnPt_V4 :
1826 return Hexagon::SXTB_cPt_V4;
1827 case Hexagon::SXTB_cdnNotPt_V4 :
1828 return Hexagon::SXTB_cNotPt_V4;
1830 case Hexagon::SXTH_cdnPt_V4 :
1831 return Hexagon::SXTH_cPt_V4;
1832 case Hexagon::SXTH_cdnNotPt_V4 :
1833 return Hexagon::SXTH_cNotPt_V4;
1835 case Hexagon::ZXTB_cdnPt_V4 :
1836 return Hexagon::ZXTB_cPt_V4;
1837 case Hexagon::ZXTB_cdnNotPt_V4 :
1838 return Hexagon::ZXTB_cNotPt_V4;
1840 case Hexagon::ZXTH_cdnPt_V4 :
1841 return Hexagon::ZXTH_cPt_V4;
1842 case Hexagon::ZXTH_cdnNotPt_V4 :
1843 return Hexagon::ZXTH_cNotPt_V4;
1847 case Hexagon::STrib_imm_cdnPt_V4 :
1848 return Hexagon::STrib_imm_cPt_V4;
1850 case Hexagon::STrib_imm_cdnNotPt_V4 :
1851 return Hexagon::STrib_imm_cNotPt_V4;
1853 case Hexagon::STrib_cdnPt_nv_V4 :
1854 case Hexagon::STrib_cPt_nv_V4 :
1855 case Hexagon::STrib_cdnPt_V4 :
1856 return Hexagon::STrib_cPt;
1858 case Hexagon::STrib_cdnNotPt_nv_V4 :
1859 case Hexagon::STrib_cNotPt_nv_V4 :
1860 case Hexagon::STrib_cdnNotPt_V4 :
1861 return Hexagon::STrib_cNotPt;
1863 case Hexagon::STrib_indexed_cdnPt_V4 :
1864 case Hexagon::STrib_indexed_cPt_nv_V4 :
1865 case Hexagon::STrib_indexed_cdnPt_nv_V4 :
1866 return Hexagon::STrib_indexed_cPt;
1868 case Hexagon::STrib_indexed_cdnNotPt_V4 :
1869 case Hexagon::STrib_indexed_cNotPt_nv_V4 :
1870 case Hexagon::STrib_indexed_cdnNotPt_nv_V4 :
1871 return Hexagon::STrib_indexed_cNotPt;
1873 case Hexagon::STrib_indexed_shl_cdnPt_nv_V4:
1874 case Hexagon::STrib_indexed_shl_cPt_nv_V4 :
1875 case Hexagon::STrib_indexed_shl_cdnPt_V4 :
1876 return Hexagon::STrib_indexed_shl_cPt_V4;
1878 case Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4:
1879 case Hexagon::STrib_indexed_shl_cNotPt_nv_V4 :
1880 case Hexagon::STrib_indexed_shl_cdnNotPt_V4 :
1881 return Hexagon::STrib_indexed_shl_cNotPt_V4;
1883 case Hexagon::POST_STbri_cdnPt_nv_V4 :
1884 case Hexagon::POST_STbri_cPt_nv_V4 :
1885 case Hexagon::POST_STbri_cdnPt_V4 :
1886 return Hexagon::POST_STbri_cPt;
1888 case Hexagon::POST_STbri_cdnNotPt_nv_V4 :
1889 case Hexagon::POST_STbri_cNotPt_nv_V4:
1890 case Hexagon::POST_STbri_cdnNotPt_V4 :
1891 return Hexagon::POST_STbri_cNotPt;
1893 case Hexagon::STb_GP_cdnPt_nv_V4:
1894 case Hexagon::STb_GP_cdnPt_V4:
1895 case Hexagon::STb_GP_cPt_nv_V4:
1896 return Hexagon::STb_GP_cPt_V4;
1898 case Hexagon::STb_GP_cdnNotPt_nv_V4:
1899 case Hexagon::STb_GP_cdnNotPt_V4:
1900 case Hexagon::STb_GP_cNotPt_nv_V4:
1901 return Hexagon::STb_GP_cNotPt_V4;
1903 case Hexagon::STrib_GP_cdnPt_nv_V4:
1904 case Hexagon::STrib_GP_cdnPt_V4:
1905 case Hexagon::STrib_GP_cPt_nv_V4:
1906 return Hexagon::STrib_GP_cPt_V4;
1908 case Hexagon::STrib_GP_cdnNotPt_nv_V4:
1909 case Hexagon::STrib_GP_cdnNotPt_V4:
1910 case Hexagon::STrib_GP_cNotPt_nv_V4:
1911 return Hexagon::STrib_GP_cNotPt_V4;
1913 // Store new-value byte - unconditional
1914 case Hexagon::STrib_nv_V4:
1915 return Hexagon::STrib;
1917 case Hexagon::STrib_indexed_nv_V4:
1918 return Hexagon::STrib_indexed;
1920 case Hexagon::STrib_indexed_shl_nv_V4:
1921 return Hexagon::STrib_indexed_shl_V4;
1923 case Hexagon::STrib_shl_nv_V4:
1924 return Hexagon::STrib_shl_V4;
1926 case Hexagon::STrib_GP_nv_V4:
1927 return Hexagon::STrib_GP_V4;
1929 case Hexagon::STb_GP_nv_V4:
1930 return Hexagon::STb_GP_V4;
1932 case Hexagon::POST_STbri_nv_V4:
1933 return Hexagon::POST_STbri;
1936 case Hexagon::STrih_imm_cdnPt_V4 :
1937 return Hexagon::STrih_imm_cPt_V4;
1939 case Hexagon::STrih_imm_cdnNotPt_V4 :
1940 return Hexagon::STrih_imm_cNotPt_V4;
1942 case Hexagon::STrih_cdnPt_nv_V4 :
1943 case Hexagon::STrih_cPt_nv_V4 :
1944 case Hexagon::STrih_cdnPt_V4 :
1945 return Hexagon::STrih_cPt;
1947 case Hexagon::STrih_cdnNotPt_nv_V4 :
1948 case Hexagon::STrih_cNotPt_nv_V4 :
1949 case Hexagon::STrih_cdnNotPt_V4 :
1950 return Hexagon::STrih_cNotPt;
1952 case Hexagon::STrih_indexed_cdnPt_nv_V4:
1953 case Hexagon::STrih_indexed_cPt_nv_V4 :
1954 case Hexagon::STrih_indexed_cdnPt_V4 :
1955 return Hexagon::STrih_indexed_cPt;
1957 case Hexagon::STrih_indexed_cdnNotPt_nv_V4:
1958 case Hexagon::STrih_indexed_cNotPt_nv_V4 :
1959 case Hexagon::STrih_indexed_cdnNotPt_V4 :
1960 return Hexagon::STrih_indexed_cNotPt;
1962 case Hexagon::STrih_indexed_shl_cdnPt_nv_V4 :
1963 case Hexagon::STrih_indexed_shl_cPt_nv_V4 :
1964 case Hexagon::STrih_indexed_shl_cdnPt_V4 :
1965 return Hexagon::STrih_indexed_shl_cPt_V4;
1967 case Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4 :
1968 case Hexagon::STrih_indexed_shl_cNotPt_nv_V4 :
1969 case Hexagon::STrih_indexed_shl_cdnNotPt_V4 :
1970 return Hexagon::STrih_indexed_shl_cNotPt_V4;
1972 case Hexagon::POST_SThri_cdnPt_nv_V4 :
1973 case Hexagon::POST_SThri_cPt_nv_V4 :
1974 case Hexagon::POST_SThri_cdnPt_V4 :
1975 return Hexagon::POST_SThri_cPt;
1977 case Hexagon::POST_SThri_cdnNotPt_nv_V4 :
1978 case Hexagon::POST_SThri_cNotPt_nv_V4 :
1979 case Hexagon::POST_SThri_cdnNotPt_V4 :
1980 return Hexagon::POST_SThri_cNotPt;
1982 case Hexagon::STh_GP_cdnPt_nv_V4:
1983 case Hexagon::STh_GP_cdnPt_V4:
1984 case Hexagon::STh_GP_cPt_nv_V4:
1985 return Hexagon::STh_GP_cPt_V4;
1987 case Hexagon::STh_GP_cdnNotPt_nv_V4:
1988 case Hexagon::STh_GP_cdnNotPt_V4:
1989 case Hexagon::STh_GP_cNotPt_nv_V4:
1990 return Hexagon::STh_GP_cNotPt_V4;
1992 case Hexagon::STrih_GP_cdnPt_nv_V4:
1993 case Hexagon::STrih_GP_cdnPt_V4:
1994 case Hexagon::STrih_GP_cPt_nv_V4:
1995 return Hexagon::STrih_GP_cPt_V4;
1997 case Hexagon::STrih_GP_cdnNotPt_nv_V4:
1998 case Hexagon::STrih_GP_cdnNotPt_V4:
1999 case Hexagon::STrih_GP_cNotPt_nv_V4:
2000 return Hexagon::STrih_GP_cNotPt_V4;
2002 // Store new-value halfword - unconditional
2004 case Hexagon::STrih_nv_V4:
2005 return Hexagon::STrih;
2007 case Hexagon::STrih_indexed_nv_V4:
2008 return Hexagon::STrih_indexed;
2010 case Hexagon::STrih_indexed_shl_nv_V4:
2011 return Hexagon::STrih_indexed_shl_V4;
2013 case Hexagon::STrih_shl_nv_V4:
2014 return Hexagon::STrih_shl_V4;
2016 case Hexagon::STrih_GP_nv_V4:
2017 return Hexagon::STrih_GP_V4;
2019 case Hexagon::STh_GP_nv_V4:
2020 return Hexagon::STh_GP_V4;
2022 case Hexagon::POST_SThri_nv_V4:
2023 return Hexagon::POST_SThri;
2027 case Hexagon::STriw_imm_cdnPt_V4 :
2028 return Hexagon::STriw_imm_cPt_V4;
2030 case Hexagon::STriw_imm_cdnNotPt_V4 :
2031 return Hexagon::STriw_imm_cNotPt_V4;
2033 case Hexagon::STriw_cdnPt_nv_V4 :
2034 case Hexagon::STriw_cPt_nv_V4 :
2035 case Hexagon::STriw_cdnPt_V4 :
2036 return Hexagon::STriw_cPt;
2038 case Hexagon::STriw_cdnNotPt_nv_V4 :
2039 case Hexagon::STriw_cNotPt_nv_V4 :
2040 case Hexagon::STriw_cdnNotPt_V4 :
2041 return Hexagon::STriw_cNotPt;
2043 case Hexagon::STriw_indexed_cdnPt_nv_V4 :
2044 case Hexagon::STriw_indexed_cPt_nv_V4 :
2045 case Hexagon::STriw_indexed_cdnPt_V4 :
2046 return Hexagon::STriw_indexed_cPt;
2048 case Hexagon::STriw_indexed_cdnNotPt_nv_V4 :
2049 case Hexagon::STriw_indexed_cNotPt_nv_V4 :
2050 case Hexagon::STriw_indexed_cdnNotPt_V4 :
2051 return Hexagon::STriw_indexed_cNotPt;
2053 case Hexagon::STriw_indexed_shl_cdnPt_nv_V4 :
2054 case Hexagon::STriw_indexed_shl_cPt_nv_V4 :
2055 case Hexagon::STriw_indexed_shl_cdnPt_V4 :
2056 return Hexagon::STriw_indexed_shl_cPt_V4;
2058 case Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4 :
2059 case Hexagon::STriw_indexed_shl_cNotPt_nv_V4 :
2060 case Hexagon::STriw_indexed_shl_cdnNotPt_V4 :
2061 return Hexagon::STriw_indexed_shl_cNotPt_V4;
2063 case Hexagon::POST_STwri_cdnPt_nv_V4 :
2064 case Hexagon::POST_STwri_cPt_nv_V4 :
2065 case Hexagon::POST_STwri_cdnPt_V4 :
2066 return Hexagon::POST_STwri_cPt;
2068 case Hexagon::POST_STwri_cdnNotPt_nv_V4 :
2069 case Hexagon::POST_STwri_cNotPt_nv_V4 :
2070 case Hexagon::POST_STwri_cdnNotPt_V4 :
2071 return Hexagon::POST_STwri_cNotPt;
2073 case Hexagon::STw_GP_cdnPt_nv_V4:
2074 case Hexagon::STw_GP_cdnPt_V4:
2075 case Hexagon::STw_GP_cPt_nv_V4:
2076 return Hexagon::STw_GP_cPt_V4;
2078 case Hexagon::STw_GP_cdnNotPt_nv_V4:
2079 case Hexagon::STw_GP_cdnNotPt_V4:
2080 case Hexagon::STw_GP_cNotPt_nv_V4:
2081 return Hexagon::STw_GP_cNotPt_V4;
2083 case Hexagon::STriw_GP_cdnPt_nv_V4:
2084 case Hexagon::STriw_GP_cdnPt_V4:
2085 case Hexagon::STriw_GP_cPt_nv_V4:
2086 return Hexagon::STriw_GP_cPt_V4;
2088 case Hexagon::STriw_GP_cdnNotPt_nv_V4:
2089 case Hexagon::STriw_GP_cdnNotPt_V4:
2090 case Hexagon::STriw_GP_cNotPt_nv_V4:
2091 return Hexagon::STriw_GP_cNotPt_V4;
2093 // Store new-value word - unconditional
2095 case Hexagon::STriw_nv_V4:
2096 return Hexagon::STriw;
2098 case Hexagon::STriw_indexed_nv_V4:
2099 return Hexagon::STriw_indexed;
2101 case Hexagon::STriw_indexed_shl_nv_V4:
2102 return Hexagon::STriw_indexed_shl_V4;
2104 case Hexagon::STriw_shl_nv_V4:
2105 return Hexagon::STriw_shl_V4;
2107 case Hexagon::STriw_GP_nv_V4:
2108 return Hexagon::STriw_GP_V4;
2110 case Hexagon::STw_GP_nv_V4:
2111 return Hexagon::STw_GP_V4;
2113 case Hexagon::POST_STwri_nv_V4:
2114 return Hexagon::POST_STwri;
2118 case Hexagon::STrid_cdnPt_V4 :
2119 return Hexagon::STrid_cPt;
2121 case Hexagon::STrid_cdnNotPt_V4 :
2122 return Hexagon::STrid_cNotPt;
2124 case Hexagon::STrid_indexed_cdnPt_V4 :
2125 return Hexagon::STrid_indexed_cPt;
2127 case Hexagon::STrid_indexed_cdnNotPt_V4 :
2128 return Hexagon::STrid_indexed_cNotPt;
2130 case Hexagon::STrid_indexed_shl_cdnPt_V4 :
2131 return Hexagon::STrid_indexed_shl_cPt_V4;
2133 case Hexagon::STrid_indexed_shl_cdnNotPt_V4 :
2134 return Hexagon::STrid_indexed_shl_cNotPt_V4;
2136 case Hexagon::POST_STdri_cdnPt_V4 :
2137 return Hexagon::POST_STdri_cPt;
2139 case Hexagon::POST_STdri_cdnNotPt_V4 :
2140 return Hexagon::POST_STdri_cNotPt;
2142 case Hexagon::STd_GP_cdnPt_V4 :
2143 return Hexagon::STd_GP_cPt_V4;
2145 case Hexagon::STd_GP_cdnNotPt_V4 :
2146 return Hexagon::STd_GP_cNotPt_V4;
2148 case Hexagon::STrid_GP_cdnPt_V4 :
2149 return Hexagon::STrid_GP_cPt_V4;
2151 case Hexagon::STrid_GP_cdnNotPt_V4 :
2152 return Hexagon::STrid_GP_cNotPt_V4;
2156 bool HexagonPacketizerList::DemoteToDotOld(MachineInstr* MI) {
2157 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
2158 int NewOpcode = GetDotOldOp(MI->getOpcode());
2159 MI->setDesc(QII->get(NewOpcode));
2163 // Returns true if an instruction is predicated on p0 and false if it's
2164 // predicated on !p0.
2166 static bool GetPredicateSense(MachineInstr* MI,
2167 const HexagonInstrInfo *QII) {
2169 switch (MI->getOpcode()) {
2170 default: llvm_unreachable("Unknown predicate sense of the instruction");
2171 case Hexagon::TFR_cPt:
2172 case Hexagon::TFR_cdnPt:
2173 case Hexagon::TFRI_cPt:
2174 case Hexagon::TFRI_cdnPt:
2175 case Hexagon::STrib_cPt :
2176 case Hexagon::STrib_cdnPt_V4 :
2177 case Hexagon::STrib_indexed_cPt :
2178 case Hexagon::STrib_indexed_cdnPt_V4 :
2179 case Hexagon::STrib_indexed_shl_cPt_V4 :
2180 case Hexagon::STrib_indexed_shl_cdnPt_V4 :
2181 case Hexagon::POST_STbri_cPt :
2182 case Hexagon::POST_STbri_cdnPt_V4 :
2183 case Hexagon::STrih_cPt :
2184 case Hexagon::STrih_cdnPt_V4 :
2185 case Hexagon::STrih_indexed_cPt :
2186 case Hexagon::STrih_indexed_cdnPt_V4 :
2187 case Hexagon::STrih_indexed_shl_cPt_V4 :
2188 case Hexagon::STrih_indexed_shl_cdnPt_V4 :
2189 case Hexagon::POST_SThri_cPt :
2190 case Hexagon::POST_SThri_cdnPt_V4 :
2191 case Hexagon::STriw_cPt :
2192 case Hexagon::STriw_cdnPt_V4 :
2193 case Hexagon::STriw_indexed_cPt :
2194 case Hexagon::STriw_indexed_cdnPt_V4 :
2195 case Hexagon::STriw_indexed_shl_cPt_V4 :
2196 case Hexagon::STriw_indexed_shl_cdnPt_V4 :
2197 case Hexagon::POST_STwri_cPt :
2198 case Hexagon::POST_STwri_cdnPt_V4 :
2199 case Hexagon::STrib_imm_cPt_V4 :
2200 case Hexagon::STrib_imm_cdnPt_V4 :
2201 case Hexagon::STrid_cPt :
2202 case Hexagon::STrid_cdnPt_V4 :
2203 case Hexagon::STrid_indexed_cPt :
2204 case Hexagon::STrid_indexed_cdnPt_V4 :
2205 case Hexagon::STrid_indexed_shl_cPt_V4 :
2206 case Hexagon::STrid_indexed_shl_cdnPt_V4 :
2207 case Hexagon::POST_STdri_cPt :
2208 case Hexagon::POST_STdri_cdnPt_V4 :
2209 case Hexagon::STrih_imm_cPt_V4 :
2210 case Hexagon::STrih_imm_cdnPt_V4 :
2211 case Hexagon::STriw_imm_cPt_V4 :
2212 case Hexagon::STriw_imm_cdnPt_V4 :
2213 case Hexagon::JMP_cdnPt :
2214 case Hexagon::LDrid_cPt :
2215 case Hexagon::LDrid_cdnPt :
2216 case Hexagon::LDrid_indexed_cPt :
2217 case Hexagon::LDrid_indexed_cdnPt :
2218 case Hexagon::POST_LDrid_cPt :
2219 case Hexagon::POST_LDrid_cdnPt_V4 :
2220 case Hexagon::LDriw_cPt :
2221 case Hexagon::LDriw_cdnPt :
2222 case Hexagon::LDriw_indexed_cPt :
2223 case Hexagon::LDriw_indexed_cdnPt :
2224 case Hexagon::POST_LDriw_cPt :
2225 case Hexagon::POST_LDriw_cdnPt_V4 :
2226 case Hexagon::LDrih_cPt :
2227 case Hexagon::LDrih_cdnPt :
2228 case Hexagon::LDrih_indexed_cPt :
2229 case Hexagon::LDrih_indexed_cdnPt :
2230 case Hexagon::POST_LDrih_cPt :
2231 case Hexagon::POST_LDrih_cdnPt_V4 :
2232 case Hexagon::LDrib_cPt :
2233 case Hexagon::LDrib_cdnPt :
2234 case Hexagon::LDrib_indexed_cPt :
2235 case Hexagon::LDrib_indexed_cdnPt :
2236 case Hexagon::POST_LDrib_cPt :
2237 case Hexagon::POST_LDrib_cdnPt_V4 :
2238 case Hexagon::LDriuh_cPt :
2239 case Hexagon::LDriuh_cdnPt :
2240 case Hexagon::LDriuh_indexed_cPt :
2241 case Hexagon::LDriuh_indexed_cdnPt :
2242 case Hexagon::POST_LDriuh_cPt :
2243 case Hexagon::POST_LDriuh_cdnPt_V4 :
2244 case Hexagon::LDriub_cPt :
2245 case Hexagon::LDriub_cdnPt :
2246 case Hexagon::LDriub_indexed_cPt :
2247 case Hexagon::LDriub_indexed_cdnPt :
2248 case Hexagon::POST_LDriub_cPt :
2249 case Hexagon::POST_LDriub_cdnPt_V4 :
2250 case Hexagon::LDrid_indexed_cPt_V4 :
2251 case Hexagon::LDrid_indexed_cdnPt_V4 :
2252 case Hexagon::LDrid_indexed_shl_cPt_V4 :
2253 case Hexagon::LDrid_indexed_shl_cdnPt_V4 :
2254 case Hexagon::LDrib_indexed_cPt_V4 :
2255 case Hexagon::LDrib_indexed_cdnPt_V4 :
2256 case Hexagon::LDrib_indexed_shl_cPt_V4 :
2257 case Hexagon::LDrib_indexed_shl_cdnPt_V4 :
2258 case Hexagon::LDriub_indexed_cPt_V4 :
2259 case Hexagon::LDriub_indexed_cdnPt_V4 :
2260 case Hexagon::LDriub_indexed_shl_cPt_V4 :
2261 case Hexagon::LDriub_indexed_shl_cdnPt_V4 :
2262 case Hexagon::LDrih_indexed_cPt_V4 :
2263 case Hexagon::LDrih_indexed_cdnPt_V4 :
2264 case Hexagon::LDrih_indexed_shl_cPt_V4 :
2265 case Hexagon::LDrih_indexed_shl_cdnPt_V4 :
2266 case Hexagon::LDriuh_indexed_cPt_V4 :
2267 case Hexagon::LDriuh_indexed_cdnPt_V4 :
2268 case Hexagon::LDriuh_indexed_shl_cPt_V4 :
2269 case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :
2270 case Hexagon::LDriw_indexed_cPt_V4 :
2271 case Hexagon::LDriw_indexed_cdnPt_V4 :
2272 case Hexagon::LDriw_indexed_shl_cPt_V4 :
2273 case Hexagon::LDriw_indexed_shl_cdnPt_V4 :
2274 case Hexagon::ADD_ri_cPt :
2275 case Hexagon::ADD_ri_cdnPt :
2276 case Hexagon::ADD_rr_cPt :
2277 case Hexagon::ADD_rr_cdnPt :
2278 case Hexagon::XOR_rr_cPt :
2279 case Hexagon::XOR_rr_cdnPt :
2280 case Hexagon::AND_rr_cPt :
2281 case Hexagon::AND_rr_cdnPt :
2282 case Hexagon::OR_rr_cPt :
2283 case Hexagon::OR_rr_cdnPt :
2284 case Hexagon::SUB_rr_cPt :
2285 case Hexagon::SUB_rr_cdnPt :
2286 case Hexagon::COMBINE_rr_cPt :
2287 case Hexagon::COMBINE_rr_cdnPt :
2288 case Hexagon::ASLH_cPt_V4 :
2289 case Hexagon::ASLH_cdnPt_V4 :
2290 case Hexagon::ASRH_cPt_V4 :
2291 case Hexagon::ASRH_cdnPt_V4 :
2292 case Hexagon::SXTB_cPt_V4 :
2293 case Hexagon::SXTB_cdnPt_V4 :
2294 case Hexagon::SXTH_cPt_V4 :
2295 case Hexagon::SXTH_cdnPt_V4 :
2296 case Hexagon::ZXTB_cPt_V4 :
2297 case Hexagon::ZXTB_cdnPt_V4 :
2298 case Hexagon::ZXTH_cPt_V4 :
2299 case Hexagon::ZXTH_cdnPt_V4 :
2300 case Hexagon::LDrid_GP_cPt_V4 :
2301 case Hexagon::LDrib_GP_cPt_V4 :
2302 case Hexagon::LDriub_GP_cPt_V4 :
2303 case Hexagon::LDrih_GP_cPt_V4 :
2304 case Hexagon::LDriuh_GP_cPt_V4 :
2305 case Hexagon::LDriw_GP_cPt_V4 :
2306 case Hexagon::LDd_GP_cPt_V4 :
2307 case Hexagon::LDb_GP_cPt_V4 :
2308 case Hexagon::LDub_GP_cPt_V4 :
2309 case Hexagon::LDh_GP_cPt_V4 :
2310 case Hexagon::LDuh_GP_cPt_V4 :
2311 case Hexagon::LDw_GP_cPt_V4 :
2312 case Hexagon::STrid_GP_cPt_V4 :
2313 case Hexagon::STrib_GP_cPt_V4 :
2314 case Hexagon::STrih_GP_cPt_V4 :
2315 case Hexagon::STriw_GP_cPt_V4 :
2316 case Hexagon::STd_GP_cPt_V4 :
2317 case Hexagon::STb_GP_cPt_V4 :
2318 case Hexagon::STh_GP_cPt_V4 :
2319 case Hexagon::STw_GP_cPt_V4 :
2320 case Hexagon::LDrid_GP_cdnPt_V4 :
2321 case Hexagon::LDrib_GP_cdnPt_V4 :
2322 case Hexagon::LDriub_GP_cdnPt_V4 :
2323 case Hexagon::LDrih_GP_cdnPt_V4 :
2324 case Hexagon::LDriuh_GP_cdnPt_V4 :
2325 case Hexagon::LDriw_GP_cdnPt_V4 :
2326 case Hexagon::LDd_GP_cdnPt_V4 :
2327 case Hexagon::LDb_GP_cdnPt_V4 :
2328 case Hexagon::LDub_GP_cdnPt_V4 :
2329 case Hexagon::LDh_GP_cdnPt_V4 :
2330 case Hexagon::LDuh_GP_cdnPt_V4 :
2331 case Hexagon::LDw_GP_cdnPt_V4 :
2332 case Hexagon::STrid_GP_cdnPt_V4 :
2333 case Hexagon::STrib_GP_cdnPt_V4 :
2334 case Hexagon::STrih_GP_cdnPt_V4 :
2335 case Hexagon::STriw_GP_cdnPt_V4 :
2336 case Hexagon::STd_GP_cdnPt_V4 :
2337 case Hexagon::STb_GP_cdnPt_V4 :
2338 case Hexagon::STh_GP_cdnPt_V4 :
2339 case Hexagon::STw_GP_cdnPt_V4 :
2342 case Hexagon::TFR_cNotPt:
2343 case Hexagon::TFR_cdnNotPt:
2344 case Hexagon::TFRI_cNotPt:
2345 case Hexagon::TFRI_cdnNotPt:
2346 case Hexagon::STrib_cNotPt :
2347 case Hexagon::STrib_cdnNotPt_V4 :
2348 case Hexagon::STrib_indexed_cNotPt :
2349 case Hexagon::STrib_indexed_cdnNotPt_V4 :
2350 case Hexagon::STrib_indexed_shl_cNotPt_V4 :
2351 case Hexagon::STrib_indexed_shl_cdnNotPt_V4 :
2352 case Hexagon::POST_STbri_cNotPt :
2353 case Hexagon::POST_STbri_cdnNotPt_V4 :
2354 case Hexagon::STrih_cNotPt :
2355 case Hexagon::STrih_cdnNotPt_V4 :
2356 case Hexagon::STrih_indexed_cNotPt :
2357 case Hexagon::STrih_indexed_cdnNotPt_V4 :
2358 case Hexagon::STrih_indexed_shl_cNotPt_V4 :
2359 case Hexagon::STrih_indexed_shl_cdnNotPt_V4 :
2360 case Hexagon::POST_SThri_cNotPt :
2361 case Hexagon::POST_SThri_cdnNotPt_V4 :
2362 case Hexagon::STriw_cNotPt :
2363 case Hexagon::STriw_cdnNotPt_V4 :
2364 case Hexagon::STriw_indexed_cNotPt :
2365 case Hexagon::STriw_indexed_cdnNotPt_V4 :
2366 case Hexagon::STriw_indexed_shl_cNotPt_V4 :
2367 case Hexagon::STriw_indexed_shl_cdnNotPt_V4 :
2368 case Hexagon::POST_STwri_cNotPt :
2369 case Hexagon::POST_STwri_cdnNotPt_V4 :
2370 case Hexagon::STrib_imm_cNotPt_V4 :
2371 case Hexagon::STrib_imm_cdnNotPt_V4 :
2372 case Hexagon::STrid_cNotPt :
2373 case Hexagon::STrid_cdnNotPt_V4 :
2374 case Hexagon::STrid_indexed_cdnNotPt_V4 :
2375 case Hexagon::STrid_indexed_cNotPt :
2376 case Hexagon::STrid_indexed_shl_cNotPt_V4 :
2377 case Hexagon::STrid_indexed_shl_cdnNotPt_V4 :
2378 case Hexagon::POST_STdri_cNotPt :
2379 case Hexagon::POST_STdri_cdnNotPt_V4 :
2380 case Hexagon::STrih_imm_cNotPt_V4 :
2381 case Hexagon::STrih_imm_cdnNotPt_V4 :
2382 case Hexagon::STriw_imm_cNotPt_V4 :
2383 case Hexagon::STriw_imm_cdnNotPt_V4 :
2384 case Hexagon::JMP_cdnNotPt :
2385 case Hexagon::LDrid_cNotPt :
2386 case Hexagon::LDrid_cdnNotPt :
2387 case Hexagon::LDrid_indexed_cNotPt :
2388 case Hexagon::LDrid_indexed_cdnNotPt :
2389 case Hexagon::POST_LDrid_cNotPt :
2390 case Hexagon::POST_LDrid_cdnNotPt_V4 :
2391 case Hexagon::LDriw_cNotPt :
2392 case Hexagon::LDriw_cdnNotPt :
2393 case Hexagon::LDriw_indexed_cNotPt :
2394 case Hexagon::LDriw_indexed_cdnNotPt :
2395 case Hexagon::POST_LDriw_cNotPt :
2396 case Hexagon::POST_LDriw_cdnNotPt_V4 :
2397 case Hexagon::LDrih_cNotPt :
2398 case Hexagon::LDrih_cdnNotPt :
2399 case Hexagon::LDrih_indexed_cNotPt :
2400 case Hexagon::LDrih_indexed_cdnNotPt :
2401 case Hexagon::POST_LDrih_cNotPt :
2402 case Hexagon::POST_LDrih_cdnNotPt_V4 :
2403 case Hexagon::LDrib_cNotPt :
2404 case Hexagon::LDrib_cdnNotPt :
2405 case Hexagon::LDrib_indexed_cNotPt :
2406 case Hexagon::LDrib_indexed_cdnNotPt :
2407 case Hexagon::POST_LDrib_cNotPt :
2408 case Hexagon::POST_LDrib_cdnNotPt_V4 :
2409 case Hexagon::LDriuh_cNotPt :
2410 case Hexagon::LDriuh_cdnNotPt :
2411 case Hexagon::LDriuh_indexed_cNotPt :
2412 case Hexagon::LDriuh_indexed_cdnNotPt :
2413 case Hexagon::POST_LDriuh_cNotPt :
2414 case Hexagon::POST_LDriuh_cdnNotPt_V4 :
2415 case Hexagon::LDriub_cNotPt :
2416 case Hexagon::LDriub_cdnNotPt :
2417 case Hexagon::LDriub_indexed_cNotPt :
2418 case Hexagon::LDriub_indexed_cdnNotPt :
2419 case Hexagon::POST_LDriub_cNotPt :
2420 case Hexagon::POST_LDriub_cdnNotPt_V4 :
2421 case Hexagon::LDrid_indexed_cNotPt_V4 :
2422 case Hexagon::LDrid_indexed_cdnNotPt_V4 :
2423 case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
2424 case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :
2425 case Hexagon::LDrib_indexed_cNotPt_V4 :
2426 case Hexagon::LDrib_indexed_cdnNotPt_V4 :
2427 case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
2428 case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :
2429 case Hexagon::LDriub_indexed_cNotPt_V4 :
2430 case Hexagon::LDriub_indexed_cdnNotPt_V4 :
2431 case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
2432 case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :
2433 case Hexagon::LDrih_indexed_cNotPt_V4 :
2434 case Hexagon::LDrih_indexed_cdnNotPt_V4 :
2435 case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
2436 case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :
2437 case Hexagon::LDriuh_indexed_cNotPt_V4 :
2438 case Hexagon::LDriuh_indexed_cdnNotPt_V4 :
2439 case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
2440 case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :
2441 case Hexagon::LDriw_indexed_cNotPt_V4 :
2442 case Hexagon::LDriw_indexed_cdnNotPt_V4 :
2443 case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
2444 case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :
2445 case Hexagon::ADD_ri_cNotPt :
2446 case Hexagon::ADD_ri_cdnNotPt :
2447 case Hexagon::ADD_rr_cNotPt :
2448 case Hexagon::ADD_rr_cdnNotPt :
2449 case Hexagon::XOR_rr_cNotPt :
2450 case Hexagon::XOR_rr_cdnNotPt :
2451 case Hexagon::AND_rr_cNotPt :
2452 case Hexagon::AND_rr_cdnNotPt :
2453 case Hexagon::OR_rr_cNotPt :
2454 case Hexagon::OR_rr_cdnNotPt :
2455 case Hexagon::SUB_rr_cNotPt :
2456 case Hexagon::SUB_rr_cdnNotPt :
2457 case Hexagon::COMBINE_rr_cNotPt :
2458 case Hexagon::COMBINE_rr_cdnNotPt :
2459 case Hexagon::ASLH_cNotPt_V4 :
2460 case Hexagon::ASLH_cdnNotPt_V4 :
2461 case Hexagon::ASRH_cNotPt_V4 :
2462 case Hexagon::ASRH_cdnNotPt_V4 :
2463 case Hexagon::SXTB_cNotPt_V4 :
2464 case Hexagon::SXTB_cdnNotPt_V4 :
2465 case Hexagon::SXTH_cNotPt_V4 :
2466 case Hexagon::SXTH_cdnNotPt_V4 :
2467 case Hexagon::ZXTB_cNotPt_V4 :
2468 case Hexagon::ZXTB_cdnNotPt_V4 :
2469 case Hexagon::ZXTH_cNotPt_V4 :
2470 case Hexagon::ZXTH_cdnNotPt_V4 :
2472 case Hexagon::LDrid_GP_cNotPt_V4 :
2473 case Hexagon::LDrib_GP_cNotPt_V4 :
2474 case Hexagon::LDriub_GP_cNotPt_V4 :
2475 case Hexagon::LDrih_GP_cNotPt_V4 :
2476 case Hexagon::LDriuh_GP_cNotPt_V4 :
2477 case Hexagon::LDriw_GP_cNotPt_V4 :
2478 case Hexagon::LDd_GP_cNotPt_V4 :
2479 case Hexagon::LDb_GP_cNotPt_V4 :
2480 case Hexagon::LDub_GP_cNotPt_V4 :
2481 case Hexagon::LDh_GP_cNotPt_V4 :
2482 case Hexagon::LDuh_GP_cNotPt_V4 :
2483 case Hexagon::LDw_GP_cNotPt_V4 :
2484 case Hexagon::STrid_GP_cNotPt_V4 :
2485 case Hexagon::STrib_GP_cNotPt_V4 :
2486 case Hexagon::STrih_GP_cNotPt_V4 :
2487 case Hexagon::STriw_GP_cNotPt_V4 :
2488 case Hexagon::STd_GP_cNotPt_V4 :
2489 case Hexagon::STb_GP_cNotPt_V4 :
2490 case Hexagon::STh_GP_cNotPt_V4 :
2491 case Hexagon::STw_GP_cNotPt_V4 :
2492 case Hexagon::LDrid_GP_cdnNotPt_V4 :
2493 case Hexagon::LDrib_GP_cdnNotPt_V4 :
2494 case Hexagon::LDriub_GP_cdnNotPt_V4 :
2495 case Hexagon::LDrih_GP_cdnNotPt_V4 :
2496 case Hexagon::LDriuh_GP_cdnNotPt_V4 :
2497 case Hexagon::LDriw_GP_cdnNotPt_V4 :
2498 case Hexagon::LDd_GP_cdnNotPt_V4 :
2499 case Hexagon::LDb_GP_cdnNotPt_V4 :
2500 case Hexagon::LDub_GP_cdnNotPt_V4 :
2501 case Hexagon::LDh_GP_cdnNotPt_V4 :
2502 case Hexagon::LDuh_GP_cdnNotPt_V4 :
2503 case Hexagon::LDw_GP_cdnNotPt_V4 :
2504 case Hexagon::STrid_GP_cdnNotPt_V4 :
2505 case Hexagon::STrib_GP_cdnNotPt_V4 :
2506 case Hexagon::STrih_GP_cdnNotPt_V4 :
2507 case Hexagon::STriw_GP_cdnNotPt_V4 :
2508 case Hexagon::STd_GP_cdnNotPt_V4 :
2509 case Hexagon::STb_GP_cdnNotPt_V4 :
2510 case Hexagon::STh_GP_cdnNotPt_V4 :
2511 case Hexagon::STw_GP_cdnNotPt_V4 :
2514 // return *some value* to avoid compiler warning
2518 bool HexagonPacketizerList::isDotNewInst(MachineInstr* MI) {
2519 if (isNewValueInst(MI))
2522 switch (MI->getOpcode()) {
2523 case Hexagon::TFR_cdnNotPt:
2524 case Hexagon::TFR_cdnPt:
2525 case Hexagon::TFRI_cdnNotPt:
2526 case Hexagon::TFRI_cdnPt:
2527 case Hexagon::LDrid_cdnPt :
2528 case Hexagon::LDrid_cdnNotPt :
2529 case Hexagon::LDrid_indexed_cdnPt :
2530 case Hexagon::LDrid_indexed_cdnNotPt :
2531 case Hexagon::POST_LDrid_cdnPt_V4 :
2532 case Hexagon::POST_LDrid_cdnNotPt_V4 :
2533 case Hexagon::LDriw_cdnPt :
2534 case Hexagon::LDriw_cdnNotPt :
2535 case Hexagon::LDriw_indexed_cdnPt :
2536 case Hexagon::LDriw_indexed_cdnNotPt :
2537 case Hexagon::POST_LDriw_cdnPt_V4 :
2538 case Hexagon::POST_LDriw_cdnNotPt_V4 :
2539 case Hexagon::LDrih_cdnPt :
2540 case Hexagon::LDrih_cdnNotPt :
2541 case Hexagon::LDrih_indexed_cdnPt :
2542 case Hexagon::LDrih_indexed_cdnNotPt :
2543 case Hexagon::POST_LDrih_cdnPt_V4 :
2544 case Hexagon::POST_LDrih_cdnNotPt_V4 :
2545 case Hexagon::LDrib_cdnPt :
2546 case Hexagon::LDrib_cdnNotPt :
2547 case Hexagon::LDrib_indexed_cdnPt :
2548 case Hexagon::LDrib_indexed_cdnNotPt :
2549 case Hexagon::POST_LDrib_cdnPt_V4 :
2550 case Hexagon::POST_LDrib_cdnNotPt_V4 :
2551 case Hexagon::LDriuh_cdnPt :
2552 case Hexagon::LDriuh_cdnNotPt :
2553 case Hexagon::LDriuh_indexed_cdnPt :
2554 case Hexagon::LDriuh_indexed_cdnNotPt :
2555 case Hexagon::POST_LDriuh_cdnPt_V4 :
2556 case Hexagon::POST_LDriuh_cdnNotPt_V4 :
2557 case Hexagon::LDriub_cdnPt :
2558 case Hexagon::LDriub_cdnNotPt :
2559 case Hexagon::LDriub_indexed_cdnPt :
2560 case Hexagon::LDriub_indexed_cdnNotPt :
2561 case Hexagon::POST_LDriub_cdnPt_V4 :
2562 case Hexagon::POST_LDriub_cdnNotPt_V4 :
2564 case Hexagon::LDrid_indexed_cdnPt_V4 :
2565 case Hexagon::LDrid_indexed_cdnNotPt_V4 :
2566 case Hexagon::LDrid_indexed_shl_cdnPt_V4 :
2567 case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :
2568 case Hexagon::LDrib_indexed_cdnPt_V4 :
2569 case Hexagon::LDrib_indexed_cdnNotPt_V4 :
2570 case Hexagon::LDrib_indexed_shl_cdnPt_V4 :
2571 case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :
2572 case Hexagon::LDriub_indexed_cdnPt_V4 :
2573 case Hexagon::LDriub_indexed_cdnNotPt_V4 :
2574 case Hexagon::LDriub_indexed_shl_cdnPt_V4 :
2575 case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :
2576 case Hexagon::LDrih_indexed_cdnPt_V4 :
2577 case Hexagon::LDrih_indexed_cdnNotPt_V4 :
2578 case Hexagon::LDrih_indexed_shl_cdnPt_V4 :
2579 case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :
2580 case Hexagon::LDriuh_indexed_cdnPt_V4 :
2581 case Hexagon::LDriuh_indexed_cdnNotPt_V4 :
2582 case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :
2583 case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :
2584 case Hexagon::LDriw_indexed_cdnPt_V4 :
2585 case Hexagon::LDriw_indexed_cdnNotPt_V4 :
2586 case Hexagon::LDriw_indexed_shl_cdnPt_V4 :
2587 case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :
2590 case Hexagon::ADD_ri_cdnPt:
2591 case Hexagon::ADD_ri_cdnNotPt:
2592 case Hexagon::ADD_rr_cdnPt:
2593 case Hexagon::ADD_rr_cdnNotPt:
2595 // Conditional logical operations
2596 case Hexagon::XOR_rr_cdnPt :
2597 case Hexagon::XOR_rr_cdnNotPt :
2598 case Hexagon::AND_rr_cdnPt :
2599 case Hexagon::AND_rr_cdnNotPt :
2600 case Hexagon::OR_rr_cdnPt :
2601 case Hexagon::OR_rr_cdnNotPt :
2603 // Conditonal subtract
2604 case Hexagon::SUB_rr_cdnPt :
2605 case Hexagon::SUB_rr_cdnNotPt :
2607 // Conditional combine
2608 case Hexagon::COMBINE_rr_cdnPt :
2609 case Hexagon::COMBINE_rr_cdnNotPt :
2611 // Conditional shift operations
2612 case Hexagon::ASLH_cdnPt_V4:
2613 case Hexagon::ASLH_cdnNotPt_V4:
2614 case Hexagon::ASRH_cdnPt_V4:
2615 case Hexagon::ASRH_cdnNotPt_V4:
2616 case Hexagon::SXTB_cdnPt_V4:
2617 case Hexagon::SXTB_cdnNotPt_V4:
2618 case Hexagon::SXTH_cdnPt_V4:
2619 case Hexagon::SXTH_cdnNotPt_V4:
2620 case Hexagon::ZXTB_cdnPt_V4:
2621 case Hexagon::ZXTB_cdnNotPt_V4:
2622 case Hexagon::ZXTH_cdnPt_V4:
2623 case Hexagon::ZXTH_cdnNotPt_V4:
2625 // Conditional stores
2626 case Hexagon::STrib_imm_cdnPt_V4 :
2627 case Hexagon::STrib_imm_cdnNotPt_V4 :
2628 case Hexagon::STrib_cdnPt_V4 :
2629 case Hexagon::STrib_cdnNotPt_V4 :
2630 case Hexagon::STrib_indexed_cdnPt_V4 :
2631 case Hexagon::STrib_indexed_cdnNotPt_V4 :
2632 case Hexagon::POST_STbri_cdnPt_V4 :
2633 case Hexagon::POST_STbri_cdnNotPt_V4 :
2634 case Hexagon::STrib_indexed_shl_cdnPt_V4 :
2635 case Hexagon::STrib_indexed_shl_cdnNotPt_V4 :
2637 // Store doubleword conditionally
2638 case Hexagon::STrid_indexed_cdnPt_V4 :
2639 case Hexagon::STrid_indexed_cdnNotPt_V4 :
2640 case Hexagon::STrid_indexed_shl_cdnPt_V4 :
2641 case Hexagon::STrid_indexed_shl_cdnNotPt_V4 :
2642 case Hexagon::POST_STdri_cdnPt_V4 :
2643 case Hexagon::POST_STdri_cdnNotPt_V4 :
2645 // Store halfword conditionally
2646 case Hexagon::STrih_cdnPt_V4 :
2647 case Hexagon::STrih_cdnNotPt_V4 :
2648 case Hexagon::STrih_indexed_cdnPt_V4 :
2649 case Hexagon::STrih_indexed_cdnNotPt_V4 :
2650 case Hexagon::STrih_imm_cdnPt_V4 :
2651 case Hexagon::STrih_imm_cdnNotPt_V4 :
2652 case Hexagon::STrih_indexed_shl_cdnPt_V4 :
2653 case Hexagon::STrih_indexed_shl_cdnNotPt_V4 :
2654 case Hexagon::POST_SThri_cdnPt_V4 :
2655 case Hexagon::POST_SThri_cdnNotPt_V4 :
2657 // Store word conditionally
2658 case Hexagon::STriw_cdnPt_V4 :
2659 case Hexagon::STriw_cdnNotPt_V4 :
2660 case Hexagon::STriw_indexed_cdnPt_V4 :
2661 case Hexagon::STriw_indexed_cdnNotPt_V4 :
2662 case Hexagon::STriw_imm_cdnPt_V4 :
2663 case Hexagon::STriw_imm_cdnNotPt_V4 :
2664 case Hexagon::STriw_indexed_shl_cdnPt_V4 :
2665 case Hexagon::STriw_indexed_shl_cdnNotPt_V4 :
2666 case Hexagon::POST_STwri_cdnPt_V4 :
2667 case Hexagon::POST_STwri_cdnNotPt_V4 :
2669 case Hexagon::LDd_GP_cdnPt_V4:
2670 case Hexagon::LDd_GP_cdnNotPt_V4:
2671 case Hexagon::LDb_GP_cdnPt_V4:
2672 case Hexagon::LDb_GP_cdnNotPt_V4:
2673 case Hexagon::LDub_GP_cdnPt_V4:
2674 case Hexagon::LDub_GP_cdnNotPt_V4:
2675 case Hexagon::LDh_GP_cdnPt_V4:
2676 case Hexagon::LDh_GP_cdnNotPt_V4:
2677 case Hexagon::LDuh_GP_cdnPt_V4:
2678 case Hexagon::LDuh_GP_cdnNotPt_V4:
2679 case Hexagon::LDw_GP_cdnPt_V4:
2680 case Hexagon::LDw_GP_cdnNotPt_V4:
2681 case Hexagon::LDrid_GP_cdnPt_V4:
2682 case Hexagon::LDrid_GP_cdnNotPt_V4:
2683 case Hexagon::LDrib_GP_cdnPt_V4:
2684 case Hexagon::LDrib_GP_cdnNotPt_V4:
2685 case Hexagon::LDriub_GP_cdnPt_V4:
2686 case Hexagon::LDriub_GP_cdnNotPt_V4:
2687 case Hexagon::LDrih_GP_cdnPt_V4:
2688 case Hexagon::LDrih_GP_cdnNotPt_V4:
2689 case Hexagon::LDriuh_GP_cdnPt_V4:
2690 case Hexagon::LDriuh_GP_cdnNotPt_V4:
2691 case Hexagon::LDriw_GP_cdnPt_V4:
2692 case Hexagon::LDriw_GP_cdnNotPt_V4:
2694 case Hexagon::STrid_GP_cdnPt_V4:
2695 case Hexagon::STrid_GP_cdnNotPt_V4:
2696 case Hexagon::STrib_GP_cdnPt_V4:
2697 case Hexagon::STrib_GP_cdnNotPt_V4:
2698 case Hexagon::STrih_GP_cdnPt_V4:
2699 case Hexagon::STrih_GP_cdnNotPt_V4:
2700 case Hexagon::STriw_GP_cdnPt_V4:
2701 case Hexagon::STriw_GP_cdnNotPt_V4:
2702 case Hexagon::STd_GP_cdnPt_V4:
2703 case Hexagon::STd_GP_cdnNotPt_V4:
2704 case Hexagon::STb_GP_cdnPt_V4:
2705 case Hexagon::STb_GP_cdnNotPt_V4:
2706 case Hexagon::STh_GP_cdnPt_V4:
2707 case Hexagon::STh_GP_cdnNotPt_V4:
2708 case Hexagon::STw_GP_cdnPt_V4:
2709 case Hexagon::STw_GP_cdnNotPt_V4:
2715 static MachineOperand& GetPostIncrementOperand(MachineInstr *MI,
2716 const HexagonInstrInfo *QII) {
2717 assert(QII->isPostIncrement(MI) && "Not a post increment operation.");
2719 // Post Increment means duplicates. Use dense map to find duplicates in the
2720 // list. Caution: Densemap initializes with the minimum of 64 buckets,
2721 // whereas there are at most 5 operands in the post increment.
2722 DenseMap<unsigned, unsigned> DefRegsSet;
2723 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++)
2724 if (MI->getOperand(opNum).isReg() &&
2725 MI->getOperand(opNum).isDef()) {
2726 DefRegsSet[MI->getOperand(opNum).getReg()] = 1;
2729 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++)
2730 if (MI->getOperand(opNum).isReg() &&
2731 MI->getOperand(opNum).isUse()) {
2732 if (DefRegsSet[MI->getOperand(opNum).getReg()]) {
2733 return MI->getOperand(opNum);
2737 if (MI->getDesc().mayLoad()) {
2738 // The 2nd operand is always the post increment operand in load.
2739 assert(MI->getOperand(1).isReg() &&
2740 "Post increment operand has be to a register.");
2741 return (MI->getOperand(1));
2743 if (MI->getDesc().mayStore()) {
2744 // The 1st operand is always the post increment operand in store.
2745 assert(MI->getOperand(0).isReg() &&
2746 "Post increment operand has be to a register.");
2747 return (MI->getOperand(0));
2750 // we should never come here.
2751 llvm_unreachable("mayLoad or mayStore not set for Post Increment operation");
2754 // get the value being stored
2755 static MachineOperand& GetStoreValueOperand(MachineInstr *MI) {
2756 // value being stored is always the last operand.
2757 return (MI->getOperand(MI->getNumOperands()-1));
2760 // can be new value store?
2761 // Following restrictions are to be respected in convert a store into
2762 // a new value store.
2763 // 1. If an instruction uses auto-increment, its address register cannot
2764 // be a new-value register. Arch Spec 5.4.2.1
2765 // 2. If an instruction uses absolute-set addressing mode,
2766 // its address register cannot be a new-value register.
2767 // Arch Spec 5.4.2.1.TODO: This is not enabled as
2768 // as absolute-set address mode patters are not implemented.
2769 // 3. If an instruction produces a 64-bit result, its registers cannot be used
2770 // as new-value registers. Arch Spec 5.4.2.2.
2771 // 4. If the instruction that sets a new-value register is conditional, then
2772 // the instruction that uses the new-value register must also be conditional,
2773 // and both must always have their predicates evaluate identically.
2774 // Arch Spec 5.4.2.3.
2775 // 5. There is an implied restriction of a packet can not have another store,
2776 // if there is a new value store in the packet. Corollary, if there is
2777 // already a store in a packet, there can not be a new value store.
2778 // Arch Spec: 3.4.4.2
2779 bool HexagonPacketizerList::CanPromoteToNewValueStore( MachineInstr *MI,
2780 MachineInstr *PacketMI, unsigned DepReg,
2781 std::map <MachineInstr*, SUnit*> MIToSUnit)
2783 // Make sure we are looking at the store
2784 if (!IsNewifyStore(MI))
2787 // Make sure there is dependency and can be new value'ed
2788 if (GetStoreValueOperand(MI).isReg() &&
2789 GetStoreValueOperand(MI).getReg() != DepReg)
2792 const HexagonRegisterInfo* QRI =
2793 (const HexagonRegisterInfo *) TM.getRegisterInfo();
2794 const MCInstrDesc& MCID = PacketMI->getDesc();
2795 // first operand is always the result
2797 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
2798 const TargetRegisterClass* PacketRC = QII->getRegClass(MCID, 0, QRI, MF);
2800 // if there is already an store in the packet, no can do new value store
2801 // Arch Spec 3.4.4.2.
2802 for (std::vector<MachineInstr*>::iterator VI = CurrentPacketMIs.begin(),
2803 VE = CurrentPacketMIs.end();
2805 SUnit* PacketSU = MIToSUnit[*VI];
2806 if (PacketSU->getInstr()->getDesc().mayStore() ||
2807 // if we have mayStore = 1 set on ALLOCFRAME and DEALLOCFRAME,
2808 // then we don't need this
2809 PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME ||
2810 PacketSU->getInstr()->getOpcode() == Hexagon::DEALLOCFRAME)
2814 if (PacketRC == &Hexagon::DoubleRegsRegClass) {
2815 // new value store constraint: double regs can not feed into new value store
2816 // arch spec section: 5.4.2.2
2820 // Make sure it's NOT the post increment register that we are going to
2822 if (QII->isPostIncrement(MI) &&
2823 MI->getDesc().mayStore() &&
2824 GetPostIncrementOperand(MI, QII).getReg() == DepReg) {
2828 if (QII->isPostIncrement(PacketMI) &&
2829 PacketMI->getDesc().mayLoad() &&
2830 GetPostIncrementOperand(PacketMI, QII).getReg() == DepReg) {
2831 // if source is post_inc, or absolute-set addressing,
2832 // it can not feed into new value store
2833 // r3 = memw(r2++#4)
2834 // memw(r30 + #-1404) = r2.new -> can not be new value store
2835 // arch spec section: 5.4.2.1
2839 // If the source that feeds the store is predicated, new value store must
2840 // also be also predicated.
2841 if (QII->isPredicated(PacketMI)) {
2842 if (!QII->isPredicated(MI))
2845 // Check to make sure that they both will have their predicates
2846 // evaluate identically
2847 unsigned predRegNumSrc = 0;
2848 unsigned predRegNumDst = 0;
2849 const TargetRegisterClass* predRegClass = NULL;
2851 // Get predicate register used in the source instruction
2852 for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {
2853 if ( PacketMI->getOperand(opNum).isReg())
2854 predRegNumSrc = PacketMI->getOperand(opNum).getReg();
2855 predRegClass = QRI->getMinimalPhysRegClass(predRegNumSrc);
2856 if (predRegClass == &Hexagon::PredRegsRegClass) {
2860 assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
2861 ("predicate register not found in a predicated PacketMI instruction"));
2863 // Get predicate register used in new-value store instruction
2864 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
2865 if ( MI->getOperand(opNum).isReg())
2866 predRegNumDst = MI->getOperand(opNum).getReg();
2867 predRegClass = QRI->getMinimalPhysRegClass(predRegNumDst);
2868 if (predRegClass == &Hexagon::PredRegsRegClass) {
2872 assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
2873 ("predicate register not found in a predicated MI instruction"));
2875 // New-value register producer and user (store) need to satisfy these
2877 // 1) Both instructions should be predicated on the same register.
2878 // 2) If producer of the new-value register is .new predicated then store
2879 // should also be .new predicated and if producer is not .new predicated
2880 // then store should not be .new predicated.
2881 // 3) Both new-value register producer and user should have same predicate
2882 // sense, i.e, either both should be negated or both should be none negated.
2884 if (( predRegNumDst != predRegNumSrc) ||
2885 isDotNewInst(PacketMI) != isDotNewInst(MI) ||
2886 GetPredicateSense(MI, QII) != GetPredicateSense(PacketMI, QII)) {
2891 // Make sure that other than the new-value register no other store instruction
2892 // register has been modified in the same packet. Predicate registers can be
2893 // modified by they should not be modified between the producer and the store
2894 // instruction as it will make them both conditional on different values.
2895 // We already know this to be true for all the instructions before and
2896 // including PacketMI. Howerver, we need to perform the check for the
2897 // remaining instructions in the packet.
2899 std::vector<MachineInstr*>::iterator VI;
2900 std::vector<MachineInstr*>::iterator VE;
2901 unsigned StartCheck = 0;
2903 for (VI=CurrentPacketMIs.begin(), VE = CurrentPacketMIs.end();
2905 SUnit* TempSU = MIToSUnit[*VI];
2906 MachineInstr* TempMI = TempSU->getInstr();
2908 // Following condition is true for all the instructions until PacketMI is
2909 // reached (StartCheck is set to 0 before the for loop).
2910 // StartCheck flag is 1 for all the instructions after PacketMI.
2911 if (TempMI != PacketMI && !StartCheck) // start processing only after
2912 continue; // encountering PacketMI
2915 if (TempMI == PacketMI) // We don't want to check PacketMI for dependence
2918 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
2919 if (MI->getOperand(opNum).isReg() &&
2920 TempSU->getInstr()->modifiesRegister(MI->getOperand(opNum).getReg(),
2926 // Make sure that for non POST_INC stores:
2927 // 1. The only use of reg is DepReg and no other registers.
2928 // This handles V4 base+index registers.
2929 // The following store can not be dot new.
2930 // Eg. r0 = add(r0, #3)a
2931 // memw(r1+r0<<#2) = r0
2932 if (!QII->isPostIncrement(MI) &&
2933 GetStoreValueOperand(MI).isReg() &&
2934 GetStoreValueOperand(MI).getReg() == DepReg) {
2935 for(unsigned opNum = 0; opNum < MI->getNumOperands()-1; opNum++) {
2936 if (MI->getOperand(opNum).isReg() &&
2937 MI->getOperand(opNum).getReg() == DepReg) {
2941 // 2. If data definition is because of implicit definition of the register,
2942 // do not newify the store. Eg.
2943 // %R9<def> = ZXTH %R12, %D6<imp-use>, %R12<imp-def>
2944 // STrih_indexed %R8, 2, %R12<kill>; mem:ST2[%scevgep343]
2945 for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {
2946 if (PacketMI->getOperand(opNum).isReg() &&
2947 PacketMI->getOperand(opNum).getReg() == DepReg &&
2948 PacketMI->getOperand(opNum).isDef() &&
2949 PacketMI->getOperand(opNum).isImplicit()) {
2955 // Can be dot new store.
2959 // can this MI to promoted to either
2960 // new value store or new value jump
2961 bool HexagonPacketizerList::CanPromoteToNewValue( MachineInstr *MI,
2962 SUnit *PacketSU, unsigned DepReg,
2963 std::map <MachineInstr*, SUnit*> MIToSUnit,
2964 MachineBasicBlock::iterator &MII)
2967 const HexagonRegisterInfo* QRI =
2968 (const HexagonRegisterInfo *) TM.getRegisterInfo();
2969 if (!QRI->Subtarget.hasV4TOps() ||
2973 MachineInstr *PacketMI = PacketSU->getInstr();
2975 // Check to see the store can be new value'ed.
2976 if (CanPromoteToNewValueStore(MI, PacketMI, DepReg, MIToSUnit))
2979 // Check to see the compare/jump can be new value'ed.
2980 // This is done as a pass on its own. Don't need to check it here.
2984 // Check to see if an instruction can be dot new
2985 // There are three kinds.
2986 // 1. dot new on predicate - V2/V3/V4
2987 // 2. dot new on stores NV/ST - V4
2988 // 3. dot new on jump NV/J - V4 -- This is generated in a pass.
2989 bool HexagonPacketizerList::CanPromoteToDotNew( MachineInstr *MI,
2990 SUnit *PacketSU, unsigned DepReg,
2991 std::map <MachineInstr*, SUnit*> MIToSUnit,
2992 MachineBasicBlock::iterator &MII,
2993 const TargetRegisterClass* RC )
2995 // already a dot new instruction
2996 if (isDotNewInst(MI) && !IsNewifyStore(MI))
2999 if (!isNewifiable(MI))
3003 if (RC == &Hexagon::PredRegsRegClass && isCondInst(MI))
3005 else if (RC != &Hexagon::PredRegsRegClass &&
3006 !IsNewifyStore(MI)) // MI is not a new-value store
3009 // Create a dot new machine instruction to see if resources can be
3010 // allocated. If not, bail out now.
3011 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
3012 int NewOpcode = GetDotNewOp(MI->getOpcode());
3013 const MCInstrDesc &desc = QII->get(NewOpcode);
3015 MachineInstr *NewMI =
3016 MI->getParent()->getParent()->CreateMachineInstr(desc, dl);
3017 bool ResourcesAvailable = ResourceTracker->canReserveResources(NewMI);
3018 MI->getParent()->getParent()->DeleteMachineInstr(NewMI);
3020 if (!ResourcesAvailable)
3023 // new value store only
3024 // new new value jump generated as a passes
3025 if (!CanPromoteToNewValue(MI, PacketSU, DepReg, MIToSUnit, MII)) {
3032 // Go through the packet instructions and search for anti dependency
3033 // between them and DepReg from MI
3034 // Consider this case:
3036 // a) %R1<def> = TFRI_cdNotPt %P3, 2
3039 // b) %P0<def> = OR_pp %P3<kill>, %P0<kill>
3040 // c) %P3<def> = TFR_PdRs %R23
3041 // d) %R1<def> = TFRI_cdnPt %P3, 4
3043 // The P3 from a) and d) will be complements after
3044 // a)'s P3 is converted to .new form
3045 // Anti Dep between c) and b) is irrelevant for this case
3046 bool HexagonPacketizerList::RestrictingDepExistInPacket (MachineInstr* MI,
3048 std::map <MachineInstr*, SUnit*> MIToSUnit) {
3050 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
3051 SUnit* PacketSUDep = MIToSUnit[MI];
3053 for (std::vector<MachineInstr*>::iterator VIN = CurrentPacketMIs.begin(),
3054 VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {
3056 // We only care for dependencies to predicated instructions
3057 if(!QII->isPredicated(*VIN)) continue;
3059 // Scheduling Unit for current insn in the packet
3060 SUnit* PacketSU = MIToSUnit[*VIN];
3062 // Look at dependencies between current members of the packet
3063 // and predicate defining instruction MI.
3064 // Make sure that dependency is on the exact register
3066 if (PacketSU->isSucc(PacketSUDep)) {
3067 for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
3068 if ((PacketSU->Succs[i].getSUnit() == PacketSUDep) &&
3069 (PacketSU->Succs[i].getKind() == SDep::Anti) &&
3070 (PacketSU->Succs[i].getReg() == DepReg)) {
3081 // Given two predicated instructions, this function detects whether
3082 // the predicates are complements
3083 bool HexagonPacketizerList::ArePredicatesComplements (MachineInstr* MI1,
3084 MachineInstr* MI2, std::map <MachineInstr*, SUnit*> MIToSUnit) {
3086 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
3087 // Currently can only reason about conditional transfers
3088 if (!QII->isConditionalTransfer(MI1) || !QII->isConditionalTransfer(MI2)) {
3092 // Scheduling unit for candidate
3093 SUnit* SU = MIToSUnit[MI1];
3095 // One corner case deals with the following scenario:
3097 // a) %R24<def> = TFR_cPt %P0, %R25
3101 // b) %R25<def> = TFR_cNotPt %P0, %R24
3102 // c) %P0<def> = CMPEQri %R26, 1
3105 // On general check a) and b) are complements, but
3106 // presence of c) will convert a) to .new form, and
3107 // then it is not a complement
3108 // We attempt to detect it by analyzing existing
3109 // dependencies in the packet
3111 // Analyze relationships between all existing members of the packet.
3112 // Look for Anti dependecy on the same predicate reg
3113 // as used in the candidate
3114 for (std::vector<MachineInstr*>::iterator VIN = CurrentPacketMIs.begin(),
3115 VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {
3117 // Scheduling Unit for current insn in the packet
3118 SUnit* PacketSU = MIToSUnit[*VIN];
3120 // If this instruction in the packet is succeeded by the candidate...
3121 if (PacketSU->isSucc(SU)) {
3122 for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
3123 // The corner case exist when there is true data
3124 // dependency between candidate and one of current
3125 // packet members, this dep is on predicate reg, and
3126 // there already exist anti dep on the same pred in
3128 if (PacketSU->Succs[i].getSUnit() == SU &&
3129 Hexagon::PredRegsRegClass.contains(
3130 PacketSU->Succs[i].getReg()) &&
3131 PacketSU->Succs[i].getKind() == SDep::Data &&
3132 // Here I know that *VIN is predicate setting instruction
3133 // with true data dep to candidate on the register
3134 // we care about - c) in the above example.
3135 // Now I need to see if there is an anti dependency
3136 // from c) to any other instruction in the
3137 // same packet on the pred reg of interest
3138 RestrictingDepExistInPacket(*VIN,PacketSU->Succs[i].getReg(),
3146 // If the above case does not apply, check regular
3147 // complement condition.
3148 // Check that the predicate register is the same and
3149 // that the predicate sense is different
3150 // We also need to differentiate .old vs. .new:
3151 // !p0 is not complimentary to p0.new
3152 return ((MI1->getOperand(1).getReg() == MI2->getOperand(1).getReg()) &&
3153 (GetPredicateSense(MI1, QII) != GetPredicateSense(MI2, QII)) &&
3154 (isDotNewInst(MI1) == isDotNewInst(MI2)));
3157 // initPacketizerState - Initialize packetizer flags
3158 void HexagonPacketizerList::initPacketizerState() {
3161 PromotedToDotNew = false;
3162 GlueToNewValueJump = false;
3163 GlueAllocframeStore = false;
3164 FoundSequentialDependence = false;
3169 // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
3170 bool HexagonPacketizerList::ignorePseudoInstruction(MachineInstr *MI,
3171 MachineBasicBlock *MBB) {
3172 if (MI->isDebugValue())
3175 // We must print out inline assembly
3176 if (MI->isInlineAsm())
3179 // We check if MI has any functional units mapped to it.
3180 // If it doesn't, we ignore the instruction.
3181 const MCInstrDesc& TID = MI->getDesc();
3182 unsigned SchedClass = TID.getSchedClass();
3183 const InstrStage* IS =
3184 ResourceTracker->getInstrItins()->beginStage(SchedClass);
3185 unsigned FuncUnits = IS->getUnits();
3189 // isSoloInstruction: - Returns true for instructions that must be
3190 // scheduled in their own packet.
3191 bool HexagonPacketizerList::isSoloInstruction(MachineInstr *MI) {
3193 if (MI->isInlineAsm())
3196 if (MI->isEHLabel())
3199 // From Hexagon V4 Programmer's Reference Manual 3.4.4 Grouping constraints:
3200 // trap, pause, barrier, icinva, isync, and syncht are solo instructions.
3201 // They must not be grouped with other instructions in a packet.
3202 if (IsSchedBarrier(MI))
3208 // isLegalToPacketizeTogether:
3209 // SUI is the current instruction that is out side of the current packet.
3210 // SUJ is the current instruction inside the current packet against which that
3211 // SUI will be packetized.
3212 bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
3213 MachineInstr *I = SUI->getInstr();
3214 MachineInstr *J = SUJ->getInstr();
3215 assert(I && J && "Unable to packetize null instruction!");
3217 const MCInstrDesc &MCIDI = I->getDesc();
3218 const MCInstrDesc &MCIDJ = J->getDesc();
3220 MachineBasicBlock::iterator II = I;
3222 const unsigned FrameSize = MF.getFrameInfo()->getStackSize();
3223 const HexagonRegisterInfo* QRI =
3224 (const HexagonRegisterInfo *) TM.getRegisterInfo();
3225 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
3227 // Inline asm cannot go in the packet.
3228 if (I->getOpcode() == Hexagon::INLINEASM)
3229 llvm_unreachable("Should not meet inline asm here!");
3231 if (isSoloInstruction(I))
3232 llvm_unreachable("Should not meet solo instr here!");
3234 // A save callee-save register function call can only be in a packet
3235 // with instructions that don't write to the callee-save registers.
3236 if ((QII->isSaveCalleeSavedRegsCall(I) &&
3237 DoesModifyCalleeSavedReg(J, QRI)) ||
3238 (QII->isSaveCalleeSavedRegsCall(J) &&
3239 DoesModifyCalleeSavedReg(I, QRI))) {
3244 // Two control flow instructions cannot go in the same packet.
3245 if (IsControlFlow(I) && IsControlFlow(J)) {
3250 // A LoopN instruction cannot appear in the same packet as a jump or call.
3251 if (IsLoopN(I) && ( IsDirectJump(J)
3253 || QII->isDeallocRet(J))) {
3257 if (IsLoopN(J) && ( IsDirectJump(I)
3259 || QII->isDeallocRet(I))) {
3264 // dealloc_return cannot appear in the same packet as a conditional or
3265 // unconditional jump.
3266 if (QII->isDeallocRet(I) && ( MCIDJ.isBranch()
3268 || MCIDJ.isBarrier())) {
3274 // V4 allows dual store. But does not allow second store, if the
3275 // first store is not in SLOT0. New value store, new value jump,
3276 // dealloc_return and memop always take SLOT0.
3277 // Arch spec 3.4.4.2
3278 if (QRI->Subtarget.hasV4TOps()) {
3280 if (MCIDI.mayStore() && MCIDJ.mayStore() && isNewValueInst(J)) {
3285 if ( (QII->isMemOp(J) && MCIDI.mayStore())
3286 || (MCIDJ.mayStore() && QII->isMemOp(I))
3287 || (QII->isMemOp(J) && QII->isMemOp(I))) {
3293 if (MCIDJ.mayStore() && QII->isDeallocRet(I)){
3298 // If an instruction feeds new value jump, glue it.
3299 MachineBasicBlock::iterator NextMII = I;
3301 MachineInstr *NextMI = NextMII;
3303 if (QII->isNewValueJump(NextMI)) {
3305 bool secondRegMatch = false;
3306 bool maintainNewValueJump = false;
3308 if (NextMI->getOperand(1).isReg() &&
3309 I->getOperand(0).getReg() == NextMI->getOperand(1).getReg()) {
3310 secondRegMatch = true;
3311 maintainNewValueJump = true;
3314 if (!secondRegMatch &&
3315 I->getOperand(0).getReg() == NextMI->getOperand(0).getReg()) {
3316 maintainNewValueJump = true;
3319 for (std::vector<MachineInstr*>::iterator
3320 VI = CurrentPacketMIs.begin(),
3321 VE = CurrentPacketMIs.end();
3322 (VI != VE && maintainNewValueJump); ++VI) {
3323 SUnit* PacketSU = MIToSUnit[*VI];
3325 // NVJ can not be part of the dual jump - Arch Spec: section 7.8
3326 if (PacketSU->getInstr()->getDesc().isCall()) {
3331 // 1. Packet does not have a store in it.
3332 // 2. If the first operand of the nvj is newified, and the second
3333 // operand is also a reg, it (second reg) is not defined in
3335 // 3. If the second operand of the nvj is newified, (which means
3336 // first operand is also a reg), first reg is not defined in
3338 if (PacketSU->getInstr()->getDesc().mayStore() ||
3339 PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME ||
3341 (!secondRegMatch && NextMI->getOperand(1).isReg() &&
3342 PacketSU->getInstr()->modifiesRegister(
3343 NextMI->getOperand(1).getReg(), QRI)) ||
3346 PacketSU->getInstr()->modifiesRegister(
3347 NextMI->getOperand(0).getReg(), QRI))) {
3353 GlueToNewValueJump = true;
3359 if (SUJ->isSucc(SUI)) {
3360 for (unsigned i = 0;
3361 (i < SUJ->Succs.size()) && !FoundSequentialDependence;
3364 if (SUJ->Succs[i].getSUnit() != SUI) {
3368 SDep::Kind DepType = SUJ->Succs[i].getKind();
3370 // For direct calls:
3371 // Ignore register dependences for call instructions for
3372 // packetization purposes except for those due to r31 and
3373 // predicate registers.
3375 // For indirect calls:
3376 // Same as direct calls + check for true dependences to the register
3377 // used in the indirect call.
3379 // We completely ignore Order dependences for call instructions
3382 // Ignore register dependences for return instructions like jumpr,
3383 // dealloc return unless we have dependencies on the explicit uses
3384 // of the registers used by jumpr (like r31) or dealloc return
3385 // (like r29 or r30).
3387 // TODO: Currently, jumpr is handling only return of r31. So, the
3388 // following logic (specificaly IsCallDependent) is working fine.
3389 // We need to enable jumpr for register other than r31 and then,
3390 // we need to rework the last part, where it handles indirect call
3391 // of that (IsCallDependent) function. Bug 6216 is opened for this.
3393 unsigned DepReg = 0;
3394 const TargetRegisterClass* RC = NULL;
3395 if (DepType == SDep::Data) {
3396 DepReg = SUJ->Succs[i].getReg();
3397 RC = QRI->getMinimalPhysRegClass(DepReg);
3399 if ((MCIDI.isCall() || MCIDI.isReturn()) &&
3400 (!IsRegDependence(DepType) ||
3401 !IsCallDependent(I, DepType, SUJ->Succs[i].getReg()))) {
3405 // For instructions that can be promoted to dot-new, try to promote.
3406 else if ((DepType == SDep::Data) &&
3407 CanPromoteToDotNew(I, SUJ, DepReg, MIToSUnit, II, RC) &&
3408 PromoteToDotNew(I, DepType, II, RC)) {
3409 PromotedToDotNew = true;
3413 else if ((DepType == SDep::Data) &&
3414 (QII->isNewValueJump(I))) {
3418 // For predicated instructions, if the predicates are complements
3419 // then there can be no dependence.
3420 else if (QII->isPredicated(I) &&
3421 QII->isPredicated(J) &&
3422 ArePredicatesComplements(I, J, MIToSUnit)) {
3426 else if (IsDirectJump(I) &&
3427 !MCIDJ.isBranch() &&
3429 (DepType == SDep::Order)) {
3430 // Ignore Order dependences between unconditional direct branches
3431 // and non-control-flow instructions
3434 else if (MCIDI.isConditionalBranch() && (DepType != SDep::Data) &&
3435 (DepType != SDep::Output)) {
3436 // Ignore all dependences for jumps except for true and output
3441 // Ignore output dependences due to superregs. We can
3442 // write to two different subregisters of R1:0 for instance
3443 // in the same cycle
3448 // If neither I nor J defines DepReg, then this is a
3449 // superfluous output dependence. The dependence must be of the
3453 // and there is an output dependence between the two instructions
3456 // We want to ignore these dependences.
3457 // Ideally, the dependence constructor should annotate such
3458 // dependences. We can then avoid this relatively expensive check.
3460 else if (DepType == SDep::Output) {
3461 // DepReg is the register that's responsible for the dependence.
3462 unsigned DepReg = SUJ->Succs[i].getReg();
3464 // Check if I and J really defines DepReg.
3465 if (I->definesRegister(DepReg) ||
3466 J->definesRegister(DepReg)) {
3467 FoundSequentialDependence = true;
3472 // We ignore Order dependences for
3473 // 1. Two loads unless they are volatile.
3474 // 2. Two stores in V4 unless they are volatile.
3475 else if ((DepType == SDep::Order) &&
3476 !I->hasOrderedMemoryRef() &&
3477 !J->hasOrderedMemoryRef()) {
3478 if (QRI->Subtarget.hasV4TOps() &&
3479 // hexagonv4 allows dual store.
3480 MCIDI.mayStore() && MCIDJ.mayStore()) {
3483 // store followed by store-- not OK on V2
3484 // store followed by load -- not OK on all (OK if addresses
3486 // load followed by store -- OK on all
3487 // load followed by load -- OK on all
3488 else if ( !MCIDJ.mayStore()) {
3492 FoundSequentialDependence = true;
3497 // For V4, special case ALLOCFRAME. Even though there is dependency
3498 // between ALLOCAFRAME and subsequent store, allow it to be
3499 // packetized in a same packet. This implies that the store is using
3500 // caller's SP. Hense, offset needs to be updated accordingly.
3501 else if (DepType == SDep::Data
3502 && QRI->Subtarget.hasV4TOps()
3503 && J->getOpcode() == Hexagon::ALLOCFRAME
3504 && (I->getOpcode() == Hexagon::STrid
3505 || I->getOpcode() == Hexagon::STriw
3506 || I->getOpcode() == Hexagon::STrib)
3507 && I->getOperand(0).getReg() == QRI->getStackRegister()
3508 && QII->isValidOffset(I->getOpcode(),
3509 I->getOperand(1).getImm() -
3510 (FrameSize + HEXAGON_LRFP_SIZE)))
3512 GlueAllocframeStore = true;
3513 // Since this store is to be glued with allocframe in the same
3514 // packet, it will use SP of the previous stack frame, i.e
3515 // caller's SP. Therefore, we need to recalculate offset according
3517 I->getOperand(1).setImm(I->getOperand(1).getImm() -
3518 (FrameSize + HEXAGON_LRFP_SIZE));
3522 // Skip over anti-dependences. Two instructions that are
3523 // anti-dependent can share a packet
3525 else if (DepType != SDep::Anti) {
3526 FoundSequentialDependence = true;
3531 if (FoundSequentialDependence) {
3540 // isLegalToPruneDependencies
3541 bool HexagonPacketizerList::isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {
3542 MachineInstr *I = SUI->getInstr();
3543 assert(I && SUJ->getInstr() && "Unable to packetize null instruction!");
3545 const unsigned FrameSize = MF.getFrameInfo()->getStackSize();
3549 // Check if the instruction was promoted to a dot-new. If so, demote it
3550 // back into a dot-old.
3551 if (PromotedToDotNew) {
3555 // Check if the instruction (must be a store) was glued with an Allocframe
3556 // instruction. If so, restore its offset to its original value, i.e. use
3557 // curent SP instead of caller's SP.
3558 if (GlueAllocframeStore) {
3559 I->getOperand(1).setImm(I->getOperand(1).getImm() +
3560 FrameSize + HEXAGON_LRFP_SIZE);
3568 MachineBasicBlock::iterator
3569 HexagonPacketizerList::addToPacket(MachineInstr *MI) {
3571 MachineBasicBlock::iterator MII = MI;
3572 MachineBasicBlock *MBB = MI->getParent();
3574 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
3576 if (GlueToNewValueJump) {
3579 MachineInstr *nvjMI = MII;
3580 assert(ResourceTracker->canReserveResources(MI));
3581 ResourceTracker->reserveResources(MI);
3582 if (QII->isExtended(MI) &&
3583 !tryAllocateResourcesForConstExt(MI)) {
3585 ResourceTracker->reserveResources(MI);
3586 assert(canReserveResourcesForConstExt(MI) &&
3587 "Ensure that there is a slot");
3588 reserveResourcesForConstExt(MI);
3589 // Reserve resources for new value jump constant extender.
3590 assert(canReserveResourcesForConstExt(MI) &&
3591 "Ensure that there is a slot");
3592 reserveResourcesForConstExt(nvjMI);
3593 assert(ResourceTracker->canReserveResources(nvjMI) &&
3594 "Ensure that there is a slot");
3596 } else if ( // Extended instruction takes two slots in the packet.
3597 // Try reserve and allocate 4-byte in the current packet first.
3598 (QII->isExtended(nvjMI)
3599 && (!tryAllocateResourcesForConstExt(nvjMI)
3600 || !ResourceTracker->canReserveResources(nvjMI)))
3601 || // For non-extended instruction, no need to allocate extra 4 bytes.
3602 (!QII->isExtended(nvjMI) &&
3603 !ResourceTracker->canReserveResources(nvjMI)))
3606 // A new and empty packet starts.
3607 // We are sure that the resources requirements can be satisfied.
3608 // Therefore, do not need to call "canReserveResources" anymore.
3609 ResourceTracker->reserveResources(MI);
3610 if (QII->isExtended(nvjMI))
3611 reserveResourcesForConstExt(nvjMI);
3613 // Here, we are sure that "reserveResources" would succeed.
3614 ResourceTracker->reserveResources(nvjMI);
3615 CurrentPacketMIs.push_back(MI);
3616 CurrentPacketMIs.push_back(nvjMI);
3618 if ( QII->isExtended(MI)
3619 && ( !tryAllocateResourcesForConstExt(MI)
3620 || !ResourceTracker->canReserveResources(MI)))
3623 // Check if the instruction was promoted to a dot-new. If so, demote it
3624 // back into a dot-old
3625 if (PromotedToDotNew) {
3628 reserveResourcesForConstExt(MI);
3630 // In case that "MI" is not an extended insn,
3631 // the resource availability has already been checked.
3632 ResourceTracker->reserveResources(MI);
3633 CurrentPacketMIs.push_back(MI);
3638 //===----------------------------------------------------------------------===//
3639 // Public Constructor Functions
3640 //===----------------------------------------------------------------------===//
3642 FunctionPass *llvm::createHexagonPacketizer() {
3643 return new HexagonPacketizer();