1 //===----- HexagonPacketizer.cpp - vliw packetizer ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements a simple VLIW packetizer using DFA. The packetizer works on
11 // machine basic blocks. For each instruction I in BB, the packetizer consults
12 // the DFA to see if machine resources are available to execute I. If so, the
13 // packetizer checks if I depends on any instruction J in the current packet.
14 // If no dependency is found, I is added to current packet and machine resource
15 // is marked as taken. If any dependency is found, a target API call is made to
16 // prune the dependence.
18 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "packets"
20 #include "llvm/CodeGen/DFAPacketizer.h"
21 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/CodeGen/MachineDominators.h"
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/MachineLoopInfo.h"
25 #include "llvm/CodeGen/ScheduleDAG.h"
26 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
27 #include "llvm/CodeGen/LatencyPriorityQueue.h"
28 #include "llvm/CodeGen/SchedulerRegistry.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
33 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetRegisterInfo.h"
37 #include "llvm/ADT/DenseMap.h"
38 #include "llvm/ADT/Statistic.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/MC/MCInstrItineraries.h"
41 #include "llvm/Support/Compiler.h"
42 #include "llvm/Support/CommandLine.h"
43 #include "llvm/Support/Debug.h"
45 #include "HexagonTargetMachine.h"
46 #include "HexagonRegisterInfo.h"
47 #include "HexagonSubtarget.h"
48 #include "HexagonMachineFunctionInfo.h"
55 class HexagonPacketizer : public MachineFunctionPass {
59 HexagonPacketizer() : MachineFunctionPass(ID) {}
61 void getAnalysisUsage(AnalysisUsage &AU) const {
63 AU.addRequired<MachineDominatorTree>();
64 AU.addPreserved<MachineDominatorTree>();
65 AU.addRequired<MachineLoopInfo>();
66 AU.addPreserved<MachineLoopInfo>();
67 MachineFunctionPass::getAnalysisUsage(AU);
70 const char *getPassName() const {
71 return "Hexagon Packetizer";
74 bool runOnMachineFunction(MachineFunction &Fn);
76 char HexagonPacketizer::ID = 0;
78 class HexagonPacketizerList : public VLIWPacketizerList {
82 // Has the instruction been promoted to a dot-new instruction.
83 bool PromotedToDotNew;
85 // Has the instruction been glued to allocframe.
86 bool GlueAllocframeStore;
88 // Has the feeder instruction been glued to new value jump.
89 bool GlueToNewValueJump;
91 // Check if there is a dependence between some instruction already in this
92 // packet and this instruction.
95 // Only check for dependence if there are resources available to
96 // schedule this instruction.
97 bool FoundSequentialDependence;
101 HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
102 MachineDominatorTree &MDT);
104 // initPacketizerState - initialize some internal flags.
105 void initPacketizerState();
107 // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
108 bool ignorePseudoInstruction(MachineInstr *MI, MachineBasicBlock *MBB);
110 // isSoloInstruction - return true if instruction MI can not be packetized
111 // with any other instruction, which means that MI itself is a packet.
112 bool isSoloInstruction(MachineInstr *MI);
114 // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
116 bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ);
118 // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
120 bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ);
122 MachineBasicBlock::iterator addToPacket(MachineInstr *MI);
124 bool IsCallDependent(MachineInstr* MI, SDep::Kind DepType, unsigned DepReg);
125 bool PromoteToDotNew(MachineInstr* MI, SDep::Kind DepType,
126 MachineBasicBlock::iterator &MII,
127 const TargetRegisterClass* RC);
128 bool CanPromoteToDotNew(MachineInstr* MI, SUnit* PacketSU,
130 std::map <MachineInstr*, SUnit*> MIToSUnit,
131 MachineBasicBlock::iterator &MII,
132 const TargetRegisterClass* RC);
133 bool CanPromoteToNewValue(MachineInstr* MI, SUnit* PacketSU,
135 std::map <MachineInstr*, SUnit*> MIToSUnit,
136 MachineBasicBlock::iterator &MII);
137 bool CanPromoteToNewValueStore(MachineInstr* MI, MachineInstr* PacketMI,
139 std::map <MachineInstr*, SUnit*> MIToSUnit);
140 bool DemoteToDotOld(MachineInstr* MI);
141 bool ArePredicatesComplements(MachineInstr* MI1, MachineInstr* MI2,
142 std::map <MachineInstr*, SUnit*> MIToSUnit);
143 bool RestrictingDepExistInPacket(MachineInstr*,
144 unsigned, std::map <MachineInstr*, SUnit*>);
145 bool isNewifiable(MachineInstr* MI);
146 bool isCondInst(MachineInstr* MI);
147 bool IsNewifyStore (MachineInstr* MI);
148 bool tryAllocateResourcesForConstExt(MachineInstr* MI);
149 bool canReserveResourcesForConstExt(MachineInstr *MI);
150 void reserveResourcesForConstExt(MachineInstr* MI);
151 bool isNewValueInst(MachineInstr* MI);
152 bool isDotNewInst(MachineInstr* MI);
156 // HexagonPacketizerList Ctor.
157 HexagonPacketizerList::HexagonPacketizerList(
158 MachineFunction &MF, MachineLoopInfo &MLI,MachineDominatorTree &MDT)
159 : VLIWPacketizerList(MF, MLI, MDT, true){
162 bool HexagonPacketizer::runOnMachineFunction(MachineFunction &Fn) {
163 const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo();
164 MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
165 MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
167 // Instantiate the packetizer.
168 HexagonPacketizerList Packetizer(Fn, MLI, MDT);
170 // DFA state table should not be empty.
171 assert(Packetizer.getResourceTracker() && "Empty DFA table!");
174 // Loop over all basic blocks and remove KILL pseudo-instructions
175 // These instructions confuse the dependence analysis. Consider:
177 // R0 = KILL R0, D0 (Insn 1)
179 // Here, Insn 1 will result in the dependence graph not emitting an output
180 // dependence between Insn 0 and Insn 2. This can lead to incorrect
183 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
184 MBB != MBBe; ++MBB) {
185 MachineBasicBlock::iterator End = MBB->end();
186 MachineBasicBlock::iterator MI = MBB->begin();
189 MachineBasicBlock::iterator DeleteMI = MI;
191 MBB->erase(DeleteMI);
199 // Loop over all of the basic blocks.
200 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
201 MBB != MBBe; ++MBB) {
202 // Find scheduling regions and schedule / packetize each region.
203 unsigned RemainingCount = MBB->size();
204 for(MachineBasicBlock::iterator RegionEnd = MBB->end();
205 RegionEnd != MBB->begin();) {
206 // The next region starts above the previous region. Look backward in the
207 // instruction stream until we find the nearest boundary.
208 MachineBasicBlock::iterator I = RegionEnd;
209 for(;I != MBB->begin(); --I, --RemainingCount) {
210 if (TII->isSchedulingBoundary(llvm::prior(I), MBB, Fn))
215 // Skip empty scheduling regions.
216 if (I == RegionEnd) {
217 RegionEnd = llvm::prior(RegionEnd);
221 // Skip regions with one instruction.
222 if (I == llvm::prior(RegionEnd)) {
223 RegionEnd = llvm::prior(RegionEnd);
227 Packetizer.PacketizeMIs(MBB, I, RegionEnd);
236 static bool IsIndirectCall(MachineInstr* MI) {
237 return ((MI->getOpcode() == Hexagon::CALLR) ||
238 (MI->getOpcode() == Hexagon::CALLRv3));
241 // Reserve resources for constant extender. Trigure an assertion if
243 void HexagonPacketizerList::reserveResourcesForConstExt(MachineInstr* MI) {
244 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
245 MachineFunction *MF = MI->getParent()->getParent();
246 MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
249 if (ResourceTracker->canReserveResources(PseudoMI)) {
250 ResourceTracker->reserveResources(PseudoMI);
251 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
253 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
254 llvm_unreachable("can not reserve resources for constant extender.");
259 bool HexagonPacketizerList::canReserveResourcesForConstExt(MachineInstr *MI) {
260 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
261 assert((QII->isExtended(MI) || QII->isConstExtended(MI)) &&
262 "Should only be called for constant extended instructions");
263 MachineFunction *MF = MI->getParent()->getParent();
264 MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
266 bool CanReserve = ResourceTracker->canReserveResources(PseudoMI);
267 MF->DeleteMachineInstr(PseudoMI);
271 // Allocate resources (i.e. 4 bytes) for constant extender. If succeed, return
272 // true, otherwise, return false.
273 bool HexagonPacketizerList::tryAllocateResourcesForConstExt(MachineInstr* MI) {
274 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
275 MachineFunction *MF = MI->getParent()->getParent();
276 MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
279 if (ResourceTracker->canReserveResources(PseudoMI)) {
280 ResourceTracker->reserveResources(PseudoMI);
281 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
284 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
290 bool HexagonPacketizerList::IsCallDependent(MachineInstr* MI,
294 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
295 const HexagonRegisterInfo* QRI =
296 (const HexagonRegisterInfo *) TM.getRegisterInfo();
298 // Check for lr dependence
299 if (DepReg == QRI->getRARegister()) {
303 if (QII->isDeallocRet(MI)) {
304 if (DepReg == QRI->getFrameRegister() ||
305 DepReg == QRI->getStackRegister())
309 // Check if this is a predicate dependence
310 const TargetRegisterClass* RC = QRI->getMinimalPhysRegClass(DepReg);
311 if (RC == &Hexagon::PredRegsRegClass) {
316 // Lastly check for an operand used in an indirect call
317 // If we had an attribute for checking if an instruction is an indirect call,
318 // then we could have avoided this relatively brittle implementation of
321 // Assumes that the first operand of the CALLr is the function address
323 if (IsIndirectCall(MI) && (DepType == SDep::Data)) {
324 MachineOperand MO = MI->getOperand(0);
325 if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg)) {
333 static bool IsRegDependence(const SDep::Kind DepType) {
334 return (DepType == SDep::Data || DepType == SDep::Anti ||
335 DepType == SDep::Output);
338 static bool IsDirectJump(MachineInstr* MI) {
339 return (MI->getOpcode() == Hexagon::JMP);
342 static bool IsSchedBarrier(MachineInstr* MI) {
343 switch (MI->getOpcode()) {
344 case Hexagon::BARRIER:
350 static bool IsControlFlow(MachineInstr* MI) {
351 return (MI->getDesc().isTerminator() || MI->getDesc().isCall());
354 bool HexagonPacketizerList::isNewValueInst(MachineInstr* MI) {
355 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
356 if (QII->isNewValueJump(MI))
359 if (QII->isNewValueStore(MI))
365 // Function returns true if an instruction can be promoted to the new-value
366 // store. It will always return false for v2 and v3.
367 // It lists all the conditional and unconditional stores that can be promoted
368 // to the new-value stores.
370 bool HexagonPacketizerList::IsNewifyStore (MachineInstr* MI) {
371 const HexagonRegisterInfo* QRI =
372 (const HexagonRegisterInfo *) TM.getRegisterInfo();
373 switch (MI->getOpcode())
377 case Hexagon::STrib_indexed:
378 case Hexagon::STrib_indexed_shl_V4:
379 case Hexagon::STrib_shl_V4:
380 case Hexagon::STb_GP_V4:
381 case Hexagon::POST_STbri:
382 case Hexagon::STrib_cPt:
383 case Hexagon::STrib_cdnPt_V4:
384 case Hexagon::STrib_cNotPt:
385 case Hexagon::STrib_cdnNotPt_V4:
386 case Hexagon::STrib_indexed_cPt:
387 case Hexagon::STrib_indexed_cdnPt_V4:
388 case Hexagon::STrib_indexed_cNotPt:
389 case Hexagon::STrib_indexed_cdnNotPt_V4:
390 case Hexagon::STrib_indexed_shl_cPt_V4:
391 case Hexagon::STrib_indexed_shl_cdnPt_V4:
392 case Hexagon::STrib_indexed_shl_cNotPt_V4:
393 case Hexagon::STrib_indexed_shl_cdnNotPt_V4:
394 case Hexagon::POST_STbri_cPt:
395 case Hexagon::POST_STbri_cdnPt_V4:
396 case Hexagon::POST_STbri_cNotPt:
397 case Hexagon::POST_STbri_cdnNotPt_V4:
398 case Hexagon::STb_GP_cPt_V4:
399 case Hexagon::STb_GP_cNotPt_V4:
400 case Hexagon::STb_GP_cdnPt_V4:
401 case Hexagon::STb_GP_cdnNotPt_V4:
405 case Hexagon::STrih_indexed:
406 case Hexagon::STrih_indexed_shl_V4:
407 case Hexagon::STrih_shl_V4:
408 case Hexagon::STh_GP_V4:
409 case Hexagon::POST_SThri:
410 case Hexagon::STrih_cPt:
411 case Hexagon::STrih_cdnPt_V4:
412 case Hexagon::STrih_cNotPt:
413 case Hexagon::STrih_cdnNotPt_V4:
414 case Hexagon::STrih_indexed_cPt:
415 case Hexagon::STrih_indexed_cdnPt_V4:
416 case Hexagon::STrih_indexed_cNotPt:
417 case Hexagon::STrih_indexed_cdnNotPt_V4:
418 case Hexagon::STrih_indexed_shl_cPt_V4:
419 case Hexagon::STrih_indexed_shl_cdnPt_V4:
420 case Hexagon::STrih_indexed_shl_cNotPt_V4:
421 case Hexagon::STrih_indexed_shl_cdnNotPt_V4:
422 case Hexagon::POST_SThri_cPt:
423 case Hexagon::POST_SThri_cdnPt_V4:
424 case Hexagon::POST_SThri_cNotPt:
425 case Hexagon::POST_SThri_cdnNotPt_V4:
426 case Hexagon::STh_GP_cPt_V4:
427 case Hexagon::STh_GP_cNotPt_V4:
428 case Hexagon::STh_GP_cdnPt_V4:
429 case Hexagon::STh_GP_cdnNotPt_V4:
433 case Hexagon::STriw_indexed:
434 case Hexagon::STriw_indexed_shl_V4:
435 case Hexagon::STriw_shl_V4:
436 case Hexagon::STw_GP_V4:
437 case Hexagon::POST_STwri:
438 case Hexagon::STriw_cPt:
439 case Hexagon::STriw_cdnPt_V4:
440 case Hexagon::STriw_cNotPt:
441 case Hexagon::STriw_cdnNotPt_V4:
442 case Hexagon::STriw_indexed_cPt:
443 case Hexagon::STriw_indexed_cdnPt_V4:
444 case Hexagon::STriw_indexed_cNotPt:
445 case Hexagon::STriw_indexed_cdnNotPt_V4:
446 case Hexagon::STriw_indexed_shl_cPt_V4:
447 case Hexagon::STriw_indexed_shl_cdnPt_V4:
448 case Hexagon::STriw_indexed_shl_cNotPt_V4:
449 case Hexagon::STriw_indexed_shl_cdnNotPt_V4:
450 case Hexagon::POST_STwri_cPt:
451 case Hexagon::POST_STwri_cdnPt_V4:
452 case Hexagon::POST_STwri_cNotPt:
453 case Hexagon::POST_STwri_cdnNotPt_V4:
454 case Hexagon::STw_GP_cPt_V4:
455 case Hexagon::STw_GP_cNotPt_V4:
456 case Hexagon::STw_GP_cdnPt_V4:
457 case Hexagon::STw_GP_cdnNotPt_V4:
458 return QRI->Subtarget.hasV4TOps();
463 static bool IsLoopN(MachineInstr *MI) {
464 return (MI->getOpcode() == Hexagon::LOOP0_i ||
465 MI->getOpcode() == Hexagon::LOOP0_r);
468 /// DoesModifyCalleeSavedReg - Returns true if the instruction modifies a
469 /// callee-saved register.
470 static bool DoesModifyCalleeSavedReg(MachineInstr *MI,
471 const TargetRegisterInfo *TRI) {
472 for (const uint16_t *CSR = TRI->getCalleeSavedRegs(); *CSR; ++CSR) {
473 unsigned CalleeSavedReg = *CSR;
474 if (MI->modifiesRegister(CalleeSavedReg, TRI))
480 // Return the new value instruction for a given store.
481 static int GetDotNewOp(const int opc) {
483 default: llvm_unreachable("Unknown .new type");
484 // store new value byte
486 return Hexagon::STrib_nv_V4;
488 case Hexagon::STrib_indexed:
489 return Hexagon::STrib_indexed_nv_V4;
491 case Hexagon::STrib_indexed_shl_V4:
492 return Hexagon::STrib_indexed_shl_nv_V4;
494 case Hexagon::STrib_shl_V4:
495 return Hexagon::STrib_shl_nv_V4;
497 case Hexagon::STb_GP_V4:
498 return Hexagon::STb_GP_nv_V4;
500 case Hexagon::POST_STbri:
501 return Hexagon::POST_STbri_nv_V4;
503 case Hexagon::STrib_cPt:
504 return Hexagon::STrib_cPt_nv_V4;
506 case Hexagon::STrib_cdnPt_V4:
507 return Hexagon::STrib_cdnPt_nv_V4;
509 case Hexagon::STrib_cNotPt:
510 return Hexagon::STrib_cNotPt_nv_V4;
512 case Hexagon::STrib_cdnNotPt_V4:
513 return Hexagon::STrib_cdnNotPt_nv_V4;
515 case Hexagon::STrib_indexed_cPt:
516 return Hexagon::STrib_indexed_cPt_nv_V4;
518 case Hexagon::STrib_indexed_cdnPt_V4:
519 return Hexagon::STrib_indexed_cdnPt_nv_V4;
521 case Hexagon::STrib_indexed_cNotPt:
522 return Hexagon::STrib_indexed_cNotPt_nv_V4;
524 case Hexagon::STrib_indexed_cdnNotPt_V4:
525 return Hexagon::STrib_indexed_cdnNotPt_nv_V4;
527 case Hexagon::STrib_indexed_shl_cPt_V4:
528 return Hexagon::STrib_indexed_shl_cPt_nv_V4;
530 case Hexagon::STrib_indexed_shl_cdnPt_V4:
531 return Hexagon::STrib_indexed_shl_cdnPt_nv_V4;
533 case Hexagon::STrib_indexed_shl_cNotPt_V4:
534 return Hexagon::STrib_indexed_shl_cNotPt_nv_V4;
536 case Hexagon::STrib_indexed_shl_cdnNotPt_V4:
537 return Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4;
539 case Hexagon::POST_STbri_cPt:
540 return Hexagon::POST_STbri_cPt_nv_V4;
542 case Hexagon::POST_STbri_cdnPt_V4:
543 return Hexagon::POST_STbri_cdnPt_nv_V4;
545 case Hexagon::POST_STbri_cNotPt:
546 return Hexagon::POST_STbri_cNotPt_nv_V4;
548 case Hexagon::POST_STbri_cdnNotPt_V4:
549 return Hexagon::POST_STbri_cdnNotPt_nv_V4;
551 case Hexagon::STb_GP_cPt_V4:
552 return Hexagon::STb_GP_cPt_nv_V4;
554 case Hexagon::STb_GP_cNotPt_V4:
555 return Hexagon::STb_GP_cNotPt_nv_V4;
557 case Hexagon::STb_GP_cdnPt_V4:
558 return Hexagon::STb_GP_cdnPt_nv_V4;
560 case Hexagon::STb_GP_cdnNotPt_V4:
561 return Hexagon::STb_GP_cdnNotPt_nv_V4;
563 // store new value halfword
565 return Hexagon::STrih_nv_V4;
567 case Hexagon::STrih_indexed:
568 return Hexagon::STrih_indexed_nv_V4;
570 case Hexagon::STrih_indexed_shl_V4:
571 return Hexagon::STrih_indexed_shl_nv_V4;
573 case Hexagon::STrih_shl_V4:
574 return Hexagon::STrih_shl_nv_V4;
576 case Hexagon::STh_GP_V4:
577 return Hexagon::STh_GP_nv_V4;
579 case Hexagon::POST_SThri:
580 return Hexagon::POST_SThri_nv_V4;
582 case Hexagon::STrih_cPt:
583 return Hexagon::STrih_cPt_nv_V4;
585 case Hexagon::STrih_cdnPt_V4:
586 return Hexagon::STrih_cdnPt_nv_V4;
588 case Hexagon::STrih_cNotPt:
589 return Hexagon::STrih_cNotPt_nv_V4;
591 case Hexagon::STrih_cdnNotPt_V4:
592 return Hexagon::STrih_cdnNotPt_nv_V4;
594 case Hexagon::STrih_indexed_cPt:
595 return Hexagon::STrih_indexed_cPt_nv_V4;
597 case Hexagon::STrih_indexed_cdnPt_V4:
598 return Hexagon::STrih_indexed_cdnPt_nv_V4;
600 case Hexagon::STrih_indexed_cNotPt:
601 return Hexagon::STrih_indexed_cNotPt_nv_V4;
603 case Hexagon::STrih_indexed_cdnNotPt_V4:
604 return Hexagon::STrih_indexed_cdnNotPt_nv_V4;
606 case Hexagon::STrih_indexed_shl_cPt_V4:
607 return Hexagon::STrih_indexed_shl_cPt_nv_V4;
609 case Hexagon::STrih_indexed_shl_cdnPt_V4:
610 return Hexagon::STrih_indexed_shl_cdnPt_nv_V4;
612 case Hexagon::STrih_indexed_shl_cNotPt_V4:
613 return Hexagon::STrih_indexed_shl_cNotPt_nv_V4;
615 case Hexagon::STrih_indexed_shl_cdnNotPt_V4:
616 return Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4;
618 case Hexagon::POST_SThri_cPt:
619 return Hexagon::POST_SThri_cPt_nv_V4;
621 case Hexagon::POST_SThri_cdnPt_V4:
622 return Hexagon::POST_SThri_cdnPt_nv_V4;
624 case Hexagon::POST_SThri_cNotPt:
625 return Hexagon::POST_SThri_cNotPt_nv_V4;
627 case Hexagon::POST_SThri_cdnNotPt_V4:
628 return Hexagon::POST_SThri_cdnNotPt_nv_V4;
630 case Hexagon::STh_GP_cPt_V4:
631 return Hexagon::STh_GP_cPt_nv_V4;
633 case Hexagon::STh_GP_cNotPt_V4:
634 return Hexagon::STh_GP_cNotPt_nv_V4;
636 case Hexagon::STh_GP_cdnPt_V4:
637 return Hexagon::STh_GP_cdnPt_nv_V4;
639 case Hexagon::STh_GP_cdnNotPt_V4:
640 return Hexagon::STh_GP_cdnNotPt_nv_V4;
642 // store new value word
644 return Hexagon::STriw_nv_V4;
646 case Hexagon::STriw_indexed:
647 return Hexagon::STriw_indexed_nv_V4;
649 case Hexagon::STriw_indexed_shl_V4:
650 return Hexagon::STriw_indexed_shl_nv_V4;
652 case Hexagon::STriw_shl_V4:
653 return Hexagon::STriw_shl_nv_V4;
655 case Hexagon::STw_GP_V4:
656 return Hexagon::STw_GP_nv_V4;
658 case Hexagon::POST_STwri:
659 return Hexagon::POST_STwri_nv_V4;
661 case Hexagon::STriw_cPt:
662 return Hexagon::STriw_cPt_nv_V4;
664 case Hexagon::STriw_cdnPt_V4:
665 return Hexagon::STriw_cdnPt_nv_V4;
667 case Hexagon::STriw_cNotPt:
668 return Hexagon::STriw_cNotPt_nv_V4;
670 case Hexagon::STriw_cdnNotPt_V4:
671 return Hexagon::STriw_cdnNotPt_nv_V4;
673 case Hexagon::STriw_indexed_cPt:
674 return Hexagon::STriw_indexed_cPt_nv_V4;
676 case Hexagon::STriw_indexed_cdnPt_V4:
677 return Hexagon::STriw_indexed_cdnPt_nv_V4;
679 case Hexagon::STriw_indexed_cNotPt:
680 return Hexagon::STriw_indexed_cNotPt_nv_V4;
682 case Hexagon::STriw_indexed_cdnNotPt_V4:
683 return Hexagon::STriw_indexed_cdnNotPt_nv_V4;
685 case Hexagon::STriw_indexed_shl_cPt_V4:
686 return Hexagon::STriw_indexed_shl_cPt_nv_V4;
688 case Hexagon::STriw_indexed_shl_cdnPt_V4:
689 return Hexagon::STriw_indexed_shl_cdnPt_nv_V4;
691 case Hexagon::STriw_indexed_shl_cNotPt_V4:
692 return Hexagon::STriw_indexed_shl_cNotPt_nv_V4;
694 case Hexagon::STriw_indexed_shl_cdnNotPt_V4:
695 return Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4;
697 case Hexagon::POST_STwri_cPt:
698 return Hexagon::POST_STwri_cPt_nv_V4;
700 case Hexagon::POST_STwri_cdnPt_V4:
701 return Hexagon::POST_STwri_cdnPt_nv_V4;
703 case Hexagon::POST_STwri_cNotPt:
704 return Hexagon::POST_STwri_cNotPt_nv_V4;
706 case Hexagon::POST_STwri_cdnNotPt_V4:
707 return Hexagon::POST_STwri_cdnNotPt_nv_V4;
709 case Hexagon::STw_GP_cPt_V4:
710 return Hexagon::STw_GP_cPt_nv_V4;
712 case Hexagon::STw_GP_cNotPt_V4:
713 return Hexagon::STw_GP_cNotPt_nv_V4;
715 case Hexagon::STw_GP_cdnPt_V4:
716 return Hexagon::STw_GP_cdnPt_nv_V4;
718 case Hexagon::STw_GP_cdnNotPt_V4:
719 return Hexagon::STw_GP_cdnNotPt_nv_V4;
724 // Return .new predicate version for an instruction
725 static int GetDotNewPredOp(const int opc) {
727 default: llvm_unreachable("Unknown .new type");
728 // Conditional stores
729 // Store byte conditionally
730 case Hexagon::STrib_cPt :
731 return Hexagon::STrib_cdnPt_V4;
733 case Hexagon::STrib_cNotPt :
734 return Hexagon::STrib_cdnNotPt_V4;
736 case Hexagon::STrib_indexed_cPt :
737 return Hexagon::STrib_indexed_cdnPt_V4;
739 case Hexagon::STrib_indexed_cNotPt :
740 return Hexagon::STrib_indexed_cdnNotPt_V4;
742 case Hexagon::STrib_imm_cPt_V4 :
743 return Hexagon::STrib_imm_cdnPt_V4;
745 case Hexagon::STrib_imm_cNotPt_V4 :
746 return Hexagon::STrib_imm_cdnNotPt_V4;
748 case Hexagon::POST_STbri_cPt :
749 return Hexagon::POST_STbri_cdnPt_V4;
751 case Hexagon::POST_STbri_cNotPt :
752 return Hexagon::POST_STbri_cdnNotPt_V4;
754 case Hexagon::STrib_indexed_shl_cPt_V4 :
755 return Hexagon::STrib_indexed_shl_cdnPt_V4;
757 case Hexagon::STrib_indexed_shl_cNotPt_V4 :
758 return Hexagon::STrib_indexed_shl_cdnNotPt_V4;
760 case Hexagon::STb_GP_cPt_V4 :
761 return Hexagon::STb_GP_cdnPt_V4;
763 case Hexagon::STb_GP_cNotPt_V4 :
764 return Hexagon::STb_GP_cdnNotPt_V4;
766 // Store doubleword conditionally
767 case Hexagon::STrid_cPt :
768 return Hexagon::STrid_cdnPt_V4;
770 case Hexagon::STrid_cNotPt :
771 return Hexagon::STrid_cdnNotPt_V4;
773 case Hexagon::STrid_indexed_cPt :
774 return Hexagon::STrid_indexed_cdnPt_V4;
776 case Hexagon::STrid_indexed_cNotPt :
777 return Hexagon::STrid_indexed_cdnNotPt_V4;
779 case Hexagon::STrid_indexed_shl_cPt_V4 :
780 return Hexagon::STrid_indexed_shl_cdnPt_V4;
782 case Hexagon::STrid_indexed_shl_cNotPt_V4 :
783 return Hexagon::STrid_indexed_shl_cdnNotPt_V4;
785 case Hexagon::POST_STdri_cPt :
786 return Hexagon::POST_STdri_cdnPt_V4;
788 case Hexagon::POST_STdri_cNotPt :
789 return Hexagon::POST_STdri_cdnNotPt_V4;
791 case Hexagon::STd_GP_cPt_V4 :
792 return Hexagon::STd_GP_cdnPt_V4;
794 case Hexagon::STd_GP_cNotPt_V4 :
795 return Hexagon::STd_GP_cdnNotPt_V4;
797 // Store halfword conditionally
798 case Hexagon::STrih_cPt :
799 return Hexagon::STrih_cdnPt_V4;
801 case Hexagon::STrih_cNotPt :
802 return Hexagon::STrih_cdnNotPt_V4;
804 case Hexagon::STrih_indexed_cPt :
805 return Hexagon::STrih_indexed_cdnPt_V4;
807 case Hexagon::STrih_indexed_cNotPt :
808 return Hexagon::STrih_indexed_cdnNotPt_V4;
810 case Hexagon::STrih_imm_cPt_V4 :
811 return Hexagon::STrih_imm_cdnPt_V4;
813 case Hexagon::STrih_imm_cNotPt_V4 :
814 return Hexagon::STrih_imm_cdnNotPt_V4;
816 case Hexagon::STrih_indexed_shl_cPt_V4 :
817 return Hexagon::STrih_indexed_shl_cdnPt_V4;
819 case Hexagon::STrih_indexed_shl_cNotPt_V4 :
820 return Hexagon::STrih_indexed_shl_cdnNotPt_V4;
822 case Hexagon::POST_SThri_cPt :
823 return Hexagon::POST_SThri_cdnPt_V4;
825 case Hexagon::POST_SThri_cNotPt :
826 return Hexagon::POST_SThri_cdnNotPt_V4;
828 case Hexagon::STh_GP_cPt_V4 :
829 return Hexagon::STh_GP_cdnPt_V4;
831 case Hexagon::STh_GP_cNotPt_V4 :
832 return Hexagon::STh_GP_cdnNotPt_V4;
834 // Store word conditionally
835 case Hexagon::STriw_cPt :
836 return Hexagon::STriw_cdnPt_V4;
838 case Hexagon::STriw_cNotPt :
839 return Hexagon::STriw_cdnNotPt_V4;
841 case Hexagon::STriw_indexed_cPt :
842 return Hexagon::STriw_indexed_cdnPt_V4;
844 case Hexagon::STriw_indexed_cNotPt :
845 return Hexagon::STriw_indexed_cdnNotPt_V4;
847 case Hexagon::STriw_imm_cPt_V4 :
848 return Hexagon::STriw_imm_cdnPt_V4;
850 case Hexagon::STriw_imm_cNotPt_V4 :
851 return Hexagon::STriw_imm_cdnNotPt_V4;
853 case Hexagon::STriw_indexed_shl_cPt_V4 :
854 return Hexagon::STriw_indexed_shl_cdnPt_V4;
856 case Hexagon::STriw_indexed_shl_cNotPt_V4 :
857 return Hexagon::STriw_indexed_shl_cdnNotPt_V4;
859 case Hexagon::POST_STwri_cPt :
860 return Hexagon::POST_STwri_cdnPt_V4;
862 case Hexagon::POST_STwri_cNotPt :
863 return Hexagon::POST_STwri_cdnNotPt_V4;
865 case Hexagon::STw_GP_cPt_V4 :
866 return Hexagon::STw_GP_cdnPt_V4;
868 case Hexagon::STw_GP_cNotPt_V4 :
869 return Hexagon::STw_GP_cdnNotPt_V4;
873 return Hexagon::JMP_cdnPt;
875 case Hexagon::JMP_cNot:
876 return Hexagon::JMP_cdnNotPt;
878 case Hexagon::JMPR_cPt:
879 return Hexagon::JMPR_cdnPt_V3;
881 case Hexagon::JMPR_cNotPt:
882 return Hexagon::JMPR_cdnNotPt_V3;
884 // Conditional Transfers
885 case Hexagon::TFR_cPt:
886 return Hexagon::TFR_cdnPt;
888 case Hexagon::TFR_cNotPt:
889 return Hexagon::TFR_cdnNotPt;
891 case Hexagon::TFRI_cPt:
892 return Hexagon::TFRI_cdnPt;
894 case Hexagon::TFRI_cNotPt:
895 return Hexagon::TFRI_cdnNotPt;
898 case Hexagon::LDrid_cPt :
899 return Hexagon::LDrid_cdnPt;
901 case Hexagon::LDrid_cNotPt :
902 return Hexagon::LDrid_cdnNotPt;
904 case Hexagon::LDrid_indexed_cPt :
905 return Hexagon::LDrid_indexed_cdnPt;
907 case Hexagon::LDrid_indexed_cNotPt :
908 return Hexagon::LDrid_indexed_cdnNotPt;
910 case Hexagon::POST_LDrid_cPt :
911 return Hexagon::POST_LDrid_cdnPt_V4;
913 case Hexagon::POST_LDrid_cNotPt :
914 return Hexagon::POST_LDrid_cdnNotPt_V4;
917 case Hexagon::LDriw_cPt :
918 return Hexagon::LDriw_cdnPt;
920 case Hexagon::LDriw_cNotPt :
921 return Hexagon::LDriw_cdnNotPt;
923 case Hexagon::LDriw_indexed_cPt :
924 return Hexagon::LDriw_indexed_cdnPt;
926 case Hexagon::LDriw_indexed_cNotPt :
927 return Hexagon::LDriw_indexed_cdnNotPt;
929 case Hexagon::POST_LDriw_cPt :
930 return Hexagon::POST_LDriw_cdnPt_V4;
932 case Hexagon::POST_LDriw_cNotPt :
933 return Hexagon::POST_LDriw_cdnNotPt_V4;
936 case Hexagon::LDrih_cPt :
937 return Hexagon::LDrih_cdnPt;
939 case Hexagon::LDrih_cNotPt :
940 return Hexagon::LDrih_cdnNotPt;
942 case Hexagon::LDrih_indexed_cPt :
943 return Hexagon::LDrih_indexed_cdnPt;
945 case Hexagon::LDrih_indexed_cNotPt :
946 return Hexagon::LDrih_indexed_cdnNotPt;
948 case Hexagon::POST_LDrih_cPt :
949 return Hexagon::POST_LDrih_cdnPt_V4;
951 case Hexagon::POST_LDrih_cNotPt :
952 return Hexagon::POST_LDrih_cdnNotPt_V4;
955 case Hexagon::LDrib_cPt :
956 return Hexagon::LDrib_cdnPt;
958 case Hexagon::LDrib_cNotPt :
959 return Hexagon::LDrib_cdnNotPt;
961 case Hexagon::LDrib_indexed_cPt :
962 return Hexagon::LDrib_indexed_cdnPt;
964 case Hexagon::LDrib_indexed_cNotPt :
965 return Hexagon::LDrib_indexed_cdnNotPt;
967 case Hexagon::POST_LDrib_cPt :
968 return Hexagon::POST_LDrib_cdnPt_V4;
970 case Hexagon::POST_LDrib_cNotPt :
971 return Hexagon::POST_LDrib_cdnNotPt_V4;
973 // Load unsigned halfword
974 case Hexagon::LDriuh_cPt :
975 return Hexagon::LDriuh_cdnPt;
977 case Hexagon::LDriuh_cNotPt :
978 return Hexagon::LDriuh_cdnNotPt;
980 case Hexagon::LDriuh_indexed_cPt :
981 return Hexagon::LDriuh_indexed_cdnPt;
983 case Hexagon::LDriuh_indexed_cNotPt :
984 return Hexagon::LDriuh_indexed_cdnNotPt;
986 case Hexagon::POST_LDriuh_cPt :
987 return Hexagon::POST_LDriuh_cdnPt_V4;
989 case Hexagon::POST_LDriuh_cNotPt :
990 return Hexagon::POST_LDriuh_cdnNotPt_V4;
992 // Load unsigned byte
993 case Hexagon::LDriub_cPt :
994 return Hexagon::LDriub_cdnPt;
996 case Hexagon::LDriub_cNotPt :
997 return Hexagon::LDriub_cdnNotPt;
999 case Hexagon::LDriub_indexed_cPt :
1000 return Hexagon::LDriub_indexed_cdnPt;
1002 case Hexagon::LDriub_indexed_cNotPt :
1003 return Hexagon::LDriub_indexed_cdnNotPt;
1005 case Hexagon::POST_LDriub_cPt :
1006 return Hexagon::POST_LDriub_cdnPt_V4;
1008 case Hexagon::POST_LDriub_cNotPt :
1009 return Hexagon::POST_LDriub_cdnNotPt_V4;
1011 // V4 indexed+scaled load
1013 case Hexagon::LDrid_indexed_shl_cPt_V4 :
1014 return Hexagon::LDrid_indexed_shl_cdnPt_V4;
1016 case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
1017 return Hexagon::LDrid_indexed_shl_cdnNotPt_V4;
1019 case Hexagon::LDrib_indexed_shl_cPt_V4 :
1020 return Hexagon::LDrib_indexed_shl_cdnPt_V4;
1022 case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
1023 return Hexagon::LDrib_indexed_shl_cdnNotPt_V4;
1025 case Hexagon::LDriub_indexed_shl_cPt_V4 :
1026 return Hexagon::LDriub_indexed_shl_cdnPt_V4;
1028 case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
1029 return Hexagon::LDriub_indexed_shl_cdnNotPt_V4;
1031 case Hexagon::LDrih_indexed_shl_cPt_V4 :
1032 return Hexagon::LDrih_indexed_shl_cdnPt_V4;
1034 case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
1035 return Hexagon::LDrih_indexed_shl_cdnNotPt_V4;
1037 case Hexagon::LDriuh_indexed_shl_cPt_V4 :
1038 return Hexagon::LDriuh_indexed_shl_cdnPt_V4;
1040 case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
1041 return Hexagon::LDriuh_indexed_shl_cdnNotPt_V4;
1043 case Hexagon::LDriw_indexed_shl_cPt_V4 :
1044 return Hexagon::LDriw_indexed_shl_cdnPt_V4;
1046 case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
1047 return Hexagon::LDriw_indexed_shl_cdnNotPt_V4;
1049 // V4 global address load
1051 case Hexagon::LDd_GP_cPt_V4:
1052 return Hexagon::LDd_GP_cdnPt_V4;
1054 case Hexagon::LDd_GP_cNotPt_V4:
1055 return Hexagon::LDd_GP_cdnNotPt_V4;
1057 case Hexagon::LDb_GP_cPt_V4:
1058 return Hexagon::LDb_GP_cdnPt_V4;
1060 case Hexagon::LDb_GP_cNotPt_V4:
1061 return Hexagon::LDb_GP_cdnNotPt_V4;
1063 case Hexagon::LDub_GP_cPt_V4:
1064 return Hexagon::LDub_GP_cdnPt_V4;
1066 case Hexagon::LDub_GP_cNotPt_V4:
1067 return Hexagon::LDub_GP_cdnNotPt_V4;
1069 case Hexagon::LDh_GP_cPt_V4:
1070 return Hexagon::LDh_GP_cdnPt_V4;
1072 case Hexagon::LDh_GP_cNotPt_V4:
1073 return Hexagon::LDh_GP_cdnNotPt_V4;
1075 case Hexagon::LDuh_GP_cPt_V4:
1076 return Hexagon::LDuh_GP_cdnPt_V4;
1078 case Hexagon::LDuh_GP_cNotPt_V4:
1079 return Hexagon::LDuh_GP_cdnNotPt_V4;
1081 case Hexagon::LDw_GP_cPt_V4:
1082 return Hexagon::LDw_GP_cdnPt_V4;
1084 case Hexagon::LDw_GP_cNotPt_V4:
1085 return Hexagon::LDw_GP_cdnNotPt_V4;
1087 // Conditional store new-value byte
1088 case Hexagon::STrib_cPt_nv_V4 :
1089 return Hexagon::STrib_cdnPt_nv_V4;
1090 case Hexagon::STrib_cNotPt_nv_V4 :
1091 return Hexagon::STrib_cdnNotPt_nv_V4;
1093 case Hexagon::STrib_indexed_cPt_nv_V4 :
1094 return Hexagon::STrib_indexed_cdnPt_nv_V4;
1095 case Hexagon::STrib_indexed_cNotPt_nv_V4 :
1096 return Hexagon::STrib_indexed_cdnNotPt_nv_V4;
1098 case Hexagon::STrib_indexed_shl_cPt_nv_V4 :
1099 return Hexagon::STrib_indexed_shl_cdnPt_nv_V4;
1100 case Hexagon::STrib_indexed_shl_cNotPt_nv_V4 :
1101 return Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4;
1103 case Hexagon::POST_STbri_cPt_nv_V4 :
1104 return Hexagon::POST_STbri_cdnPt_nv_V4;
1105 case Hexagon::POST_STbri_cNotPt_nv_V4 :
1106 return Hexagon::POST_STbri_cdnNotPt_nv_V4;
1108 case Hexagon::STb_GP_cPt_nv_V4 :
1109 return Hexagon::STb_GP_cdnPt_nv_V4;
1111 case Hexagon::STb_GP_cNotPt_nv_V4 :
1112 return Hexagon::STb_GP_cdnNotPt_nv_V4;
1114 // Conditional store new-value halfword
1115 case Hexagon::STrih_cPt_nv_V4 :
1116 return Hexagon::STrih_cdnPt_nv_V4;
1117 case Hexagon::STrih_cNotPt_nv_V4 :
1118 return Hexagon::STrih_cdnNotPt_nv_V4;
1120 case Hexagon::STrih_indexed_cPt_nv_V4 :
1121 return Hexagon::STrih_indexed_cdnPt_nv_V4;
1122 case Hexagon::STrih_indexed_cNotPt_nv_V4 :
1123 return Hexagon::STrih_indexed_cdnNotPt_nv_V4;
1125 case Hexagon::STrih_indexed_shl_cPt_nv_V4 :
1126 return Hexagon::STrih_indexed_shl_cdnPt_nv_V4;
1127 case Hexagon::STrih_indexed_shl_cNotPt_nv_V4 :
1128 return Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4;
1130 case Hexagon::POST_SThri_cPt_nv_V4 :
1131 return Hexagon::POST_SThri_cdnPt_nv_V4;
1132 case Hexagon::POST_SThri_cNotPt_nv_V4 :
1133 return Hexagon::POST_SThri_cdnNotPt_nv_V4;
1135 case Hexagon::STh_GP_cPt_nv_V4 :
1136 return Hexagon::STh_GP_cdnPt_nv_V4;
1138 case Hexagon::STh_GP_cNotPt_nv_V4 :
1139 return Hexagon::STh_GP_cdnNotPt_nv_V4;
1141 // Conditional store new-value word
1142 case Hexagon::STriw_cPt_nv_V4 :
1143 return Hexagon::STriw_cdnPt_nv_V4;
1144 case Hexagon::STriw_cNotPt_nv_V4 :
1145 return Hexagon::STriw_cdnNotPt_nv_V4;
1147 case Hexagon::STriw_indexed_cPt_nv_V4 :
1148 return Hexagon::STriw_indexed_cdnPt_nv_V4;
1149 case Hexagon::STriw_indexed_cNotPt_nv_V4 :
1150 return Hexagon::STriw_indexed_cdnNotPt_nv_V4;
1152 case Hexagon::STriw_indexed_shl_cPt_nv_V4 :
1153 return Hexagon::STriw_indexed_shl_cdnPt_nv_V4;
1154 case Hexagon::STriw_indexed_shl_cNotPt_nv_V4 :
1155 return Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4;
1157 case Hexagon::POST_STwri_cPt_nv_V4 :
1158 return Hexagon::POST_STwri_cdnPt_nv_V4;
1159 case Hexagon::POST_STwri_cNotPt_nv_V4:
1160 return Hexagon::POST_STwri_cdnNotPt_nv_V4;
1162 case Hexagon::STw_GP_cPt_nv_V4 :
1163 return Hexagon::STw_GP_cdnPt_nv_V4;
1165 case Hexagon::STw_GP_cNotPt_nv_V4 :
1166 return Hexagon::STw_GP_cdnNotPt_nv_V4;
1169 case Hexagon::ADD_ri_cPt :
1170 return Hexagon::ADD_ri_cdnPt;
1171 case Hexagon::ADD_ri_cNotPt :
1172 return Hexagon::ADD_ri_cdnNotPt;
1174 case Hexagon::ADD_rr_cPt :
1175 return Hexagon::ADD_rr_cdnPt;
1176 case Hexagon::ADD_rr_cNotPt :
1177 return Hexagon::ADD_rr_cdnNotPt;
1179 // Conditional logical Operations
1180 case Hexagon::XOR_rr_cPt :
1181 return Hexagon::XOR_rr_cdnPt;
1182 case Hexagon::XOR_rr_cNotPt :
1183 return Hexagon::XOR_rr_cdnNotPt;
1185 case Hexagon::AND_rr_cPt :
1186 return Hexagon::AND_rr_cdnPt;
1187 case Hexagon::AND_rr_cNotPt :
1188 return Hexagon::AND_rr_cdnNotPt;
1190 case Hexagon::OR_rr_cPt :
1191 return Hexagon::OR_rr_cdnPt;
1192 case Hexagon::OR_rr_cNotPt :
1193 return Hexagon::OR_rr_cdnNotPt;
1195 // Conditional Subtract
1196 case Hexagon::SUB_rr_cPt :
1197 return Hexagon::SUB_rr_cdnPt;
1198 case Hexagon::SUB_rr_cNotPt :
1199 return Hexagon::SUB_rr_cdnNotPt;
1201 // Conditional combine
1202 case Hexagon::COMBINE_rr_cPt :
1203 return Hexagon::COMBINE_rr_cdnPt;
1204 case Hexagon::COMBINE_rr_cNotPt :
1205 return Hexagon::COMBINE_rr_cdnNotPt;
1207 case Hexagon::ASLH_cPt_V4 :
1208 return Hexagon::ASLH_cdnPt_V4;
1209 case Hexagon::ASLH_cNotPt_V4 :
1210 return Hexagon::ASLH_cdnNotPt_V4;
1212 case Hexagon::ASRH_cPt_V4 :
1213 return Hexagon::ASRH_cdnPt_V4;
1214 case Hexagon::ASRH_cNotPt_V4 :
1215 return Hexagon::ASRH_cdnNotPt_V4;
1217 case Hexagon::SXTB_cPt_V4 :
1218 return Hexagon::SXTB_cdnPt_V4;
1219 case Hexagon::SXTB_cNotPt_V4 :
1220 return Hexagon::SXTB_cdnNotPt_V4;
1222 case Hexagon::SXTH_cPt_V4 :
1223 return Hexagon::SXTH_cdnPt_V4;
1224 case Hexagon::SXTH_cNotPt_V4 :
1225 return Hexagon::SXTH_cdnNotPt_V4;
1227 case Hexagon::ZXTB_cPt_V4 :
1228 return Hexagon::ZXTB_cdnPt_V4;
1229 case Hexagon::ZXTB_cNotPt_V4 :
1230 return Hexagon::ZXTB_cdnNotPt_V4;
1232 case Hexagon::ZXTH_cPt_V4 :
1233 return Hexagon::ZXTH_cdnPt_V4;
1234 case Hexagon::ZXTH_cNotPt_V4 :
1235 return Hexagon::ZXTH_cdnNotPt_V4;
1239 // Returns true if an instruction can be promoted to .new predicate
1240 // or new-value store.
1241 bool HexagonPacketizerList::isNewifiable(MachineInstr* MI) {
1242 if ( isCondInst(MI) || IsNewifyStore(MI))
1248 bool HexagonPacketizerList::isCondInst (MachineInstr* MI) {
1249 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1250 const MCInstrDesc& TID = MI->getDesc();
1251 // bug 5670: until that is fixed,
1252 // this portion is disabled.
1253 if ( TID.isConditionalBranch() // && !IsRegisterJump(MI)) ||
1254 || QII->isConditionalTransfer(MI)
1255 || QII->isConditionalALU32(MI)
1256 || QII->isConditionalLoad(MI)
1257 || QII->isConditionalStore(MI)) {
1264 // Promote an instructiont to its .new form.
1265 // At this time, we have already made a call to CanPromoteToDotNew
1266 // and made sure that it can *indeed* be promoted.
1267 bool HexagonPacketizerList::PromoteToDotNew(MachineInstr* MI,
1268 SDep::Kind DepType, MachineBasicBlock::iterator &MII,
1269 const TargetRegisterClass* RC) {
1271 assert (DepType == SDep::Data);
1272 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1275 if (RC == &Hexagon::PredRegsRegClass)
1276 NewOpcode = GetDotNewPredOp(MI->getOpcode());
1278 NewOpcode = GetDotNewOp(MI->getOpcode());
1279 MI->setDesc(QII->get(NewOpcode));
1284 // Returns the most basic instruction for the .new predicated instructions and
1285 // new-value stores.
1286 // For example, all of the following instructions will be converted back to the
1287 // same instruction:
1288 // 1) if (p0.new) memw(R0+#0) = R1.new --->
1289 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
1290 // 3) if (p0.new) memw(R0+#0) = R1 --->
1292 // To understand the translation of instruction 1 to its original form, consider
1293 // a packet with 3 instructions.
1294 // { p0 = cmp.eq(R0,R1)
1295 // if (p0.new) R2 = add(R3, R4)
1296 // R5 = add (R3, R1)
1298 // if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet
1300 // This instruction can be part of the previous packet only if both p0 and R2
1301 // are promoted to .new values. This promotion happens in steps, first
1302 // predicate register is promoted to .new and in the next iteration R2 is
1303 // promoted. Therefore, in case of dependence check failure (due to R5) during
1304 // next iteration, it should be converted back to its most basic form.
1306 static int GetDotOldOp(const int opc) {
1308 default: llvm_unreachable("Unknown .old type");
1309 case Hexagon::TFR_cdnPt:
1310 return Hexagon::TFR_cPt;
1312 case Hexagon::TFR_cdnNotPt:
1313 return Hexagon::TFR_cNotPt;
1315 case Hexagon::TFRI_cdnPt:
1316 return Hexagon::TFRI_cPt;
1318 case Hexagon::TFRI_cdnNotPt:
1319 return Hexagon::TFRI_cNotPt;
1321 case Hexagon::JMP_cdnPt:
1322 return Hexagon::JMP_c;
1324 case Hexagon::JMP_cdnNotPt:
1325 return Hexagon::JMP_cNot;
1327 case Hexagon::JMPR_cdnPt_V3:
1328 return Hexagon::JMPR_cPt;
1330 case Hexagon::JMPR_cdnNotPt_V3:
1331 return Hexagon::JMPR_cNotPt;
1335 case Hexagon::LDrid_cdnPt :
1336 return Hexagon::LDrid_cPt;
1338 case Hexagon::LDrid_cdnNotPt :
1339 return Hexagon::LDrid_cNotPt;
1341 case Hexagon::LDrid_indexed_cdnPt :
1342 return Hexagon::LDrid_indexed_cPt;
1344 case Hexagon::LDrid_indexed_cdnNotPt :
1345 return Hexagon::LDrid_indexed_cNotPt;
1347 case Hexagon::POST_LDrid_cdnPt_V4 :
1348 return Hexagon::POST_LDrid_cPt;
1350 case Hexagon::POST_LDrid_cdnNotPt_V4 :
1351 return Hexagon::POST_LDrid_cNotPt;
1355 case Hexagon::LDriw_cdnPt :
1356 return Hexagon::LDriw_cPt;
1358 case Hexagon::LDriw_cdnNotPt :
1359 return Hexagon::LDriw_cNotPt;
1361 case Hexagon::LDriw_indexed_cdnPt :
1362 return Hexagon::LDriw_indexed_cPt;
1364 case Hexagon::LDriw_indexed_cdnNotPt :
1365 return Hexagon::LDriw_indexed_cNotPt;
1367 case Hexagon::POST_LDriw_cdnPt_V4 :
1368 return Hexagon::POST_LDriw_cPt;
1370 case Hexagon::POST_LDriw_cdnNotPt_V4 :
1371 return Hexagon::POST_LDriw_cNotPt;
1375 case Hexagon::LDrih_cdnPt :
1376 return Hexagon::LDrih_cPt;
1378 case Hexagon::LDrih_cdnNotPt :
1379 return Hexagon::LDrih_cNotPt;
1381 case Hexagon::LDrih_indexed_cdnPt :
1382 return Hexagon::LDrih_indexed_cPt;
1384 case Hexagon::LDrih_indexed_cdnNotPt :
1385 return Hexagon::LDrih_indexed_cNotPt;
1387 case Hexagon::POST_LDrih_cdnPt_V4 :
1388 return Hexagon::POST_LDrih_cPt;
1390 case Hexagon::POST_LDrih_cdnNotPt_V4 :
1391 return Hexagon::POST_LDrih_cNotPt;
1395 case Hexagon::LDrib_cdnPt :
1396 return Hexagon::LDrib_cPt;
1398 case Hexagon::LDrib_cdnNotPt :
1399 return Hexagon::LDrib_cNotPt;
1401 case Hexagon::LDrib_indexed_cdnPt :
1402 return Hexagon::LDrib_indexed_cPt;
1404 case Hexagon::LDrib_indexed_cdnNotPt :
1405 return Hexagon::LDrib_indexed_cNotPt;
1407 case Hexagon::POST_LDrib_cdnPt_V4 :
1408 return Hexagon::POST_LDrib_cPt;
1410 case Hexagon::POST_LDrib_cdnNotPt_V4 :
1411 return Hexagon::POST_LDrib_cNotPt;
1413 // Load unsigned half
1415 case Hexagon::LDriuh_cdnPt :
1416 return Hexagon::LDriuh_cPt;
1418 case Hexagon::LDriuh_cdnNotPt :
1419 return Hexagon::LDriuh_cNotPt;
1421 case Hexagon::LDriuh_indexed_cdnPt :
1422 return Hexagon::LDriuh_indexed_cPt;
1424 case Hexagon::LDriuh_indexed_cdnNotPt :
1425 return Hexagon::LDriuh_indexed_cNotPt;
1427 case Hexagon::POST_LDriuh_cdnPt_V4 :
1428 return Hexagon::POST_LDriuh_cPt;
1430 case Hexagon::POST_LDriuh_cdnNotPt_V4 :
1431 return Hexagon::POST_LDriuh_cNotPt;
1433 // Load unsigned byte
1434 case Hexagon::LDriub_cdnPt :
1435 return Hexagon::LDriub_cPt;
1437 case Hexagon::LDriub_cdnNotPt :
1438 return Hexagon::LDriub_cNotPt;
1440 case Hexagon::LDriub_indexed_cdnPt :
1441 return Hexagon::LDriub_indexed_cPt;
1443 case Hexagon::LDriub_indexed_cdnNotPt :
1444 return Hexagon::LDriub_indexed_cNotPt;
1446 case Hexagon::POST_LDriub_cdnPt_V4 :
1447 return Hexagon::POST_LDriub_cPt;
1449 case Hexagon::POST_LDriub_cdnNotPt_V4 :
1450 return Hexagon::POST_LDriub_cNotPt;
1452 // V4 indexed+scaled Load
1454 case Hexagon::LDrid_indexed_shl_cdnPt_V4 :
1455 return Hexagon::LDrid_indexed_shl_cPt_V4;
1457 case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :
1458 return Hexagon::LDrid_indexed_shl_cNotPt_V4;
1460 case Hexagon::LDrib_indexed_shl_cdnPt_V4 :
1461 return Hexagon::LDrib_indexed_shl_cPt_V4;
1463 case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :
1464 return Hexagon::LDrib_indexed_shl_cNotPt_V4;
1466 case Hexagon::LDriub_indexed_shl_cdnPt_V4 :
1467 return Hexagon::LDriub_indexed_shl_cPt_V4;
1469 case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :
1470 return Hexagon::LDriub_indexed_shl_cNotPt_V4;
1472 case Hexagon::LDrih_indexed_shl_cdnPt_V4 :
1473 return Hexagon::LDrih_indexed_shl_cPt_V4;
1475 case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :
1476 return Hexagon::LDrih_indexed_shl_cNotPt_V4;
1478 case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :
1479 return Hexagon::LDriuh_indexed_shl_cPt_V4;
1481 case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :
1482 return Hexagon::LDriuh_indexed_shl_cNotPt_V4;
1484 case Hexagon::LDriw_indexed_shl_cdnPt_V4 :
1485 return Hexagon::LDriw_indexed_shl_cPt_V4;
1487 case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :
1488 return Hexagon::LDriw_indexed_shl_cNotPt_V4;
1490 // V4 global address load
1492 case Hexagon::LDd_GP_cdnPt_V4:
1493 return Hexagon::LDd_GP_cPt_V4;
1495 case Hexagon::LDd_GP_cdnNotPt_V4:
1496 return Hexagon::LDd_GP_cNotPt_V4;
1498 case Hexagon::LDb_GP_cdnPt_V4:
1499 return Hexagon::LDb_GP_cPt_V4;
1501 case Hexagon::LDb_GP_cdnNotPt_V4:
1502 return Hexagon::LDb_GP_cNotPt_V4;
1504 case Hexagon::LDub_GP_cdnPt_V4:
1505 return Hexagon::LDub_GP_cPt_V4;
1507 case Hexagon::LDub_GP_cdnNotPt_V4:
1508 return Hexagon::LDub_GP_cNotPt_V4;
1510 case Hexagon::LDh_GP_cdnPt_V4:
1511 return Hexagon::LDh_GP_cPt_V4;
1513 case Hexagon::LDh_GP_cdnNotPt_V4:
1514 return Hexagon::LDh_GP_cNotPt_V4;
1516 case Hexagon::LDuh_GP_cdnPt_V4:
1517 return Hexagon::LDuh_GP_cPt_V4;
1519 case Hexagon::LDuh_GP_cdnNotPt_V4:
1520 return Hexagon::LDuh_GP_cNotPt_V4;
1522 case Hexagon::LDw_GP_cdnPt_V4:
1523 return Hexagon::LDw_GP_cPt_V4;
1525 case Hexagon::LDw_GP_cdnNotPt_V4:
1526 return Hexagon::LDw_GP_cNotPt_V4;
1530 case Hexagon::ADD_ri_cdnPt :
1531 return Hexagon::ADD_ri_cPt;
1532 case Hexagon::ADD_ri_cdnNotPt :
1533 return Hexagon::ADD_ri_cNotPt;
1535 case Hexagon::ADD_rr_cdnPt :
1536 return Hexagon::ADD_rr_cPt;
1537 case Hexagon::ADD_rr_cdnNotPt:
1538 return Hexagon::ADD_rr_cNotPt;
1540 // Conditional logical Operations
1542 case Hexagon::XOR_rr_cdnPt :
1543 return Hexagon::XOR_rr_cPt;
1544 case Hexagon::XOR_rr_cdnNotPt :
1545 return Hexagon::XOR_rr_cNotPt;
1547 case Hexagon::AND_rr_cdnPt :
1548 return Hexagon::AND_rr_cPt;
1549 case Hexagon::AND_rr_cdnNotPt :
1550 return Hexagon::AND_rr_cNotPt;
1552 case Hexagon::OR_rr_cdnPt :
1553 return Hexagon::OR_rr_cPt;
1554 case Hexagon::OR_rr_cdnNotPt :
1555 return Hexagon::OR_rr_cNotPt;
1557 // Conditional Subtract
1559 case Hexagon::SUB_rr_cdnPt :
1560 return Hexagon::SUB_rr_cPt;
1561 case Hexagon::SUB_rr_cdnNotPt :
1562 return Hexagon::SUB_rr_cNotPt;
1564 // Conditional combine
1566 case Hexagon::COMBINE_rr_cdnPt :
1567 return Hexagon::COMBINE_rr_cPt;
1568 case Hexagon::COMBINE_rr_cdnNotPt :
1569 return Hexagon::COMBINE_rr_cNotPt;
1571 // Conditional shift operations
1573 case Hexagon::ASLH_cdnPt_V4 :
1574 return Hexagon::ASLH_cPt_V4;
1575 case Hexagon::ASLH_cdnNotPt_V4 :
1576 return Hexagon::ASLH_cNotPt_V4;
1578 case Hexagon::ASRH_cdnPt_V4 :
1579 return Hexagon::ASRH_cPt_V4;
1580 case Hexagon::ASRH_cdnNotPt_V4 :
1581 return Hexagon::ASRH_cNotPt_V4;
1583 case Hexagon::SXTB_cdnPt_V4 :
1584 return Hexagon::SXTB_cPt_V4;
1585 case Hexagon::SXTB_cdnNotPt_V4 :
1586 return Hexagon::SXTB_cNotPt_V4;
1588 case Hexagon::SXTH_cdnPt_V4 :
1589 return Hexagon::SXTH_cPt_V4;
1590 case Hexagon::SXTH_cdnNotPt_V4 :
1591 return Hexagon::SXTH_cNotPt_V4;
1593 case Hexagon::ZXTB_cdnPt_V4 :
1594 return Hexagon::ZXTB_cPt_V4;
1595 case Hexagon::ZXTB_cdnNotPt_V4 :
1596 return Hexagon::ZXTB_cNotPt_V4;
1598 case Hexagon::ZXTH_cdnPt_V4 :
1599 return Hexagon::ZXTH_cPt_V4;
1600 case Hexagon::ZXTH_cdnNotPt_V4 :
1601 return Hexagon::ZXTH_cNotPt_V4;
1605 case Hexagon::STrib_imm_cdnPt_V4 :
1606 return Hexagon::STrib_imm_cPt_V4;
1608 case Hexagon::STrib_imm_cdnNotPt_V4 :
1609 return Hexagon::STrib_imm_cNotPt_V4;
1611 case Hexagon::STrib_cdnPt_nv_V4 :
1612 case Hexagon::STrib_cPt_nv_V4 :
1613 case Hexagon::STrib_cdnPt_V4 :
1614 return Hexagon::STrib_cPt;
1616 case Hexagon::STrib_cdnNotPt_nv_V4 :
1617 case Hexagon::STrib_cNotPt_nv_V4 :
1618 case Hexagon::STrib_cdnNotPt_V4 :
1619 return Hexagon::STrib_cNotPt;
1621 case Hexagon::STrib_indexed_cdnPt_V4 :
1622 case Hexagon::STrib_indexed_cPt_nv_V4 :
1623 case Hexagon::STrib_indexed_cdnPt_nv_V4 :
1624 return Hexagon::STrib_indexed_cPt;
1626 case Hexagon::STrib_indexed_cdnNotPt_V4 :
1627 case Hexagon::STrib_indexed_cNotPt_nv_V4 :
1628 case Hexagon::STrib_indexed_cdnNotPt_nv_V4 :
1629 return Hexagon::STrib_indexed_cNotPt;
1631 case Hexagon::STrib_indexed_shl_cdnPt_nv_V4:
1632 case Hexagon::STrib_indexed_shl_cPt_nv_V4 :
1633 case Hexagon::STrib_indexed_shl_cdnPt_V4 :
1634 return Hexagon::STrib_indexed_shl_cPt_V4;
1636 case Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4:
1637 case Hexagon::STrib_indexed_shl_cNotPt_nv_V4 :
1638 case Hexagon::STrib_indexed_shl_cdnNotPt_V4 :
1639 return Hexagon::STrib_indexed_shl_cNotPt_V4;
1641 case Hexagon::POST_STbri_cdnPt_nv_V4 :
1642 case Hexagon::POST_STbri_cPt_nv_V4 :
1643 case Hexagon::POST_STbri_cdnPt_V4 :
1644 return Hexagon::POST_STbri_cPt;
1646 case Hexagon::POST_STbri_cdnNotPt_nv_V4 :
1647 case Hexagon::POST_STbri_cNotPt_nv_V4:
1648 case Hexagon::POST_STbri_cdnNotPt_V4 :
1649 return Hexagon::POST_STbri_cNotPt;
1651 case Hexagon::STb_GP_cdnPt_nv_V4:
1652 case Hexagon::STb_GP_cdnPt_V4:
1653 case Hexagon::STb_GP_cPt_nv_V4:
1654 return Hexagon::STb_GP_cPt_V4;
1656 case Hexagon::STb_GP_cdnNotPt_nv_V4:
1657 case Hexagon::STb_GP_cdnNotPt_V4:
1658 case Hexagon::STb_GP_cNotPt_nv_V4:
1659 return Hexagon::STb_GP_cNotPt_V4;
1661 // Store new-value byte - unconditional
1662 case Hexagon::STrib_nv_V4:
1663 return Hexagon::STrib;
1665 case Hexagon::STrib_indexed_nv_V4:
1666 return Hexagon::STrib_indexed;
1668 case Hexagon::STrib_indexed_shl_nv_V4:
1669 return Hexagon::STrib_indexed_shl_V4;
1671 case Hexagon::STrib_shl_nv_V4:
1672 return Hexagon::STrib_shl_V4;
1674 case Hexagon::STb_GP_nv_V4:
1675 return Hexagon::STb_GP_V4;
1677 case Hexagon::POST_STbri_nv_V4:
1678 return Hexagon::POST_STbri;
1681 case Hexagon::STrih_imm_cdnPt_V4 :
1682 return Hexagon::STrih_imm_cPt_V4;
1684 case Hexagon::STrih_imm_cdnNotPt_V4 :
1685 return Hexagon::STrih_imm_cNotPt_V4;
1687 case Hexagon::STrih_cdnPt_nv_V4 :
1688 case Hexagon::STrih_cPt_nv_V4 :
1689 case Hexagon::STrih_cdnPt_V4 :
1690 return Hexagon::STrih_cPt;
1692 case Hexagon::STrih_cdnNotPt_nv_V4 :
1693 case Hexagon::STrih_cNotPt_nv_V4 :
1694 case Hexagon::STrih_cdnNotPt_V4 :
1695 return Hexagon::STrih_cNotPt;
1697 case Hexagon::STrih_indexed_cdnPt_nv_V4:
1698 case Hexagon::STrih_indexed_cPt_nv_V4 :
1699 case Hexagon::STrih_indexed_cdnPt_V4 :
1700 return Hexagon::STrih_indexed_cPt;
1702 case Hexagon::STrih_indexed_cdnNotPt_nv_V4:
1703 case Hexagon::STrih_indexed_cNotPt_nv_V4 :
1704 case Hexagon::STrih_indexed_cdnNotPt_V4 :
1705 return Hexagon::STrih_indexed_cNotPt;
1707 case Hexagon::STrih_indexed_shl_cdnPt_nv_V4 :
1708 case Hexagon::STrih_indexed_shl_cPt_nv_V4 :
1709 case Hexagon::STrih_indexed_shl_cdnPt_V4 :
1710 return Hexagon::STrih_indexed_shl_cPt_V4;
1712 case Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4 :
1713 case Hexagon::STrih_indexed_shl_cNotPt_nv_V4 :
1714 case Hexagon::STrih_indexed_shl_cdnNotPt_V4 :
1715 return Hexagon::STrih_indexed_shl_cNotPt_V4;
1717 case Hexagon::POST_SThri_cdnPt_nv_V4 :
1718 case Hexagon::POST_SThri_cPt_nv_V4 :
1719 case Hexagon::POST_SThri_cdnPt_V4 :
1720 return Hexagon::POST_SThri_cPt;
1722 case Hexagon::POST_SThri_cdnNotPt_nv_V4 :
1723 case Hexagon::POST_SThri_cNotPt_nv_V4 :
1724 case Hexagon::POST_SThri_cdnNotPt_V4 :
1725 return Hexagon::POST_SThri_cNotPt;
1727 case Hexagon::STh_GP_cdnPt_nv_V4:
1728 case Hexagon::STh_GP_cdnPt_V4:
1729 case Hexagon::STh_GP_cPt_nv_V4:
1730 return Hexagon::STh_GP_cPt_V4;
1732 case Hexagon::STh_GP_cdnNotPt_nv_V4:
1733 case Hexagon::STh_GP_cdnNotPt_V4:
1734 case Hexagon::STh_GP_cNotPt_nv_V4:
1735 return Hexagon::STh_GP_cNotPt_V4;
1737 // Store new-value halfword - unconditional
1739 case Hexagon::STrih_nv_V4:
1740 return Hexagon::STrih;
1742 case Hexagon::STrih_indexed_nv_V4:
1743 return Hexagon::STrih_indexed;
1745 case Hexagon::STrih_indexed_shl_nv_V4:
1746 return Hexagon::STrih_indexed_shl_V4;
1748 case Hexagon::STrih_shl_nv_V4:
1749 return Hexagon::STrih_shl_V4;
1751 case Hexagon::STh_GP_nv_V4:
1752 return Hexagon::STh_GP_V4;
1754 case Hexagon::POST_SThri_nv_V4:
1755 return Hexagon::POST_SThri;
1759 case Hexagon::STriw_imm_cdnPt_V4 :
1760 return Hexagon::STriw_imm_cPt_V4;
1762 case Hexagon::STriw_imm_cdnNotPt_V4 :
1763 return Hexagon::STriw_imm_cNotPt_V4;
1765 case Hexagon::STriw_cdnPt_nv_V4 :
1766 case Hexagon::STriw_cPt_nv_V4 :
1767 case Hexagon::STriw_cdnPt_V4 :
1768 return Hexagon::STriw_cPt;
1770 case Hexagon::STriw_cdnNotPt_nv_V4 :
1771 case Hexagon::STriw_cNotPt_nv_V4 :
1772 case Hexagon::STriw_cdnNotPt_V4 :
1773 return Hexagon::STriw_cNotPt;
1775 case Hexagon::STriw_indexed_cdnPt_nv_V4 :
1776 case Hexagon::STriw_indexed_cPt_nv_V4 :
1777 case Hexagon::STriw_indexed_cdnPt_V4 :
1778 return Hexagon::STriw_indexed_cPt;
1780 case Hexagon::STriw_indexed_cdnNotPt_nv_V4 :
1781 case Hexagon::STriw_indexed_cNotPt_nv_V4 :
1782 case Hexagon::STriw_indexed_cdnNotPt_V4 :
1783 return Hexagon::STriw_indexed_cNotPt;
1785 case Hexagon::STriw_indexed_shl_cdnPt_nv_V4 :
1786 case Hexagon::STriw_indexed_shl_cPt_nv_V4 :
1787 case Hexagon::STriw_indexed_shl_cdnPt_V4 :
1788 return Hexagon::STriw_indexed_shl_cPt_V4;
1790 case Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4 :
1791 case Hexagon::STriw_indexed_shl_cNotPt_nv_V4 :
1792 case Hexagon::STriw_indexed_shl_cdnNotPt_V4 :
1793 return Hexagon::STriw_indexed_shl_cNotPt_V4;
1795 case Hexagon::POST_STwri_cdnPt_nv_V4 :
1796 case Hexagon::POST_STwri_cPt_nv_V4 :
1797 case Hexagon::POST_STwri_cdnPt_V4 :
1798 return Hexagon::POST_STwri_cPt;
1800 case Hexagon::POST_STwri_cdnNotPt_nv_V4 :
1801 case Hexagon::POST_STwri_cNotPt_nv_V4 :
1802 case Hexagon::POST_STwri_cdnNotPt_V4 :
1803 return Hexagon::POST_STwri_cNotPt;
1805 case Hexagon::STw_GP_cdnPt_nv_V4:
1806 case Hexagon::STw_GP_cdnPt_V4:
1807 case Hexagon::STw_GP_cPt_nv_V4:
1808 return Hexagon::STw_GP_cPt_V4;
1810 case Hexagon::STw_GP_cdnNotPt_nv_V4:
1811 case Hexagon::STw_GP_cdnNotPt_V4:
1812 case Hexagon::STw_GP_cNotPt_nv_V4:
1813 return Hexagon::STw_GP_cNotPt_V4;
1815 // Store new-value word - unconditional
1817 case Hexagon::STriw_nv_V4:
1818 return Hexagon::STriw;
1820 case Hexagon::STriw_indexed_nv_V4:
1821 return Hexagon::STriw_indexed;
1823 case Hexagon::STriw_indexed_shl_nv_V4:
1824 return Hexagon::STriw_indexed_shl_V4;
1826 case Hexagon::STriw_shl_nv_V4:
1827 return Hexagon::STriw_shl_V4;
1829 case Hexagon::STw_GP_nv_V4:
1830 return Hexagon::STw_GP_V4;
1832 case Hexagon::POST_STwri_nv_V4:
1833 return Hexagon::POST_STwri;
1837 case Hexagon::STrid_cdnPt_V4 :
1838 return Hexagon::STrid_cPt;
1840 case Hexagon::STrid_cdnNotPt_V4 :
1841 return Hexagon::STrid_cNotPt;
1843 case Hexagon::STrid_indexed_cdnPt_V4 :
1844 return Hexagon::STrid_indexed_cPt;
1846 case Hexagon::STrid_indexed_cdnNotPt_V4 :
1847 return Hexagon::STrid_indexed_cNotPt;
1849 case Hexagon::STrid_indexed_shl_cdnPt_V4 :
1850 return Hexagon::STrid_indexed_shl_cPt_V4;
1852 case Hexagon::STrid_indexed_shl_cdnNotPt_V4 :
1853 return Hexagon::STrid_indexed_shl_cNotPt_V4;
1855 case Hexagon::POST_STdri_cdnPt_V4 :
1856 return Hexagon::POST_STdri_cPt;
1858 case Hexagon::POST_STdri_cdnNotPt_V4 :
1859 return Hexagon::POST_STdri_cNotPt;
1861 case Hexagon::STd_GP_cdnPt_V4 :
1862 return Hexagon::STd_GP_cPt_V4;
1864 case Hexagon::STd_GP_cdnNotPt_V4 :
1865 return Hexagon::STd_GP_cNotPt_V4;
1870 bool HexagonPacketizerList::DemoteToDotOld(MachineInstr* MI) {
1871 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1872 int NewOpcode = GetDotOldOp(MI->getOpcode());
1873 MI->setDesc(QII->get(NewOpcode));
1877 // Returns true if an instruction is predicated on p0 and false if it's
1878 // predicated on !p0.
1880 static bool GetPredicateSense(MachineInstr* MI,
1881 const HexagonInstrInfo *QII) {
1883 switch (MI->getOpcode()) {
1884 default: llvm_unreachable("Unknown predicate sense of the instruction");
1885 case Hexagon::TFR_cPt:
1886 case Hexagon::TFR_cdnPt:
1887 case Hexagon::TFRI_cPt:
1888 case Hexagon::TFRI_cdnPt:
1889 case Hexagon::STrib_cPt :
1890 case Hexagon::STrib_cdnPt_V4 :
1891 case Hexagon::STrib_indexed_cPt :
1892 case Hexagon::STrib_indexed_cdnPt_V4 :
1893 case Hexagon::STrib_indexed_shl_cPt_V4 :
1894 case Hexagon::STrib_indexed_shl_cdnPt_V4 :
1895 case Hexagon::POST_STbri_cPt :
1896 case Hexagon::POST_STbri_cdnPt_V4 :
1897 case Hexagon::STrih_cPt :
1898 case Hexagon::STrih_cdnPt_V4 :
1899 case Hexagon::STrih_indexed_cPt :
1900 case Hexagon::STrih_indexed_cdnPt_V4 :
1901 case Hexagon::STrih_indexed_shl_cPt_V4 :
1902 case Hexagon::STrih_indexed_shl_cdnPt_V4 :
1903 case Hexagon::POST_SThri_cPt :
1904 case Hexagon::POST_SThri_cdnPt_V4 :
1905 case Hexagon::STriw_cPt :
1906 case Hexagon::STriw_cdnPt_V4 :
1907 case Hexagon::STriw_indexed_cPt :
1908 case Hexagon::STriw_indexed_cdnPt_V4 :
1909 case Hexagon::STriw_indexed_shl_cPt_V4 :
1910 case Hexagon::STriw_indexed_shl_cdnPt_V4 :
1911 case Hexagon::POST_STwri_cPt :
1912 case Hexagon::POST_STwri_cdnPt_V4 :
1913 case Hexagon::STrib_imm_cPt_V4 :
1914 case Hexagon::STrib_imm_cdnPt_V4 :
1915 case Hexagon::STrid_cPt :
1916 case Hexagon::STrid_cdnPt_V4 :
1917 case Hexagon::STrid_indexed_cPt :
1918 case Hexagon::STrid_indexed_cdnPt_V4 :
1919 case Hexagon::STrid_indexed_shl_cPt_V4 :
1920 case Hexagon::STrid_indexed_shl_cdnPt_V4 :
1921 case Hexagon::POST_STdri_cPt :
1922 case Hexagon::POST_STdri_cdnPt_V4 :
1923 case Hexagon::STrih_imm_cPt_V4 :
1924 case Hexagon::STrih_imm_cdnPt_V4 :
1925 case Hexagon::STriw_imm_cPt_V4 :
1926 case Hexagon::STriw_imm_cdnPt_V4 :
1927 case Hexagon::JMP_cdnPt :
1928 case Hexagon::LDrid_cPt :
1929 case Hexagon::LDrid_cdnPt :
1930 case Hexagon::LDrid_indexed_cPt :
1931 case Hexagon::LDrid_indexed_cdnPt :
1932 case Hexagon::POST_LDrid_cPt :
1933 case Hexagon::POST_LDrid_cdnPt_V4 :
1934 case Hexagon::LDriw_cPt :
1935 case Hexagon::LDriw_cdnPt :
1936 case Hexagon::LDriw_indexed_cPt :
1937 case Hexagon::LDriw_indexed_cdnPt :
1938 case Hexagon::POST_LDriw_cPt :
1939 case Hexagon::POST_LDriw_cdnPt_V4 :
1940 case Hexagon::LDrih_cPt :
1941 case Hexagon::LDrih_cdnPt :
1942 case Hexagon::LDrih_indexed_cPt :
1943 case Hexagon::LDrih_indexed_cdnPt :
1944 case Hexagon::POST_LDrih_cPt :
1945 case Hexagon::POST_LDrih_cdnPt_V4 :
1946 case Hexagon::LDrib_cPt :
1947 case Hexagon::LDrib_cdnPt :
1948 case Hexagon::LDrib_indexed_cPt :
1949 case Hexagon::LDrib_indexed_cdnPt :
1950 case Hexagon::POST_LDrib_cPt :
1951 case Hexagon::POST_LDrib_cdnPt_V4 :
1952 case Hexagon::LDriuh_cPt :
1953 case Hexagon::LDriuh_cdnPt :
1954 case Hexagon::LDriuh_indexed_cPt :
1955 case Hexagon::LDriuh_indexed_cdnPt :
1956 case Hexagon::POST_LDriuh_cPt :
1957 case Hexagon::POST_LDriuh_cdnPt_V4 :
1958 case Hexagon::LDriub_cPt :
1959 case Hexagon::LDriub_cdnPt :
1960 case Hexagon::LDriub_indexed_cPt :
1961 case Hexagon::LDriub_indexed_cdnPt :
1962 case Hexagon::POST_LDriub_cPt :
1963 case Hexagon::POST_LDriub_cdnPt_V4 :
1964 case Hexagon::LDrid_indexed_shl_cPt_V4 :
1965 case Hexagon::LDrid_indexed_shl_cdnPt_V4 :
1966 case Hexagon::LDrib_indexed_shl_cPt_V4 :
1967 case Hexagon::LDrib_indexed_shl_cdnPt_V4 :
1968 case Hexagon::LDriub_indexed_shl_cPt_V4 :
1969 case Hexagon::LDriub_indexed_shl_cdnPt_V4 :
1970 case Hexagon::LDrih_indexed_shl_cPt_V4 :
1971 case Hexagon::LDrih_indexed_shl_cdnPt_V4 :
1972 case Hexagon::LDriuh_indexed_shl_cPt_V4 :
1973 case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :
1974 case Hexagon::LDriw_indexed_shl_cPt_V4 :
1975 case Hexagon::LDriw_indexed_shl_cdnPt_V4 :
1976 case Hexagon::ADD_ri_cPt :
1977 case Hexagon::ADD_ri_cdnPt :
1978 case Hexagon::ADD_rr_cPt :
1979 case Hexagon::ADD_rr_cdnPt :
1980 case Hexagon::XOR_rr_cPt :
1981 case Hexagon::XOR_rr_cdnPt :
1982 case Hexagon::AND_rr_cPt :
1983 case Hexagon::AND_rr_cdnPt :
1984 case Hexagon::OR_rr_cPt :
1985 case Hexagon::OR_rr_cdnPt :
1986 case Hexagon::SUB_rr_cPt :
1987 case Hexagon::SUB_rr_cdnPt :
1988 case Hexagon::COMBINE_rr_cPt :
1989 case Hexagon::COMBINE_rr_cdnPt :
1990 case Hexagon::ASLH_cPt_V4 :
1991 case Hexagon::ASLH_cdnPt_V4 :
1992 case Hexagon::ASRH_cPt_V4 :
1993 case Hexagon::ASRH_cdnPt_V4 :
1994 case Hexagon::SXTB_cPt_V4 :
1995 case Hexagon::SXTB_cdnPt_V4 :
1996 case Hexagon::SXTH_cPt_V4 :
1997 case Hexagon::SXTH_cdnPt_V4 :
1998 case Hexagon::ZXTB_cPt_V4 :
1999 case Hexagon::ZXTB_cdnPt_V4 :
2000 case Hexagon::ZXTH_cPt_V4 :
2001 case Hexagon::ZXTH_cdnPt_V4 :
2002 case Hexagon::LDd_GP_cPt_V4 :
2003 case Hexagon::LDb_GP_cPt_V4 :
2004 case Hexagon::LDub_GP_cPt_V4 :
2005 case Hexagon::LDh_GP_cPt_V4 :
2006 case Hexagon::LDuh_GP_cPt_V4 :
2007 case Hexagon::LDw_GP_cPt_V4 :
2008 case Hexagon::STd_GP_cPt_V4 :
2009 case Hexagon::STb_GP_cPt_V4 :
2010 case Hexagon::STh_GP_cPt_V4 :
2011 case Hexagon::STw_GP_cPt_V4 :
2012 case Hexagon::LDd_GP_cdnPt_V4 :
2013 case Hexagon::LDb_GP_cdnPt_V4 :
2014 case Hexagon::LDub_GP_cdnPt_V4 :
2015 case Hexagon::LDh_GP_cdnPt_V4 :
2016 case Hexagon::LDuh_GP_cdnPt_V4 :
2017 case Hexagon::LDw_GP_cdnPt_V4 :
2018 case Hexagon::STd_GP_cdnPt_V4 :
2019 case Hexagon::STb_GP_cdnPt_V4 :
2020 case Hexagon::STh_GP_cdnPt_V4 :
2021 case Hexagon::STw_GP_cdnPt_V4 :
2024 case Hexagon::TFR_cNotPt:
2025 case Hexagon::TFR_cdnNotPt:
2026 case Hexagon::TFRI_cNotPt:
2027 case Hexagon::TFRI_cdnNotPt:
2028 case Hexagon::STrib_cNotPt :
2029 case Hexagon::STrib_cdnNotPt_V4 :
2030 case Hexagon::STrib_indexed_cNotPt :
2031 case Hexagon::STrib_indexed_cdnNotPt_V4 :
2032 case Hexagon::STrib_indexed_shl_cNotPt_V4 :
2033 case Hexagon::STrib_indexed_shl_cdnNotPt_V4 :
2034 case Hexagon::POST_STbri_cNotPt :
2035 case Hexagon::POST_STbri_cdnNotPt_V4 :
2036 case Hexagon::STrih_cNotPt :
2037 case Hexagon::STrih_cdnNotPt_V4 :
2038 case Hexagon::STrih_indexed_cNotPt :
2039 case Hexagon::STrih_indexed_cdnNotPt_V4 :
2040 case Hexagon::STrih_indexed_shl_cNotPt_V4 :
2041 case Hexagon::STrih_indexed_shl_cdnNotPt_V4 :
2042 case Hexagon::POST_SThri_cNotPt :
2043 case Hexagon::POST_SThri_cdnNotPt_V4 :
2044 case Hexagon::STriw_cNotPt :
2045 case Hexagon::STriw_cdnNotPt_V4 :
2046 case Hexagon::STriw_indexed_cNotPt :
2047 case Hexagon::STriw_indexed_cdnNotPt_V4 :
2048 case Hexagon::STriw_indexed_shl_cNotPt_V4 :
2049 case Hexagon::STriw_indexed_shl_cdnNotPt_V4 :
2050 case Hexagon::POST_STwri_cNotPt :
2051 case Hexagon::POST_STwri_cdnNotPt_V4 :
2052 case Hexagon::STrib_imm_cNotPt_V4 :
2053 case Hexagon::STrib_imm_cdnNotPt_V4 :
2054 case Hexagon::STrid_cNotPt :
2055 case Hexagon::STrid_cdnNotPt_V4 :
2056 case Hexagon::STrid_indexed_cdnNotPt_V4 :
2057 case Hexagon::STrid_indexed_cNotPt :
2058 case Hexagon::STrid_indexed_shl_cNotPt_V4 :
2059 case Hexagon::STrid_indexed_shl_cdnNotPt_V4 :
2060 case Hexagon::POST_STdri_cNotPt :
2061 case Hexagon::POST_STdri_cdnNotPt_V4 :
2062 case Hexagon::STrih_imm_cNotPt_V4 :
2063 case Hexagon::STrih_imm_cdnNotPt_V4 :
2064 case Hexagon::STriw_imm_cNotPt_V4 :
2065 case Hexagon::STriw_imm_cdnNotPt_V4 :
2066 case Hexagon::JMP_cdnNotPt :
2067 case Hexagon::LDrid_cNotPt :
2068 case Hexagon::LDrid_cdnNotPt :
2069 case Hexagon::LDrid_indexed_cNotPt :
2070 case Hexagon::LDrid_indexed_cdnNotPt :
2071 case Hexagon::POST_LDrid_cNotPt :
2072 case Hexagon::POST_LDrid_cdnNotPt_V4 :
2073 case Hexagon::LDriw_cNotPt :
2074 case Hexagon::LDriw_cdnNotPt :
2075 case Hexagon::LDriw_indexed_cNotPt :
2076 case Hexagon::LDriw_indexed_cdnNotPt :
2077 case Hexagon::POST_LDriw_cNotPt :
2078 case Hexagon::POST_LDriw_cdnNotPt_V4 :
2079 case Hexagon::LDrih_cNotPt :
2080 case Hexagon::LDrih_cdnNotPt :
2081 case Hexagon::LDrih_indexed_cNotPt :
2082 case Hexagon::LDrih_indexed_cdnNotPt :
2083 case Hexagon::POST_LDrih_cNotPt :
2084 case Hexagon::POST_LDrih_cdnNotPt_V4 :
2085 case Hexagon::LDrib_cNotPt :
2086 case Hexagon::LDrib_cdnNotPt :
2087 case Hexagon::LDrib_indexed_cNotPt :
2088 case Hexagon::LDrib_indexed_cdnNotPt :
2089 case Hexagon::POST_LDrib_cNotPt :
2090 case Hexagon::POST_LDrib_cdnNotPt_V4 :
2091 case Hexagon::LDriuh_cNotPt :
2092 case Hexagon::LDriuh_cdnNotPt :
2093 case Hexagon::LDriuh_indexed_cNotPt :
2094 case Hexagon::LDriuh_indexed_cdnNotPt :
2095 case Hexagon::POST_LDriuh_cNotPt :
2096 case Hexagon::POST_LDriuh_cdnNotPt_V4 :
2097 case Hexagon::LDriub_cNotPt :
2098 case Hexagon::LDriub_cdnNotPt :
2099 case Hexagon::LDriub_indexed_cNotPt :
2100 case Hexagon::LDriub_indexed_cdnNotPt :
2101 case Hexagon::POST_LDriub_cNotPt :
2102 case Hexagon::POST_LDriub_cdnNotPt_V4 :
2103 case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
2104 case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :
2105 case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
2106 case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :
2107 case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
2108 case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :
2109 case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
2110 case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :
2111 case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
2112 case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :
2113 case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
2114 case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :
2115 case Hexagon::ADD_ri_cNotPt :
2116 case Hexagon::ADD_ri_cdnNotPt :
2117 case Hexagon::ADD_rr_cNotPt :
2118 case Hexagon::ADD_rr_cdnNotPt :
2119 case Hexagon::XOR_rr_cNotPt :
2120 case Hexagon::XOR_rr_cdnNotPt :
2121 case Hexagon::AND_rr_cNotPt :
2122 case Hexagon::AND_rr_cdnNotPt :
2123 case Hexagon::OR_rr_cNotPt :
2124 case Hexagon::OR_rr_cdnNotPt :
2125 case Hexagon::SUB_rr_cNotPt :
2126 case Hexagon::SUB_rr_cdnNotPt :
2127 case Hexagon::COMBINE_rr_cNotPt :
2128 case Hexagon::COMBINE_rr_cdnNotPt :
2129 case Hexagon::ASLH_cNotPt_V4 :
2130 case Hexagon::ASLH_cdnNotPt_V4 :
2131 case Hexagon::ASRH_cNotPt_V4 :
2132 case Hexagon::ASRH_cdnNotPt_V4 :
2133 case Hexagon::SXTB_cNotPt_V4 :
2134 case Hexagon::SXTB_cdnNotPt_V4 :
2135 case Hexagon::SXTH_cNotPt_V4 :
2136 case Hexagon::SXTH_cdnNotPt_V4 :
2137 case Hexagon::ZXTB_cNotPt_V4 :
2138 case Hexagon::ZXTB_cdnNotPt_V4 :
2139 case Hexagon::ZXTH_cNotPt_V4 :
2140 case Hexagon::ZXTH_cdnNotPt_V4 :
2142 case Hexagon::LDd_GP_cNotPt_V4 :
2143 case Hexagon::LDb_GP_cNotPt_V4 :
2144 case Hexagon::LDub_GP_cNotPt_V4 :
2145 case Hexagon::LDh_GP_cNotPt_V4 :
2146 case Hexagon::LDuh_GP_cNotPt_V4 :
2147 case Hexagon::LDw_GP_cNotPt_V4 :
2148 case Hexagon::STd_GP_cNotPt_V4 :
2149 case Hexagon::STb_GP_cNotPt_V4 :
2150 case Hexagon::STh_GP_cNotPt_V4 :
2151 case Hexagon::STw_GP_cNotPt_V4 :
2152 case Hexagon::LDd_GP_cdnNotPt_V4 :
2153 case Hexagon::LDb_GP_cdnNotPt_V4 :
2154 case Hexagon::LDub_GP_cdnNotPt_V4 :
2155 case Hexagon::LDh_GP_cdnNotPt_V4 :
2156 case Hexagon::LDuh_GP_cdnNotPt_V4 :
2157 case Hexagon::LDw_GP_cdnNotPt_V4 :
2158 case Hexagon::STd_GP_cdnNotPt_V4 :
2159 case Hexagon::STb_GP_cdnNotPt_V4 :
2160 case Hexagon::STh_GP_cdnNotPt_V4 :
2161 case Hexagon::STw_GP_cdnNotPt_V4 :
2164 // return *some value* to avoid compiler warning
2168 bool HexagonPacketizerList::isDotNewInst(MachineInstr* MI) {
2169 if (isNewValueInst(MI))
2172 switch (MI->getOpcode()) {
2173 case Hexagon::TFR_cdnNotPt:
2174 case Hexagon::TFR_cdnPt:
2175 case Hexagon::TFRI_cdnNotPt:
2176 case Hexagon::TFRI_cdnPt:
2177 case Hexagon::LDrid_cdnPt :
2178 case Hexagon::LDrid_cdnNotPt :
2179 case Hexagon::LDrid_indexed_cdnPt :
2180 case Hexagon::LDrid_indexed_cdnNotPt :
2181 case Hexagon::POST_LDrid_cdnPt_V4 :
2182 case Hexagon::POST_LDrid_cdnNotPt_V4 :
2183 case Hexagon::LDriw_cdnPt :
2184 case Hexagon::LDriw_cdnNotPt :
2185 case Hexagon::LDriw_indexed_cdnPt :
2186 case Hexagon::LDriw_indexed_cdnNotPt :
2187 case Hexagon::POST_LDriw_cdnPt_V4 :
2188 case Hexagon::POST_LDriw_cdnNotPt_V4 :
2189 case Hexagon::LDrih_cdnPt :
2190 case Hexagon::LDrih_cdnNotPt :
2191 case Hexagon::LDrih_indexed_cdnPt :
2192 case Hexagon::LDrih_indexed_cdnNotPt :
2193 case Hexagon::POST_LDrih_cdnPt_V4 :
2194 case Hexagon::POST_LDrih_cdnNotPt_V4 :
2195 case Hexagon::LDrib_cdnPt :
2196 case Hexagon::LDrib_cdnNotPt :
2197 case Hexagon::LDrib_indexed_cdnPt :
2198 case Hexagon::LDrib_indexed_cdnNotPt :
2199 case Hexagon::POST_LDrib_cdnPt_V4 :
2200 case Hexagon::POST_LDrib_cdnNotPt_V4 :
2201 case Hexagon::LDriuh_cdnPt :
2202 case Hexagon::LDriuh_cdnNotPt :
2203 case Hexagon::LDriuh_indexed_cdnPt :
2204 case Hexagon::LDriuh_indexed_cdnNotPt :
2205 case Hexagon::POST_LDriuh_cdnPt_V4 :
2206 case Hexagon::POST_LDriuh_cdnNotPt_V4 :
2207 case Hexagon::LDriub_cdnPt :
2208 case Hexagon::LDriub_cdnNotPt :
2209 case Hexagon::LDriub_indexed_cdnPt :
2210 case Hexagon::LDriub_indexed_cdnNotPt :
2211 case Hexagon::POST_LDriub_cdnPt_V4 :
2212 case Hexagon::POST_LDriub_cdnNotPt_V4 :
2214 case Hexagon::LDrid_indexed_shl_cdnPt_V4 :
2215 case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :
2216 case Hexagon::LDrib_indexed_shl_cdnPt_V4 :
2217 case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :
2218 case Hexagon::LDriub_indexed_shl_cdnPt_V4 :
2219 case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :
2220 case Hexagon::LDrih_indexed_shl_cdnPt_V4 :
2221 case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :
2222 case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :
2223 case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :
2224 case Hexagon::LDriw_indexed_shl_cdnPt_V4 :
2225 case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :
2228 case Hexagon::ADD_ri_cdnPt:
2229 case Hexagon::ADD_ri_cdnNotPt:
2230 case Hexagon::ADD_rr_cdnPt:
2231 case Hexagon::ADD_rr_cdnNotPt:
2233 // Conditional logical operations
2234 case Hexagon::XOR_rr_cdnPt :
2235 case Hexagon::XOR_rr_cdnNotPt :
2236 case Hexagon::AND_rr_cdnPt :
2237 case Hexagon::AND_rr_cdnNotPt :
2238 case Hexagon::OR_rr_cdnPt :
2239 case Hexagon::OR_rr_cdnNotPt :
2241 // Conditonal subtract
2242 case Hexagon::SUB_rr_cdnPt :
2243 case Hexagon::SUB_rr_cdnNotPt :
2245 // Conditional combine
2246 case Hexagon::COMBINE_rr_cdnPt :
2247 case Hexagon::COMBINE_rr_cdnNotPt :
2249 // Conditional shift operations
2250 case Hexagon::ASLH_cdnPt_V4:
2251 case Hexagon::ASLH_cdnNotPt_V4:
2252 case Hexagon::ASRH_cdnPt_V4:
2253 case Hexagon::ASRH_cdnNotPt_V4:
2254 case Hexagon::SXTB_cdnPt_V4:
2255 case Hexagon::SXTB_cdnNotPt_V4:
2256 case Hexagon::SXTH_cdnPt_V4:
2257 case Hexagon::SXTH_cdnNotPt_V4:
2258 case Hexagon::ZXTB_cdnPt_V4:
2259 case Hexagon::ZXTB_cdnNotPt_V4:
2260 case Hexagon::ZXTH_cdnPt_V4:
2261 case Hexagon::ZXTH_cdnNotPt_V4:
2263 // Conditional stores
2264 case Hexagon::STrib_imm_cdnPt_V4 :
2265 case Hexagon::STrib_imm_cdnNotPt_V4 :
2266 case Hexagon::STrib_cdnPt_V4 :
2267 case Hexagon::STrib_cdnNotPt_V4 :
2268 case Hexagon::STrib_indexed_cdnPt_V4 :
2269 case Hexagon::STrib_indexed_cdnNotPt_V4 :
2270 case Hexagon::POST_STbri_cdnPt_V4 :
2271 case Hexagon::POST_STbri_cdnNotPt_V4 :
2272 case Hexagon::STrib_indexed_shl_cdnPt_V4 :
2273 case Hexagon::STrib_indexed_shl_cdnNotPt_V4 :
2275 // Store doubleword conditionally
2276 case Hexagon::STrid_indexed_cdnPt_V4 :
2277 case Hexagon::STrid_indexed_cdnNotPt_V4 :
2278 case Hexagon::STrid_indexed_shl_cdnPt_V4 :
2279 case Hexagon::STrid_indexed_shl_cdnNotPt_V4 :
2280 case Hexagon::POST_STdri_cdnPt_V4 :
2281 case Hexagon::POST_STdri_cdnNotPt_V4 :
2283 // Store halfword conditionally
2284 case Hexagon::STrih_cdnPt_V4 :
2285 case Hexagon::STrih_cdnNotPt_V4 :
2286 case Hexagon::STrih_indexed_cdnPt_V4 :
2287 case Hexagon::STrih_indexed_cdnNotPt_V4 :
2288 case Hexagon::STrih_imm_cdnPt_V4 :
2289 case Hexagon::STrih_imm_cdnNotPt_V4 :
2290 case Hexagon::STrih_indexed_shl_cdnPt_V4 :
2291 case Hexagon::STrih_indexed_shl_cdnNotPt_V4 :
2292 case Hexagon::POST_SThri_cdnPt_V4 :
2293 case Hexagon::POST_SThri_cdnNotPt_V4 :
2295 // Store word conditionally
2296 case Hexagon::STriw_cdnPt_V4 :
2297 case Hexagon::STriw_cdnNotPt_V4 :
2298 case Hexagon::STriw_indexed_cdnPt_V4 :
2299 case Hexagon::STriw_indexed_cdnNotPt_V4 :
2300 case Hexagon::STriw_imm_cdnPt_V4 :
2301 case Hexagon::STriw_imm_cdnNotPt_V4 :
2302 case Hexagon::STriw_indexed_shl_cdnPt_V4 :
2303 case Hexagon::STriw_indexed_shl_cdnNotPt_V4 :
2304 case Hexagon::POST_STwri_cdnPt_V4 :
2305 case Hexagon::POST_STwri_cdnNotPt_V4 :
2307 case Hexagon::LDd_GP_cdnPt_V4:
2308 case Hexagon::LDd_GP_cdnNotPt_V4:
2309 case Hexagon::LDb_GP_cdnPt_V4:
2310 case Hexagon::LDb_GP_cdnNotPt_V4:
2311 case Hexagon::LDub_GP_cdnPt_V4:
2312 case Hexagon::LDub_GP_cdnNotPt_V4:
2313 case Hexagon::LDh_GP_cdnPt_V4:
2314 case Hexagon::LDh_GP_cdnNotPt_V4:
2315 case Hexagon::LDuh_GP_cdnPt_V4:
2316 case Hexagon::LDuh_GP_cdnNotPt_V4:
2317 case Hexagon::LDw_GP_cdnPt_V4:
2318 case Hexagon::LDw_GP_cdnNotPt_V4:
2320 case Hexagon::STd_GP_cdnPt_V4:
2321 case Hexagon::STd_GP_cdnNotPt_V4:
2322 case Hexagon::STb_GP_cdnPt_V4:
2323 case Hexagon::STb_GP_cdnNotPt_V4:
2324 case Hexagon::STh_GP_cdnPt_V4:
2325 case Hexagon::STh_GP_cdnNotPt_V4:
2326 case Hexagon::STw_GP_cdnPt_V4:
2327 case Hexagon::STw_GP_cdnNotPt_V4:
2333 static MachineOperand& GetPostIncrementOperand(MachineInstr *MI,
2334 const HexagonInstrInfo *QII) {
2335 assert(QII->isPostIncrement(MI) && "Not a post increment operation.");
2337 // Post Increment means duplicates. Use dense map to find duplicates in the
2338 // list. Caution: Densemap initializes with the minimum of 64 buckets,
2339 // whereas there are at most 5 operands in the post increment.
2340 DenseMap<unsigned, unsigned> DefRegsSet;
2341 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++)
2342 if (MI->getOperand(opNum).isReg() &&
2343 MI->getOperand(opNum).isDef()) {
2344 DefRegsSet[MI->getOperand(opNum).getReg()] = 1;
2347 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++)
2348 if (MI->getOperand(opNum).isReg() &&
2349 MI->getOperand(opNum).isUse()) {
2350 if (DefRegsSet[MI->getOperand(opNum).getReg()]) {
2351 return MI->getOperand(opNum);
2355 if (MI->getDesc().mayLoad()) {
2356 // The 2nd operand is always the post increment operand in load.
2357 assert(MI->getOperand(1).isReg() &&
2358 "Post increment operand has be to a register.");
2359 return (MI->getOperand(1));
2361 if (MI->getDesc().mayStore()) {
2362 // The 1st operand is always the post increment operand in store.
2363 assert(MI->getOperand(0).isReg() &&
2364 "Post increment operand has be to a register.");
2365 return (MI->getOperand(0));
2368 // we should never come here.
2369 llvm_unreachable("mayLoad or mayStore not set for Post Increment operation");
2372 // get the value being stored
2373 static MachineOperand& GetStoreValueOperand(MachineInstr *MI) {
2374 // value being stored is always the last operand.
2375 return (MI->getOperand(MI->getNumOperands()-1));
2378 // can be new value store?
2379 // Following restrictions are to be respected in convert a store into
2380 // a new value store.
2381 // 1. If an instruction uses auto-increment, its address register cannot
2382 // be a new-value register. Arch Spec 5.4.2.1
2383 // 2. If an instruction uses absolute-set addressing mode,
2384 // its address register cannot be a new-value register.
2385 // Arch Spec 5.4.2.1.TODO: This is not enabled as
2386 // as absolute-set address mode patters are not implemented.
2387 // 3. If an instruction produces a 64-bit result, its registers cannot be used
2388 // as new-value registers. Arch Spec 5.4.2.2.
2389 // 4. If the instruction that sets a new-value register is conditional, then
2390 // the instruction that uses the new-value register must also be conditional,
2391 // and both must always have their predicates evaluate identically.
2392 // Arch Spec 5.4.2.3.
2393 // 5. There is an implied restriction of a packet can not have another store,
2394 // if there is a new value store in the packet. Corollary, if there is
2395 // already a store in a packet, there can not be a new value store.
2396 // Arch Spec: 3.4.4.2
2397 bool HexagonPacketizerList::CanPromoteToNewValueStore( MachineInstr *MI,
2398 MachineInstr *PacketMI, unsigned DepReg,
2399 std::map <MachineInstr*, SUnit*> MIToSUnit)
2401 // Make sure we are looking at the store
2402 if (!IsNewifyStore(MI))
2405 // Make sure there is dependency and can be new value'ed
2406 if (GetStoreValueOperand(MI).isReg() &&
2407 GetStoreValueOperand(MI).getReg() != DepReg)
2410 const HexagonRegisterInfo* QRI =
2411 (const HexagonRegisterInfo *) TM.getRegisterInfo();
2412 const MCInstrDesc& MCID = PacketMI->getDesc();
2413 // first operand is always the result
2415 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
2416 const TargetRegisterClass* PacketRC = QII->getRegClass(MCID, 0, QRI, MF);
2418 // if there is already an store in the packet, no can do new value store
2419 // Arch Spec 3.4.4.2.
2420 for (std::vector<MachineInstr*>::iterator VI = CurrentPacketMIs.begin(),
2421 VE = CurrentPacketMIs.end();
2423 SUnit* PacketSU = MIToSUnit[*VI];
2424 if (PacketSU->getInstr()->getDesc().mayStore() ||
2425 // if we have mayStore = 1 set on ALLOCFRAME and DEALLOCFRAME,
2426 // then we don't need this
2427 PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME ||
2428 PacketSU->getInstr()->getOpcode() == Hexagon::DEALLOCFRAME)
2432 if (PacketRC == &Hexagon::DoubleRegsRegClass) {
2433 // new value store constraint: double regs can not feed into new value store
2434 // arch spec section: 5.4.2.2
2438 // Make sure it's NOT the post increment register that we are going to
2440 if (QII->isPostIncrement(MI) &&
2441 MI->getDesc().mayStore() &&
2442 GetPostIncrementOperand(MI, QII).getReg() == DepReg) {
2446 if (QII->isPostIncrement(PacketMI) &&
2447 PacketMI->getDesc().mayLoad() &&
2448 GetPostIncrementOperand(PacketMI, QII).getReg() == DepReg) {
2449 // if source is post_inc, or absolute-set addressing,
2450 // it can not feed into new value store
2451 // r3 = memw(r2++#4)
2452 // memw(r30 + #-1404) = r2.new -> can not be new value store
2453 // arch spec section: 5.4.2.1
2457 // If the source that feeds the store is predicated, new value store must
2458 // also be also predicated.
2459 if (QII->isPredicated(PacketMI)) {
2460 if (!QII->isPredicated(MI))
2463 // Check to make sure that they both will have their predicates
2464 // evaluate identically
2465 unsigned predRegNumSrc = 0;
2466 unsigned predRegNumDst = 0;
2467 const TargetRegisterClass* predRegClass = NULL;
2469 // Get predicate register used in the source instruction
2470 for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {
2471 if ( PacketMI->getOperand(opNum).isReg())
2472 predRegNumSrc = PacketMI->getOperand(opNum).getReg();
2473 predRegClass = QRI->getMinimalPhysRegClass(predRegNumSrc);
2474 if (predRegClass == &Hexagon::PredRegsRegClass) {
2478 assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
2479 ("predicate register not found in a predicated PacketMI instruction"));
2481 // Get predicate register used in new-value store instruction
2482 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
2483 if ( MI->getOperand(opNum).isReg())
2484 predRegNumDst = MI->getOperand(opNum).getReg();
2485 predRegClass = QRI->getMinimalPhysRegClass(predRegNumDst);
2486 if (predRegClass == &Hexagon::PredRegsRegClass) {
2490 assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
2491 ("predicate register not found in a predicated MI instruction"));
2493 // New-value register producer and user (store) need to satisfy these
2495 // 1) Both instructions should be predicated on the same register.
2496 // 2) If producer of the new-value register is .new predicated then store
2497 // should also be .new predicated and if producer is not .new predicated
2498 // then store should not be .new predicated.
2499 // 3) Both new-value register producer and user should have same predicate
2500 // sense, i.e, either both should be negated or both should be none negated.
2502 if (( predRegNumDst != predRegNumSrc) ||
2503 isDotNewInst(PacketMI) != isDotNewInst(MI) ||
2504 GetPredicateSense(MI, QII) != GetPredicateSense(PacketMI, QII)) {
2509 // Make sure that other than the new-value register no other store instruction
2510 // register has been modified in the same packet. Predicate registers can be
2511 // modified by they should not be modified between the producer and the store
2512 // instruction as it will make them both conditional on different values.
2513 // We already know this to be true for all the instructions before and
2514 // including PacketMI. Howerver, we need to perform the check for the
2515 // remaining instructions in the packet.
2517 std::vector<MachineInstr*>::iterator VI;
2518 std::vector<MachineInstr*>::iterator VE;
2519 unsigned StartCheck = 0;
2521 for (VI=CurrentPacketMIs.begin(), VE = CurrentPacketMIs.end();
2523 SUnit* TempSU = MIToSUnit[*VI];
2524 MachineInstr* TempMI = TempSU->getInstr();
2526 // Following condition is true for all the instructions until PacketMI is
2527 // reached (StartCheck is set to 0 before the for loop).
2528 // StartCheck flag is 1 for all the instructions after PacketMI.
2529 if (TempMI != PacketMI && !StartCheck) // start processing only after
2530 continue; // encountering PacketMI
2533 if (TempMI == PacketMI) // We don't want to check PacketMI for dependence
2536 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
2537 if (MI->getOperand(opNum).isReg() &&
2538 TempSU->getInstr()->modifiesRegister(MI->getOperand(opNum).getReg(),
2544 // Make sure that for non POST_INC stores:
2545 // 1. The only use of reg is DepReg and no other registers.
2546 // This handles V4 base+index registers.
2547 // The following store can not be dot new.
2548 // Eg. r0 = add(r0, #3)a
2549 // memw(r1+r0<<#2) = r0
2550 if (!QII->isPostIncrement(MI) &&
2551 GetStoreValueOperand(MI).isReg() &&
2552 GetStoreValueOperand(MI).getReg() == DepReg) {
2553 for(unsigned opNum = 0; opNum < MI->getNumOperands()-1; opNum++) {
2554 if (MI->getOperand(opNum).isReg() &&
2555 MI->getOperand(opNum).getReg() == DepReg) {
2559 // 2. If data definition is because of implicit definition of the register,
2560 // do not newify the store. Eg.
2561 // %R9<def> = ZXTH %R12, %D6<imp-use>, %R12<imp-def>
2562 // STrih_indexed %R8, 2, %R12<kill>; mem:ST2[%scevgep343]
2563 for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {
2564 if (PacketMI->getOperand(opNum).isReg() &&
2565 PacketMI->getOperand(opNum).getReg() == DepReg &&
2566 PacketMI->getOperand(opNum).isDef() &&
2567 PacketMI->getOperand(opNum).isImplicit()) {
2573 // Can be dot new store.
2577 // can this MI to promoted to either
2578 // new value store or new value jump
2579 bool HexagonPacketizerList::CanPromoteToNewValue( MachineInstr *MI,
2580 SUnit *PacketSU, unsigned DepReg,
2581 std::map <MachineInstr*, SUnit*> MIToSUnit,
2582 MachineBasicBlock::iterator &MII)
2585 const HexagonRegisterInfo* QRI =
2586 (const HexagonRegisterInfo *) TM.getRegisterInfo();
2587 if (!QRI->Subtarget.hasV4TOps() ||
2591 MachineInstr *PacketMI = PacketSU->getInstr();
2593 // Check to see the store can be new value'ed.
2594 if (CanPromoteToNewValueStore(MI, PacketMI, DepReg, MIToSUnit))
2597 // Check to see the compare/jump can be new value'ed.
2598 // This is done as a pass on its own. Don't need to check it here.
2602 // Check to see if an instruction can be dot new
2603 // There are three kinds.
2604 // 1. dot new on predicate - V2/V3/V4
2605 // 2. dot new on stores NV/ST - V4
2606 // 3. dot new on jump NV/J - V4 -- This is generated in a pass.
2607 bool HexagonPacketizerList::CanPromoteToDotNew( MachineInstr *MI,
2608 SUnit *PacketSU, unsigned DepReg,
2609 std::map <MachineInstr*, SUnit*> MIToSUnit,
2610 MachineBasicBlock::iterator &MII,
2611 const TargetRegisterClass* RC )
2613 // already a dot new instruction
2614 if (isDotNewInst(MI) && !IsNewifyStore(MI))
2617 if (!isNewifiable(MI))
2621 if (RC == &Hexagon::PredRegsRegClass && isCondInst(MI))
2623 else if (RC != &Hexagon::PredRegsRegClass &&
2624 !IsNewifyStore(MI)) // MI is not a new-value store
2627 // Create a dot new machine instruction to see if resources can be
2628 // allocated. If not, bail out now.
2629 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
2630 int NewOpcode = GetDotNewOp(MI->getOpcode());
2631 const MCInstrDesc &desc = QII->get(NewOpcode);
2633 MachineInstr *NewMI =
2634 MI->getParent()->getParent()->CreateMachineInstr(desc, dl);
2635 bool ResourcesAvailable = ResourceTracker->canReserveResources(NewMI);
2636 MI->getParent()->getParent()->DeleteMachineInstr(NewMI);
2638 if (!ResourcesAvailable)
2641 // new value store only
2642 // new new value jump generated as a passes
2643 if (!CanPromoteToNewValue(MI, PacketSU, DepReg, MIToSUnit, MII)) {
2650 // Go through the packet instructions and search for anti dependency
2651 // between them and DepReg from MI
2652 // Consider this case:
2654 // a) %R1<def> = TFRI_cdNotPt %P3, 2
2657 // b) %P0<def> = OR_pp %P3<kill>, %P0<kill>
2658 // c) %P3<def> = TFR_PdRs %R23
2659 // d) %R1<def> = TFRI_cdnPt %P3, 4
2661 // The P3 from a) and d) will be complements after
2662 // a)'s P3 is converted to .new form
2663 // Anti Dep between c) and b) is irrelevant for this case
2664 bool HexagonPacketizerList::RestrictingDepExistInPacket (MachineInstr* MI,
2666 std::map <MachineInstr*, SUnit*> MIToSUnit) {
2668 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
2669 SUnit* PacketSUDep = MIToSUnit[MI];
2671 for (std::vector<MachineInstr*>::iterator VIN = CurrentPacketMIs.begin(),
2672 VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {
2674 // We only care for dependencies to predicated instructions
2675 if(!QII->isPredicated(*VIN)) continue;
2677 // Scheduling Unit for current insn in the packet
2678 SUnit* PacketSU = MIToSUnit[*VIN];
2680 // Look at dependencies between current members of the packet
2681 // and predicate defining instruction MI.
2682 // Make sure that dependency is on the exact register
2684 if (PacketSU->isSucc(PacketSUDep)) {
2685 for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
2686 if ((PacketSU->Succs[i].getSUnit() == PacketSUDep) &&
2687 (PacketSU->Succs[i].getKind() == SDep::Anti) &&
2688 (PacketSU->Succs[i].getReg() == DepReg)) {
2699 // Given two predicated instructions, this function detects whether
2700 // the predicates are complements
2701 bool HexagonPacketizerList::ArePredicatesComplements (MachineInstr* MI1,
2702 MachineInstr* MI2, std::map <MachineInstr*, SUnit*> MIToSUnit) {
2704 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
2705 // Currently can only reason about conditional transfers
2706 if (!QII->isConditionalTransfer(MI1) || !QII->isConditionalTransfer(MI2)) {
2710 // Scheduling unit for candidate
2711 SUnit* SU = MIToSUnit[MI1];
2713 // One corner case deals with the following scenario:
2715 // a) %R24<def> = TFR_cPt %P0, %R25
2719 // b) %R25<def> = TFR_cNotPt %P0, %R24
2720 // c) %P0<def> = CMPEQri %R26, 1
2723 // On general check a) and b) are complements, but
2724 // presence of c) will convert a) to .new form, and
2725 // then it is not a complement
2726 // We attempt to detect it by analyzing existing
2727 // dependencies in the packet
2729 // Analyze relationships between all existing members of the packet.
2730 // Look for Anti dependecy on the same predicate reg
2731 // as used in the candidate
2732 for (std::vector<MachineInstr*>::iterator VIN = CurrentPacketMIs.begin(),
2733 VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {
2735 // Scheduling Unit for current insn in the packet
2736 SUnit* PacketSU = MIToSUnit[*VIN];
2738 // If this instruction in the packet is succeeded by the candidate...
2739 if (PacketSU->isSucc(SU)) {
2740 for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
2741 // The corner case exist when there is true data
2742 // dependency between candidate and one of current
2743 // packet members, this dep is on predicate reg, and
2744 // there already exist anti dep on the same pred in
2746 if (PacketSU->Succs[i].getSUnit() == SU &&
2747 Hexagon::PredRegsRegClass.contains(
2748 PacketSU->Succs[i].getReg()) &&
2749 PacketSU->Succs[i].getKind() == SDep::Data &&
2750 // Here I know that *VIN is predicate setting instruction
2751 // with true data dep to candidate on the register
2752 // we care about - c) in the above example.
2753 // Now I need to see if there is an anti dependency
2754 // from c) to any other instruction in the
2755 // same packet on the pred reg of interest
2756 RestrictingDepExistInPacket(*VIN,PacketSU->Succs[i].getReg(),
2764 // If the above case does not apply, check regular
2765 // complement condition.
2766 // Check that the predicate register is the same and
2767 // that the predicate sense is different
2768 // We also need to differentiate .old vs. .new:
2769 // !p0 is not complimentary to p0.new
2770 return ((MI1->getOperand(1).getReg() == MI2->getOperand(1).getReg()) &&
2771 (GetPredicateSense(MI1, QII) != GetPredicateSense(MI2, QII)) &&
2772 (isDotNewInst(MI1) == isDotNewInst(MI2)));
2775 // initPacketizerState - Initialize packetizer flags
2776 void HexagonPacketizerList::initPacketizerState() {
2779 PromotedToDotNew = false;
2780 GlueToNewValueJump = false;
2781 GlueAllocframeStore = false;
2782 FoundSequentialDependence = false;
2787 // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
2788 bool HexagonPacketizerList::ignorePseudoInstruction(MachineInstr *MI,
2789 MachineBasicBlock *MBB) {
2790 if (MI->isDebugValue())
2793 // We must print out inline assembly
2794 if (MI->isInlineAsm())
2797 // We check if MI has any functional units mapped to it.
2798 // If it doesn't, we ignore the instruction.
2799 const MCInstrDesc& TID = MI->getDesc();
2800 unsigned SchedClass = TID.getSchedClass();
2801 const InstrStage* IS =
2802 ResourceTracker->getInstrItins()->beginStage(SchedClass);
2803 unsigned FuncUnits = IS->getUnits();
2807 // isSoloInstruction: - Returns true for instructions that must be
2808 // scheduled in their own packet.
2809 bool HexagonPacketizerList::isSoloInstruction(MachineInstr *MI) {
2811 if (MI->isInlineAsm())
2814 if (MI->isEHLabel())
2817 // From Hexagon V4 Programmer's Reference Manual 3.4.4 Grouping constraints:
2818 // trap, pause, barrier, icinva, isync, and syncht are solo instructions.
2819 // They must not be grouped with other instructions in a packet.
2820 if (IsSchedBarrier(MI))
2826 // isLegalToPacketizeTogether:
2827 // SUI is the current instruction that is out side of the current packet.
2828 // SUJ is the current instruction inside the current packet against which that
2829 // SUI will be packetized.
2830 bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
2831 MachineInstr *I = SUI->getInstr();
2832 MachineInstr *J = SUJ->getInstr();
2833 assert(I && J && "Unable to packetize null instruction!");
2835 const MCInstrDesc &MCIDI = I->getDesc();
2836 const MCInstrDesc &MCIDJ = J->getDesc();
2838 MachineBasicBlock::iterator II = I;
2840 const unsigned FrameSize = MF.getFrameInfo()->getStackSize();
2841 const HexagonRegisterInfo* QRI =
2842 (const HexagonRegisterInfo *) TM.getRegisterInfo();
2843 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
2845 // Inline asm cannot go in the packet.
2846 if (I->getOpcode() == Hexagon::INLINEASM)
2847 llvm_unreachable("Should not meet inline asm here!");
2849 if (isSoloInstruction(I))
2850 llvm_unreachable("Should not meet solo instr here!");
2852 // A save callee-save register function call can only be in a packet
2853 // with instructions that don't write to the callee-save registers.
2854 if ((QII->isSaveCalleeSavedRegsCall(I) &&
2855 DoesModifyCalleeSavedReg(J, QRI)) ||
2856 (QII->isSaveCalleeSavedRegsCall(J) &&
2857 DoesModifyCalleeSavedReg(I, QRI))) {
2862 // Two control flow instructions cannot go in the same packet.
2863 if (IsControlFlow(I) && IsControlFlow(J)) {
2868 // A LoopN instruction cannot appear in the same packet as a jump or call.
2869 if (IsLoopN(I) && ( IsDirectJump(J)
2871 || QII->isDeallocRet(J))) {
2875 if (IsLoopN(J) && ( IsDirectJump(I)
2877 || QII->isDeallocRet(I))) {
2882 // dealloc_return cannot appear in the same packet as a conditional or
2883 // unconditional jump.
2884 if (QII->isDeallocRet(I) && ( MCIDJ.isBranch()
2886 || MCIDJ.isBarrier())) {
2892 // V4 allows dual store. But does not allow second store, if the
2893 // first store is not in SLOT0. New value store, new value jump,
2894 // dealloc_return and memop always take SLOT0.
2895 // Arch spec 3.4.4.2
2896 if (QRI->Subtarget.hasV4TOps()) {
2898 if (MCIDI.mayStore() && MCIDJ.mayStore() && isNewValueInst(J)) {
2903 if ( (QII->isMemOp(J) && MCIDI.mayStore())
2904 || (MCIDJ.mayStore() && QII->isMemOp(I))
2905 || (QII->isMemOp(J) && QII->isMemOp(I))) {
2911 if (MCIDJ.mayStore() && QII->isDeallocRet(I)){
2916 // If an instruction feeds new value jump, glue it.
2917 MachineBasicBlock::iterator NextMII = I;
2919 MachineInstr *NextMI = NextMII;
2921 if (QII->isNewValueJump(NextMI)) {
2923 bool secondRegMatch = false;
2924 bool maintainNewValueJump = false;
2926 if (NextMI->getOperand(1).isReg() &&
2927 I->getOperand(0).getReg() == NextMI->getOperand(1).getReg()) {
2928 secondRegMatch = true;
2929 maintainNewValueJump = true;
2932 if (!secondRegMatch &&
2933 I->getOperand(0).getReg() == NextMI->getOperand(0).getReg()) {
2934 maintainNewValueJump = true;
2937 for (std::vector<MachineInstr*>::iterator
2938 VI = CurrentPacketMIs.begin(),
2939 VE = CurrentPacketMIs.end();
2940 (VI != VE && maintainNewValueJump); ++VI) {
2941 SUnit* PacketSU = MIToSUnit[*VI];
2943 // NVJ can not be part of the dual jump - Arch Spec: section 7.8
2944 if (PacketSU->getInstr()->getDesc().isCall()) {
2949 // 1. Packet does not have a store in it.
2950 // 2. If the first operand of the nvj is newified, and the second
2951 // operand is also a reg, it (second reg) is not defined in
2953 // 3. If the second operand of the nvj is newified, (which means
2954 // first operand is also a reg), first reg is not defined in
2956 if (PacketSU->getInstr()->getDesc().mayStore() ||
2957 PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME ||
2959 (!secondRegMatch && NextMI->getOperand(1).isReg() &&
2960 PacketSU->getInstr()->modifiesRegister(
2961 NextMI->getOperand(1).getReg(), QRI)) ||
2964 PacketSU->getInstr()->modifiesRegister(
2965 NextMI->getOperand(0).getReg(), QRI))) {
2971 GlueToNewValueJump = true;
2977 if (SUJ->isSucc(SUI)) {
2978 for (unsigned i = 0;
2979 (i < SUJ->Succs.size()) && !FoundSequentialDependence;
2982 if (SUJ->Succs[i].getSUnit() != SUI) {
2986 SDep::Kind DepType = SUJ->Succs[i].getKind();
2988 // For direct calls:
2989 // Ignore register dependences for call instructions for
2990 // packetization purposes except for those due to r31 and
2991 // predicate registers.
2993 // For indirect calls:
2994 // Same as direct calls + check for true dependences to the register
2995 // used in the indirect call.
2997 // We completely ignore Order dependences for call instructions
3000 // Ignore register dependences for return instructions like jumpr,
3001 // dealloc return unless we have dependencies on the explicit uses
3002 // of the registers used by jumpr (like r31) or dealloc return
3003 // (like r29 or r30).
3005 // TODO: Currently, jumpr is handling only return of r31. So, the
3006 // following logic (specificaly IsCallDependent) is working fine.
3007 // We need to enable jumpr for register other than r31 and then,
3008 // we need to rework the last part, where it handles indirect call
3009 // of that (IsCallDependent) function. Bug 6216 is opened for this.
3011 unsigned DepReg = 0;
3012 const TargetRegisterClass* RC = NULL;
3013 if (DepType == SDep::Data) {
3014 DepReg = SUJ->Succs[i].getReg();
3015 RC = QRI->getMinimalPhysRegClass(DepReg);
3017 if ((MCIDI.isCall() || MCIDI.isReturn()) &&
3018 (!IsRegDependence(DepType) ||
3019 !IsCallDependent(I, DepType, SUJ->Succs[i].getReg()))) {
3023 // For instructions that can be promoted to dot-new, try to promote.
3024 else if ((DepType == SDep::Data) &&
3025 CanPromoteToDotNew(I, SUJ, DepReg, MIToSUnit, II, RC) &&
3026 PromoteToDotNew(I, DepType, II, RC)) {
3027 PromotedToDotNew = true;
3031 else if ((DepType == SDep::Data) &&
3032 (QII->isNewValueJump(I))) {
3036 // For predicated instructions, if the predicates are complements
3037 // then there can be no dependence.
3038 else if (QII->isPredicated(I) &&
3039 QII->isPredicated(J) &&
3040 ArePredicatesComplements(I, J, MIToSUnit)) {
3044 else if (IsDirectJump(I) &&
3045 !MCIDJ.isBranch() &&
3047 (DepType == SDep::Order)) {
3048 // Ignore Order dependences between unconditional direct branches
3049 // and non-control-flow instructions
3052 else if (MCIDI.isConditionalBranch() && (DepType != SDep::Data) &&
3053 (DepType != SDep::Output)) {
3054 // Ignore all dependences for jumps except for true and output
3059 // Ignore output dependences due to superregs. We can
3060 // write to two different subregisters of R1:0 for instance
3061 // in the same cycle
3066 // If neither I nor J defines DepReg, then this is a
3067 // superfluous output dependence. The dependence must be of the
3071 // and there is an output dependence between the two instructions
3074 // We want to ignore these dependences.
3075 // Ideally, the dependence constructor should annotate such
3076 // dependences. We can then avoid this relatively expensive check.
3078 else if (DepType == SDep::Output) {
3079 // DepReg is the register that's responsible for the dependence.
3080 unsigned DepReg = SUJ->Succs[i].getReg();
3082 // Check if I and J really defines DepReg.
3083 if (I->definesRegister(DepReg) ||
3084 J->definesRegister(DepReg)) {
3085 FoundSequentialDependence = true;
3090 // We ignore Order dependences for
3091 // 1. Two loads unless they are volatile.
3092 // 2. Two stores in V4 unless they are volatile.
3093 else if ((DepType == SDep::Order) &&
3094 !I->hasOrderedMemoryRef() &&
3095 !J->hasOrderedMemoryRef()) {
3096 if (QRI->Subtarget.hasV4TOps() &&
3097 // hexagonv4 allows dual store.
3098 MCIDI.mayStore() && MCIDJ.mayStore()) {
3101 // store followed by store-- not OK on V2
3102 // store followed by load -- not OK on all (OK if addresses
3104 // load followed by store -- OK on all
3105 // load followed by load -- OK on all
3106 else if ( !MCIDJ.mayStore()) {
3110 FoundSequentialDependence = true;
3115 // For V4, special case ALLOCFRAME. Even though there is dependency
3116 // between ALLOCAFRAME and subsequent store, allow it to be
3117 // packetized in a same packet. This implies that the store is using
3118 // caller's SP. Hense, offset needs to be updated accordingly.
3119 else if (DepType == SDep::Data
3120 && QRI->Subtarget.hasV4TOps()
3121 && J->getOpcode() == Hexagon::ALLOCFRAME
3122 && (I->getOpcode() == Hexagon::STrid
3123 || I->getOpcode() == Hexagon::STriw
3124 || I->getOpcode() == Hexagon::STrib)
3125 && I->getOperand(0).getReg() == QRI->getStackRegister()
3126 && QII->isValidOffset(I->getOpcode(),
3127 I->getOperand(1).getImm() -
3128 (FrameSize + HEXAGON_LRFP_SIZE)))
3130 GlueAllocframeStore = true;
3131 // Since this store is to be glued with allocframe in the same
3132 // packet, it will use SP of the previous stack frame, i.e
3133 // caller's SP. Therefore, we need to recalculate offset according
3135 I->getOperand(1).setImm(I->getOperand(1).getImm() -
3136 (FrameSize + HEXAGON_LRFP_SIZE));
3140 // Skip over anti-dependences. Two instructions that are
3141 // anti-dependent can share a packet
3143 else if (DepType != SDep::Anti) {
3144 FoundSequentialDependence = true;
3149 if (FoundSequentialDependence) {
3158 // isLegalToPruneDependencies
3159 bool HexagonPacketizerList::isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {
3160 MachineInstr *I = SUI->getInstr();
3161 assert(I && SUJ->getInstr() && "Unable to packetize null instruction!");
3163 const unsigned FrameSize = MF.getFrameInfo()->getStackSize();
3167 // Check if the instruction was promoted to a dot-new. If so, demote it
3168 // back into a dot-old.
3169 if (PromotedToDotNew) {
3173 // Check if the instruction (must be a store) was glued with an Allocframe
3174 // instruction. If so, restore its offset to its original value, i.e. use
3175 // curent SP instead of caller's SP.
3176 if (GlueAllocframeStore) {
3177 I->getOperand(1).setImm(I->getOperand(1).getImm() +
3178 FrameSize + HEXAGON_LRFP_SIZE);
3186 MachineBasicBlock::iterator
3187 HexagonPacketizerList::addToPacket(MachineInstr *MI) {
3189 MachineBasicBlock::iterator MII = MI;
3190 MachineBasicBlock *MBB = MI->getParent();
3192 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
3194 if (GlueToNewValueJump) {
3197 MachineInstr *nvjMI = MII;
3198 assert(ResourceTracker->canReserveResources(MI));
3199 ResourceTracker->reserveResources(MI);
3200 if ((QII->isExtended(MI) || QII->isConstExtended(MI)) &&
3201 !tryAllocateResourcesForConstExt(MI)) {
3203 ResourceTracker->reserveResources(MI);
3204 assert(canReserveResourcesForConstExt(MI) &&
3205 "Ensure that there is a slot");
3206 reserveResourcesForConstExt(MI);
3207 // Reserve resources for new value jump constant extender.
3208 assert(canReserveResourcesForConstExt(MI) &&
3209 "Ensure that there is a slot");
3210 reserveResourcesForConstExt(nvjMI);
3211 assert(ResourceTracker->canReserveResources(nvjMI) &&
3212 "Ensure that there is a slot");
3214 } else if ( // Extended instruction takes two slots in the packet.
3215 // Try reserve and allocate 4-byte in the current packet first.
3216 (QII->isExtended(nvjMI)
3217 && (!tryAllocateResourcesForConstExt(nvjMI)
3218 || !ResourceTracker->canReserveResources(nvjMI)))
3219 || // For non-extended instruction, no need to allocate extra 4 bytes.
3220 (!QII->isExtended(nvjMI) &&
3221 !ResourceTracker->canReserveResources(nvjMI)))
3224 // A new and empty packet starts.
3225 // We are sure that the resources requirements can be satisfied.
3226 // Therefore, do not need to call "canReserveResources" anymore.
3227 ResourceTracker->reserveResources(MI);
3228 if (QII->isExtended(nvjMI))
3229 reserveResourcesForConstExt(nvjMI);
3231 // Here, we are sure that "reserveResources" would succeed.
3232 ResourceTracker->reserveResources(nvjMI);
3233 CurrentPacketMIs.push_back(MI);
3234 CurrentPacketMIs.push_back(nvjMI);
3236 if ( (QII->isExtended(MI) || QII->isConstExtended(MI))
3237 && ( !tryAllocateResourcesForConstExt(MI)
3238 || !ResourceTracker->canReserveResources(MI)))
3241 // Check if the instruction was promoted to a dot-new. If so, demote it
3242 // back into a dot-old
3243 if (PromotedToDotNew) {
3246 reserveResourcesForConstExt(MI);
3248 // In case that "MI" is not an extended insn,
3249 // the resource availability has already been checked.
3250 ResourceTracker->reserveResources(MI);
3251 CurrentPacketMIs.push_back(MI);
3256 //===----------------------------------------------------------------------===//
3257 // Public Constructor Functions
3258 //===----------------------------------------------------------------------===//
3260 FunctionPass *llvm::createHexagonPacketizer() {
3261 return new HexagonPacketizer();