1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implements the info about Hexagon target spec.
12 //===----------------------------------------------------------------------===//
14 #include "HexagonTargetMachine.h"
16 #include "HexagonISelLowering.h"
17 #include "llvm/Module.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/PassManager.h"
20 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
21 #include "llvm/Transforms/Scalar.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/TargetRegistry.h"
28 opt<bool> DisableHardwareLoops(
29 "disable-hexagon-hwloops", cl::Hidden,
30 cl::desc("Disable Hardware Loops for Hexagon target"));
32 opt<bool> DisableCExtOpt(
33 "disable-hexagon-cextopt", cl::Hidden,
34 cl::desc("Disable Optimization of Constant Extenders"));
36 /// HexagonTargetMachineModule - Note that this is used on hosts that
37 /// cannot link in a library unless there are references into the
38 /// library. In particular, it seems that it is not possible to get
39 /// things to work on Win32 without this. Though it is unused, do not
41 extern "C" int HexagonTargetMachineModule;
42 int HexagonTargetMachineModule = 0;
44 extern "C" void LLVMInitializeHexagonTarget() {
45 // Register the target.
46 RegisterTargetMachine<HexagonTargetMachine> X(TheHexagonTarget);
50 /// HexagonTargetMachine ctor - Create an ILP32 architecture model.
53 /// Hexagon_TODO: Do I need an aggregate alignment?
55 HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT,
56 StringRef CPU, StringRef FS,
57 const TargetOptions &Options,
61 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
62 DataLayout("e-p:32:32:32-"
63 "i64:64:64-i32:32:32-i16:16:16-i1:32:32-"
64 "f64:64:64-f32:32:32-a0:0-n32") ,
65 Subtarget(TT, CPU, FS), InstrInfo(Subtarget), TLInfo(*this),
67 FrameLowering(Subtarget),
68 InstrItins(&Subtarget.getInstrItineraryData()) {
72 // addPassesForOptimizations - Allow the backend (target) to add Target
73 // Independent Optimization passes to the Pass Manager.
74 bool HexagonTargetMachine::addPassesForOptimizations(PassManagerBase &PM) {
76 PM.add(createConstantPropagationPass());
77 PM.add(createLoopSimplifyPass());
78 PM.add(createDeadCodeEliminationPass());
79 PM.add(createConstantPropagationPass());
80 PM.add(createLoopUnrollPass());
81 PM.add(createLoopStrengthReducePass(getTargetLowering()));
86 /// Hexagon Code Generator Pass Configuration Options.
87 class HexagonPassConfig : public TargetPassConfig {
89 HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
90 : TargetPassConfig(TM, PM) {}
92 HexagonTargetMachine &getHexagonTargetMachine() const {
93 return getTM<HexagonTargetMachine>();
96 virtual bool addInstSelector();
97 virtual bool addPreRegAlloc();
98 virtual bool addPostRegAlloc();
99 virtual bool addPreSched2();
100 virtual bool addPreEmitPass();
104 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
105 return new HexagonPassConfig(this, PM);
108 bool HexagonPassConfig::addInstSelector() {
109 PM->add(createHexagonRemoveExtendOps(getHexagonTargetMachine()));
110 PM->add(createHexagonISelDag(getHexagonTargetMachine()));
111 PM->add(createHexagonPeephole());
116 bool HexagonPassConfig::addPreRegAlloc() {
117 if (!DisableCExtOpt) {
118 PM->add(createHexagonOptimizeConstExt(getHexagonTargetMachine()));
120 if (!DisableHardwareLoops) {
121 PM->add(createHexagonHardwareLoops());
126 bool HexagonPassConfig::addPostRegAlloc() {
127 PM->add(createHexagonCFGOptimizer(getHexagonTargetMachine()));
132 bool HexagonPassConfig::addPreSched2() {
133 addPass(IfConverterID);
137 bool HexagonPassConfig::addPreEmitPass() {
139 if (!DisableHardwareLoops) {
140 PM->add(createHexagonFixupHwLoops());
143 // Expand Spill code for predicate registers.
144 PM->add(createHexagonExpandPredSpillCode(getHexagonTargetMachine()));
146 // Split up TFRcondsets into conditional transfers.
147 PM->add(createHexagonSplitTFRCondSets(getHexagonTargetMachine()));
150 PM->add(createHexagonPacketizer());