1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implements the info about Hexagon target spec.
12 //===----------------------------------------------------------------------===//
14 #include "HexagonTargetMachine.h"
16 #include "HexagonISelLowering.h"
17 #include "HexagonMachineScheduler.h"
18 #include "HexagonTargetObjectFile.h"
19 #include "HexagonTargetTransformInfo.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/IR/LegacyPassManager.h"
22 #include "llvm/IR/Module.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
26 #include "llvm/Transforms/Scalar.h"
30 static cl:: opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
31 cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
33 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
34 cl::Hidden, cl::ZeroOrMore, cl::init(false),
35 cl::desc("Disable Hexagon CFG Optimization"));
37 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
38 cl::init(true), cl::Hidden, cl::ZeroOrMore,
39 cl::desc("Early expansion of MUX"));
41 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
42 cl::Hidden, cl::desc("Generate \"insert\" instructions"));
44 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
45 cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
47 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
48 cl::Hidden, cl::desc("Generate \"extract\" instructions"));
50 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
51 cl::desc("Enable converting conditional transfers into MUX instructions"));
53 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
54 cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
55 "predicate instructions"));
57 /// HexagonTargetMachineModule - Note that this is used on hosts that
58 /// cannot link in a library unless there are references into the
59 /// library. In particular, it seems that it is not possible to get
60 /// things to work on Win32 without this. Though it is unused, do not
62 extern "C" int HexagonTargetMachineModule;
63 int HexagonTargetMachineModule = 0;
65 extern "C" void LLVMInitializeHexagonTarget() {
66 // Register the target.
67 RegisterTargetMachine<HexagonTargetMachine> X(TheHexagonTarget);
70 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
71 return new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
74 static MachineSchedRegistry
75 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
76 createVLIWMachineSched);
79 FunctionPass *createHexagonCFGOptimizer();
80 FunctionPass *createHexagonCommonGEP();
81 FunctionPass *createHexagonCopyToCombine();
82 FunctionPass *createHexagonExpandCondsets();
83 FunctionPass *createHexagonExpandPredSpillCode();
84 FunctionPass *createHexagonFixupHwLoops();
85 FunctionPass *createHexagonGenExtract();
86 FunctionPass *createHexagonGenInsert();
87 FunctionPass *createHexagonGenMux();
88 FunctionPass *createHexagonGenPredicate();
89 FunctionPass *createHexagonHardwareLoops();
90 FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
91 CodeGenOpt::Level OptLevel);
92 FunctionPass *createHexagonNewValueJump();
93 FunctionPass *createHexagonPacketizer();
94 FunctionPass *createHexagonPeephole();
95 FunctionPass *createHexagonRemoveExtendArgs(const HexagonTargetMachine &TM);
96 FunctionPass *createHexagonSplitConst32AndConst64();
97 } // end namespace llvm;
99 /// HexagonTargetMachine ctor - Create an ILP32 architecture model.
102 /// Hexagon_TODO: Do I need an aggregate alignment?
104 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
105 StringRef CPU, StringRef FS,
106 const TargetOptions &Options,
107 Reloc::Model RM, CodeModel::Model CM,
108 CodeGenOpt::Level OL)
109 : LLVMTargetMachine(T, "e-m:e-p:32:32-i1:32-i64:64-a:0-n32", TT, CPU, FS,
110 Options, RM, CM, OL),
111 TLOF(make_unique<HexagonTargetObjectFile>()) {
115 const HexagonSubtarget *
116 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
117 AttributeSet FnAttrs = F.getAttributes();
119 FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
121 FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
123 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
124 ? CPUAttr.getValueAsString().str()
126 std::string FS = !FSAttr.hasAttribute(Attribute::None)
127 ? FSAttr.getValueAsString().str()
130 auto &I = SubtargetMap[CPU + FS];
132 // This needs to be done before we create a new subtarget since any
133 // creation will depend on the TM and the code generation flags on the
134 // function that reside in TargetOptions.
135 resetTargetOptions(F);
136 I = llvm::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
141 TargetIRAnalysis HexagonTargetMachine::getTargetIRAnalysis() {
142 return TargetIRAnalysis([this](Function &F) {
143 return TargetTransformInfo(HexagonTTIImpl(this, F));
148 HexagonTargetMachine::~HexagonTargetMachine() {}
151 /// Hexagon Code Generator Pass Configuration Options.
152 class HexagonPassConfig : public TargetPassConfig {
154 HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
155 : TargetPassConfig(TM, PM) {
156 bool NoOpt = (TM->getOptLevel() == CodeGenOpt::None);
158 if (EnableExpandCondsets) {
159 Pass *Exp = createHexagonExpandCondsets();
160 insertPass(&RegisterCoalescerID, IdentifyingPassPtr(Exp));
165 HexagonTargetMachine &getHexagonTargetMachine() const {
166 return getTM<HexagonTargetMachine>();
170 createMachineScheduler(MachineSchedContext *C) const override {
171 return createVLIWMachineSched(C);
174 void addIRPasses() override;
175 bool addInstSelector() override;
176 void addPreRegAlloc() override;
177 void addPostRegAlloc() override;
178 void addPreSched2() override;
179 void addPreEmitPass() override;
183 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
184 return new HexagonPassConfig(this, PM);
187 void HexagonPassConfig::addIRPasses() {
188 TargetPassConfig::addIRPasses();
189 bool NoOpt = (getOptLevel() == CodeGenOpt::None);
191 addPass(createAtomicExpandPass(TM));
194 addPass(createHexagonCommonGEP());
195 // Replace certain combinations of shifts and ands with extracts.
196 if (EnableGenExtract)
197 addPass(createHexagonGenExtract());
201 bool HexagonPassConfig::addInstSelector() {
202 HexagonTargetMachine &TM = getHexagonTargetMachine();
203 bool NoOpt = (getOptLevel() == CodeGenOpt::None);
206 addPass(createHexagonRemoveExtendArgs(TM));
208 addPass(createHexagonISelDag(TM, getOptLevel()));
211 // Create logical operations on predicate registers.
213 addPass(createHexagonGenPredicate(), false);
214 addPass(createHexagonPeephole());
215 printAndVerify("After hexagon peephole pass");
217 addPass(createHexagonGenInsert(), false);
223 void HexagonPassConfig::addPreRegAlloc() {
224 if (getOptLevel() != CodeGenOpt::None)
225 if (!DisableHardwareLoops)
226 addPass(createHexagonHardwareLoops(), false);
229 void HexagonPassConfig::addPostRegAlloc() {
230 if (getOptLevel() != CodeGenOpt::None)
231 if (!DisableHexagonCFGOpt)
232 addPass(createHexagonCFGOptimizer(), false);
235 void HexagonPassConfig::addPreSched2() {
236 addPass(createHexagonCopyToCombine(), false);
237 if (getOptLevel() != CodeGenOpt::None)
238 addPass(&IfConverterID, false);
239 addPass(createHexagonSplitConst32AndConst64());
242 void HexagonPassConfig::addPreEmitPass() {
243 bool NoOpt = (getOptLevel() == CodeGenOpt::None);
246 addPass(createHexagonNewValueJump(), false);
248 // Expand Spill code for predicate registers.
249 addPass(createHexagonExpandPredSpillCode(), false);
253 if (!DisableHardwareLoops)
254 addPass(createHexagonFixupHwLoops(), false);
255 // Generate MUX from pairs of conditional transfers.
257 addPass(createHexagonGenMux(), false);
259 addPass(createHexagonPacketizer(), false);