1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 #include "HexagonMCAsmInfo.h"
14 #include "HexagonTargetMachine.h"
16 #include "HexagonISelLowering.h"
17 #include "llvm/Module.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/PassManager.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
22 #include "llvm/Transforms/Scalar.h"
23 #include "llvm/Support/TargetRegistry.h"
26 #define GET_REGINFO_MC_DESC
27 #define GET_REGINFO_TARGET_DESC
28 #include "HexagonGenRegisterInfo.inc"
30 extern "C" void LLVMInitializeHexagonTargetMC() {}
35 opt<bool> DisableHardwareLoops(
36 "disable-hexagon-hwloops", cl::Hidden,
37 cl::desc("Disable Hardware Loops for Hexagon target"));
39 /// HexagonTargetMachineModule - Note that this is used on hosts that
40 /// cannot link in a library unless there are references into the
41 /// library. In particular, it seems that it is not possible to get
42 /// things to work on Win32 without this. Though it is unused, do not
44 extern "C" int HexagonTargetMachineModule;
45 int HexagonTargetMachineModule = 0;
47 extern "C" void LLVMInitializeHexagonTarget() {
48 // Register the target.
49 RegisterTargetMachine<HexagonTargetMachine> X(TheHexagonTarget);
51 // Register the target asm info.
52 RegisterMCAsmInfo<HexagonMCAsmInfo> A(TheHexagonTarget);
56 /// HexagonTargetMachine ctor - Create an ILP32 architecture model.
59 /// Hexagon_TODO: Do I need an aggregate alignment?
61 HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT,
62 StringRef CPU, StringRef FS,
63 TargetOptions Options,
67 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
68 DataLayout("e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-a0:0") ,
69 Subtarget(TT, CPU, FS), TLInfo(*this), InstrInfo(Subtarget),
71 FrameLowering(Subtarget),
72 InstrItins(&Subtarget.getInstrItineraryData()) {
76 // addPassesForOptimizations - Allow the backend (target) to add Target
77 // Independent Optimization passes to the Pass Manager.
78 bool HexagonTargetMachine::addPassesForOptimizations(PassManagerBase &PM) {
80 PM.add(createConstantPropagationPass());
81 PM.add(createLoopSimplifyPass());
82 PM.add(createDeadCodeEliminationPass());
83 PM.add(createConstantPropagationPass());
84 PM.add(createLoopUnrollPass());
85 PM.add(createLoopStrengthReducePass(getTargetLowering()));
89 bool HexagonTargetMachine::addInstSelector(PassManagerBase &PM) {
90 PM.add(createHexagonRemoveExtendOps(*this));
91 PM.add(createHexagonISelDag(*this));
96 bool HexagonTargetMachine::addPreRegAlloc(PassManagerBase &PM) {
97 if (!DisableHardwareLoops) {
98 PM.add(createHexagonHardwareLoops());
104 bool HexagonTargetMachine::addPostRegAlloc(PassManagerBase &PM) {
105 PM.add(createHexagonCFGOptimizer(*this));
110 bool HexagonTargetMachine::addPreSched2(PassManagerBase &PM) {
111 PM.add(createIfConverterPass());
115 bool HexagonTargetMachine::addPreEmitPass(PassManagerBase &PM) {
117 if (!DisableHardwareLoops) {
118 PM.add(createHexagonFixupHwLoops());
121 // Expand Spill code for predicate registers.
122 PM.add(createHexagonExpandPredSpillCode(*this));
124 // Split up TFRcondsets into conditional transfers.
125 PM.add(createHexagonSplitTFRCondSets(*this));