1 //===-- HexagonSplitTFRCondSets.cpp - split TFR condsets into xfers -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
10 // This pass tries to provide opportunities for better optimization of muxes.
11 // The default code generated for something like: flag = (a == b) ? 1 : 3;
14 // {p0 = cmp.eq(r0,r1)}
15 // {r3 = mux(p0,#1,#3)}
17 // This requires two packets. If we use .new predicated immediate transfers,
18 // then we can do this in a single packet, e.g.:
20 // {p0 = cmp.eq(r0,r1)
21 // if (p0.new) r3 = #1
22 // if (!p0.new) r3 = #3}
24 // Note that the conditional assignments are not generated in .new form here.
25 // We assume opptimisically that they will be formed later.
27 //===----------------------------------------------------------------------===//
30 #include "HexagonMachineFunctionInfo.h"
31 #include "HexagonSubtarget.h"
32 #include "HexagonTargetMachine.h"
33 #include "llvm/CodeGen/LatencyPriorityQueue.h"
34 #include "llvm/CodeGen/MachineDominators.h"
35 #include "llvm/CodeGen/MachineFunctionPass.h"
36 #include "llvm/CodeGen/MachineInstrBuilder.h"
37 #include "llvm/CodeGen/MachineLoopInfo.h"
38 #include "llvm/CodeGen/MachineRegisterInfo.h"
39 #include "llvm/CodeGen/Passes.h"
40 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
41 #include "llvm/CodeGen/SchedulerRegistry.h"
42 #include "llvm/Support/Compiler.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/MathExtras.h"
45 #include "llvm/Target/TargetInstrInfo.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetRegisterInfo.h"
51 #define DEBUG_TYPE "xfer"
54 void initializeHexagonSplitTFRCondSetsPass(PassRegistry&);
60 class HexagonSplitTFRCondSets : public MachineFunctionPass {
61 const HexagonTargetMachine &QTM;
62 const HexagonSubtarget &QST;
66 HexagonSplitTFRCondSets(const HexagonTargetMachine& TM) :
67 MachineFunctionPass(ID), QTM(TM), QST(*TM.getSubtargetImpl()) {
68 initializeHexagonSplitTFRCondSetsPass(*PassRegistry::getPassRegistry());
71 const char *getPassName() const override {
72 return "Hexagon Split TFRCondSets";
74 bool runOnMachineFunction(MachineFunction &Fn) override;
78 char HexagonSplitTFRCondSets::ID = 0;
81 bool HexagonSplitTFRCondSets::runOnMachineFunction(MachineFunction &Fn) {
83 const TargetInstrInfo *TII = QTM.getSubtargetImpl()->getInstrInfo();
85 // Loop over all of the basic blocks.
86 for (MachineFunction::iterator MBBb = Fn.begin(), MBBe = Fn.end();
87 MBBb != MBBe; ++MBBb) {
88 MachineBasicBlock* MBB = MBBb;
89 // Traverse the basic block.
90 for (MachineBasicBlock::iterator MII = MBB->begin(); MII != MBB->end();
92 MachineInstr *MI = MII;
94 switch(MI->getOpcode()) {
95 case Hexagon::TFR_condset_rr_f:
96 case Hexagon::TFR_condset_rr64_f: {
97 int DestReg = MI->getOperand(0).getReg();
98 int SrcReg1 = MI->getOperand(2).getReg();
99 int SrcReg2 = MI->getOperand(3).getReg();
101 if (MI->getOpcode() == Hexagon::TFR_condset_rr_f) {
102 Opc1 = Hexagon::A2_tfrt;
103 Opc2 = Hexagon::A2_tfrf;
105 else if (MI->getOpcode() == Hexagon::TFR_condset_rr64_f) {
106 Opc1 = Hexagon::A2_tfrpt;
107 Opc2 = Hexagon::A2_tfrpf;
110 // Minor optimization: do not emit the predicated copy if the source
111 // and the destination is the same register.
112 if (DestReg != SrcReg1) {
113 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Opc1),
114 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg1);
116 if (DestReg != SrcReg2) {
117 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Opc2),
118 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg2);
120 MII = MBB->erase(MI);
124 case Hexagon::TFR_condset_ri:
125 case Hexagon::TFR_condset_ri_f: {
126 int DestReg = MI->getOperand(0).getReg();
127 int SrcReg1 = MI->getOperand(2).getReg();
129 // Do not emit the predicated copy if the source and the destination
130 // is the same register.
131 if (DestReg != SrcReg1) {
132 BuildMI(*MBB, MII, MI->getDebugLoc(),
133 TII->get(Hexagon::A2_tfrt), DestReg).
134 addReg(MI->getOperand(1).getReg()).addReg(SrcReg1);
136 if (MI->getOpcode() == Hexagon::TFR_condset_ri ) {
137 BuildMI(*MBB, MII, MI->getDebugLoc(),
138 TII->get(Hexagon::C2_cmoveif), DestReg).
139 addReg(MI->getOperand(1).getReg()).
140 addImm(MI->getOperand(3).getImm());
141 } else if (MI->getOpcode() == Hexagon::TFR_condset_ri_f ) {
142 BuildMI(*MBB, MII, MI->getDebugLoc(),
143 TII->get(Hexagon::TFRI_cNotPt_f), DestReg).
144 addReg(MI->getOperand(1).getReg()).
145 addFPImm(MI->getOperand(3).getFPImm());
148 MII = MBB->erase(MI);
152 case Hexagon::TFR_condset_ir:
153 case Hexagon::TFR_condset_ir_f: {
154 int DestReg = MI->getOperand(0).getReg();
155 int SrcReg2 = MI->getOperand(3).getReg();
157 if (MI->getOpcode() == Hexagon::TFR_condset_ir ) {
158 BuildMI(*MBB, MII, MI->getDebugLoc(),
159 TII->get(Hexagon::C2_cmoveit), DestReg).
160 addReg(MI->getOperand(1).getReg()).
161 addImm(MI->getOperand(2).getImm());
162 } else if (MI->getOpcode() == Hexagon::TFR_condset_ir_f ) {
163 BuildMI(*MBB, MII, MI->getDebugLoc(),
164 TII->get(Hexagon::TFRI_cPt_f), DestReg).
165 addReg(MI->getOperand(1).getReg()).
166 addFPImm(MI->getOperand(2).getFPImm());
169 // Do not emit the predicated copy if the source and
170 // the destination is the same register.
171 if (DestReg != SrcReg2) {
172 BuildMI(*MBB, MII, MI->getDebugLoc(),
173 TII->get(Hexagon::A2_tfrf), DestReg).
174 addReg(MI->getOperand(1).getReg()).addReg(SrcReg2);
176 MII = MBB->erase(MI);
180 case Hexagon::TFR_condset_ii:
181 case Hexagon::TFR_condset_ii_f: {
182 int DestReg = MI->getOperand(0).getReg();
183 int SrcReg1 = MI->getOperand(1).getReg();
185 if (MI->getOpcode() == Hexagon::TFR_condset_ii ) {
186 int Immed1 = MI->getOperand(2).getImm();
187 int Immed2 = MI->getOperand(3).getImm();
188 BuildMI(*MBB, MII, MI->getDebugLoc(),
189 TII->get(Hexagon::C2_cmoveit),
190 DestReg).addReg(SrcReg1).addImm(Immed1);
191 BuildMI(*MBB, MII, MI->getDebugLoc(),
192 TII->get(Hexagon::C2_cmoveif),
193 DestReg).addReg(SrcReg1).addImm(Immed2);
194 } else if (MI->getOpcode() == Hexagon::TFR_condset_ii_f ) {
195 BuildMI(*MBB, MII, MI->getDebugLoc(),
196 TII->get(Hexagon::TFRI_cPt_f), DestReg).
198 addFPImm(MI->getOperand(2).getFPImm());
199 BuildMI(*MBB, MII, MI->getDebugLoc(),
200 TII->get(Hexagon::TFRI_cNotPt_f), DestReg).
202 addFPImm(MI->getOperand(3).getFPImm());
204 MII = MBB->erase(MI);
216 //===----------------------------------------------------------------------===//
217 // Public Constructor Functions
218 //===----------------------------------------------------------------------===//
220 static void initializePassOnce(PassRegistry &Registry) {
221 const char *Name = "Hexagon Split TFRCondSets";
222 PassInfo *PI = new PassInfo(Name, "hexagon-split-tfr",
223 &HexagonSplitTFRCondSets::ID, nullptr, false,
225 Registry.registerPass(*PI, true);
228 void llvm::initializeHexagonSplitTFRCondSetsPass(PassRegistry &Registry) {
229 CALL_ONCE_INITIALIZATION(initializePassOnce)
233 llvm::createHexagonSplitTFRCondSets(const HexagonTargetMachine &TM) {
234 return new HexagonSplitTFRCondSets(TM);