1 //=== HexagonSplitConst32AndConst64.cpp - split CONST32/Const64 into HI/LO ===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // When the compiler is invoked with no small data, for instance, with the -G0
11 // command line option, then all CONST32_* opcodes should be broken down into
12 // appropriate LO and HI instructions. This splitting is done by this pass.
13 // The only reason this is not done in the DAG lowering itself is that there
14 // is no simple way of getting the register allocator to allot the same hard
15 // register to the result of LO and HI instructions. This pass is always
16 // scheduled after register allocation.
18 //===----------------------------------------------------------------------===//
20 #include "HexagonTargetMachine.h"
21 #include "HexagonMachineFunctionInfo.h"
22 #include "HexagonSubtarget.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/CodeGen/LatencyPriorityQueue.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineLoopInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/Passes.h"
31 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
32 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
33 #include "llvm/CodeGen/SchedulerRegistry.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Compiler.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Target/TargetInstrInfo.h"
39 #include "llvm/Target/TargetMachine.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
45 #define DEBUG_TYPE "xfer"
49 class HexagonSplitConst32AndConst64 : public MachineFunctionPass {
50 const HexagonTargetMachine &QTM;
54 HexagonSplitConst32AndConst64(const HexagonTargetMachine &TM)
55 : MachineFunctionPass(ID), QTM(TM) {}
57 const char *getPassName() const override {
58 return "Hexagon Split Const32s and Const64s";
60 bool runOnMachineFunction(MachineFunction &Fn) override;
64 char HexagonSplitConst32AndConst64::ID = 0;
67 bool HexagonSplitConst32AndConst64::runOnMachineFunction(MachineFunction &Fn) {
69 const TargetInstrInfo *TII = QTM.getInstrInfo();
71 // Loop over all of the basic blocks
72 for (MachineFunction::iterator MBBb = Fn.begin(), MBBe = Fn.end();
73 MBBb != MBBe; ++MBBb) {
74 MachineBasicBlock* MBB = MBBb;
75 // Traverse the basic block
76 MachineBasicBlock::iterator MII = MBB->begin();
77 MachineBasicBlock::iterator MIE = MBB->end ();
79 MachineInstr *MI = MII;
80 int Opc = MI->getOpcode();
81 if (Opc == Hexagon::CONST32_set) {
82 int DestReg = MI->getOperand(0).getReg();
83 MachineOperand &Symbol = MI->getOperand (1);
85 BuildMI (*MBB, MII, MI->getDebugLoc(),
86 TII->get(Hexagon::LO), DestReg).addOperand(Symbol);
87 BuildMI (*MBB, MII, MI->getDebugLoc(),
88 TII->get(Hexagon::HI), DestReg).addOperand(Symbol);
89 // MBB->erase returns the iterator to the next instruction, which is the
90 // one we want to process next
91 MII = MBB->erase (MI);
94 else if (Opc == Hexagon::CONST32_set_jt) {
95 int DestReg = MI->getOperand(0).getReg();
96 MachineOperand &Symbol = MI->getOperand (1);
98 BuildMI (*MBB, MII, MI->getDebugLoc(),
99 TII->get(Hexagon::LO_jt), DestReg).addOperand(Symbol);
100 BuildMI (*MBB, MII, MI->getDebugLoc(),
101 TII->get(Hexagon::HI_jt), DestReg).addOperand(Symbol);
102 // MBB->erase returns the iterator to the next instruction, which is the
103 // one we want to process next
104 MII = MBB->erase (MI);
107 else if (Opc == Hexagon::CONST32_Label) {
108 int DestReg = MI->getOperand(0).getReg();
109 MachineOperand &Symbol = MI->getOperand (1);
111 BuildMI (*MBB, MII, MI->getDebugLoc(),
112 TII->get(Hexagon::LO_label), DestReg).addOperand(Symbol);
113 BuildMI (*MBB, MII, MI->getDebugLoc(),
114 TII->get(Hexagon::HI_label), DestReg).addOperand(Symbol);
115 // MBB->erase returns the iterator to the next instruction, which is the
116 // one we want to process next
117 MII = MBB->erase (MI);
120 else if (Opc == Hexagon::CONST32_Int_Real) {
121 int DestReg = MI->getOperand(0).getReg();
122 int64_t ImmValue = MI->getOperand(1).getImm ();
124 BuildMI (*MBB, MII, MI->getDebugLoc(),
125 TII->get(Hexagon::LOi), DestReg).addImm(ImmValue);
126 BuildMI (*MBB, MII, MI->getDebugLoc(),
127 TII->get(Hexagon::HIi), DestReg).addImm(ImmValue);
128 MII = MBB->erase (MI);
131 else if (Opc == Hexagon::CONST64_Int_Real) {
132 int DestReg = MI->getOperand(0).getReg();
133 int64_t ImmValue = MI->getOperand(1).getImm ();
135 QTM.getRegisterInfo()->getSubReg (DestReg, Hexagon::subreg_loreg);
137 QTM.getRegisterInfo()->getSubReg (DestReg, Hexagon::subreg_hireg);
139 int32_t LowWord = (ImmValue & 0xFFFFFFFF);
140 int32_t HighWord = (ImmValue >> 32) & 0xFFFFFFFF;
142 // Lower Registers Lower Half
143 BuildMI (*MBB, MII, MI->getDebugLoc(),
144 TII->get(Hexagon::LOi), DestLo).addImm(LowWord);
145 // Lower Registers Higher Half
146 BuildMI (*MBB, MII, MI->getDebugLoc(),
147 TII->get(Hexagon::HIi), DestLo).addImm(LowWord);
148 // Higher Registers Lower Half
149 BuildMI (*MBB, MII, MI->getDebugLoc(),
150 TII->get(Hexagon::LOi), DestHi).addImm(HighWord);
151 // Higher Registers Higher Half.
152 BuildMI (*MBB, MII, MI->getDebugLoc(),
153 TII->get(Hexagon::HIi), DestHi).addImm(HighWord);
154 MII = MBB->erase (MI);
166 //===----------------------------------------------------------------------===//
167 // Public Constructor Functions
168 //===----------------------------------------------------------------------===//
171 llvm::createHexagonSplitConst32AndConst64(const HexagonTargetMachine &TM) {
172 return new HexagonSplitConst32AndConst64(TM);