1 //===----- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements NewValueJump pass in Hexagon.
11 // Ideally, we should merge this as a Peephole pass prior to register
12 // allocation, but because we have a spill in between the feeder and new value
13 // jump instructions, we are forced to write after register allocation.
14 // Having said that, we should re-attempt to pull this earlier at some point
17 // The basic approach looks for sequence of predicated jump, compare instruciton
18 // that genereates the predicate and, the feeder to the predicate. Once it finds
19 // all, it collapses compare and jump instruction into a new valu jump
23 //===----------------------------------------------------------------------===//
24 #define DEBUG_TYPE "hexagon-nvj"
26 #include "HexagonInstrInfo.h"
27 #include "HexagonMachineFunctionInfo.h"
28 #include "HexagonRegisterInfo.h"
29 #include "HexagonSubtarget.h"
30 #include "HexagonTargetMachine.h"
31 #include "llvm/ADT/DenseMap.h"
32 #include "llvm/ADT/Statistic.h"
33 #include "llvm/CodeGen/LiveVariables.h"
34 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
35 #include "llvm/CodeGen/MachineFunctionPass.h"
36 #include "llvm/CodeGen/MachineInstrBuilder.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/Passes.h"
39 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
40 #include "llvm/PassSupport.h"
41 #include "llvm/Support/CommandLine.h"
42 #include "llvm/Support/Compiler.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Target/TargetInstrInfo.h"
45 #include "llvm/Target/TargetMachine.h"
46 #include "llvm/Target/TargetRegisterInfo.h"
50 STATISTIC(NumNVJGenerated, "Number of New Value Jump Instructions created");
53 DbgNVJCount("nvj-count", cl::init(-1), cl::Hidden, cl::desc(
54 "Maximum number of predicated jumps to be converted to New Value Jump"));
56 static cl::opt<bool> DisableNewValueJumps("disable-nvjump", cl::Hidden,
57 cl::ZeroOrMore, cl::init(false),
58 cl::desc("Disable New Value Jumps"));
61 struct HexagonNewValueJump : public MachineFunctionPass {
62 const HexagonInstrInfo *QII;
63 const HexagonRegisterInfo *QRI;
68 HexagonNewValueJump() : MachineFunctionPass(ID) { }
70 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
71 AU.addRequired<MachineBranchProbabilityInfo>();
72 MachineFunctionPass::getAnalysisUsage(AU);
75 const char *getPassName() const {
76 return "Hexagon NewValueJump";
79 virtual bool runOnMachineFunction(MachineFunction &Fn);
82 /// \brief A handle to the branch probability pass.
83 const MachineBranchProbabilityInfo *MBPI;
87 } // end of anonymous namespace
89 char HexagonNewValueJump::ID = 0;
91 // We have identified this II could be feeder to NVJ,
92 // verify that it can be.
93 static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII,
94 const TargetRegisterInfo *TRI,
95 MachineBasicBlock::iterator II,
96 MachineBasicBlock::iterator end,
97 MachineBasicBlock::iterator skip,
98 MachineFunction &MF) {
100 // Predicated instruction can not be feeder to NVJ.
101 if (QII->isPredicated(II))
104 // Bail out if feederReg is a paired register (double regs in
105 // our case). One would think that we can check to see if a given
106 // register cmpReg1 or cmpReg2 is a sub register of feederReg
107 // using -- if (QRI->isSubRegister(feederReg, cmpReg1) logic
108 // before the callsite of this function
109 // But we can not as it comes in the following fashion.
110 // %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill>
111 // %R0<def> = KILL %R0, %D0<imp-use,kill>
112 // %P0<def> = CMPEQri %R0<kill>, 0
113 // Hence, we need to check if it's a KILL instruction.
114 if (II->getOpcode() == TargetOpcode::KILL)
118 // Make sure there there is no 'def' or 'use' of any of the uses of
119 // feeder insn between it's definition, this MI and jump, jmpInst
120 // skipping compare, cmpInst.
121 // Here's the example.
122 // r21=memub(r22+r24<<#0)
123 // p0 = cmp.eq(r21, #0)
124 // r4=memub(r3+r21<<#0)
125 // if (p0.new) jump:t .LBB29_45
126 // Without this check, it will be converted into
127 // r4=memub(r3+r21<<#0)
128 // r21=memub(r22+r24<<#0)
129 // p0 = cmp.eq(r21, #0)
130 // if (p0.new) jump:t .LBB29_45
131 // and result WAR hazards if converted to New Value Jump.
133 for (unsigned i = 0; i < II->getNumOperands(); ++i) {
134 if (II->getOperand(i).isReg() &&
135 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) {
136 MachineBasicBlock::iterator localII = II;
138 unsigned Reg = II->getOperand(i).getReg();
139 for (MachineBasicBlock::iterator localBegin = localII;
140 localBegin != end; ++localBegin) {
141 if (localBegin == skip ) continue;
142 // Check for Subregisters too.
143 if (localBegin->modifiesRegister(Reg, TRI) ||
144 localBegin->readsRegister(Reg, TRI))
152 // These are the common checks that need to performed
154 // 1. compare instruction can be moved before jump.
155 // 2. feeder to the compare instruction can be moved before jump.
156 static bool commonChecksToProhibitNewValueJump(bool afterRA,
157 MachineBasicBlock::iterator MII) {
159 // If store in path, bail out.
160 if (MII->getDesc().mayStore())
163 // if call in path, bail out.
164 if (MII->getOpcode() == Hexagon::CALLv3)
167 // if NVJ is running prior to RA, do the following checks.
169 // The following Target Opcode instructions are spurious
170 // to new value jump. If they are in the path, bail out.
171 // KILL sets kill flag on the opcode. It also sets up a
172 // single register, out of pair.
173 // %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill>
174 // %R0<def> = KILL %R0, %D0<imp-use,kill>
175 // %P0<def> = CMPEQri %R0<kill>, 0
176 // PHI can be anything after RA.
177 // COPY can remateriaze things in between feeder, compare and nvj.
178 if (MII->getOpcode() == TargetOpcode::KILL ||
179 MII->getOpcode() == TargetOpcode::PHI ||
180 MII->getOpcode() == TargetOpcode::COPY)
183 // The following pseudo Hexagon instructions sets "use" and "def"
184 // of registers by individual passes in the backend. At this time,
185 // we don't know the scope of usage and definitions of these
187 if (MII->getOpcode() == Hexagon::TFR_condset_rr ||
188 MII->getOpcode() == Hexagon::TFR_condset_ii ||
189 MII->getOpcode() == Hexagon::TFR_condset_ri ||
190 MII->getOpcode() == Hexagon::TFR_condset_ir ||
191 MII->getOpcode() == Hexagon::LDriw_pred ||
192 MII->getOpcode() == Hexagon::STriw_pred)
199 static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII,
200 const TargetRegisterInfo *TRI,
201 MachineBasicBlock::iterator II,
205 MachineBasicBlock::iterator end,
206 MachineFunction &MF) {
208 MachineInstr *MI = II;
210 // If the second operand of the compare is an imm, make sure it's in the
211 // range specified by the arch.
213 int64_t v = MI->getOperand(2).getImm();
215 if (!(isUInt<5>(v) ||
216 ((MI->getOpcode() == Hexagon::CMPEQri ||
217 MI->getOpcode() == Hexagon::CMPGTri) &&
222 unsigned cmpReg1, cmpOp2;
223 cmpReg1 = MI->getOperand(1).getReg();
226 cmpOp2 = MI->getOperand(2).getReg();
228 // Make sure that that second register is not from COPY
229 // At machine code level, we don't need this, but if we decide
230 // to move new value jump prior to RA, we would be needing this.
231 MachineRegisterInfo &MRI = MF.getRegInfo();
232 if (secondReg && !TargetRegisterInfo::isPhysicalRegister(cmpOp2)) {
233 MachineInstr *def = MRI.getVRegDef(cmpOp2);
234 if (def->getOpcode() == TargetOpcode::COPY)
239 // Walk the instructions after the compare (predicate def) to the jump,
240 // and satisfy the following conditions.
242 for (MachineBasicBlock::iterator localII = II; localII != end;
246 // If "common" checks fail, bail out.
247 if (!commonChecksToProhibitNewValueJump(optLocation, localII))
251 // If there is a def or use of predicate (result of compare), bail out.
252 if (localII->modifiesRegister(pReg, TRI) ||
253 localII->readsRegister(pReg, TRI))
257 // If there is a def of any of the use of the compare (operands of compare),
260 // p0 = cmp.eq(r2, r0)
262 // if (p0.new) jump:t .LBB28_3
263 if (localII->modifiesRegister(cmpReg1, TRI) ||
264 (secondReg && localII->modifiesRegister(cmpOp2, TRI)))
270 // Given a compare operator, return a matching New Value Jump
271 // compare operator. Make sure that MI here is included in
272 // HexagonInstrInfo.cpp::isNewValueJumpCandidate
273 static unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg,
274 bool secondRegNewified,
275 MachineBasicBlock *jmpTarget,
276 const MachineBranchProbabilityInfo
279 MachineBasicBlock *Src = MI->getParent();
280 const BranchProbability Prediction =
281 MBPI->getEdgeProbability(Src, jmpTarget);
283 if (Prediction >= BranchProbability(1,2))
286 switch (MI->getOpcode()) {
287 case Hexagon::CMPEQrr:
288 return taken ? Hexagon::JMP_EQrrPt_nv_V4 : Hexagon::JMP_EQrrPnt_nv_V4;
290 case Hexagon::CMPEQri: {
292 return taken ? Hexagon::JMP_EQriPt_nv_V4 : Hexagon::JMP_EQriPnt_nv_V4;
294 return taken ? Hexagon::JMP_EQriPtneg_nv_V4
295 : Hexagon::JMP_EQriPntneg_nv_V4;
298 case Hexagon::CMPGTrr: {
299 if (secondRegNewified)
300 return taken ? Hexagon::JMP_GTrrdnPt_nv_V4
301 : Hexagon::JMP_GTrrdnPnt_nv_V4;
303 return taken ? Hexagon::JMP_GTrrPt_nv_V4
304 : Hexagon::JMP_GTrrPnt_nv_V4;
307 case Hexagon::CMPGTri: {
309 return taken ? Hexagon::JMP_GTriPt_nv_V4 : Hexagon::JMP_GTriPnt_nv_V4;
311 return taken ? Hexagon::JMP_GTriPtneg_nv_V4
312 : Hexagon::JMP_GTriPntneg_nv_V4;
315 case Hexagon::CMPGTUrr: {
316 if (secondRegNewified)
317 return taken ? Hexagon::JMP_GTUrrdnPt_nv_V4
318 : Hexagon::JMP_GTUrrdnPnt_nv_V4;
320 return taken ? Hexagon::JMP_GTUrrPt_nv_V4 : Hexagon::JMP_GTUrrPnt_nv_V4;
323 case Hexagon::CMPGTUri:
324 return taken ? Hexagon::JMP_GTUriPt_nv_V4 : Hexagon::JMP_GTUriPnt_nv_V4;
327 llvm_unreachable("Could not find matching New Value Jump instruction.");
329 // return *some value* to avoid compiler warning
333 bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
335 DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n"
336 << "********** Function: "
337 << MF.getName() << "\n");
340 // for now disable this, if we move NewValueJump before register
341 // allocation we need this information.
342 LiveVariables &LVs = getAnalysis<LiveVariables>();
345 QII = static_cast<const HexagonInstrInfo *>(MF.getTarget().getInstrInfo());
347 static_cast<const HexagonRegisterInfo *>(MF.getTarget().getRegisterInfo());
348 MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
350 if (!QRI->Subtarget.hasV4TOps() ||
351 DisableNewValueJumps) {
355 int nvjCount = DbgNVJCount;
356 int nvjGenerated = 0;
358 // Loop through all the bb's of the function
359 for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end();
360 MBBb != MBBe; ++MBBb) {
361 MachineBasicBlock* MBB = MBBb;
363 DEBUG(dbgs() << "** dumping bb ** "
364 << MBB->getNumber() << "\n");
366 DEBUG(dbgs() << "\n" << "********** dumping instr bottom up **********\n");
367 bool foundJump = false;
368 bool foundCompare = false;
369 bool invertPredicate = false;
370 unsigned predReg = 0; // predicate reg of the jump.
371 unsigned cmpReg1 = 0;
373 bool MO1IsKill = false;
374 bool MO2IsKill = false;
375 MachineBasicBlock::iterator jmpPos;
376 MachineBasicBlock::iterator cmpPos;
377 MachineInstr *cmpInstr = NULL, *jmpInstr = NULL;
378 MachineBasicBlock *jmpTarget = NULL;
379 bool afterRA = false;
380 bool isSecondOpReg = false;
381 bool isSecondOpNewified = false;
382 // Traverse the basic block - bottom up
383 for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin();
385 MachineInstr *MI = --MII;
386 if (MI->isDebugValue()) {
390 if ((nvjCount == 0) || (nvjCount > -1 && nvjCount <= nvjGenerated))
393 DEBUG(dbgs() << "Instr: "; MI->dump(); dbgs() << "\n");
396 (MI->getOpcode() == Hexagon::JMP_t ||
397 MI->getOpcode() == Hexagon::JMP_f ||
398 MI->getOpcode() == Hexagon::JMP_tnew_t ||
399 MI->getOpcode() == Hexagon::JMP_tnew_nt ||
400 MI->getOpcode() == Hexagon::JMP_fnew_t ||
401 MI->getOpcode() == Hexagon::JMP_fnew_nt)) {
402 // This is where you would insert your compare and
403 // instr that feeds compare
406 predReg = MI->getOperand(0).getReg();
407 afterRA = TargetRegisterInfo::isPhysicalRegister(predReg);
409 // If ifconverter had not messed up with the kill flags of the
410 // operands, the following check on the kill flag would suffice.
411 // if(!jmpInstr->getOperand(0).isKill()) break;
413 // This predicate register is live out out of BB
414 // this would only work if we can actually use Live
415 // variable analysis on phy regs - but LLVM does not
416 // provide LV analysis on phys regs.
417 //if(LVs.isLiveOut(predReg, *MBB)) break;
419 // Get all the successors of this block - which will always
420 // be 2. Check if the predicate register is live in in those
421 // successor. If yes, we can not delete the predicate -
422 // I am doing this only because LLVM does not provide LiveOut
424 bool predLive = false;
425 for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
426 SIE = MBB->succ_end(); SI != SIE; ++SI) {
427 MachineBasicBlock* succMBB = *SI;
428 if (succMBB->isLiveIn(predReg)) {
435 jmpTarget = MI->getOperand(1).getMBB();
437 if (MI->getOpcode() == Hexagon::JMP_f ||
438 MI->getOpcode() == Hexagon::JMP_fnew_t ||
439 MI->getOpcode() == Hexagon::JMP_fnew_nt) {
440 invertPredicate = true;
445 // No new value jump if there is a barrier. A barrier has to be in its
446 // own packet. A barrier has zero operands. We conservatively bail out
447 // here if we see any instruction with zero operands.
448 if (foundJump && MI->getNumOperands() == 0)
453 MI->getOperand(0).isReg() &&
454 MI->getOperand(0).getReg() == predReg) {
456 // Not all compares can be new value compare. Arch Spec: 7.6.1.1
457 if (QII->isNewValueJumpCandidate(MI)) {
459 assert((MI->getDesc().isCompare()) &&
460 "Only compare instruction can be collapsed into New Value Jump");
461 isSecondOpReg = MI->getOperand(2).isReg();
463 if (!canCompareBeNewValueJump(QII, QRI, MII, predReg, isSecondOpReg,
464 afterRA, jmpPos, MF))
471 // We need cmpReg1 and cmpOp2(imm or reg) while building
472 // new value jump instruction.
473 cmpReg1 = MI->getOperand(1).getReg();
474 if (MI->getOperand(1).isKill())
478 cmpOp2 = MI->getOperand(2).getReg();
479 if (MI->getOperand(2).isKill())
482 cmpOp2 = MI->getOperand(2).getImm();
487 if (foundCompare && foundJump) {
489 // If "common" checks fail, bail out on this BB.
490 if (!commonChecksToProhibitNewValueJump(afterRA, MII))
493 bool foundFeeder = false;
494 MachineBasicBlock::iterator feederPos = MII;
495 if (MI->getOperand(0).isReg() &&
496 MI->getOperand(0).isDef() &&
497 (MI->getOperand(0).getReg() == cmpReg1 ||
499 MI->getOperand(0).getReg() == (unsigned) cmpOp2))) {
501 unsigned feederReg = MI->getOperand(0).getReg();
503 // First try to see if we can get the feeder from the first operand
504 // of the compare. If we can not, and if secondOpReg is true
505 // (second operand of the compare is also register), try that one.
506 // TODO: Try to come up with some heuristic to figure out which
507 // feeder would benefit.
509 if (feederReg == cmpReg1) {
510 if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF)) {
521 feederReg == (unsigned) cmpOp2)
522 if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF))
526 // In case of CMPLT, or CMPLTU, or EQ with the second register
527 // to newify, swap the operands.
528 if (cmpInstr->getOpcode() == Hexagon::CMPEQrr &&
529 feederReg == (unsigned) cmpOp2) {
530 unsigned tmp = cmpReg1;
531 bool tmpIsKill = MO1IsKill;
533 MO1IsKill = MO2IsKill;
535 MO2IsKill = tmpIsKill;
538 // Now we have swapped the operands, all we need to check is,
539 // if the second operand (after swap) is the feeder.
540 // And if it is, make a note.
541 if (feederReg == (unsigned)cmpOp2)
542 isSecondOpNewified = true;
545 // Now that we are moving feeder close the jump,
546 // make sure we are respecting the kill values of
547 // the operands of the feeder.
549 bool updatedIsKill = false;
550 for (unsigned i = 0; i < MI->getNumOperands(); i++) {
551 MachineOperand &MO = MI->getOperand(i);
552 if (MO.isReg() && MO.isUse()) {
553 unsigned feederReg = MO.getReg();
554 for (MachineBasicBlock::iterator localII = feederPos,
555 end = jmpPos; localII != end; localII++) {
556 MachineInstr *localMI = localII;
557 for (unsigned j = 0; j < localMI->getNumOperands(); j++) {
558 MachineOperand &localMO = localMI->getOperand(j);
559 if (localMO.isReg() && localMO.isUse() &&
560 localMO.isKill() && feederReg == localMO.getReg()) {
561 // We found that there is kill of a use register
562 // Set up a kill flag on the register
563 localMO.setIsKill(false);
565 updatedIsKill = true;
569 if (updatedIsKill) break;
572 if (updatedIsKill) break;
575 MBB->splice(jmpPos, MI->getParent(), MI);
576 MBB->splice(jmpPos, MI->getParent(), cmpInstr);
577 DebugLoc dl = MI->getDebugLoc();
580 assert((QII->isNewValueJumpCandidate(cmpInstr)) &&
581 "This compare is not a New Value Jump candidate.");
582 unsigned opc = getNewValueJumpOpcode(cmpInstr, cmpOp2,
586 opc = QII->getInvertedPredicatedOpcode(opc);
589 NewMI = BuildMI(*MBB, jmpPos, dl,
591 .addReg(cmpReg1, getKillRegState(MO1IsKill))
592 .addReg(cmpOp2, getKillRegState(MO2IsKill))
595 else if ((cmpInstr->getOpcode() == Hexagon::CMPEQri ||
596 cmpInstr->getOpcode() == Hexagon::CMPGTri) &&
598 // Corresponding new-value compare jump instructions don't have the
599 // operand for -1 immediate value.
600 NewMI = BuildMI(*MBB, jmpPos, dl,
602 .addReg(cmpReg1, getKillRegState(MO1IsKill))
606 NewMI = BuildMI(*MBB, jmpPos, dl,
608 .addReg(cmpReg1, getKillRegState(MO1IsKill))
612 assert(NewMI && "New Value Jump Instruction Not created!");
613 if (cmpInstr->getOperand(0).isReg() &&
614 cmpInstr->getOperand(0).isKill())
615 cmpInstr->getOperand(0).setIsKill(false);
616 if (cmpInstr->getOperand(1).isReg() &&
617 cmpInstr->getOperand(1).isKill())
618 cmpInstr->getOperand(1).setIsKill(false);
619 cmpInstr->eraseFromParent();
620 jmpInstr->eraseFromParent();
633 FunctionPass *llvm::createHexagonNewValueJump() {
634 return new HexagonNewValueJump();