lib/Target/Hexagon/HexagonIntrinsics.td

   1 //===-- HexagonIntrinsics.td - Instruction intrinsics ------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 // This is populated based on the following specs:
  10 // Hexagon V2 Architecture
  11 // Application-Level Specification
  12 // 80-V9418-8 Rev. B
  13 // March 4, 2008
  14 //===----------------------------------------------------------------------===//
  15
  16 class T_I_pat <InstHexagon MI, Intrinsic IntID>
  17   : Pat <(IntID imm:$Is),
  18          (MI imm:$Is)>;
  19
  20 class T_R_pat <InstHexagon MI, Intrinsic IntID>
  21   : Pat <(IntID I32:$Rs),
  22          (MI I32:$Rs)>;
  23
  24 class T_II_pat <InstHexagon MI, Intrinsic IntID, PatFrag Imm1, PatFrag Imm2>
  25   : Pat<(IntID Imm1:$Is, Imm2:$It),
  26         (MI Imm1:$Is, Imm2:$It)>;
  27
  28 class T_RI_pat <InstHexagon MI, Intrinsic IntID, PatLeaf ImmPred = PatLeaf<(i32 imm)>>
  29   : Pat<(IntID I32:$Rs, ImmPred:$It),
  30         (MI I32:$Rs, ImmPred:$It)>;
  31
  32 class T_IR_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred = PatLeaf<(i32 imm)>>
  33   : Pat<(IntID ImmPred:$Is, I32:$Rt),
  34         (MI ImmPred:$Is, I32:$Rt)>;
  35
  36 class T_RR_pat <InstHexagon MI, Intrinsic IntID>
  37   : Pat <(IntID I32:$Rs, I32:$Rt),
  38          (MI I32:$Rs, I32:$Rt)>;
  39
  40 class T_PP_pat <InstHexagon MI, Intrinsic IntID>
  41   : Pat <(IntID I64:$Rs, I64:$Rt),
  42          (MI DoubleRegs:$Rs, DoubleRegs:$Rt)>;
  43
  44 class T_QII_pat <InstHexagon MI, Intrinsic IntID, PatFrag Imm1, PatFrag Imm2>
  45   : Pat <(IntID (i32 PredRegs:$Ps), Imm1:$Is, Imm2:$It),
  46          (MI PredRegs:$Ps, Imm1:$Is, Imm2:$It)>;
  47
  48 class T_QRI_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred>
  49   : Pat <(IntID (i32 PredRegs:$Ps), I32:$Rs, ImmPred:$Is),
  50          (MI PredRegs:$Ps, I32:$Rs, ImmPred:$Is)>;
  51
  52 class T_QIR_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred>
  53   : Pat <(IntID (i32 PredRegs:$Ps), ImmPred:$Is, I32:$Rs),
  54          (MI PredRegs:$Ps, ImmPred:$Is, I32:$Rs)>;
  55
  56 class T_RRI_pat <InstHexagon MI, Intrinsic IntID>
  57   : Pat <(IntID I32:$Rs, I32:$Rt, imm:$Iu),
  58          (MI I32:$Rs, I32:$Rt, imm:$Iu)>;
  59
  60 class T_RRR_pat <InstHexagon MI, Intrinsic IntID>
  61   : Pat <(IntID I32:$Rs, I32:$Rt, I32:$Ru),
  62          (MI I32:$Rs, I32:$Rt, I32:$Ru)>;
  63
  64 class T_PRR_pat <InstHexagon MI, Intrinsic IntID>
  65   : Pat <(IntID I64:$Rs, I32:$Rt, I32:$Ru),
  66          (MI DoubleRegs:$Rs, I32:$Rt, I32:$Ru)>;
  67
  68 //===----------------------------------------------------------------------===//
  69 // MPYS / Multipy signed/unsigned halfwords
  70 //Rd=mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
  71 //===----------------------------------------------------------------------===//
  72
  73 def : T_RR_pat <M2_mpy_ll_s1, int_hexagon_M2_mpy_ll_s1>;
  74 def : T_RR_pat <M2_mpy_ll_s0, int_hexagon_M2_mpy_ll_s0>;
  75 def : T_RR_pat <M2_mpy_lh_s1, int_hexagon_M2_mpy_lh_s1>;
  76 def : T_RR_pat <M2_mpy_lh_s0, int_hexagon_M2_mpy_lh_s0>;
  77 def : T_RR_pat <M2_mpy_hl_s1, int_hexagon_M2_mpy_hl_s1>;
  78 def : T_RR_pat <M2_mpy_hl_s0, int_hexagon_M2_mpy_hl_s0>;
  79 def : T_RR_pat <M2_mpy_hh_s1, int_hexagon_M2_mpy_hh_s1>;
  80 def : T_RR_pat <M2_mpy_hh_s0, int_hexagon_M2_mpy_hh_s0>;
  81
  82 def : T_RR_pat <M2_mpyu_ll_s1, int_hexagon_M2_mpyu_ll_s1>;
  83 def : T_RR_pat <M2_mpyu_ll_s0, int_hexagon_M2_mpyu_ll_s0>;
  84 def : T_RR_pat <M2_mpyu_lh_s1, int_hexagon_M2_mpyu_lh_s1>;
  85 def : T_RR_pat <M2_mpyu_lh_s0, int_hexagon_M2_mpyu_lh_s0>;
  86 def : T_RR_pat <M2_mpyu_hl_s1, int_hexagon_M2_mpyu_hl_s1>;
  87 def : T_RR_pat <M2_mpyu_hl_s0, int_hexagon_M2_mpyu_hl_s0>;
  88 def : T_RR_pat <M2_mpyu_hh_s1, int_hexagon_M2_mpyu_hh_s1>;
  89 def : T_RR_pat <M2_mpyu_hh_s0, int_hexagon_M2_mpyu_hh_s0>;
  90
  91 def : T_RR_pat <M2_mpy_sat_ll_s1, int_hexagon_M2_mpy_sat_ll_s1>;
  92 def : T_RR_pat <M2_mpy_sat_ll_s0, int_hexagon_M2_mpy_sat_ll_s0>;
  93 def : T_RR_pat <M2_mpy_sat_lh_s1, int_hexagon_M2_mpy_sat_lh_s1>;
  94 def : T_RR_pat <M2_mpy_sat_lh_s0, int_hexagon_M2_mpy_sat_lh_s0>;
  95 def : T_RR_pat <M2_mpy_sat_hl_s1, int_hexagon_M2_mpy_sat_hl_s1>;
  96 def : T_RR_pat <M2_mpy_sat_hl_s0, int_hexagon_M2_mpy_sat_hl_s0>;
  97 def : T_RR_pat <M2_mpy_sat_hh_s1, int_hexagon_M2_mpy_sat_hh_s1>;
  98 def : T_RR_pat <M2_mpy_sat_hh_s0, int_hexagon_M2_mpy_sat_hh_s0>;
  99
 100 def : T_RR_pat <M2_mpy_rnd_ll_s1, int_hexagon_M2_mpy_rnd_ll_s1>;
 101 def : T_RR_pat <M2_mpy_rnd_ll_s0, int_hexagon_M2_mpy_rnd_ll_s0>;
 102 def : T_RR_pat <M2_mpy_rnd_lh_s1, int_hexagon_M2_mpy_rnd_lh_s1>;
 103 def : T_RR_pat <M2_mpy_rnd_lh_s0, int_hexagon_M2_mpy_rnd_lh_s0>;
 104 def : T_RR_pat <M2_mpy_rnd_hl_s1, int_hexagon_M2_mpy_rnd_hl_s1>;
 105 def : T_RR_pat <M2_mpy_rnd_hl_s0, int_hexagon_M2_mpy_rnd_hl_s0>;
 106 def : T_RR_pat <M2_mpy_rnd_hh_s1, int_hexagon_M2_mpy_rnd_hh_s1>;
 107 def : T_RR_pat <M2_mpy_rnd_hh_s0, int_hexagon_M2_mpy_rnd_hh_s0>;
 108
 109 def : T_RR_pat <M2_mpy_sat_rnd_ll_s1, int_hexagon_M2_mpy_sat_rnd_ll_s1>;
 110 def : T_RR_pat <M2_mpy_sat_rnd_ll_s0, int_hexagon_M2_mpy_sat_rnd_ll_s0>;
 111 def : T_RR_pat <M2_mpy_sat_rnd_lh_s1, int_hexagon_M2_mpy_sat_rnd_lh_s1>;
 112 def : T_RR_pat <M2_mpy_sat_rnd_lh_s0, int_hexagon_M2_mpy_sat_rnd_lh_s0>;
 113 def : T_RR_pat <M2_mpy_sat_rnd_hl_s1, int_hexagon_M2_mpy_sat_rnd_hl_s1>;
 114 def : T_RR_pat <M2_mpy_sat_rnd_hl_s0, int_hexagon_M2_mpy_sat_rnd_hl_s0>;
 115 def : T_RR_pat <M2_mpy_sat_rnd_hh_s1, int_hexagon_M2_mpy_sat_rnd_hh_s1>;
 116 def : T_RR_pat <M2_mpy_sat_rnd_hh_s0, int_hexagon_M2_mpy_sat_rnd_hh_s0>;
 117
 118
 119 //===----------------------------------------------------------------------===//
 120 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
 121 // result from the accumulator.
 122 //Rx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
 123 //===----------------------------------------------------------------------===//
 124
 125 def : T_RRR_pat <M2_mpy_acc_ll_s1, int_hexagon_M2_mpy_acc_ll_s1>;
 126 def : T_RRR_pat <M2_mpy_acc_ll_s0, int_hexagon_M2_mpy_acc_ll_s0>;
 127 def : T_RRR_pat <M2_mpy_acc_lh_s1, int_hexagon_M2_mpy_acc_lh_s1>;
 128 def : T_RRR_pat <M2_mpy_acc_lh_s0, int_hexagon_M2_mpy_acc_lh_s0>;
 129 def : T_RRR_pat <M2_mpy_acc_hl_s1, int_hexagon_M2_mpy_acc_hl_s1>;
 130 def : T_RRR_pat <M2_mpy_acc_hl_s0, int_hexagon_M2_mpy_acc_hl_s0>;
 131 def : T_RRR_pat <M2_mpy_acc_hh_s1, int_hexagon_M2_mpy_acc_hh_s1>;
 132 def : T_RRR_pat <M2_mpy_acc_hh_s0, int_hexagon_M2_mpy_acc_hh_s0>;
 133
 134 def : T_RRR_pat <M2_mpyu_acc_ll_s1, int_hexagon_M2_mpyu_acc_ll_s1>;
 135 def : T_RRR_pat <M2_mpyu_acc_ll_s0, int_hexagon_M2_mpyu_acc_ll_s0>;
 136 def : T_RRR_pat <M2_mpyu_acc_lh_s1, int_hexagon_M2_mpyu_acc_lh_s1>;
 137 def : T_RRR_pat <M2_mpyu_acc_lh_s0, int_hexagon_M2_mpyu_acc_lh_s0>;
 138 def : T_RRR_pat <M2_mpyu_acc_hl_s1, int_hexagon_M2_mpyu_acc_hl_s1>;
 139 def : T_RRR_pat <M2_mpyu_acc_hl_s0, int_hexagon_M2_mpyu_acc_hl_s0>;
 140 def : T_RRR_pat <M2_mpyu_acc_hh_s1, int_hexagon_M2_mpyu_acc_hh_s1>;
 141 def : T_RRR_pat <M2_mpyu_acc_hh_s0, int_hexagon_M2_mpyu_acc_hh_s0>;
 142
 143 def : T_RRR_pat <M2_mpy_nac_ll_s1, int_hexagon_M2_mpy_nac_ll_s1>;
 144 def : T_RRR_pat <M2_mpy_nac_ll_s0, int_hexagon_M2_mpy_nac_ll_s0>;
 145 def : T_RRR_pat <M2_mpy_nac_lh_s1, int_hexagon_M2_mpy_nac_lh_s1>;
 146 def : T_RRR_pat <M2_mpy_nac_lh_s0, int_hexagon_M2_mpy_nac_lh_s0>;
 147 def : T_RRR_pat <M2_mpy_nac_hl_s1, int_hexagon_M2_mpy_nac_hl_s1>;
 148 def : T_RRR_pat <M2_mpy_nac_hl_s0, int_hexagon_M2_mpy_nac_hl_s0>;
 149 def : T_RRR_pat <M2_mpy_nac_hh_s1, int_hexagon_M2_mpy_nac_hh_s1>;
 150 def : T_RRR_pat <M2_mpy_nac_hh_s0, int_hexagon_M2_mpy_nac_hh_s0>;
 151
 152 def : T_RRR_pat <M2_mpyu_nac_ll_s1, int_hexagon_M2_mpyu_nac_ll_s1>;
 153 def : T_RRR_pat <M2_mpyu_nac_ll_s0, int_hexagon_M2_mpyu_nac_ll_s0>;
 154 def : T_RRR_pat <M2_mpyu_nac_lh_s1, int_hexagon_M2_mpyu_nac_lh_s1>;
 155 def : T_RRR_pat <M2_mpyu_nac_lh_s0, int_hexagon_M2_mpyu_nac_lh_s0>;
 156 def : T_RRR_pat <M2_mpyu_nac_hl_s1, int_hexagon_M2_mpyu_nac_hl_s1>;
 157 def : T_RRR_pat <M2_mpyu_nac_hl_s0, int_hexagon_M2_mpyu_nac_hl_s0>;
 158 def : T_RRR_pat <M2_mpyu_nac_hh_s1, int_hexagon_M2_mpyu_nac_hh_s1>;
 159 def : T_RRR_pat <M2_mpyu_nac_hh_s0, int_hexagon_M2_mpyu_nac_hh_s0>;
 160
 161 def : T_RRR_pat <M2_mpy_acc_sat_ll_s1, int_hexagon_M2_mpy_acc_sat_ll_s1>;
 162 def : T_RRR_pat <M2_mpy_acc_sat_ll_s0, int_hexagon_M2_mpy_acc_sat_ll_s0>;
 163 def : T_RRR_pat <M2_mpy_acc_sat_lh_s1, int_hexagon_M2_mpy_acc_sat_lh_s1>;
 164 def : T_RRR_pat <M2_mpy_acc_sat_lh_s0, int_hexagon_M2_mpy_acc_sat_lh_s0>;
 165 def : T_RRR_pat <M2_mpy_acc_sat_hl_s1, int_hexagon_M2_mpy_acc_sat_hl_s1>;
 166 def : T_RRR_pat <M2_mpy_acc_sat_hl_s0, int_hexagon_M2_mpy_acc_sat_hl_s0>;
 167 def : T_RRR_pat <M2_mpy_acc_sat_hh_s1, int_hexagon_M2_mpy_acc_sat_hh_s1>;
 168 def : T_RRR_pat <M2_mpy_acc_sat_hh_s0, int_hexagon_M2_mpy_acc_sat_hh_s0>;
 169
 170 def : T_RRR_pat <M2_mpy_nac_sat_ll_s1, int_hexagon_M2_mpy_nac_sat_ll_s1>;
 171 def : T_RRR_pat <M2_mpy_nac_sat_ll_s0, int_hexagon_M2_mpy_nac_sat_ll_s0>;
 172 def : T_RRR_pat <M2_mpy_nac_sat_lh_s1, int_hexagon_M2_mpy_nac_sat_lh_s1>;
 173 def : T_RRR_pat <M2_mpy_nac_sat_lh_s0, int_hexagon_M2_mpy_nac_sat_lh_s0>;
 174 def : T_RRR_pat <M2_mpy_nac_sat_hl_s1, int_hexagon_M2_mpy_nac_sat_hl_s1>;
 175 def : T_RRR_pat <M2_mpy_nac_sat_hl_s0, int_hexagon_M2_mpy_nac_sat_hl_s0>;
 176 def : T_RRR_pat <M2_mpy_nac_sat_hh_s1, int_hexagon_M2_mpy_nac_sat_hh_s1>;
 177 def : T_RRR_pat <M2_mpy_nac_sat_hh_s0, int_hexagon_M2_mpy_nac_sat_hh_s0>;
 178
 179
 180 //===----------------------------------------------------------------------===//
 181 // Multiply signed/unsigned halfwords with and without saturation and rounding
 182 // into a 64-bits destination register.
 183 //===----------------------------------------------------------------------===//
 184
 185 def : T_RR_pat <M2_mpyd_hh_s0, int_hexagon_M2_mpyd_hh_s0>;
 186 def : T_RR_pat <M2_mpyd_hl_s0, int_hexagon_M2_mpyd_hl_s0>;
 187 def : T_RR_pat <M2_mpyd_lh_s0, int_hexagon_M2_mpyd_lh_s0>;
 188 def : T_RR_pat <M2_mpyd_ll_s0, int_hexagon_M2_mpyd_ll_s0>;
 189 def : T_RR_pat <M2_mpyd_hh_s1, int_hexagon_M2_mpyd_hh_s1>;
 190 def : T_RR_pat <M2_mpyd_hl_s1, int_hexagon_M2_mpyd_hl_s1>;
 191 def : T_RR_pat <M2_mpyd_lh_s1, int_hexagon_M2_mpyd_lh_s1>;
 192 def : T_RR_pat <M2_mpyd_ll_s1, int_hexagon_M2_mpyd_ll_s1>;
 193
 194 def : T_RR_pat <M2_mpyd_rnd_hh_s0, int_hexagon_M2_mpyd_rnd_hh_s0>;
 195 def : T_RR_pat <M2_mpyd_rnd_hl_s0, int_hexagon_M2_mpyd_rnd_hl_s0>;
 196 def : T_RR_pat <M2_mpyd_rnd_lh_s0, int_hexagon_M2_mpyd_rnd_lh_s0>;
 197 def : T_RR_pat <M2_mpyd_rnd_ll_s0, int_hexagon_M2_mpyd_rnd_ll_s0>;
 198 def : T_RR_pat <M2_mpyd_rnd_hh_s1, int_hexagon_M2_mpyd_rnd_hh_s1>;
 199 def : T_RR_pat <M2_mpyd_rnd_hl_s1, int_hexagon_M2_mpyd_rnd_hl_s1>;
 200 def : T_RR_pat <M2_mpyd_rnd_lh_s1, int_hexagon_M2_mpyd_rnd_lh_s1>;
 201 def : T_RR_pat <M2_mpyd_rnd_ll_s1, int_hexagon_M2_mpyd_rnd_ll_s1>;
 202
 203 def : T_RR_pat <M2_mpyud_hh_s0, int_hexagon_M2_mpyud_hh_s0>;
 204 def : T_RR_pat <M2_mpyud_hl_s0, int_hexagon_M2_mpyud_hl_s0>;
 205 def : T_RR_pat <M2_mpyud_lh_s0, int_hexagon_M2_mpyud_lh_s0>;
 206 def : T_RR_pat <M2_mpyud_ll_s0, int_hexagon_M2_mpyud_ll_s0>;
 207 def : T_RR_pat <M2_mpyud_hh_s1, int_hexagon_M2_mpyud_hh_s1>;
 208 def : T_RR_pat <M2_mpyud_hl_s1, int_hexagon_M2_mpyud_hl_s1>;
 209 def : T_RR_pat <M2_mpyud_lh_s1, int_hexagon_M2_mpyud_lh_s1>;
 210 def : T_RR_pat <M2_mpyud_ll_s1, int_hexagon_M2_mpyud_ll_s1>;
 211
 212 //===----------------------------------------------------------------------===//
 213 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
 214 // result from the 64-bit destination register.
 215 //Rxx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
 216 //===----------------------------------------------------------------------===//
 217
 218 def : T_PRR_pat <M2_mpyd_acc_hh_s0, int_hexagon_M2_mpyd_acc_hh_s0>;
 219 def : T_PRR_pat <M2_mpyd_acc_hl_s0, int_hexagon_M2_mpyd_acc_hl_s0>;
 220 def : T_PRR_pat <M2_mpyd_acc_lh_s0, int_hexagon_M2_mpyd_acc_lh_s0>;
 221 def : T_PRR_pat <M2_mpyd_acc_ll_s0, int_hexagon_M2_mpyd_acc_ll_s0>;
 222
 223 def : T_PRR_pat <M2_mpyd_acc_hh_s1, int_hexagon_M2_mpyd_acc_hh_s1>;
 224 def : T_PRR_pat <M2_mpyd_acc_hl_s1, int_hexagon_M2_mpyd_acc_hl_s1>;
 225 def : T_PRR_pat <M2_mpyd_acc_lh_s1, int_hexagon_M2_mpyd_acc_lh_s1>;
 226 def : T_PRR_pat <M2_mpyd_acc_ll_s1, int_hexagon_M2_mpyd_acc_ll_s1>;
 227
 228 def : T_PRR_pat <M2_mpyd_nac_hh_s0, int_hexagon_M2_mpyd_nac_hh_s0>;
 229 def : T_PRR_pat <M2_mpyd_nac_hl_s0, int_hexagon_M2_mpyd_nac_hl_s0>;
 230 def : T_PRR_pat <M2_mpyd_nac_lh_s0, int_hexagon_M2_mpyd_nac_lh_s0>;
 231 def : T_PRR_pat <M2_mpyd_nac_ll_s0, int_hexagon_M2_mpyd_nac_ll_s0>;
 232
 233 def : T_PRR_pat <M2_mpyd_nac_hh_s1, int_hexagon_M2_mpyd_nac_hh_s1>;
 234 def : T_PRR_pat <M2_mpyd_nac_hl_s1, int_hexagon_M2_mpyd_nac_hl_s1>;
 235 def : T_PRR_pat <M2_mpyd_nac_lh_s1, int_hexagon_M2_mpyd_nac_lh_s1>;
 236 def : T_PRR_pat <M2_mpyd_nac_ll_s1, int_hexagon_M2_mpyd_nac_ll_s1>;
 237
 238 def : T_PRR_pat <M2_mpyud_acc_hh_s0, int_hexagon_M2_mpyud_acc_hh_s0>;
 239 def : T_PRR_pat <M2_mpyud_acc_hl_s0, int_hexagon_M2_mpyud_acc_hl_s0>;
 240 def : T_PRR_pat <M2_mpyud_acc_lh_s0, int_hexagon_M2_mpyud_acc_lh_s0>;
 241 def : T_PRR_pat <M2_mpyud_acc_ll_s0, int_hexagon_M2_mpyud_acc_ll_s0>;
 242
 243 def : T_PRR_pat <M2_mpyud_acc_hh_s1, int_hexagon_M2_mpyud_acc_hh_s1>;
 244 def : T_PRR_pat <M2_mpyud_acc_hl_s1, int_hexagon_M2_mpyud_acc_hl_s1>;
 245 def : T_PRR_pat <M2_mpyud_acc_lh_s1, int_hexagon_M2_mpyud_acc_lh_s1>;
 246 def : T_PRR_pat <M2_mpyud_acc_ll_s1, int_hexagon_M2_mpyud_acc_ll_s1>;
 247
 248 def : T_PRR_pat <M2_mpyud_nac_hh_s0, int_hexagon_M2_mpyud_nac_hh_s0>;
 249 def : T_PRR_pat <M2_mpyud_nac_hl_s0, int_hexagon_M2_mpyud_nac_hl_s0>;
 250 def : T_PRR_pat <M2_mpyud_nac_lh_s0, int_hexagon_M2_mpyud_nac_lh_s0>;
 251 def : T_PRR_pat <M2_mpyud_nac_ll_s0, int_hexagon_M2_mpyud_nac_ll_s0>;
 252
 253 def : T_PRR_pat <M2_mpyud_nac_hh_s1, int_hexagon_M2_mpyud_nac_hh_s1>;
 254 def : T_PRR_pat <M2_mpyud_nac_hl_s1, int_hexagon_M2_mpyud_nac_hl_s1>;
 255 def : T_PRR_pat <M2_mpyud_nac_lh_s1, int_hexagon_M2_mpyud_nac_lh_s1>;
 256 def : T_PRR_pat <M2_mpyud_nac_ll_s1, int_hexagon_M2_mpyud_nac_ll_s1>;
 257
 258
 259 //===----------------------------------------------------------------------===//
 260 // Add/Subtract halfword
 261 // Rd=add(Rt.L,Rs.[HL])[:sat]
 262 // Rd=sub(Rt.L,Rs.[HL])[:sat]
 263 // Rd=add(Rt.[LH],Rs.[HL])[:sat][:<16]
 264 // Rd=sub(Rt.[LH],Rs.[HL])[:sat][:<16]
 265 //===----------------------------------------------------------------------===//
 266
 267 //Rd=add(Rt.L,Rs.[LH])
 268 def : T_RR_pat <A2_addh_l16_ll,     int_hexagon_A2_addh_l16_ll>;
 269 def : T_RR_pat <A2_addh_l16_hl,     int_hexagon_A2_addh_l16_hl>;
 270
 271 //Rd=add(Rt.L,Rs.[LH]):sat
 272 def : T_RR_pat <A2_addh_l16_sat_ll, int_hexagon_A2_addh_l16_sat_ll>;
 273 def : T_RR_pat <A2_addh_l16_sat_hl, int_hexagon_A2_addh_l16_sat_hl>;
 274
 275 //Rd=sub(Rt.L,Rs.[LH])
 276 def : T_RR_pat <A2_subh_l16_ll,     int_hexagon_A2_subh_l16_ll>;
 277 def : T_RR_pat <A2_subh_l16_hl,     int_hexagon_A2_subh_l16_hl>;
 278
 279 //Rd=sub(Rt.L,Rs.[LH]):sat
 280 def : T_RR_pat <A2_subh_l16_sat_ll, int_hexagon_A2_subh_l16_sat_ll>;
 281 def : T_RR_pat <A2_subh_l16_sat_hl, int_hexagon_A2_subh_l16_sat_hl>;
 282
 283 //Rd=add(Rt.[LH],Rs.[LH]):<<16
 284 def : T_RR_pat <A2_addh_h16_ll,     int_hexagon_A2_addh_h16_ll>;
 285 def : T_RR_pat <A2_addh_h16_lh,     int_hexagon_A2_addh_h16_lh>;
 286 def : T_RR_pat <A2_addh_h16_hl,     int_hexagon_A2_addh_h16_hl>;
 287 def : T_RR_pat <A2_addh_h16_hh,     int_hexagon_A2_addh_h16_hh>;
 288
 289 //Rd=sub(Rt.[LH],Rs.[LH]):<<16
 290 def : T_RR_pat <A2_subh_h16_ll,     int_hexagon_A2_subh_h16_ll>;
 291 def : T_RR_pat <A2_subh_h16_lh,     int_hexagon_A2_subh_h16_lh>;
 292 def : T_RR_pat <A2_subh_h16_hl,     int_hexagon_A2_subh_h16_hl>;
 293 def : T_RR_pat <A2_subh_h16_hh,     int_hexagon_A2_subh_h16_hh>;
 294
 295 //Rd=add(Rt.[LH],Rs.[LH]):sat:<<16
 296 def : T_RR_pat <A2_addh_h16_sat_ll, int_hexagon_A2_addh_h16_sat_ll>;
 297 def : T_RR_pat <A2_addh_h16_sat_lh, int_hexagon_A2_addh_h16_sat_lh>;
 298 def : T_RR_pat <A2_addh_h16_sat_hl, int_hexagon_A2_addh_h16_sat_hl>;
 299 def : T_RR_pat <A2_addh_h16_sat_hh, int_hexagon_A2_addh_h16_sat_hh>;
 300
 301 //Rd=sub(Rt.[LH],Rs.[LH]):sat:<<16
 302 def : T_RR_pat <A2_subh_h16_sat_ll, int_hexagon_A2_subh_h16_sat_ll>;
 303 def : T_RR_pat <A2_subh_h16_sat_lh, int_hexagon_A2_subh_h16_sat_lh>;
 304 def : T_RR_pat <A2_subh_h16_sat_hl, int_hexagon_A2_subh_h16_sat_hl>;
 305 def : T_RR_pat <A2_subh_h16_sat_hh, int_hexagon_A2_subh_h16_sat_hh>;
 306
 307 // ALU64 / ALU / min max
 308 def : T_RR_pat<A2_max,  int_hexagon_A2_max>;
 309 def : T_RR_pat<A2_min,  int_hexagon_A2_min>;
 310 def : T_RR_pat<A2_maxu, int_hexagon_A2_maxu>;
 311 def : T_RR_pat<A2_minu, int_hexagon_A2_minu>;
 312
 313 /********************************************************************
 314 *            ALU32/ALU                                              *
 315 *********************************************************************/
 316 def : T_RR_pat<A2_add,      int_hexagon_A2_add>;
 317 def : T_RI_pat<ADD_ri,      int_hexagon_A2_addi>;
 318 def : T_RR_pat<A2_sub,      int_hexagon_A2_sub>;
 319 def : T_IR_pat<SUB_ri,      int_hexagon_A2_subri>;
 320 def : T_RR_pat<A2_and,      int_hexagon_A2_and>;
 321 def : T_RI_pat<AND_ri,      int_hexagon_A2_andir>;
 322 def : T_RR_pat<A2_or,       int_hexagon_A2_or>;
 323 def : T_RI_pat<OR_ri,       int_hexagon_A2_orir>;
 324 def : T_RR_pat<A2_xor,      int_hexagon_A2_xor>;
 325 def : T_RR_pat<A2_combinew, int_hexagon_A2_combinew>;
 326
 327 // Assembler mapped from Rd32=not(Rs32) to Rd32=sub(#-1,Rs32)
 328 def : Pat <(int_hexagon_A2_not (I32:$Rs)),
 329            (SUB_ri -1, IntRegs:$Rs)>;
 330
 331 // Assembler mapped from Rd32=neg(Rs32) to Rd32=sub(#0,Rs32)
 332 def : Pat <(int_hexagon_A2_neg IntRegs:$Rs),
 333            (SUB_ri 0, IntRegs:$Rs)>;
 334
 335 // Transfer immediate
 336 def  : Pat <(int_hexagon_A2_tfril (I32:$Rs), u16_0ImmPred:$Is),
 337             (A2_tfril IntRegs:$Rs, u16_0ImmPred:$Is)>;
 338 def  : Pat <(int_hexagon_A2_tfrih (I32:$Rs), u16_0ImmPred:$Is),
 339             (A2_tfrih IntRegs:$Rs, u16_0ImmPred:$Is)>;
 340
 341 //  Transfer Register/immediate.
 342 def : T_R_pat <A2_tfr, int_hexagon_A2_tfr>;
 343 def : T_I_pat <A2_tfrsi, int_hexagon_A2_tfrsi>;
 344
 345 // Assembler mapped from Rdd32=Rss32 to Rdd32=combine(Rss.H32,Rss.L32)
 346 def : Pat<(int_hexagon_A2_tfrp DoubleRegs:$src),
 347           (A2_combinew (HiReg DoubleRegs:$src), (LoReg DoubleRegs:$src))>;
 348
 349 /********************************************************************
 350 *            ALU32/PERM                                             *
 351 *********************************************************************/
 352 // Combine
 353 def: T_RR_pat<A2_combine_hh, int_hexagon_A2_combine_hh>;
 354 def: T_RR_pat<A2_combine_hl, int_hexagon_A2_combine_hl>;
 355 def: T_RR_pat<A2_combine_lh, int_hexagon_A2_combine_lh>;
 356 def: T_RR_pat<A2_combine_ll, int_hexagon_A2_combine_ll>;
 357
 358 def: T_II_pat<A2_combineii, int_hexagon_A2_combineii, s8ExtPred, s8ImmPred>;
 359
 360 def: Pat<(i32 (int_hexagon_C2_mux (I32:$Rp), (I32:$Rs),
 361                                                      (I32:$Rt))),
 362          (i32 (C2_mux (C2_tfrrp IntRegs:$Rp), IntRegs:$Rs, IntRegs:$Rt))>;
 363
 364 // Mux
 365 def : T_QRI_pat<C2_muxir, int_hexagon_C2_muxir, s8ExtPred>;
 366 def : T_QIR_pat<C2_muxri, int_hexagon_C2_muxri, s8ExtPred>;
 367 def : T_QII_pat<C2_muxii, int_hexagon_C2_muxii, s8ExtPred, s8ImmPred>;
 368
 369 // Shift halfword
 370 def : T_R_pat<A2_aslh, int_hexagon_A2_aslh>;
 371 def : T_R_pat<A2_asrh, int_hexagon_A2_asrh>;
 372 def : T_R_pat<A2_asrh, int_hexagon_SI_to_SXTHI_asrh>;
 373
 374 // Sign/zero extend
 375 def : T_R_pat<A2_sxth, int_hexagon_A2_sxth>;
 376 def : T_R_pat<A2_sxtb, int_hexagon_A2_sxtb>;
 377 def : T_R_pat<A2_zxth, int_hexagon_A2_zxth>;
 378 def : T_R_pat<A2_zxtb, int_hexagon_A2_zxtb>;
 379
 380 /********************************************************************
 381 *            ALU64/ALU                                              *
 382 *********************************************************************/
 383 def: T_RR_pat<A2_addsat,   int_hexagon_A2_addsat>;
 384 def: T_RR_pat<A2_subsat,   int_hexagon_A2_subsat>;
 385 def: T_PP_pat<A2_addp,     int_hexagon_A2_addp>;
 386 def: T_PP_pat<A2_subp,     int_hexagon_A2_subp>;
 387
 388 def: T_PP_pat<A2_andp,     int_hexagon_A2_andp>;
 389 def: T_PP_pat<A2_orp,      int_hexagon_A2_orp>;
 390 def: T_PP_pat<A2_xorp,     int_hexagon_A2_xorp>;
 391
 392 def: T_PP_pat<S2_parityp,  int_hexagon_S2_parityp>;
 393 def: T_RR_pat<S2_packhl,   int_hexagon_S2_packhl>;
 394
 395 // Multiply 32x32 and use lower result
 396 def : T_RRI_pat <M2_macsip, int_hexagon_M2_macsip>;
 397 def : T_RRI_pat <M2_macsin, int_hexagon_M2_macsin>;
 398 def : T_RRR_pat <M2_maci, int_hexagon_M2_maci>;
 399
 400 // Subtract and accumulate
 401 def : T_RRR_pat <M2_subacc, int_hexagon_M2_subacc>;
 402
 403 // Add and accumulate
 404 def : T_RRR_pat <M2_acci,   int_hexagon_M2_acci>;
 405 def : T_RRR_pat <M2_nacci,  int_hexagon_M2_nacci>;
 406 def : T_RRI_pat <M2_accii,  int_hexagon_M2_accii>;
 407 def : T_RRI_pat <M2_naccii, int_hexagon_M2_naccii>;
 408
 409 // XOR and XOR with destination
 410 def : T_RRR_pat <M2_xor_xacc, int_hexagon_M2_xor_xacc>;
 411
 412 //
 413 // ALU 32 types.
 414 //
 415
 416 class qi_ALU32_sisi<string opc, Intrinsic IntID>
 417   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 418              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 419              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 420
 421 class qi_ALU32_sis10<string opc, Intrinsic IntID>
 422   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
 423              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 424              [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 425
 426 class qi_ALU32_sis8<string opc, Intrinsic IntID>
 427   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
 428              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 429              [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 430
 431 class qi_ALU32_siu8<string opc, Intrinsic IntID>
 432   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
 433              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 434              [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 435
 436 class qi_ALU32_siu9<string opc, Intrinsic IntID>
 437   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u9Imm:$src2),
 438              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 439              [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 440
 441 class si_ALU32_qisisi<string opc, Intrinsic IntID>
 442   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
 443                                       IntRegs:$src3),
 444              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
 445              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
 446                                         IntRegs:$src3))]>;
 447
 448 class si_ALU32_qis8si<string opc, Intrinsic IntID>
 449   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2,
 450                                        IntRegs:$src3),
 451              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, $src3)")),
 452              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2,
 453                                         IntRegs:$src3))]>;
 454
 455 class si_ALU32_qisis8<string opc, Intrinsic IntID>
 456   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
 457                                        s8Imm:$src3),
 458              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
 459              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
 460                                         imm:$src3))]>;
 461
 462 class si_ALU32_qis8s8<string opc, Intrinsic IntID>
 463   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2, s8Imm:$src3),
 464              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, #$src3)")),
 465              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2, imm:$src3))]>;
 466
 467 class si_ALU32_sisi<string opc, Intrinsic IntID>
 468   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 469              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 470              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 471
 472 class si_ALU32_sisi_sat<string opc, Intrinsic IntID>
 473   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 474              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
 475              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 476
 477 class si_ALU32_sisi_rnd<string opc, Intrinsic IntID>
 478   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 479              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
 480              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 481
 482 class si_ALU32_sis16<string opc, Intrinsic IntID>
 483   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s16Imm:$src2),
 484              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 485              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 486
 487 class si_ALU32_sis10<string opc, Intrinsic IntID>
 488   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
 489              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 490              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 491
 492 class si_ALU32_s10si<string opc, Intrinsic IntID>
 493   : ALU32_rr<(outs IntRegs:$dst), (ins s10Imm:$src1, IntRegs:$src2),
 494              !strconcat("$dst = ", !strconcat(opc , "(#$src1, $src2)")),
 495              [(set IntRegs:$dst, (IntID imm:$src1, IntRegs:$src2))]>;
 496
 497 class si_lo_ALU32_siu16<string opc, Intrinsic IntID>
 498   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u16Imm:$src2),
 499              !strconcat("$dst.l = ", !strconcat(opc , "#$src2")),
 500              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 501
 502 class si_hi_ALU32_siu16<string opc, Intrinsic IntID>
 503   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u16Imm:$src2),
 504              !strconcat("$dst.h = ", !strconcat(opc , "#$src2")),
 505              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 506
 507 class si_ALU32_s16<string opc, Intrinsic IntID>
 508   : ALU32_rr<(outs IntRegs:$dst), (ins s16Imm:$src1),
 509              !strconcat("$dst = ", !strconcat(opc , "#$src1")),
 510              [(set IntRegs:$dst, (IntID imm:$src1))]>;
 511
 512 class di_ALU32_s8<string opc, Intrinsic IntID>
 513   : ALU32_rr<(outs DoubleRegs:$dst), (ins s8Imm:$src1),
 514              !strconcat("$dst = ", !strconcat(opc , "#$src1")),
 515              [(set DoubleRegs:$dst, (IntID imm:$src1))]>;
 516
 517 class di_ALU64_di<string opc, Intrinsic IntID>
 518   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
 519              !strconcat("$dst = ", !strconcat(opc , "$src")),
 520              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
 521
 522 class si_ALU32_si<string opc, Intrinsic IntID>
 523   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
 524              !strconcat("$dst = ", !strconcat(opc , "($src)")),
 525              [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
 526
 527 class si_ALU32_si_tfr<string opc, Intrinsic IntID>
 528   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
 529              !strconcat("$dst = ", !strconcat(opc , "$src")),
 530              [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
 531
 532 //
 533 // ALU 64 types.
 534 //
 535
 536 class si_ALU64_si_sat<string opc, Intrinsic IntID>
 537   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
 538              !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
 539              [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
 540
 541 class si_ALU64_didi<string opc, Intrinsic IntID>
 542   : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 543              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 544              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
 545
 546 class di_ALU64_sidi<string opc, Intrinsic IntID>
 547   : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2),
 548              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 549              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2))]>;
 550
 551 class di_ALU64_didi<string opc, Intrinsic IntID>
 552   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 553              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 554              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
 555                                            DoubleRegs:$src2))]>;
 556
 557 class di_ALU64_qididi<string opc, Intrinsic IntID>
 558   : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2,
 559                                           DoubleRegs:$src3),
 560              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
 561              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2,
 562                                            DoubleRegs:$src3))]>;
 563
 564 class di_ALU64_sisi<string opc, Intrinsic IntID>
 565   : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 566              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 567              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 568
 569 class di_ALU64_didi_sat<string opc, Intrinsic IntID>
 570   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 571              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
 572              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
 573                                            DoubleRegs:$src2))]>;
 574
 575 class di_ALU64_didi_rnd<string opc, Intrinsic IntID>
 576   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 577              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
 578              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
 579                                            DoubleRegs:$src2))]>;
 580
 581 class di_ALU64_didi_crnd<string opc, Intrinsic IntID>
 582   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 583              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):crnd")),
 584              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
 585                                            DoubleRegs:$src2))]>;
 586
 587 class di_ALU64_didi_rnd_sat<string opc, Intrinsic IntID>
 588   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 589              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd:sat")),
 590              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
 591                                            DoubleRegs:$src2))]>;
 592
 593 class di_ALU64_didi_crnd_sat<string opc, Intrinsic IntID>
 594   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 595              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):crnd:sat")),
 596              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
 597                                            DoubleRegs:$src2))]>;
 598
 599 class qi_ALU64_didi<string opc, Intrinsic IntID>
 600   : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 601              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 602              [(set PredRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
 603
 604 class si_ALU64_sisi<string opc, Intrinsic IntID>
 605   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 606              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 607              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 608
 609 class si_ALU64_sisi_sat_lh<string opc, Intrinsic IntID>
 610   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 611              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):sat")),
 612              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 613
 614 class si_ALU64_sisi_l16_sat_hh<string opc, Intrinsic IntID>
 615   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 616              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):sat")),
 617              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 618
 619 class si_ALU64_sisi_l16_sat_lh<string opc, Intrinsic IntID>
 620   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 621              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):sat")),
 622              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 623
 624 class si_ALU64_sisi_l16_sat_hl<string opc, Intrinsic IntID>
 625   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 626              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):sat")),
 627              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 628
 629 class si_ALU64_sisi_l16_sat_ll<string opc, Intrinsic IntID>
 630   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 631              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):sat")),
 632              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 633
 634 class si_ALU64_sisi_l16_hh<string opc, Intrinsic IntID>
 635   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 636              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H)")),
 637              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 638
 639 class si_ALU64_sisi_l16_hl<string opc, Intrinsic IntID>
 640   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 641              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L)")),
 642              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 643
 644 class si_ALU64_sisi_l16_lh<string opc, Intrinsic IntID>
 645   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 646              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
 647              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 648
 649 class si_ALU64_sisi_l16_ll<string opc, Intrinsic IntID>
 650   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 651              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
 652              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 653
 654 class si_ALU64_sisi_h16_sat_hh<string opc, Intrinsic IntID>
 655   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 656              !strconcat("$dst = ", !strconcat(opc ,
 657                                               "($src1.H, $src2.H):sat:<<16")),
 658              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 659
 660 class si_ALU64_sisi_h16_sat_lh<string opc, Intrinsic IntID>
 661   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 662              !strconcat("$dst = ", !strconcat(opc ,
 663                                               "($src1.L, $src2.H):sat:<<16")),
 664              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 665
 666 class si_ALU64_sisi_h16_sat_hl<string opc, Intrinsic IntID>
 667   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 668              !strconcat("$dst = ", !strconcat(opc ,
 669                                               "($src1.H, $src2.L):sat:<<16")),
 670              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 671
 672 class si_ALU64_sisi_h16_sat_ll<string opc, Intrinsic IntID>
 673   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 674              !strconcat("$dst = ", !strconcat(opc ,
 675                                               "($src1.L, $src2.L):sat:<<16")),
 676              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 677
 678 class si_ALU64_sisi_h16_hh<string opc, Intrinsic IntID>
 679   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 680              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):<<16")),
 681              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 682
 683 class si_ALU64_sisi_h16_hl<string opc, Intrinsic IntID>
 684   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 685              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):<<16")),
 686              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 687
 688 class si_ALU64_sisi_h16_lh<string opc, Intrinsic IntID>
 689   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 690              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):<<16")),
 691              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 692
 693 class si_ALU64_sisi_h16_ll<string opc, Intrinsic IntID>
 694   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 695              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):<<16")),
 696              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 697
 698 class si_ALU64_sisi_lh<string opc, Intrinsic IntID>
 699   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 700              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
 701              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 702
 703 class si_ALU64_sisi_ll<string opc, Intrinsic IntID>
 704   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 705              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
 706              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 707
 708 class si_ALU64_sisi_sat<string opc, Intrinsic IntID>
 709   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 710              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
 711              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 712
 713 //
 714 // SInst classes.
 715 //
 716
 717 class qi_SInst_qi<string opc, Intrinsic IntID>
 718   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
 719              !strconcat("$dst = ", !strconcat(opc , "($src)")),
 720              [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
 721
 722 class qi_SInst_qi_pxfer<string opc, Intrinsic IntID>
 723   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
 724              !strconcat("$dst = ", !strconcat(opc , "$src")),
 725              [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
 726
 727 class qi_SInst_qiqi<string opc, Intrinsic IntID>
 728   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 729              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 730              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 731
 732 class qi_SInst_qiqi_neg<string opc, Intrinsic IntID>
 733   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 734              !strconcat("$dst = ", !strconcat(opc , "($src1, !$src2)")),
 735              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 736
 737 class di_SInst_di<string opc, Intrinsic IntID>
 738   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
 739              !strconcat("$dst = ", !strconcat(opc , "($src)")),
 740              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
 741
 742 class di_SInst_di_sat<string opc, Intrinsic IntID>
 743   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
 744              !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
 745              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
 746
 747 class si_SInst_di<string opc, Intrinsic IntID>
 748   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src),
 749           !strconcat("$dst = ", !strconcat(opc , "($src)")),
 750           [(set IntRegs:$dst, (IntID DoubleRegs:$src))]>;
 751
 752 class si_SInst_di_sat<string opc, Intrinsic IntID>
 753   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src),
 754           !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
 755           [(set IntRegs:$dst, (IntID DoubleRegs:$src))]>;
 756
 757 class di_SInst_disi<string opc, Intrinsic IntID>
 758   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
 759           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 760           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
 761
 762 class di_SInst_didi<string opc, Intrinsic IntID>
 763   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 764           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 765           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
 766
 767 class di_SInst_si<string opc, Intrinsic IntID>
 768   : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
 769           !strconcat("$dst = ", !strconcat(opc , "($src1)")),
 770           [(set DoubleRegs:$dst, (IntID IntRegs:$src1))]>;
 771
 772 class si_SInst_sisiu3<string opc, Intrinsic IntID>
 773   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, u3Imm:$src3),
 774           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
 775           [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
 776                                      imm:$src3))]>;
 777
 778 class si_SInst_diu5<string opc, Intrinsic IntID>
 779   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, u5Imm:$src2),
 780           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 781           [(set IntRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2))]>;
 782
 783 class si_SInst_disi<string opc, Intrinsic IntID>
 784   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
 785           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 786           [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
 787
 788 class si_SInst_sidi<string opc, Intrinsic IntID>
 789   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2),
 790           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 791           [(set IntRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2))]>;
 792
 793 class di_SInst_disisi<string opc, Intrinsic IntID>
 794   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2,
 795                                        IntRegs:$src3),
 796           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
 797           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2,
 798                                         IntRegs:$src3))]>;
 799
 800 class di_SInst_sisi<string opc, Intrinsic IntID>
 801   : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 802           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 803           [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 804
 805 class qi_SInst_siu5<string opc, Intrinsic IntID>
 806   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
 807           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 808           [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 809
 810 class qi_SInst_siu6<string opc, Intrinsic IntID>
 811   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u6Imm:$src2),
 812           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 813           [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 814
 815 class qi_SInst_sisi<string opc, Intrinsic IntID>
 816   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 817           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 818           [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 819
 820 class si_SInst_si<string opc, Intrinsic IntID>
 821   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
 822           !strconcat("$dst = ", !strconcat(opc , "($src)")),
 823           [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
 824
 825 class si_SInst_si_sat<string opc, Intrinsic IntID>
 826   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
 827           !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
 828           [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
 829
 830 class di_SInst_qi<string opc, Intrinsic IntID>
 831   : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src),
 832           !strconcat("$dst = ", !strconcat(opc , "($src)")),
 833           [(set DoubleRegs:$dst, (IntID IntRegs:$src))]>;
 834
 835 class si_SInst_qi<string opc, Intrinsic IntID>
 836   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
 837           !strconcat("$dst = ", !strconcat(opc , "$src")),
 838           [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
 839
 840 class si_SInst_qiqi<string opc, Intrinsic IntID>
 841   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 842           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 843           [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 844
 845 class qi_SInst_si<string opc, Intrinsic IntID>
 846   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
 847           !strconcat("$dst = ", !strconcat(opc , "$src")),
 848           [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
 849
 850 class si_SInst_sisi<string opc, Intrinsic IntID>
 851   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 852           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 853           [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 854
 855 class di_SInst_diu6<string opc, Intrinsic IntID>
 856   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
 857           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 858           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2))]>;
 859
 860 class si_SInst_siu5<string opc, Intrinsic IntID>
 861   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
 862           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 863           [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 864
 865 class si_SInst_siu5_rnd<string opc, Intrinsic IntID>
 866   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
 867           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2):rnd")),
 868           [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 869
 870 class si_SInst_siu5u5<string opc, Intrinsic IntID>
 871   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2, u5Imm:$src3),
 872           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, #$src3)")),
 873           [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2, imm:$src3))]>;
 874
 875 class si_SInst_sisisi_acc<string opc, Intrinsic IntID>
 876   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 877                                         IntRegs:$src2),
 878               !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
 879               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 880                                          IntRegs:$src2))],
 881               "$dst2 = $dst">;
 882
 883 class si_SInst_sisisi_nac<string opc, Intrinsic IntID>
 884   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 885                                         IntRegs:$src2),
 886               !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
 887               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 888                                          IntRegs:$src2))],
 889               "$dst2 = $dst">;
 890
 891 class di_SInst_didisi_acc<string opc, Intrinsic IntID>
 892   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 893                                            IntRegs:$src2),
 894                !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
 895                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
 896                                              DoubleRegs:$src1,
 897                                              IntRegs:$src2))],
 898                "$dst2 = $dst">;
 899
 900 class di_SInst_didisi_nac<string opc, Intrinsic IntID>
 901   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 902                                            IntRegs:$src2),
 903           !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
 904           [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
 905                                         DoubleRegs:$src1, IntRegs:$src2))],
 906           "$dst2 = $dst">;
 907
 908 class si_SInst_sisiu5u5<string opc, Intrinsic IntID>
 909   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 910                                         u5Imm:$src2, u5Imm:$src3),
 911               !strconcat("$dst = ", !strconcat(opc ,
 912                                                "($src1, #$src2, #$src3)")),
 913               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 914                                          imm:$src2, imm:$src3))],
 915               "$dst2 = $dst">;
 916
 917 class si_SInst_sisidi<string opc, Intrinsic IntID>
 918   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 919                                         DoubleRegs:$src2),
 920               !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 921               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 922                                          DoubleRegs:$src2))],
 923               "$dst2 = $dst">;
 924
 925 class di_SInst_didiu6u6<string opc, Intrinsic IntID>
 926   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 927                                            u6Imm:$src2, u6Imm:$src3),
 928               !strconcat("$dst = ", !strconcat(opc ,
 929                                                "($src1, #$src2, #$src3)")),
 930               [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
 931                                             imm:$src2, imm:$src3))],
 932               "$dst2 = $dst">;
 933
 934 class di_SInst_dididi<string opc, Intrinsic IntID>
 935   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 936                                            DoubleRegs:$src2),
 937               !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 938               [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
 939                                             DoubleRegs:$src1,
 940                                             DoubleRegs:$src2))],
 941               "$dst2 = $dst">;
 942
 943 class di_SInst_diu6u6<string opc, Intrinsic IntID>
 944   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2,
 945                                        u6Imm:$src3),
 946           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, #$src3)")),
 947           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2,
 948                                         imm:$src3))]>;
 949
 950 class di_SInst_didiqi<string opc, Intrinsic IntID>
 951   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2,
 952                                        IntRegs:$src3),
 953           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
 954           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2,
 955                                         IntRegs:$src3))]>;
 956
 957 class di_SInst_didiu3<string opc, Intrinsic IntID>
 958   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2,
 959                                        u3Imm:$src3),
 960           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
 961           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2,
 962                                         imm:$src3))]>;
 963
 964 class di_SInst_didisi_or<string opc, Intrinsic IntID>
 965   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 966                                            IntRegs:$src2),
 967           !strconcat("$dst |= ", !strconcat(opc , "($src1, $src2)")),
 968           [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
 969                                         IntRegs:$src2))],
 970           "$dst2 = $dst">;
 971
 972 class di_SInst_didisi_and<string opc, Intrinsic IntID>
 973   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 974                                            IntRegs:$src2),
 975           !strconcat("$dst &= ", !strconcat(opc , "($src1, $src2)")),
 976           [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
 977                                         IntRegs:$src2))],
 978           "$dst2 = $dst">;
 979
 980 class di_SInst_didiu6_and<string opc, Intrinsic IntID>
 981   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 982                                            u6Imm:$src2),
 983           !strconcat("$dst &= ", !strconcat(opc , "($src1, #$src2)")),
 984           [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
 985                                         imm:$src2))],
 986           "$dst2 = $dst">;
 987
 988 class di_SInst_didiu6_or<string opc, Intrinsic IntID>
 989   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 990                                            u6Imm:$src2),
 991           !strconcat("$dst |= ", !strconcat(opc , "($src1, #$src2)")),
 992           [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
 993                                         imm:$src2))],
 994           "$dst2 = $dst">;
 995
 996 class di_SInst_didiu6_xor<string opc, Intrinsic IntID>
 997   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 998                                            u6Imm:$src2),
 999           !strconcat("$dst ^= ", !strconcat(opc , "($src1, #$src2)")),
1000           [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
1001                                         imm:$src2))],
1002           "$dst2 = $dst">;
1003
1004 class si_SInst_sisisi_and<string opc, Intrinsic IntID>
1005   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1006                                         IntRegs:$src2),
1007               !strconcat("$dst &= ", !strconcat(opc , "($src1, $src2)")),
1008               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1009                                          IntRegs:$src2))],
1010               "$dst2 = $dst">;
1011
1012 class si_SInst_sisisi_or<string opc, Intrinsic IntID>
1013   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1014                                         IntRegs:$src2),
1015               !strconcat("$dst |= ", !strconcat(opc , "($src1, $src2)")),
1016               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1017                                          IntRegs:$src2))],
1018               "$dst2 = $dst">;
1019
1020
1021 class si_SInst_sisiu5_and<string opc, Intrinsic IntID>
1022   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1023                                         u5Imm:$src2),
1024               !strconcat("$dst &= ", !strconcat(opc , "($src1, #$src2)")),
1025               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1026                                          imm:$src2))],
1027               "$dst2 = $dst">;
1028
1029 class si_SInst_sisiu5_or<string opc, Intrinsic IntID>
1030   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1031                                         u5Imm:$src2),
1032               !strconcat("$dst |= ", !strconcat(opc , "($src1, #$src2)")),
1033               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1034                                          imm:$src2))],
1035               "$dst2 = $dst">;
1036
1037 class si_SInst_sisiu5_xor<string opc, Intrinsic IntID>
1038   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1039                                         u5Imm:$src2),
1040               !strconcat("$dst ^= ", !strconcat(opc , "($src1, #$src2)")),
1041               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1042                                          imm:$src2))],
1043               "$dst2 = $dst">;
1044
1045 class si_SInst_sisiu5_acc<string opc, Intrinsic IntID>
1046   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1047                                         u5Imm:$src2),
1048               !strconcat("$dst += ", !strconcat(opc , "($src1, #$src2)")),
1049               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1050                                          imm:$src2))],
1051               "$dst2 = $dst">;
1052
1053 class si_SInst_sisiu5_nac<string opc, Intrinsic IntID>
1054   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1055                                         u5Imm:$src2),
1056               !strconcat("$dst -= ", !strconcat(opc , "($src1, #$src2)")),
1057               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1058                                          imm:$src2))],
1059               "$dst2 = $dst">;
1060
1061 class di_SInst_didiu6_acc<string opc, Intrinsic IntID>
1062   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1063                                            u5Imm:$src2),
1064               !strconcat("$dst += ", !strconcat(opc , "($src1, #$src2)")),
1065               [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1066                                             DoubleRegs:$src1, imm:$src2))],
1067               "$dst2 = $dst">;
1068
1069 class di_SInst_didiu6_nac<string opc, Intrinsic IntID>
1070   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1071                                            u5Imm:$src2),
1072               !strconcat("$dst -= ", !strconcat(opc , "($src1, #$src2)")),
1073               [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
1074                                             imm:$src2))],
1075               "$dst2 = $dst">;
1076
1077
1078 //
1079 // MInst classes.
1080 //
1081
1082 class di_MInst_sisi_rnd_hh_s1<string opc, Intrinsic IntID>
1083   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1084                !strconcat("$dst = ", !strconcat(opc ,
1085                                                 "($src1.H, $src2.H):<<1:rnd")),
1086                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1087
1088 class di_MInst_sisi_rnd_hh<string opc, Intrinsic IntID>
1089   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1090                !strconcat("$dst = ", !strconcat(opc ,
1091                                                 "($src1.H, $src2.H):rnd")),
1092                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1093
1094 class di_MInst_sisi_rnd_hl_s1<string opc, Intrinsic IntID>
1095   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1096                !strconcat("$dst = ", !strconcat(opc ,
1097                                                 "($src1.H, $src2.L):<<1:rnd")),
1098                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1099
1100 class di_MInst_sisi_rnd_hl<string opc, Intrinsic IntID>
1101   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1102                !strconcat("$dst = ", !strconcat(opc ,
1103                                                 "($src1.H, $src2.L):rnd")),
1104                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1105
1106 class di_MInst_sisi_rnd_lh_s1<string opc, Intrinsic IntID>
1107   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1108                !strconcat("$dst = ", !strconcat(opc ,
1109                                                 "($src1.L, $src2.H):<<1:rnd")),
1110                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1111
1112 class di_MInst_sisi_rnd_lh<string opc, Intrinsic IntID>
1113   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1114                !strconcat("$dst = ", !strconcat(opc ,
1115                                                 "($src1.L, $src2.H):rnd")),
1116                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1117
1118 class di_MInst_sisi_rnd_ll_s1<string opc, Intrinsic IntID>
1119   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1120                !strconcat("$dst = ", !strconcat(opc ,
1121                                                 "($src1.L, $src2.L):<<1:rnd")),
1122                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1123
1124 class di_MInst_sisi_rnd_ll<string opc, Intrinsic IntID>
1125   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1126                !strconcat("$dst = ", !strconcat(opc ,
1127                                                 "($src1.L, $src2.L):rnd")),
1128                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1129
1130 class di_MInst_disisi_acc<string opc, Intrinsic IntID>
1131   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1132                                            IntRegs:$src2),
1133              !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
1134              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1135                                            IntRegs:$src2))],
1136              "$dst2 = $dst">;
1137
1138 class di_MInst_disisi_nac<string opc, Intrinsic IntID>
1139   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1140                                            IntRegs:$src2),
1141              !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
1142              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1143                                            IntRegs:$src2))],
1144              "$dst2 = $dst">;
1145
1146 class di_MInst_disisi_acc_sat<string opc, Intrinsic IntID>
1147   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1148                                            IntRegs:$src2),
1149              !strconcat("$dst += ", !strconcat(opc , "($src1, $src2):sat")),
1150              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1151                                            IntRegs:$src2))],
1152              "$dst2 = $dst">;
1153
1154 class di_MInst_disisi_nac_sat<string opc, Intrinsic IntID>
1155   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1156                                            IntRegs:$src2),
1157              !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2):sat")),
1158              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1159                                            IntRegs:$src2))],
1160              "$dst2 = $dst">;
1161
1162 class di_MInst_disisi_acc_sat_conj<string opc, Intrinsic IntID>
1163   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1164                                            IntRegs:$src2),
1165              !strconcat("$dst += ", !strconcat(opc , "($src1, $src2*):sat")),
1166              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1167                                            IntRegs:$src2))],
1168              "$dst2 = $dst">;
1169
1170 class di_MInst_disisi_nac_sat_conj<string opc, Intrinsic IntID>
1171   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1172                                            IntRegs:$src2),
1173              !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2*):sat")),
1174              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1175                                            IntRegs:$src2))],
1176              "$dst2 = $dst">;
1177
1178 class di_MInst_disisi_nac_s1_sat<string opc, Intrinsic IntID>
1179   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1180                                            IntRegs:$src2),
1181              !strconcat("$dst -= ", !strconcat(opc ,
1182                                                "($src1, $src2):<<1:sat")),
1183              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1184                                            IntRegs:$src2))],
1185              "$dst2 = $dst">;
1186
1187 class di_MInst_disisi_acc_s1_sat_conj<string opc, Intrinsic IntID>
1188   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1189                                            IntRegs:$src2),
1190              !strconcat("$dst += ", !strconcat(opc ,
1191                                                "($src1, $src2*):<<1:sat")),
1192              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1193                                            IntRegs:$src2))],
1194              "$dst2 = $dst">;
1195
1196 class di_MInst_disisi_nac_s1_sat_conj<string opc, Intrinsic IntID>
1197   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1198                                            IntRegs:$src2),
1199              !strconcat("$dst -= ", !strconcat(opc ,
1200                                                "($src1, $src2*):<<1:sat")),
1201              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1202                                            IntRegs:$src2))],
1203              "$dst2 = $dst">;
1204
1205 class di_MInst_s8s8<string opc, Intrinsic IntID>
1206   : MInst<(outs DoubleRegs:$dst), (ins s8Imm:$src1, s8Imm:$src2),
1207              !strconcat("$dst = ", !strconcat(opc , "(#$src1, #$src2)")),
1208              [(set DoubleRegs:$dst, (IntID imm:$src1, imm:$src2))]>;
1209
1210 class si_MInst_sis9<string opc, Intrinsic IntID>
1211   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Imm:$src2),
1212              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
1213              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
1214
1215 class si_MInst_sisi<string opc, Intrinsic IntID>
1216   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1217              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1218              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1219
1220 class di_MInst_sisi_hh<string opc, Intrinsic IntID>
1221   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1222              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H)")),
1223              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1224
1225 class di_MInst_sisi_hh_s1<string opc, Intrinsic IntID>
1226   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1227              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):<<1")),
1228              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1229
1230 class di_MInst_sisi_lh<string opc, Intrinsic IntID>
1231   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1232              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
1233              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1234
1235 class di_MInst_sisi_lh_s1<string opc, Intrinsic IntID>
1236   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1237              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):<<1")),
1238              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1239
1240 class di_MInst_sisi_hl<string opc, Intrinsic IntID>
1241   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1242              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L)")),
1243              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1244
1245 class di_MInst_sisi_hl_s1<string opc, Intrinsic IntID>
1246   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1247              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):<<1")),
1248              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1249
1250 class di_MInst_sisi_ll<string opc, Intrinsic IntID>
1251   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1252              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
1253              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1254
1255 class di_MInst_sisi_ll_s1<string opc, Intrinsic IntID>
1256   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1257              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):<<1")),
1258              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1259
1260
1261 class si_MInst_sisi_hh<string opc, Intrinsic IntID>
1262   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1263              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H)")),
1264              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1265
1266 class si_MInst_sisi_hh_s1<string opc, Intrinsic IntID>
1267   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1268              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):<<1")),
1269              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1270
1271 class si_MInst_sisi_lh<string opc, Intrinsic IntID>
1272   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1273              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
1274              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1275
1276 class si_MInst_sisi_lh_s1<string opc, Intrinsic IntID>
1277   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1278              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):<<1")),
1279              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1280
1281 class si_MInst_sisi_hl<string opc, Intrinsic IntID>
1282   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1283              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L)")),
1284              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1285
1286 class si_MInst_sisi_hl_s1<string opc, Intrinsic IntID>
1287   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1288              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):<<1")),
1289              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1290
1291 class si_MInst_sisi_ll<string opc, Intrinsic IntID>
1292   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1293              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
1294              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1295
1296 class si_MInst_sisi_ll_s1<string opc, Intrinsic IntID>
1297   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1298              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):<<1")),
1299              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1300
1301 class si_MInst_sisi_up<string opc, Intrinsic IntID>
1302   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1303              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1304              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1305
1306 class di_MInst_didi<string opc, Intrinsic IntID>
1307   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1308              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1309              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1310                                            DoubleRegs:$src2))]>;
1311
1312 class di_MInst_didi_conj<string opc, Intrinsic IntID>
1313   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1314              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2*)")),
1315              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1316                                            DoubleRegs:$src2))]>;
1317
1318 class di_MInst_sisi_s1_sat_conj<string opc, Intrinsic IntID>
1319   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1320              !strconcat("$dst = ", !strconcat(opc ,
1321                                               "($src1, $src2*):<<1:sat")),
1322              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1323
1324 class di_MInst_didi_s1_rnd_sat<string opc, Intrinsic IntID>
1325   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1326              !strconcat("$dst = ", !strconcat(opc ,
1327                                               "($src1, $src2):<<1:rnd:sat")),
1328              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1329                                            DoubleRegs:$src2))]>;
1330
1331 class di_MInst_didi_sat<string opc, Intrinsic IntID>
1332   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1333              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1334              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1335                                            DoubleRegs:$src2))]>;
1336
1337 class di_MInst_didi_rnd_sat<string opc, Intrinsic IntID>
1338   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1339              !strconcat("$dst = ", !strconcat(opc ,
1340                                               "($src1, $src2):rnd:sat")),
1341              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1342                                            DoubleRegs:$src2))]>;
1343
1344 class si_SInst_sisi_sat<string opc, Intrinsic IntID>
1345   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1346           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1347           [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1348
1349 class si_SInst_didi_sat<string opc, Intrinsic IntID>
1350   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1351           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1352           [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1353
1354 class si_SInst_disi_s1_rnd_sat<string opc, Intrinsic IntID>
1355   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1356              !strconcat("$dst = ", !strconcat(opc ,
1357                                               "($src1, $src2):<<1:rnd:sat")),
1358              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
1359
1360 class si_MInst_sisi_s1_rnd_sat<string opc, Intrinsic IntID>
1361   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1362              !strconcat("$dst = ", !strconcat(opc ,
1363                                               "($src1, $src2):<<1:rnd:sat")),
1364              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1365
1366 class si_MInst_sisi_l_s1_rnd_sat<string opc, Intrinsic IntID>
1367   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1368              !strconcat("$dst = ", !strconcat(opc ,
1369                                               "($src1, $src2.L):<<1:rnd:sat")),
1370              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1371
1372 class si_MInst_sisi_h_s1_rnd_sat<string opc, Intrinsic IntID>
1373   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1374              !strconcat("$dst = ", !strconcat(opc ,
1375                                               "($src1, $src2.H):<<1:rnd:sat")),
1376              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1377
1378 class si_MInst_sisi_rnd_sat_conj<string opc, Intrinsic IntID>
1379   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1380              !strconcat("$dst = ", !strconcat(opc ,
1381                                               "($src1, $src2*):rnd:sat")),
1382              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1383
1384 class si_MInst_sisi_s1_rnd_sat_conj<string opc, Intrinsic IntID>
1385   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1386              !strconcat("$dst = ", !strconcat(opc ,
1387                                               "($src1, $src2*):<<1:rnd:sat")),
1388              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1389
1390 class si_MInst_sisi_rnd_sat<string opc, Intrinsic IntID>
1391   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1392              !strconcat("$dst = ", !strconcat(opc ,
1393                                               "($src1, $src2):rnd:sat")),
1394              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1395
1396 class si_MInst_sisi_rnd<string opc, Intrinsic IntID>
1397   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1398              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
1399              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1400
1401 class si_MInst_sisisi_xacc<string opc, Intrinsic IntID>
1402   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1403                                         IntRegs:$src3),
1404              !strconcat("$dst ^= ", !strconcat(opc , "($src2, $src3)")),
1405              [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1406                                         IntRegs:$src3))],
1407              "$dst2 = $dst">;
1408
1409 class si_MInst_sisisi_acc<string opc, Intrinsic IntID>
1410   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1411                                         IntRegs:$src3),
1412              !strconcat("$dst += ", !strconcat(opc , "($src2, $src3)")),
1413              [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1414                                         IntRegs:$src3))],
1415              "$dst2 = $dst">;
1416
1417 class si_MInst_sisisi_nac<string opc, Intrinsic IntID>
1418   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1419                                         IntRegs:$src3),
1420              !strconcat("$dst -= ", !strconcat(opc , "($src2, $src3)")),
1421              [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1422                                         IntRegs:$src3))],
1423              "$dst2 = $dst">;
1424
1425 class si_MInst_sisis8_acc<string opc, Intrinsic IntID>
1426   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1427                                         s8Imm:$src3),
1428              !strconcat("$dst += ", !strconcat(opc , "($src2, #$src3)")),
1429              [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1430                                         imm:$src3))],
1431              "$dst2 = $dst">;
1432
1433 class si_MInst_sisis8_nac<string opc, Intrinsic IntID>
1434   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1435                                         s8Imm:$src3),
1436              !strconcat("$dst -= ", !strconcat(opc , "($src2, #$src3)")),
1437              [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1438                                         imm:$src3))],
1439              "$dst2 = $dst">;
1440
1441 class si_MInst_sisiu4u5<string opc, Intrinsic IntID>
1442   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1443                                         u4Imm:$src2, u5Imm:$src3),
1444                !strconcat("$dst = ", !strconcat(opc ,
1445                                                 "($src1, #$src2, #$src3)")),
1446                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1447                                           imm:$src2, imm:$src3))],
1448                "$dst2 = $dst">;
1449
1450 class si_MInst_sisiu8_acc<string opc, Intrinsic IntID>
1451   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1452                                         u8Imm:$src3),
1453                !strconcat("$dst += ", !strconcat(opc , "($src2, #$src3)")),
1454                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1455                                           imm:$src3))],
1456                "$dst2 = $dst">;
1457
1458 class si_MInst_sisiu8_nac<string opc, Intrinsic IntID>
1459   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1460                                         u8Imm:$src3),
1461                !strconcat("$dst -= ", !strconcat(opc , "($src2, #$src3)")),
1462                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1463                                           imm:$src3))],
1464                "$dst2 = $dst">;
1465
1466 class si_MInst_sisisi_acc_hh<string opc, Intrinsic IntID>
1467   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1468                                         IntRegs:$src2),
1469                !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.H)")),
1470                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1471                                           IntRegs:$src2))],
1472                "$dst2 = $dst">;
1473
1474 class si_MInst_sisisi_acc_sat_lh<string opc, Intrinsic IntID>
1475   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1476                                         IntRegs:$src2),
1477                !strconcat("$dst += ", !strconcat(opc ,
1478                                                  "($src1.L, $src2.H):sat")),
1479                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1480                                           IntRegs:$src2))],
1481                "$dst2 = $dst">;
1482
1483 class si_MInst_sisisi_acc_sat_lh_s1<string opc, Intrinsic IntID>
1484   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1485                                         IntRegs:$src2),
1486                !strconcat("$dst += ", !strconcat(opc ,
1487                                                  "($src1.L, $src2.H):<<1:sat")),
1488                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1489                                           IntRegs:$src2))],
1490                "$dst2 = $dst">;
1491
1492 class si_MInst_sisisi_acc_sat_hh<string opc, Intrinsic IntID>
1493   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1494                                         IntRegs:$src2),
1495                !strconcat("$dst += ", !strconcat(opc ,
1496                                                  "($src1.H, $src2.H):sat")),
1497                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1498                                           IntRegs:$src2))],
1499                "$dst2 = $dst">;
1500
1501 class si_MInst_sisisi_acc_sat_hh_s1<string opc, Intrinsic IntID>
1502   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1503                                         IntRegs:$src2),
1504                !strconcat("$dst += ", !strconcat(opc ,
1505                                                  "($src1.H, $src2.H):<<1:sat")),
1506                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1507                                           IntRegs:$src2))],
1508                "$dst2 = $dst">;
1509
1510 class si_MInst_sisisi_acc_hh_s1<string opc, Intrinsic IntID>
1511   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1512                                         IntRegs:$src2),
1513                !strconcat("$dst += ", !strconcat(opc ,
1514                                                  "($src1.H, $src2.H):<<1")),
1515                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1516                                           IntRegs:$src2))],
1517                "$dst2 = $dst">;
1518
1519 class si_MInst_sisisi_nac_hh<string opc, Intrinsic IntID>
1520   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1521                                         IntRegs:$src2),
1522                !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.H)")),
1523                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1524                                           IntRegs:$src2))],
1525                "$dst2 = $dst">;
1526
1527 class si_MInst_sisisi_nac_sat_hh_s1<string opc, Intrinsic IntID>
1528   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1529                                         IntRegs:$src2),
1530                !strconcat("$dst -= ", !strconcat(opc ,
1531                                                  "($src1.H, $src2.H):<<1:sat")),
1532                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1533                                           IntRegs:$src2))],
1534                "$dst2 = $dst">;
1535
1536 class si_MInst_sisisi_nac_sat_hh<string opc, Intrinsic IntID>
1537   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1538                                         IntRegs:$src2),
1539                !strconcat("$dst -= ", !strconcat(opc ,
1540                                                  "($src1.H, $src2.H):sat")),
1541                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1542                                           IntRegs:$src2))],
1543                "$dst2 = $dst">;
1544
1545 class si_MInst_sisisi_nac_sat_hl_s1<string opc, Intrinsic IntID>
1546   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1547                                         IntRegs:$src2),
1548                !strconcat("$dst -= ", !strconcat(opc ,
1549                                                  "($src1.H, $src2.L):<<1:sat")),
1550                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1551                                           IntRegs:$src2))],
1552                "$dst2 = $dst">;
1553
1554 class si_MInst_sisisi_nac_sat_hl<string opc, Intrinsic IntID>
1555   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1556                                         IntRegs:$src2),
1557                !strconcat("$dst -= ", !strconcat(opc ,
1558                                                  "($src1.H, $src2.L):sat")),
1559                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1560                                           IntRegs:$src2))],
1561                "$dst2 = $dst">;
1562
1563 class si_MInst_sisisi_nac_sat_lh_s1<string opc, Intrinsic IntID>
1564   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1565                                         IntRegs:$src2),
1566                !strconcat("$dst -= ", !strconcat(opc ,
1567                                                  "($src1.L, $src2.H):<<1:sat")),
1568                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1569                                           IntRegs:$src2))],
1570                "$dst2 = $dst">;
1571
1572 class si_MInst_sisisi_nac_sat_lh<string opc, Intrinsic IntID>
1573   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1574                                         IntRegs:$src2),
1575                !strconcat("$dst -= ", !strconcat(opc ,
1576                                                  "($src1.L, $src2.H):sat")),
1577                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1578                                           IntRegs:$src2))],
1579                "$dst2 = $dst">;
1580
1581 class si_MInst_sisisi_nac_sat_ll_s1<string opc, Intrinsic IntID>
1582   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1583                                         IntRegs:$src2),
1584                !strconcat("$dst -= ", !strconcat(opc ,
1585                                                  "($src1.L, $src2.L):<<1:sat")),
1586                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1587                                           IntRegs:$src2))],
1588                "$dst2 = $dst">;
1589
1590 class si_MInst_sisisi_nac_sat_ll<string opc, Intrinsic IntID>
1591   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1592                                         IntRegs:$src2),
1593                !strconcat("$dst -= ", !strconcat(opc ,
1594                                                  "($src1.L, $src2.L):sat")),
1595                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1596                                           IntRegs:$src2))],
1597                "$dst2 = $dst">;
1598
1599 class si_MInst_sisisi_nac_hh_s1<string opc, Intrinsic IntID>
1600   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1601                                         IntRegs:$src2),
1602                !strconcat("$dst -= ", !strconcat(opc ,
1603                                                  "($src1.H, $src2.H):<<1")),
1604                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1605                                           IntRegs:$src2))],
1606                "$dst2 = $dst">;
1607
1608 class si_MInst_sisisi_acc_hl<string opc, Intrinsic IntID>
1609   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1610                                         IntRegs:$src2),
1611                !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.L)")),
1612                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1613                                           IntRegs:$src2))],
1614                "$dst2 = $dst">;
1615
1616 class si_MInst_sisisi_acc_hl_s1<string opc, Intrinsic IntID>
1617   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1618                                         IntRegs:$src2),
1619                !strconcat("$dst += ", !strconcat(opc ,
1620                                                  "($src1.H, $src2.L):<<1")),
1621                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1622                                           IntRegs:$src2))],
1623                "$dst2 = $dst">;
1624
1625 class si_MInst_sisisi_nac_hl<string opc, Intrinsic IntID>
1626   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1627                                         IntRegs:$src2),
1628                !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.L)")),
1629                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1630                                           IntRegs:$src2))],
1631                "$dst2 = $dst">;
1632
1633 class si_MInst_sisisi_nac_hl_s1<string opc, Intrinsic IntID>
1634   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1635                                         IntRegs:$src2),
1636                !strconcat("$dst -= ", !strconcat(opc ,
1637                                                  "($src1.H, $src2.L):<<1")),
1638                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1639                                           IntRegs:$src2))],
1640                "$dst2 = $dst">;
1641
1642 class si_MInst_sisisi_acc_lh<string opc, Intrinsic IntID>
1643   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1644                                         IntRegs:$src2),
1645                !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.H)")),
1646                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1647                                           IntRegs:$src2))],
1648                "$dst2 = $dst">;
1649
1650 class si_MInst_sisisi_acc_lh_s1<string opc, Intrinsic IntID>
1651   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1652                                         IntRegs:$src2),
1653                !strconcat("$dst += ", !strconcat(opc ,
1654                                                  "($src1.L, $src2.H):<<1")),
1655                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1656                                           IntRegs:$src2))],
1657                "$dst2 = $dst">;
1658
1659 class si_MInst_sisisi_nac_lh<string opc, Intrinsic IntID>
1660   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1661                                         IntRegs:$src2),
1662                !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.H)")),
1663                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1664                                           IntRegs:$src2))],
1665                "$dst2 = $dst">;
1666
1667 class si_MInst_sisisi_nac_lh_s1<string opc, Intrinsic IntID>
1668   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1669                                         IntRegs:$src2),
1670                !strconcat("$dst -= ", !strconcat(opc ,
1671                                                  "($src1.L, $src2.H):<<1")),
1672                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1673                                           IntRegs:$src2))],
1674                "$dst2 = $dst">;
1675
1676 class si_MInst_sisisi_acc_ll<string opc, Intrinsic IntID>
1677   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1678                                         IntRegs:$src2),
1679                !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.L)")),
1680                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1681                                           IntRegs:$src2))],
1682                "$dst2 = $dst">;
1683
1684 class si_MInst_sisisi_acc_ll_s1<string opc, Intrinsic IntID>
1685   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1686                                         IntRegs:$src2),
1687                !strconcat("$dst += ", !strconcat(opc ,
1688                                                  "($src1.L, $src2.L):<<1")),
1689                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1690                                           IntRegs:$src2))],
1691                "$dst2 = $dst">;
1692
1693 class si_MInst_sisisi_acc_sat_ll_s1<string opc, Intrinsic IntID>
1694   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1695                                         IntRegs:$src2),
1696                !strconcat("$dst += ", !strconcat(opc ,
1697                                                  "($src1.L, $src2.L):<<1:sat")),
1698                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1699                                           IntRegs:$src2))],
1700                "$dst2 = $dst">;
1701
1702 class si_MInst_sisisi_acc_sat_hl_s1<string opc, Intrinsic IntID>
1703   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1704                                         IntRegs:$src2),
1705                !strconcat("$dst += ", !strconcat(opc ,
1706                                                  "($src1.H, $src2.L):<<1:sat")),
1707                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1708                                           IntRegs:$src2))],
1709                "$dst2 = $dst">;
1710
1711 class si_MInst_sisisi_acc_sat_ll<string opc, Intrinsic IntID>
1712   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1713                                         IntRegs:$src2),
1714                !strconcat("$dst += ", !strconcat(opc ,
1715                                                  "($src1.L, $src2.L):sat")),
1716                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1717                                           IntRegs:$src2))],
1718                "$dst2 = $dst">;
1719
1720 class si_MInst_sisisi_acc_sat_hl<string opc, Intrinsic IntID>
1721   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1722                                         IntRegs:$src2),
1723                !strconcat("$dst += ", !strconcat(opc ,
1724                                                  "($src1.H, $src2.L):sat")),
1725                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1726                                           IntRegs:$src2))],
1727                "$dst2 = $dst">;
1728
1729 class si_MInst_sisisi_nac_ll<string opc, Intrinsic IntID>
1730   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1731                                         IntRegs:$src2),
1732                !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.L)")),
1733                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1734                                           IntRegs:$src2))],
1735                "$dst2 = $dst">;
1736
1737 class si_MInst_sisisi_nac_ll_s1<string opc, Intrinsic IntID>
1738   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1739                                         IntRegs:$src2),
1740                !strconcat("$dst -= ", !strconcat(opc ,
1741                                                  "($src1.L, $src2.L):<<1")),
1742                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1743                                           IntRegs:$src2))],
1744                "$dst2 = $dst">;
1745
1746 class si_MInst_sisisi_nac_hh_sat<string opc, Intrinsic IntID>
1747   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1748                                         IntRegs:$src2),
1749                !strconcat("$dst -= ", !strconcat(opc ,
1750                                                  "($src1.H, $src2.H):sat")),
1751                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1752                                           IntRegs:$src2))],
1753                "$dst2 = $dst">;
1754
1755 class si_MInst_sisisi_nac_hh_s1_sat<string opc, Intrinsic IntID>
1756   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1757                                         IntRegs:$src2),
1758                !strconcat("$dst -= ", !strconcat(opc ,
1759                                                  "($src1.H, $src2.H):<<1:sat")),
1760                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1761                                           IntRegs:$src2))],
1762                "$dst2 = $dst">;
1763
1764 class si_MInst_sisisi_nac_hl_sat<string opc, Intrinsic IntID>
1765   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1766                                         IntRegs:$src2),
1767                !strconcat("$dst -= ", !strconcat(opc ,
1768                                                  "($src1.H, $src2.L):sat")),
1769                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1770                                           IntRegs:$src2))],
1771                "$dst2 = $dst">;
1772
1773 class si_MInst_sisisi_nac_hl_s1_sat<string opc, Intrinsic IntID>
1774   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1775                                         IntRegs:$src2),
1776                !strconcat("$dst -= ", !strconcat(opc ,
1777                                                  "($src1.H, $src2.L):<<1:sat")),
1778                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1779                                           IntRegs:$src2))],
1780                "$dst2 = $dst">;
1781
1782 class si_MInst_sisisi_nac_lh_sat<string opc, Intrinsic IntID>
1783   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1784                                         IntRegs:$src2),
1785                !strconcat("$dst -= ", !strconcat(opc ,
1786                                                  "($src1.L, $src2.H):sat")),
1787                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1788                                           IntRegs:$src2))],
1789                "$dst2 = $dst">;
1790
1791 class si_MInst_sisisi_nac_lh_s1_sat<string opc, Intrinsic IntID>
1792   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1793                                         IntRegs:$src2),
1794                !strconcat("$dst -= ", !strconcat(opc ,
1795                                                  "($src1.L, $src2.H):<<1:sat")),
1796                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1797                                           IntRegs:$src2))],
1798                "$dst2 = $dst">;
1799
1800 class si_MInst_sisisi_nac_ll_sat<string opc, Intrinsic IntID>
1801   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1802                                         IntRegs:$src2),
1803                !strconcat("$dst -= ", !strconcat(opc ,
1804                                                  "($src1.L, $src2.L):sat")),
1805                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1806                                           IntRegs:$src2))],
1807                "$dst2 = $dst">;
1808
1809 class si_MInst_sisisi_nac_ll_s1_sat<string opc, Intrinsic IntID>
1810   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1811                                         IntRegs:$src2),
1812                !strconcat("$dst -= ", !strconcat(opc ,
1813                                                  "($src1.L, $src2.L):<<1:sat")),
1814                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1815                                           IntRegs:$src2))],
1816                "$dst2 = $dst">;
1817
1818 class di_ALU32_sisi<string opc, Intrinsic IntID>
1819   : ALU32_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1820              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1821              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1822
1823 class di_MInst_sisi<string opc, Intrinsic IntID>
1824   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1825              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1826              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1827
1828 class di_MInst_sisi_sat<string opc, Intrinsic IntID>
1829   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1830              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1831              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1832
1833 class di_MInst_sisi_sat_conj<string opc, Intrinsic IntID>
1834   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1835              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2*):sat")),
1836              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1837
1838 class di_MInst_sisi_s1_sat<string opc, Intrinsic IntID>
1839   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1840              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
1841              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1842
1843 class di_MInst_didi_s1_sat<string opc, Intrinsic IntID>
1844   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1845              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
1846              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1847                                            DoubleRegs:$src2))]>;
1848
1849 class si_MInst_didi_s1_rnd_sat<string opc, Intrinsic IntID>
1850   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1851              !strconcat("$dst = ", !strconcat(opc ,
1852                                               "($src1, $src2):<<1:rnd:sat")),
1853              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1854
1855 class si_MInst_didi_rnd_sat<string opc, Intrinsic IntID>
1856   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1857              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd:sat")),
1858              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1859
1860 class si_MInst_sisi_sat_hh<string opc, Intrinsic IntID>
1861   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1862              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):sat")),
1863              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1864
1865 class si_MInst_sisi_sat_hh_s1<string opc, Intrinsic IntID>
1866   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1867                !strconcat("$dst = ", !strconcat(opc ,
1868                                                 "($src1.H, $src2.H):<<1:sat")),
1869                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1870
1871 class si_MInst_sisi_sat_hl<string opc, Intrinsic IntID>
1872   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1873              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):sat")),
1874              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1875
1876 class si_MInst_sisi_sat_hl_s1<string opc, Intrinsic IntID>
1877   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1878                !strconcat("$dst = ", !strconcat(opc ,
1879                                                 "($src1.H, $src2.L):<<1:sat")),
1880                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1881
1882 class si_MInst_sisi_sat_lh<string opc, Intrinsic IntID>
1883   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1884              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):sat")),
1885              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1886
1887 class si_MInst_sisi_sat_lh_s1<string opc, Intrinsic IntID>
1888   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1889                !strconcat("$dst = ", !strconcat(opc ,
1890                                                 "($src1.L, $src2.H):<<1:sat")),
1891                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1892
1893 class si_MInst_sisi_sat_ll<string opc, Intrinsic IntID>
1894   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1895              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):sat")),
1896              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1897
1898 class si_MInst_sisi_sat_ll_s1<string opc, Intrinsic IntID>
1899   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1900                !strconcat("$dst = ", !strconcat(opc ,
1901                                                 "($src1.L, $src2.L):<<1:sat")),
1902                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1903
1904 class si_MInst_sisi_sat_rnd_hh<string opc, Intrinsic IntID>
1905   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1906                !strconcat("$dst = ", !strconcat(opc ,
1907                                                 "($src1.H, $src2.H):rnd:sat")),
1908                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1909
1910 class si_MInst_sisi_rnd_hh<string opc, Intrinsic IntID>
1911   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1912                !strconcat("$dst = ", !strconcat(opc ,
1913                                                 "($src1.H, $src2.H):rnd")),
1914                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1915
1916 class si_MInst_sisi_rnd_hh_s1<string opc, Intrinsic IntID>
1917   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1918                !strconcat("$dst = ", !strconcat(opc ,
1919                                                 "($src1.H, $src2.H):<<1:rnd")),
1920                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1921
1922 class si_MInst_sisi_sat_rnd_hh_s1<string opc, Intrinsic IntID>
1923   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1924                !strconcat("$dst = ",
1925                           !strconcat(opc ,
1926                                      "($src1.H, $src2.H):<<1:rnd:sat")),
1927                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1928
1929 class si_MInst_sisi_rnd_hl<string opc, Intrinsic IntID>
1930   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1931                !strconcat("$dst = ",
1932                           !strconcat(opc , "($src1.H, $src2.L):rnd")),
1933                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1934
1935 class si_MInst_sisi_rnd_hl_s1<string opc, Intrinsic IntID>
1936   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1937                !strconcat("$dst = ",
1938                           !strconcat(opc , "($src1.H, $src2.L):<<1:rnd")),
1939                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1940
1941 class si_MInst_sisi_sat_rnd_hl<string opc, Intrinsic IntID>
1942   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1943                !strconcat("$dst = ",
1944                           !strconcat(opc , "($src1.H, $src2.L):rnd:sat")),
1945                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1946
1947 class si_MInst_sisi_sat_rnd_hl_s1<string opc, Intrinsic IntID>
1948   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1949                !strconcat("$dst = ",
1950                           !strconcat(opc , "($src1.H, $src2.L):<<1:rnd:sat")),
1951                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1952
1953 class si_MInst_sisi_rnd_lh<string opc, Intrinsic IntID>
1954   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1955                !strconcat("$dst = ",
1956                           !strconcat(opc , "($src1.L, $src2.H):rnd")),
1957                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1958
1959 class si_MInst_sisi_sat_rnd_lh<string opc, Intrinsic IntID>
1960   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1961                !strconcat("$dst = ",
1962                           !strconcat(opc , "($src1.L, $src2.H):rnd:sat")),
1963                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1964
1965 class si_MInst_sisi_sat_rnd_lh_s1<string opc, Intrinsic IntID>
1966   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1967                !strconcat("$dst = ",
1968                           !strconcat(opc , "($src1.L, $src2.H):<<1:rnd:sat")),
1969                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1970
1971 class si_MInst_sisi_rnd_lh_s1<string opc, Intrinsic IntID>
1972   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1973                !strconcat("$dst = ",
1974                           !strconcat(opc , "($src1.L, $src2.H):<<1:rnd")),
1975                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1976
1977 class si_MInst_sisi_sat_rnd_ll<string opc, Intrinsic IntID>
1978   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1979                !strconcat("$dst = ",
1980                           !strconcat(opc , "($src1.L, $src2.L):rnd:sat")),
1981                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1982
1983 class si_MInst_sisi_sat_rnd_ll_s1<string opc, Intrinsic IntID>
1984   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1985                !strconcat("$dst = ",
1986                           !strconcat(opc , "($src1.L, $src2.L):<<1:rnd:sat")),
1987                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1988
1989 class si_MInst_sisi_rnd_ll<string opc, Intrinsic IntID>
1990   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1991                !strconcat("$dst = ",
1992                           !strconcat(opc , "($src1.L, $src2.L):rnd")),
1993                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1994
1995 class si_MInst_sisi_rnd_ll_s1<string opc, Intrinsic IntID>
1996   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1997                !strconcat("$dst = ",
1998                           !strconcat(opc , "($src1.L, $src2.L):<<1:rnd")),
1999                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2000
2001 class di_MInst_dididi_acc_sat<string opc, Intrinsic IntID>
2002   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
2003                                            DoubleRegs:$src1, DoubleRegs:$src2),
2004                !strconcat("$dst += ", !strconcat(opc , "($src1, $src2):sat")),
2005                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
2006                                              DoubleRegs:$src1,
2007                                              DoubleRegs:$src2))],
2008                "$dst2 = $dst">;
2009
2010 class di_MInst_dididi_acc_rnd_sat<string opc, Intrinsic IntID>
2011   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
2012                                            DoubleRegs:$src2),
2013                !strconcat("$dst += ",
2014                           !strconcat(opc , "($src1, $src2):rnd:sat")),
2015                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
2016                                              DoubleRegs:$src1,
2017                                              DoubleRegs:$src2))],
2018                "$dst2 = $dst">;
2019
2020 class di_MInst_dididi_acc_s1<string opc, Intrinsic IntID>
2021   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
2022                                            DoubleRegs:$src1,
2023                                            DoubleRegs:$src2),
2024                !strconcat("$dst += ",
2025                           !strconcat(opc , "($src1, $src2):<<1")),
2026                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
2027                                              DoubleRegs:$src1,
2028                                              DoubleRegs:$src2))],
2029                "$dst2 = $dst">;
2030
2031
2032 class di_MInst_dididi_acc_s1_sat<string opc, Intrinsic IntID>
2033   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
2034                                            DoubleRegs:$src1,
2035                                            DoubleRegs:$src2),
2036                !strconcat("$dst += ",
2037                           !strconcat(opc , "($src1, $src2):<<1:sat")),
2038                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
2039                                              DoubleRegs:$src1,
2040                                              DoubleRegs:$src2))],
2041                "$dst2 = $dst">;
2042
2043 class di_MInst_dididi_acc_s1_rnd_sat<string opc, Intrinsic IntID>
2044   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
2045                                            DoubleRegs:$src2),
2046                !strconcat("$dst += ",
2047                           !strconcat(opc , "($src1, $src2):<<1:rnd:sat")),
2048                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
2049                                              DoubleRegs:$src1,
2050                                              DoubleRegs:$src2))],
2051                "$dst2 = $dst">;
2052
2053 class di_MInst_dididi_acc<string opc, Intrinsic IntID>
2054   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
2055                                            DoubleRegs:$src2),
2056                !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
2057                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
2058                                              DoubleRegs:$src1,
2059                                              DoubleRegs:$src2))],
2060                "$dst2 = $dst">;
2061
2062 class di_MInst_dididi_acc_conj<string opc, Intrinsic IntID>
2063   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
2064                                            DoubleRegs:$src2),
2065                !strconcat("$dst += ", !strconcat(opc , "($src1, $src2*)")),
2066                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
2067                                              DoubleRegs:$src1,
2068                                              DoubleRegs:$src2))],
2069                "$dst2 = $dst">;
2070
2071 class di_MInst_disisi_acc_hh<string opc, Intrinsic IntID>
2072   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2073                                            IntRegs:$src2),
2074                !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.H)")),
2075                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2076                                              IntRegs:$src2))],
2077                "$dst2 = $dst">;
2078
2079 class di_MInst_disisi_acc_hl<string opc, Intrinsic IntID>
2080   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2081                                            IntRegs:$src2),
2082                !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.L)")),
2083                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2084                                              IntRegs:$src2))],
2085                "$dst2 = $dst">;
2086
2087 class di_MInst_disisi_acc_lh<string opc, Intrinsic IntID>
2088   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2089                                            IntRegs:$src2),
2090                !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.H)")),
2091                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2092                                              IntRegs:$src2))],
2093                "$dst2 = $dst">;
2094
2095 class di_MInst_disisi_acc_ll<string opc, Intrinsic IntID>
2096   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2097                                            IntRegs:$src2),
2098                !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.L)")),
2099                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2100                                              IntRegs:$src2))],
2101                "$dst2 = $dst">;
2102
2103 class di_MInst_disisi_acc_hh_s1<string opc, Intrinsic IntID>
2104   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2105                                            IntRegs:$src2),
2106                !strconcat("$dst += ",
2107                           !strconcat(opc , "($src1.H, $src2.H):<<1")),
2108                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2109                                              IntRegs:$src2))],
2110                "$dst2 = $dst">;
2111
2112 class di_MInst_disisi_acc_hl_s1<string opc, Intrinsic IntID>
2113   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2114                                            IntRegs:$src2),
2115                !strconcat("$dst += ",
2116                           !strconcat(opc , "($src1.H, $src2.L):<<1")),
2117                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2118                                              IntRegs:$src2))],
2119                "$dst2 = $dst">;
2120
2121 class di_MInst_disisi_acc_lh_s1<string opc, Intrinsic IntID>
2122   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2123                                            IntRegs:$src2),
2124                !strconcat("$dst += ",
2125                           !strconcat(opc , "($src1.L, $src2.H):<<1")),
2126                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2127                                              IntRegs:$src2))],
2128                "$dst2 = $dst">;
2129
2130 class di_MInst_disisi_acc_ll_s1<string opc, Intrinsic IntID>
2131   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2132                                            IntRegs:$src2),
2133                !strconcat("$dst += ",
2134                           !strconcat(opc , "($src1.L, $src2.L):<<1")),
2135                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2136                                              IntRegs:$src2))],
2137                "$dst2 = $dst">;
2138
2139 class di_MInst_disisi_nac_hh<string opc, Intrinsic IntID>
2140   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2141                                            IntRegs:$src2),
2142                !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.H)")),
2143                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2144                                              IntRegs:$src2))],
2145                "$dst2 = $dst">;
2146
2147 class di_MInst_disisi_nac_hl<string opc, Intrinsic IntID>
2148   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2149                                            IntRegs:$src2),
2150                !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.L)")),
2151                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2152                                              IntRegs:$src2))],
2153                "$dst2 = $dst">;
2154
2155 class di_MInst_disisi_nac_lh<string opc, Intrinsic IntID>
2156   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2157                                            IntRegs:$src2),
2158                !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.H)")),
2159                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2160                                              IntRegs:$src2))],
2161                "$dst2 = $dst">;
2162
2163 class di_MInst_disisi_nac_ll<string opc, Intrinsic IntID>
2164   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2165                                            IntRegs:$src2),
2166                !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.L)")),
2167                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2168                                              IntRegs:$src2))],
2169                "$dst2 = $dst">;
2170
2171 class di_MInst_disisi_nac_hh_s1<string opc, Intrinsic IntID>
2172   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2173                                            IntRegs:$src2),
2174                !strconcat("$dst -= ",
2175                           !strconcat(opc , "($src1.H, $src2.H):<<1")),
2176                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2177                                              IntRegs:$src2))],
2178                "$dst2 = $dst">;
2179
2180 class di_MInst_disisi_nac_hl_s1<string opc, Intrinsic IntID>
2181   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2182                                            IntRegs:$src2),
2183                !strconcat("$dst -= ",
2184                           !strconcat(opc , "($src1.H, $src2.L):<<1")),
2185                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2186                                              IntRegs:$src2))],
2187                "$dst2 = $dst">;
2188
2189 class di_MInst_disisi_nac_lh_s1<string opc, Intrinsic IntID>
2190   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2191                                            IntRegs:$src2),
2192                !strconcat("$dst -= ",
2193                           !strconcat(opc , "($src1.L, $src2.H):<<1")),
2194                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2195                                              IntRegs:$src2))],
2196                "$dst2 = $dst">;
2197
2198 class di_MInst_disisi_nac_ll_s1<string opc, Intrinsic IntID>
2199   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2200                                            IntRegs:$src2),
2201                !strconcat("$dst -= ",
2202                           !strconcat(opc , "($src1.L, $src2.L):<<1")),
2203                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2204                                              IntRegs:$src2))],
2205                "$dst2 = $dst">;
2206
2207 class di_MInst_disisi_acc_s1_sat<string opc, Intrinsic IntID>
2208   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2209                                            IntRegs:$src2),
2210                !strconcat("$dst += ",
2211                           !strconcat(opc , "($src1, $src2):<<1:sat")),
2212                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2213                                              IntRegs:$src2))],
2214                "$dst2 = $dst">;
2215
2216 class di_MInst_disi_s1_sat<string opc, Intrinsic IntID>
2217   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
2218              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
2219              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
2220
2221 class di_MInst_didisi_acc_s1_sat<string opc, Intrinsic IntID>
2222   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
2223                                            IntRegs:$src2),
2224                !strconcat("$dst += ",
2225                           !strconcat(opc , "($src1, $src2):<<1:sat")),
2226                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
2227                                              DoubleRegs:$src1,
2228                                              IntRegs:$src2))],
2229                "$dst2 = $dst">;
2230
2231 class si_MInst_disi_s1_rnd_sat<string opc, Intrinsic IntID>
2232   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
2233              !strconcat("$dst = ",
2234                         !strconcat(opc , "($src1, $src2):<<1:rnd:sat")),
2235              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
2236
2237 class si_MInst_didi<string opc, Intrinsic IntID>
2238   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
2239              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
2240              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
2241
2242 //
2243 // LDInst classes.
2244 //
2245 let mayLoad = 1, hasSideEffects = 0 in
2246 class di_LDInstPI_diu4<string opc, Intrinsic IntID>
2247   : LDInstPI<(outs IntRegs:$dst, DoubleRegs:$dst2),
2248            (ins IntRegs:$src1, IntRegs:$src2, CtrRegs:$src3, s4Imm:$offset),
2249            "$dst2 = memd($src1++#$offset:circ($src3))",
2250            [],
2251            "$src1 = $dst">;
2252
2253 /********************************************************************
2254 *            ALU32/PERM                                             *
2255 *********************************************************************/
2256
2257 // ALU32 / PERM / Combine.
2258 def HEXAGON_A2_combinew:
2259   di_ALU32_sisi                   <"combine",  int_hexagon_A2_combinew>;
2260 def HEXAGON_A2_combine_hh:
2261   si_MInst_sisi_hh                <"combine",  int_hexagon_A2_combine_hh>;
2262 def HEXAGON_A2_combine_lh:
2263   si_MInst_sisi_lh                <"combine",  int_hexagon_A2_combine_lh>;
2264 def HEXAGON_A2_combine_hl:
2265   si_MInst_sisi_hl                <"combine",  int_hexagon_A2_combine_hl>;
2266 def HEXAGON_A2_combine_ll:
2267   si_MInst_sisi_ll                <"combine",  int_hexagon_A2_combine_ll>;
2268 def HEXAGON_A2_combineii:
2269   di_MInst_s8s8                   <"combine",  int_hexagon_A2_combineii>;
2270
2271 // ALU32 / PERM / Mux.
2272 def HEXAGON_C2_mux:
2273   si_ALU32_qisisi                 <"mux",      int_hexagon_C2_mux>;
2274
2275 // ALU32 / PERM / Shift halfword.
2276 def HEXAGON_A2_aslh:
2277   si_ALU32_si                     <"aslh",     int_hexagon_A2_aslh>;
2278 def HEXAGON_A2_asrh:
2279   si_ALU32_si                     <"asrh",     int_hexagon_A2_asrh>;
2280 def SI_to_SXTHI_asrh:
2281   si_ALU32_si                     <"asrh",     int_hexagon_SI_to_SXTHI_asrh>;
2282
2283 // ALU32 / PERM / Sign/zero extend.
2284 def HEXAGON_A2_sxth:
2285   si_ALU32_si                     <"sxth",     int_hexagon_A2_sxth>;
2286 def HEXAGON_A2_sxtb:
2287   si_ALU32_si                     <"sxtb",     int_hexagon_A2_sxtb>;
2288 def HEXAGON_A2_zxth:
2289   si_ALU32_si                     <"zxth",     int_hexagon_A2_zxth>;
2290 def HEXAGON_A2_zxtb:
2291   si_ALU32_si                     <"zxtb",     int_hexagon_A2_zxtb>;
2292
2293 /********************************************************************
2294 *            ALU32/PRED                                             *
2295 *********************************************************************/
2296
2297 // ALU32 / PRED / Compare.
2298 def HEXAGON_C2_cmpeq:
2299   qi_ALU32_sisi                   <"cmp.eq",   int_hexagon_C2_cmpeq>;
2300 def HEXAGON_C2_cmpeqi:
2301   qi_ALU32_sis10                  <"cmp.eq",   int_hexagon_C2_cmpeqi>;
2302 def HEXAGON_C2_cmpgei:
2303   qi_ALU32_sis8                   <"cmp.ge",   int_hexagon_C2_cmpgei>;
2304 def HEXAGON_C2_cmpgeui:
2305   qi_ALU32_siu8                   <"cmp.geu",  int_hexagon_C2_cmpgeui>;
2306 def HEXAGON_C2_cmpgt:
2307   qi_ALU32_sisi                   <"cmp.gt",   int_hexagon_C2_cmpgt>;
2308 def HEXAGON_C2_cmpgti:
2309   qi_ALU32_sis10                  <"cmp.gt",   int_hexagon_C2_cmpgti>;
2310 def HEXAGON_C2_cmpgtu:
2311   qi_ALU32_sisi                   <"cmp.gtu",  int_hexagon_C2_cmpgtu>;
2312 def HEXAGON_C2_cmpgtui:
2313   qi_ALU32_siu9                   <"cmp.gtu",  int_hexagon_C2_cmpgtui>;
2314 def HEXAGON_C2_cmplt:
2315   qi_ALU32_sisi                   <"cmp.lt",   int_hexagon_C2_cmplt>;
2316 def HEXAGON_C2_cmpltu:
2317   qi_ALU32_sisi                   <"cmp.ltu",  int_hexagon_C2_cmpltu>;
2318
2319 /********************************************************************
2320 *            ALU32/VH                                               *
2321 *********************************************************************/
2322
2323 // ALU32 / VH / Vector add halfwords.
2324 // Rd32=vadd[u]h(Rs32,Rt32:sat]
2325 def HEXAGON_A2_svaddh:
2326   si_ALU32_sisi                   <"vaddh",    int_hexagon_A2_svaddh>;
2327 def HEXAGON_A2_svaddhs:
2328   si_ALU32_sisi_sat               <"vaddh",    int_hexagon_A2_svaddhs>;
2329 def HEXAGON_A2_svadduhs:
2330   si_ALU32_sisi_sat               <"vadduh",   int_hexagon_A2_svadduhs>;
2331
2332 // ALU32 / VH / Vector average halfwords.
2333 def HEXAGON_A2_svavgh:
2334   si_ALU32_sisi                   <"vavgh",    int_hexagon_A2_svavgh>;
2335 def HEXAGON_A2_svavghs:
2336   si_ALU32_sisi_rnd               <"vavgh",    int_hexagon_A2_svavghs>;
2337 def HEXAGON_A2_svnavgh:
2338   si_ALU32_sisi                   <"vnavgh",   int_hexagon_A2_svnavgh>;
2339
2340 // ALU32 / VH / Vector subtract halfwords.
2341 def HEXAGON_A2_svsubh:
2342   si_ALU32_sisi                   <"vsubh",    int_hexagon_A2_svsubh>;
2343 def HEXAGON_A2_svsubhs:
2344   si_ALU32_sisi_sat               <"vsubh",    int_hexagon_A2_svsubhs>;
2345 def HEXAGON_A2_svsubuhs:
2346   si_ALU32_sisi_sat               <"vsubuh",   int_hexagon_A2_svsubuhs>;
2347
2348 /********************************************************************
2349 *            ALU64/ALU                                              *
2350 *********************************************************************/
2351
2352 // ALU64 / ALU / Add.
2353 def HEXAGON_A2_addp:
2354   di_ALU64_didi                   <"add",      int_hexagon_A2_addp>;
2355 def HEXAGON_A2_addsat:
2356   si_ALU64_sisi_sat               <"add",      int_hexagon_A2_addsat>;
2357
2358 // ALU64 / ALU / Compare.
2359 def HEXAGON_C2_cmpeqp:
2360   qi_ALU64_didi                   <"cmp.eq",   int_hexagon_C2_cmpeqp>;
2361 def HEXAGON_C2_cmpgtp:
2362   qi_ALU64_didi                   <"cmp.gt",   int_hexagon_C2_cmpgtp>;
2363 def HEXAGON_C2_cmpgtup:
2364   qi_ALU64_didi                   <"cmp.gtu",  int_hexagon_C2_cmpgtup>;
2365
2366 // ALU64 / ALU / Logical operations.
2367 def HEXAGON_A2_andp:
2368   di_ALU64_didi                   <"and",      int_hexagon_A2_andp>;
2369 def HEXAGON_A2_orp:
2370   di_ALU64_didi                   <"or",       int_hexagon_A2_orp>;
2371 def HEXAGON_A2_xorp:
2372   di_ALU64_didi                   <"xor",      int_hexagon_A2_xorp>;
2373
2374 // ALU64 / ALU / Subtract.
2375 def HEXAGON_A2_subp:
2376   di_ALU64_didi                   <"sub",      int_hexagon_A2_subp>;
2377 def HEXAGON_A2_subsat:
2378   si_ALU64_sisi_sat               <"sub",      int_hexagon_A2_subsat>;
2379
2380 // ALU64 / ALU / Transfer register.
2381 def HEXAGON_A2_tfrp:
2382   di_ALU64_di                     <"",         int_hexagon_A2_tfrp>;
2383
2384 /********************************************************************
2385 *            ALU64/BIT                                              *
2386 *********************************************************************/
2387
2388 // ALU64 / BIT / Masked parity.
2389 def HEXAGON_S2_parityp:
2390   si_ALU64_didi                   <"parity",   int_hexagon_S2_parityp>;
2391
2392 /********************************************************************
2393 *            ALU64/PERM                                             *
2394 *********************************************************************/
2395
2396 // ALU64 / PERM / Vector pack high and low halfwords.
2397 def HEXAGON_S2_packhl:
2398   di_ALU64_sisi                   <"packhl",   int_hexagon_S2_packhl>;
2399
2400 /********************************************************************
2401 *            ALU64/VB                                               *
2402 *********************************************************************/
2403
2404 // ALU64 / VB / Vector add unsigned bytes.
2405 def HEXAGON_A2_vaddub:
2406   di_ALU64_didi                   <"vaddub",   int_hexagon_A2_vaddub>;
2407 def HEXAGON_A2_vaddubs:
2408   di_ALU64_didi_sat               <"vaddub",   int_hexagon_A2_vaddubs>;
2409
2410 // ALU64 / VB / Vector average unsigned bytes.
2411 def HEXAGON_A2_vavgub:
2412   di_ALU64_didi                   <"vavgub",   int_hexagon_A2_vavgub>;
2413 def HEXAGON_A2_vavgubr:
2414   di_ALU64_didi_rnd               <"vavgub",   int_hexagon_A2_vavgubr>;
2415
2416 // ALU64 / VB / Vector compare unsigned bytes.
2417 def HEXAGON_A2_vcmpbeq:
2418   qi_ALU64_didi                   <"vcmpb.eq", int_hexagon_A2_vcmpbeq>;
2419 def HEXAGON_A2_vcmpbgtu:
2420   qi_ALU64_didi                   <"vcmpb.gtu",int_hexagon_A2_vcmpbgtu>;
2421
2422 // ALU64 / VB / Vector maximum/minimum unsigned bytes.
2423 def HEXAGON_A2_vmaxub:
2424   di_ALU64_didi                   <"vmaxub",   int_hexagon_A2_vmaxub>;
2425 def HEXAGON_A2_vminub:
2426   di_ALU64_didi                   <"vminub",   int_hexagon_A2_vminub>;
2427
2428 // ALU64 / VB / Vector subtract unsigned bytes.
2429 def HEXAGON_A2_vsubub:
2430   di_ALU64_didi                   <"vsubub",   int_hexagon_A2_vsubub>;
2431 def HEXAGON_A2_vsububs:
2432   di_ALU64_didi_sat               <"vsubub",   int_hexagon_A2_vsububs>;
2433
2434 // ALU64 / VB / Vector mux.
2435 def HEXAGON_C2_vmux:
2436   di_ALU64_qididi                 <"vmux",     int_hexagon_C2_vmux>;
2437
2438
2439 /********************************************************************
2440 *            ALU64/VH                                               *
2441 *********************************************************************/
2442
2443 // ALU64 / VH / Vector add halfwords.
2444 // Rdd64=vadd[u]h(Rss64,Rtt64:sat]
2445 def HEXAGON_A2_vaddh:
2446   di_ALU64_didi                   <"vaddh",    int_hexagon_A2_vaddh>;
2447 def HEXAGON_A2_vaddhs:
2448   di_ALU64_didi_sat               <"vaddh",    int_hexagon_A2_vaddhs>;
2449 def HEXAGON_A2_vadduhs:
2450   di_ALU64_didi_sat               <"vadduh",   int_hexagon_A2_vadduhs>;
2451
2452 // ALU64 / VH / Vector average halfwords.
2453 // Rdd64=v[n]avg[u]h(Rss64,Rtt64:rnd/:crnd][:sat]
2454 def HEXAGON_A2_vavgh:
2455   di_ALU64_didi                   <"vavgh",    int_hexagon_A2_vavgh>;
2456 def HEXAGON_A2_vavghcr:
2457   di_ALU64_didi_crnd              <"vavgh",    int_hexagon_A2_vavghcr>;
2458 def HEXAGON_A2_vavghr:
2459   di_ALU64_didi_rnd               <"vavgh",    int_hexagon_A2_vavghr>;
2460 def HEXAGON_A2_vavguh:
2461   di_ALU64_didi                   <"vavguh",   int_hexagon_A2_vavguh>;
2462 def HEXAGON_A2_vavguhr:
2463   di_ALU64_didi_rnd               <"vavguh",   int_hexagon_A2_vavguhr>;
2464 def HEXAGON_A2_vnavgh:
2465   di_ALU64_didi                   <"vnavgh",   int_hexagon_A2_vnavgh>;
2466 def HEXAGON_A2_vnavghcr:
2467   di_ALU64_didi_crnd_sat          <"vnavgh",   int_hexagon_A2_vnavghcr>;
2468 def HEXAGON_A2_vnavghr:
2469   di_ALU64_didi_rnd_sat           <"vnavgh",   int_hexagon_A2_vnavghr>;
2470
2471 // ALU64 / VH / Vector compare halfwords.
2472 def HEXAGON_A2_vcmpheq:
2473   qi_ALU64_didi                   <"vcmph.eq", int_hexagon_A2_vcmpheq>;
2474 def HEXAGON_A2_vcmphgt:
2475   qi_ALU64_didi                   <"vcmph.gt", int_hexagon_A2_vcmphgt>;
2476 def HEXAGON_A2_vcmphgtu:
2477   qi_ALU64_didi                   <"vcmph.gtu",int_hexagon_A2_vcmphgtu>;
2478
2479 // ALU64 / VH / Vector maximum halfwords.
2480 def HEXAGON_A2_vmaxh:
2481   di_ALU64_didi                   <"vmaxh",    int_hexagon_A2_vmaxh>;
2482 def HEXAGON_A2_vmaxuh:
2483   di_ALU64_didi                   <"vmaxuh",   int_hexagon_A2_vmaxuh>;
2484
2485 // ALU64 / VH / Vector minimum halfwords.
2486 def HEXAGON_A2_vminh:
2487   di_ALU64_didi                   <"vminh",    int_hexagon_A2_vminh>;
2488 def HEXAGON_A2_vminuh:
2489   di_ALU64_didi                   <"vminuh",   int_hexagon_A2_vminuh>;
2490
2491 // ALU64 / VH / Vector subtract halfwords.
2492 def HEXAGON_A2_vsubh:
2493   di_ALU64_didi                   <"vsubh",    int_hexagon_A2_vsubh>;
2494 def HEXAGON_A2_vsubhs:
2495   di_ALU64_didi_sat               <"vsubh",    int_hexagon_A2_vsubhs>;
2496 def HEXAGON_A2_vsubuhs:
2497   di_ALU64_didi_sat               <"vsubuh",   int_hexagon_A2_vsubuhs>;
2498
2499
2500 /********************************************************************
2501 *            ALU64/VW                                               *
2502 *********************************************************************/
2503
2504 // ALU64 / VW / Vector add words.
2505 // Rdd32=vaddw(Rss32,Rtt32)[:sat]
2506 def HEXAGON_A2_vaddw:
2507   di_ALU64_didi                   <"vaddw",    int_hexagon_A2_vaddw>;
2508 def HEXAGON_A2_vaddws:
2509   di_ALU64_didi_sat               <"vaddw",   int_hexagon_A2_vaddws>;
2510
2511 // ALU64 / VW / Vector average words.
2512 def HEXAGON_A2_vavguw:
2513   di_ALU64_didi                   <"vavguw",   int_hexagon_A2_vavguw>;
2514 def HEXAGON_A2_vavguwr:
2515   di_ALU64_didi_rnd               <"vavguw",   int_hexagon_A2_vavguwr>;
2516 def HEXAGON_A2_vavgw:
2517   di_ALU64_didi                   <"vavgw",    int_hexagon_A2_vavgw>;
2518 def HEXAGON_A2_vavgwcr:
2519   di_ALU64_didi_crnd              <"vavgw",    int_hexagon_A2_vavgwcr>;
2520 def HEXAGON_A2_vavgwr:
2521   di_ALU64_didi_rnd               <"vavgw",    int_hexagon_A2_vavgwr>;
2522 def HEXAGON_A2_vnavgw:
2523   di_ALU64_didi                   <"vnavgw",   int_hexagon_A2_vnavgw>;
2524 def HEXAGON_A2_vnavgwcr:
2525   di_ALU64_didi_crnd_sat          <"vnavgw",   int_hexagon_A2_vnavgwcr>;
2526 def HEXAGON_A2_vnavgwr:
2527   di_ALU64_didi_rnd_sat           <"vnavgw",   int_hexagon_A2_vnavgwr>;
2528
2529 // ALU64 / VW / Vector compare words.
2530 def HEXAGON_A2_vcmpweq:
2531   qi_ALU64_didi                   <"vcmpw.eq", int_hexagon_A2_vcmpweq>;
2532 def HEXAGON_A2_vcmpwgt:
2533   qi_ALU64_didi                   <"vcmpw.gt", int_hexagon_A2_vcmpwgt>;
2534 def HEXAGON_A2_vcmpwgtu:
2535   qi_ALU64_didi                   <"vcmpw.gtu",int_hexagon_A2_vcmpwgtu>;
2536
2537 // ALU64 / VW / Vector maximum words.
2538 def HEXAGON_A2_vmaxw:
2539   di_ALU64_didi                   <"vmaxw",    int_hexagon_A2_vmaxw>;
2540 def HEXAGON_A2_vmaxuw:
2541   di_ALU64_didi                   <"vmaxuw",   int_hexagon_A2_vmaxuw>;
2542
2543 // ALU64 / VW / Vector minimum words.
2544 def HEXAGON_A2_vminw:
2545   di_ALU64_didi                   <"vminw",    int_hexagon_A2_vminw>;
2546 def HEXAGON_A2_vminuw:
2547   di_ALU64_didi                   <"vminuw",   int_hexagon_A2_vminuw>;
2548
2549 // ALU64 / VW / Vector subtract words.
2550 def HEXAGON_A2_vsubw:
2551   di_ALU64_didi                   <"vsubw",    int_hexagon_A2_vsubw>;
2552 def HEXAGON_A2_vsubws:
2553   di_ALU64_didi_sat               <"vsubw",    int_hexagon_A2_vsubws>;
2554
2555
2556 /********************************************************************
2557 *            CR                                                     *
2558 *********************************************************************/
2559
2560 // CR / Logical reductions on predicates.
2561 def HEXAGON_C2_all8:
2562   qi_SInst_qi                     <"all8",     int_hexagon_C2_all8>;
2563 def HEXAGON_C2_any8:
2564   qi_SInst_qi                     <"any8",     int_hexagon_C2_any8>;
2565
2566 // CR / Logical operations on predicates.
2567 def HEXAGON_C2_pxfer_map:
2568   qi_SInst_qi_pxfer               <"",         int_hexagon_C2_pxfer_map>;
2569 def HEXAGON_C2_and:
2570   qi_SInst_qiqi                   <"and",      int_hexagon_C2_and>;
2571 def HEXAGON_C2_andn:
2572   qi_SInst_qiqi_neg               <"and",      int_hexagon_C2_andn>;
2573 def HEXAGON_C2_not:
2574   qi_SInst_qi                     <"not",      int_hexagon_C2_not>;
2575 def HEXAGON_C2_or:
2576   qi_SInst_qiqi                   <"or",       int_hexagon_C2_or>;
2577 def HEXAGON_C2_orn:
2578   qi_SInst_qiqi_neg               <"or",       int_hexagon_C2_orn>;
2579 def HEXAGON_C2_xor:
2580   qi_SInst_qiqi                   <"xor",      int_hexagon_C2_xor>;
2581
2582
2583 /********************************************************************
2584 *            MTYPE/ALU                                              *
2585 *********************************************************************/
2586
2587 // MTYPE / ALU / Add and accumulate.
2588 def HEXAGON_M2_acci:
2589   si_MInst_sisisi_acc             <"add",      int_hexagon_M2_acci>;
2590 def HEXAGON_M2_accii:
2591   si_MInst_sisis8_acc             <"add",      int_hexagon_M2_accii>;
2592 def HEXAGON_M2_nacci:
2593   si_MInst_sisisi_nac             <"add",      int_hexagon_M2_nacci>;
2594 def HEXAGON_M2_naccii:
2595   si_MInst_sisis8_nac             <"add",      int_hexagon_M2_naccii>;
2596
2597 // MTYPE / ALU / Subtract and accumulate.
2598 def HEXAGON_M2_subacc:
2599   si_MInst_sisisi_acc             <"sub",      int_hexagon_M2_subacc>;
2600
2601 // MTYPE / ALU / Vector absolute difference.
2602 def HEXAGON_M2_vabsdiffh:
2603   di_MInst_didi                   <"vabsdiffh",int_hexagon_M2_vabsdiffh>;
2604 def HEXAGON_M2_vabsdiffw:
2605   di_MInst_didi                   <"vabsdiffw",int_hexagon_M2_vabsdiffw>;
2606
2607 // MTYPE / ALU / XOR and xor with destination.
2608 def HEXAGON_M2_xor_xacc:
2609   si_MInst_sisisi_xacc            <"xor",      int_hexagon_M2_xor_xacc>;
2610
2611
2612 /********************************************************************
2613 *            MTYPE/COMPLEX                                          *
2614 *********************************************************************/
2615
2616 // MTYPE / COMPLEX / Complex multiply.
2617 // Rdd[-+]=cmpy(Rs, Rt:<<1]:sat
2618 def HEXAGON_M2_cmpys_s1:
2619   di_MInst_sisi_s1_sat            <"cmpy",     int_hexagon_M2_cmpys_s1>;
2620 def HEXAGON_M2_cmpys_s0:
2621   di_MInst_sisi_sat               <"cmpy",     int_hexagon_M2_cmpys_s0>;
2622 def HEXAGON_M2_cmpysc_s1:
2623   di_MInst_sisi_s1_sat_conj       <"cmpy",     int_hexagon_M2_cmpysc_s1>;
2624 def HEXAGON_M2_cmpysc_s0:
2625   di_MInst_sisi_sat_conj          <"cmpy",     int_hexagon_M2_cmpysc_s0>;
2626
2627 def HEXAGON_M2_cmacs_s1:
2628   di_MInst_disisi_acc_s1_sat      <"cmpy",     int_hexagon_M2_cmacs_s1>;
2629 def HEXAGON_M2_cmacs_s0:
2630   di_MInst_disisi_acc_sat         <"cmpy",     int_hexagon_M2_cmacs_s0>;
2631 def HEXAGON_M2_cmacsc_s1:
2632   di_MInst_disisi_acc_s1_sat_conj <"cmpy",     int_hexagon_M2_cmacsc_s1>;
2633 def HEXAGON_M2_cmacsc_s0:
2634   di_MInst_disisi_acc_sat_conj    <"cmpy",     int_hexagon_M2_cmacsc_s0>;
2635
2636 def HEXAGON_M2_cnacs_s1:
2637   di_MInst_disisi_nac_s1_sat      <"cmpy",     int_hexagon_M2_cnacs_s1>;
2638 def HEXAGON_M2_cnacs_s0:
2639   di_MInst_disisi_nac_sat         <"cmpy",     int_hexagon_M2_cnacs_s0>;
2640 def HEXAGON_M2_cnacsc_s1:
2641   di_MInst_disisi_nac_s1_sat_conj <"cmpy",     int_hexagon_M2_cnacsc_s1>;
2642 def HEXAGON_M2_cnacsc_s0:
2643   di_MInst_disisi_nac_sat_conj    <"cmpy",     int_hexagon_M2_cnacsc_s0>;
2644
2645 // MTYPE / COMPLEX / Complex multiply real or imaginary.
2646 def HEXAGON_M2_cmpyr_s0:
2647   di_MInst_sisi                   <"cmpyr",    int_hexagon_M2_cmpyr_s0>;
2648 def HEXAGON_M2_cmacr_s0:
2649   di_MInst_disisi_acc             <"cmpyr",    int_hexagon_M2_cmacr_s0>;
2650
2651 def HEXAGON_M2_cmpyi_s0:
2652   di_MInst_sisi                   <"cmpyi",    int_hexagon_M2_cmpyi_s0>;
2653 def HEXAGON_M2_cmaci_s0:
2654   di_MInst_disisi_acc             <"cmpyi",    int_hexagon_M2_cmaci_s0>;
2655
2656 // MTYPE / COMPLEX / Complex multiply with round and pack.
2657 // Rxx32+=cmpy(Rs32,[*]Rt32:<<1]:rnd:sat
2658 def HEXAGON_M2_cmpyrs_s0:
2659   si_MInst_sisi_rnd_sat           <"cmpy",     int_hexagon_M2_cmpyrs_s0>;
2660 def HEXAGON_M2_cmpyrs_s1:
2661   si_MInst_sisi_s1_rnd_sat        <"cmpy",     int_hexagon_M2_cmpyrs_s1>;
2662
2663 def HEXAGON_M2_cmpyrsc_s0:
2664   si_MInst_sisi_rnd_sat_conj      <"cmpy",     int_hexagon_M2_cmpyrsc_s0>;
2665 def HEXAGON_M2_cmpyrsc_s1:
2666   si_MInst_sisi_s1_rnd_sat_conj   <"cmpy",     int_hexagon_M2_cmpyrsc_s1>;
2667
2668 //MTYPE / COMPLEX / Vector complex multiply real or imaginary.
2669 def HEXAGON_M2_vcmpy_s0_sat_i:
2670   di_MInst_didi_sat               <"vcmpyi",   int_hexagon_M2_vcmpy_s0_sat_i>;
2671 def HEXAGON_M2_vcmpy_s1_sat_i:
2672   di_MInst_didi_s1_sat            <"vcmpyi",   int_hexagon_M2_vcmpy_s1_sat_i>;
2673
2674 def HEXAGON_M2_vcmpy_s0_sat_r:
2675   di_MInst_didi_sat               <"vcmpyr",   int_hexagon_M2_vcmpy_s0_sat_r>;
2676 def HEXAGON_M2_vcmpy_s1_sat_r:
2677   di_MInst_didi_s1_sat            <"vcmpyr",   int_hexagon_M2_vcmpy_s1_sat_r>;
2678
2679 def HEXAGON_M2_vcmac_s0_sat_i:
2680   di_MInst_dididi_acc_sat         <"vcmpyi",   int_hexagon_M2_vcmac_s0_sat_i>;
2681 def HEXAGON_M2_vcmac_s0_sat_r:
2682   di_MInst_dididi_acc_sat         <"vcmpyr",   int_hexagon_M2_vcmac_s0_sat_r>;
2683
2684 //MTYPE / COMPLEX / Vector reduce complex multiply real or imaginary.
2685 def HEXAGON_M2_vrcmpyi_s0:
2686   di_MInst_didi                   <"vrcmpyi",  int_hexagon_M2_vrcmpyi_s0>;
2687 def HEXAGON_M2_vrcmpyr_s0:
2688   di_MInst_didi                   <"vrcmpyr",  int_hexagon_M2_vrcmpyr_s0>;
2689
2690 def HEXAGON_M2_vrcmpyi_s0c:
2691   di_MInst_didi_conj              <"vrcmpyi",  int_hexagon_M2_vrcmpyi_s0c>;
2692 def HEXAGON_M2_vrcmpyr_s0c:
2693   di_MInst_didi_conj              <"vrcmpyr",  int_hexagon_M2_vrcmpyr_s0c>;
2694
2695 def HEXAGON_M2_vrcmaci_s0:
2696   di_MInst_dididi_acc             <"vrcmpyi",  int_hexagon_M2_vrcmaci_s0>;
2697 def HEXAGON_M2_vrcmacr_s0:
2698   di_MInst_dididi_acc             <"vrcmpyr",  int_hexagon_M2_vrcmacr_s0>;
2699
2700 def HEXAGON_M2_vrcmaci_s0c:
2701   di_MInst_dididi_acc_conj        <"vrcmpyi",  int_hexagon_M2_vrcmaci_s0c>;
2702 def HEXAGON_M2_vrcmacr_s0c:
2703   di_MInst_dididi_acc_conj        <"vrcmpyr",  int_hexagon_M2_vrcmacr_s0c>;
2704
2705
2706 /********************************************************************
2707 *            MTYPE/MPYH                                             *
2708 *********************************************************************/
2709
2710 // MTYPE / MPYH / Multiply and use lower result.
2711 //def HEXAGON_M2_mpysmi:
2712 //FIXME: Hexagon_M2_mpysmi should really by of the type si_MInst_sim9,
2713 // not si_MInst_sis9 - but for now, we will use s9.
2714 // def Hexagon_M2_mpysmi:
2715 //  si_MInst_sim9                   <"mpyi",     int_hexagon_M2_mpysmi>;
2716 def Hexagon_M2_mpysmi:
2717   si_MInst_sis9                   <"mpyi",     int_hexagon_M2_mpysmi>;
2718 def HEXAGON_M2_mpyi:
2719   si_MInst_sisi                   <"mpyi",     int_hexagon_M2_mpyi>;
2720 def HEXAGON_M2_mpyui:
2721   si_MInst_sisi                   <"mpyui",    int_hexagon_M2_mpyui>;
2722 def HEXAGON_M2_macsip:
2723   si_MInst_sisiu8_acc             <"mpyi",     int_hexagon_M2_macsip>;
2724 def HEXAGON_M2_maci:
2725   si_MInst_sisisi_acc             <"mpyi",     int_hexagon_M2_maci>;
2726 def HEXAGON_M2_macsin:
2727   si_MInst_sisiu8_nac             <"mpyi",     int_hexagon_M2_macsin>;
2728
2729 // MTYPE / MPYH / Multiply word by half (32x16).
2730 //Rdd[+]=vmpywoh(Rss,Rtt)[:<<1][:rnd][:sat]
2731 //Rdd[+]=vmpyweh(Rss,Rtt)[:<<1][:rnd][:sat]
2732 def HEXAGON_M2_mmpyl_rs1:
2733   di_MInst_didi_s1_rnd_sat        <"vmpyweh",  int_hexagon_M2_mmpyl_rs1>;
2734 def HEXAGON_M2_mmpyl_s1:
2735   di_MInst_didi_s1_sat            <"vmpyweh",  int_hexagon_M2_mmpyl_s1>;
2736 def HEXAGON_M2_mmpyl_rs0:
2737   di_MInst_didi_rnd_sat           <"vmpyweh",  int_hexagon_M2_mmpyl_rs0>;
2738 def HEXAGON_M2_mmpyl_s0:
2739   di_MInst_didi_sat               <"vmpyweh",  int_hexagon_M2_mmpyl_s0>;
2740 def HEXAGON_M2_mmpyh_rs1:
2741   di_MInst_didi_s1_rnd_sat        <"vmpywoh",  int_hexagon_M2_mmpyh_rs1>;
2742 def HEXAGON_M2_mmpyh_s1:
2743   di_MInst_didi_s1_sat            <"vmpywoh",  int_hexagon_M2_mmpyh_s1>;
2744 def HEXAGON_M2_mmpyh_rs0:
2745   di_MInst_didi_rnd_sat           <"vmpywoh",  int_hexagon_M2_mmpyh_rs0>;
2746 def HEXAGON_M2_mmpyh_s0:
2747   di_MInst_didi_sat               <"vmpywoh",  int_hexagon_M2_mmpyh_s0>;
2748 def HEXAGON_M2_mmacls_rs1:
2749   di_MInst_dididi_acc_s1_rnd_sat  <"vmpyweh",  int_hexagon_M2_mmacls_rs1>;
2750 def HEXAGON_M2_mmacls_s1:
2751   di_MInst_dididi_acc_s1_sat      <"vmpyweh",  int_hexagon_M2_mmacls_s1>;
2752 def HEXAGON_M2_mmacls_rs0:
2753   di_MInst_dididi_acc_rnd_sat     <"vmpyweh",  int_hexagon_M2_mmacls_rs0>;
2754 def HEXAGON_M2_mmacls_s0:
2755   di_MInst_dididi_acc_sat         <"vmpyweh",  int_hexagon_M2_mmacls_s0>;
2756 def HEXAGON_M2_mmachs_rs1:
2757   di_MInst_dididi_acc_s1_rnd_sat  <"vmpywoh",  int_hexagon_M2_mmachs_rs1>;
2758 def HEXAGON_M2_mmachs_s1:
2759   di_MInst_dididi_acc_s1_sat      <"vmpywoh",  int_hexagon_M2_mmachs_s1>;
2760 def HEXAGON_M2_mmachs_rs0:
2761   di_MInst_dididi_acc_rnd_sat     <"vmpywoh",  int_hexagon_M2_mmachs_rs0>;
2762 def HEXAGON_M2_mmachs_s0:
2763   di_MInst_dididi_acc_sat         <"vmpywoh",  int_hexagon_M2_mmachs_s0>;
2764
2765 // MTYPE / MPYH / Multiply word by unsigned half (32x16).
2766 //Rdd[+]=vmpywouh(Rss,Rtt)[:<<1][:rnd][:sat]
2767 //Rdd[+]=vmpyweuh(Rss,Rtt)[:<<1][:rnd][:sat]
2768 def HEXAGON_M2_mmpyul_rs1:
2769   di_MInst_didi_s1_rnd_sat        <"vmpyweuh", int_hexagon_M2_mmpyul_rs1>;
2770 def HEXAGON_M2_mmpyul_s1:
2771   di_MInst_didi_s1_sat            <"vmpyweuh", int_hexagon_M2_mmpyul_s1>;
2772 def HEXAGON_M2_mmpyul_rs0:
2773   di_MInst_didi_rnd_sat           <"vmpyweuh", int_hexagon_M2_mmpyul_rs0>;
2774 def HEXAGON_M2_mmpyul_s0:
2775   di_MInst_didi_sat               <"vmpyweuh", int_hexagon_M2_mmpyul_s0>;
2776 def HEXAGON_M2_mmpyuh_rs1:
2777   di_MInst_didi_s1_rnd_sat        <"vmpywouh", int_hexagon_M2_mmpyuh_rs1>;
2778 def HEXAGON_M2_mmpyuh_s1:
2779   di_MInst_didi_s1_sat            <"vmpywouh", int_hexagon_M2_mmpyuh_s1>;
2780 def HEXAGON_M2_mmpyuh_rs0:
2781   di_MInst_didi_rnd_sat           <"vmpywouh", int_hexagon_M2_mmpyuh_rs0>;
2782 def HEXAGON_M2_mmpyuh_s0:
2783   di_MInst_didi_sat               <"vmpywouh", int_hexagon_M2_mmpyuh_s0>;
2784 def HEXAGON_M2_mmaculs_rs1:
2785   di_MInst_dididi_acc_s1_rnd_sat  <"vmpyweuh", int_hexagon_M2_mmaculs_rs1>;
2786 def HEXAGON_M2_mmaculs_s1:
2787   di_MInst_dididi_acc_s1_sat      <"vmpyweuh", int_hexagon_M2_mmaculs_s1>;
2788 def HEXAGON_M2_mmaculs_rs0:
2789   di_MInst_dididi_acc_rnd_sat     <"vmpyweuh", int_hexagon_M2_mmaculs_rs0>;
2790 def HEXAGON_M2_mmaculs_s0:
2791   di_MInst_dididi_acc_sat         <"vmpyweuh", int_hexagon_M2_mmaculs_s0>;
2792 def HEXAGON_M2_mmacuhs_rs1:
2793   di_MInst_dididi_acc_s1_rnd_sat  <"vmpywouh", int_hexagon_M2_mmacuhs_rs1>;
2794 def HEXAGON_M2_mmacuhs_s1:
2795   di_MInst_dididi_acc_s1_sat      <"vmpywouh", int_hexagon_M2_mmacuhs_s1>;
2796 def HEXAGON_M2_mmacuhs_rs0:
2797   di_MInst_dididi_acc_rnd_sat     <"vmpywouh", int_hexagon_M2_mmacuhs_rs0>;
2798 def HEXAGON_M2_mmacuhs_s0:
2799   di_MInst_dididi_acc_sat         <"vmpywouh", int_hexagon_M2_mmacuhs_s0>;
2800
2801 // MTYPE / MPYH / Multiply and use upper result.
2802 def HEXAGON_M2_hmmpyh_rs1:
2803   si_MInst_sisi_h_s1_rnd_sat      <"mpy",      int_hexagon_M2_hmmpyh_rs1>;
2804 def HEXAGON_M2_hmmpyl_rs1:
2805   si_MInst_sisi_l_s1_rnd_sat      <"mpy",      int_hexagon_M2_hmmpyl_rs1>;
2806 def HEXAGON_M2_mpy_up:
2807   si_MInst_sisi                   <"mpy",      int_hexagon_M2_mpy_up>;
2808 def HEXAGON_M2_dpmpyss_rnd_s0:
2809   si_MInst_sisi_rnd               <"mpy",      int_hexagon_M2_dpmpyss_rnd_s0>;
2810 def HEXAGON_M2_mpyu_up:
2811   si_MInst_sisi                   <"mpyu",     int_hexagon_M2_mpyu_up>;
2812
2813 // MTYPE / MPYH / Multiply and use full result.
2814 def HEXAGON_M2_dpmpyuu_s0:
2815   di_MInst_sisi                   <"mpyu",     int_hexagon_M2_dpmpyuu_s0>;
2816 def HEXAGON_M2_dpmpyuu_acc_s0:
2817   di_MInst_disisi_acc             <"mpyu",     int_hexagon_M2_dpmpyuu_acc_s0>;
2818 def HEXAGON_M2_dpmpyuu_nac_s0:
2819   di_MInst_disisi_nac             <"mpyu",     int_hexagon_M2_dpmpyuu_nac_s0>;
2820 def HEXAGON_M2_dpmpyss_s0:
2821   di_MInst_sisi                   <"mpy",      int_hexagon_M2_dpmpyss_s0>;
2822 def HEXAGON_M2_dpmpyss_acc_s0:
2823   di_MInst_disisi_acc             <"mpy",      int_hexagon_M2_dpmpyss_acc_s0>;
2824 def HEXAGON_M2_dpmpyss_nac_s0:
2825   di_MInst_disisi_nac             <"mpy",      int_hexagon_M2_dpmpyss_nac_s0>;
2826
2827 /********************************************************************
2828 *            MTYPE/VB                                               *
2829 *********************************************************************/
2830
2831 // MTYPE / VB / Vector reduce add unsigned bytes.
2832 def HEXAGON_A2_vraddub:
2833   di_MInst_didi                   <"vraddub", int_hexagon_A2_vraddub>;
2834 def HEXAGON_A2_vraddub_acc:
2835   di_MInst_dididi_acc             <"vraddub", int_hexagon_A2_vraddub_acc>;
2836
2837 // MTYPE / VB / Vector sum of absolute differences unsigned bytes.
2838 def HEXAGON_A2_vrsadub:
2839   di_MInst_didi                   <"vrsadub", int_hexagon_A2_vrsadub>;
2840 def HEXAGON_A2_vrsadub_acc:
2841   di_MInst_dididi_acc             <"vrsadub", int_hexagon_A2_vrsadub_acc>;
2842
2843 /********************************************************************
2844 *            MTYPE/VH                                               *
2845 *********************************************************************/
2846
2847 // MTYPE / VH / Vector dual multiply.
2848 def HEXAGON_M2_vdmpys_s1:
2849   di_MInst_didi_s1_sat            <"vdmpy",   int_hexagon_M2_vdmpys_s1>;
2850 def HEXAGON_M2_vdmpys_s0:
2851   di_MInst_didi_sat               <"vdmpy",   int_hexagon_M2_vdmpys_s0>;
2852 def HEXAGON_M2_vdmacs_s1:
2853   di_MInst_dididi_acc_s1_sat      <"vdmpy",   int_hexagon_M2_vdmacs_s1>;
2854 def HEXAGON_M2_vdmacs_s0:
2855   di_MInst_dididi_acc_sat         <"vdmpy",   int_hexagon_M2_vdmacs_s0>;
2856
2857 // MTYPE / VH / Vector dual multiply with round and pack.
2858 def HEXAGON_M2_vdmpyrs_s0:
2859   si_MInst_didi_rnd_sat           <"vdmpy",   int_hexagon_M2_vdmpyrs_s0>;
2860 def HEXAGON_M2_vdmpyrs_s1:
2861   si_MInst_didi_s1_rnd_sat        <"vdmpy",   int_hexagon_M2_vdmpyrs_s1>;
2862
2863 // MTYPE / VH / Vector multiply even halfwords.
2864 def HEXAGON_M2_vmpy2es_s1:
2865   di_MInst_didi_s1_sat            <"vmpyeh",  int_hexagon_M2_vmpy2es_s1>;
2866 def HEXAGON_M2_vmpy2es_s0:
2867   di_MInst_didi_sat               <"vmpyeh",  int_hexagon_M2_vmpy2es_s0>;
2868 def HEXAGON_M2_vmac2es:
2869   di_MInst_dididi_acc             <"vmpyeh",  int_hexagon_M2_vmac2es>;
2870 def HEXAGON_M2_vmac2es_s1:
2871   di_MInst_dididi_acc_s1_sat      <"vmpyeh",  int_hexagon_M2_vmac2es_s1>;
2872 def HEXAGON_M2_vmac2es_s0:
2873   di_MInst_dididi_acc_sat         <"vmpyeh",  int_hexagon_M2_vmac2es_s0>;
2874
2875 // MTYPE / VH / Vector multiply halfwords.
2876 def HEXAGON_M2_vmpy2s_s0:
2877   di_MInst_sisi_sat               <"vmpyh",   int_hexagon_M2_vmpy2s_s0>;
2878 def HEXAGON_M2_vmpy2s_s1:
2879   di_MInst_sisi_s1_sat            <"vmpyh",   int_hexagon_M2_vmpy2s_s1>;
2880 def HEXAGON_M2_vmac2:
2881   di_MInst_disisi_acc             <"vmpyh",   int_hexagon_M2_vmac2>;
2882 def HEXAGON_M2_vmac2s_s0:
2883   di_MInst_disisi_acc_sat         <"vmpyh",   int_hexagon_M2_vmac2s_s0>;
2884 def HEXAGON_M2_vmac2s_s1:
2885   di_MInst_disisi_acc_s1_sat      <"vmpyh",   int_hexagon_M2_vmac2s_s1>;
2886
2887 // MTYPE / VH / Vector multiply halfwords with round and pack.
2888 def HEXAGON_M2_vmpy2s_s0pack:
2889   si_MInst_sisi_rnd_sat           <"vmpyh",   int_hexagon_M2_vmpy2s_s0pack>;
2890 def HEXAGON_M2_vmpy2s_s1pack:
2891   si_MInst_sisi_s1_rnd_sat        <"vmpyh",   int_hexagon_M2_vmpy2s_s1pack>;
2892
2893 // MTYPE / VH / Vector reduce multiply halfwords.
2894 // Rxx32+=vrmpyh(Rss32,Rtt32)
2895 def HEXAGON_M2_vrmpy_s0:
2896   di_MInst_didi                   <"vrmpyh",  int_hexagon_M2_vrmpy_s0>;
2897 def HEXAGON_M2_vrmac_s0:
2898   di_MInst_dididi_acc             <"vrmpyh",  int_hexagon_M2_vrmac_s0>;
2899
2900
2901 /********************************************************************
2902 *            STYPE/ALU                                              *
2903 *********************************************************************/
2904
2905 // STYPE / ALU / Absolute value.
2906 def HEXAGON_A2_abs:
2907   si_SInst_si                     <"abs",     int_hexagon_A2_abs>;
2908 def HEXAGON_A2_absp:
2909   di_SInst_di                     <"abs",     int_hexagon_A2_absp>;
2910 def HEXAGON_A2_abssat:
2911   si_SInst_si_sat                 <"abs",     int_hexagon_A2_abssat>;
2912
2913 // STYPE / ALU / Logical Not.
2914 def HEXAGON_A2_notp:
2915   di_SInst_di                     <"not",     int_hexagon_A2_notp>;
2916
2917 // STYPE / ALU / Sign extend word to doubleword.
2918 def HEXAGON_A2_sxtw:
2919   di_SInst_si                     <"sxtw",     int_hexagon_A2_sxtw>;
2920
2921
2922 /********************************************************************
2923 *            STYPE/BIT                                              *
2924 *********************************************************************/
2925
2926 // STYPE / BIT / Count leading.
2927 def HEXAGON_S2_cl0:
2928   si_SInst_si                     <"cl0",     int_hexagon_S2_cl0>;
2929 def HEXAGON_S2_cl0p:
2930   si_SInst_di                     <"cl0",     int_hexagon_S2_cl0p>;
2931 def HEXAGON_S2_cl1:
2932   si_SInst_si                     <"cl1",     int_hexagon_S2_cl1>;
2933 def HEXAGON_S2_cl1p:
2934   si_SInst_di                     <"cl1",     int_hexagon_S2_cl1p>;
2935 def HEXAGON_S2_clb:
2936   si_SInst_si                     <"clb",     int_hexagon_S2_clb>;
2937 def HEXAGON_S2_clbp:
2938   si_SInst_di                     <"clb",     int_hexagon_S2_clbp>;
2939 def HEXAGON_S2_clbnorm:
2940   si_SInst_si                     <"normamt", int_hexagon_S2_clbnorm>;
2941
2942 // STYPE / BIT / Count trailing.
2943 def HEXAGON_S2_ct0:
2944   si_SInst_si                     <"ct0",     int_hexagon_S2_ct0>;
2945 def HEXAGON_S2_ct1:
2946   si_SInst_si                     <"ct1",     int_hexagon_S2_ct1>;
2947
2948 // STYPE / BIT / Compare bit mask.
2949 def Hexagon_C2_bitsclr:
2950   qi_SInst_sisi                   <"bitsclr", int_hexagon_C2_bitsclr>;
2951 def Hexagon_C2_bitsclri:
2952   qi_SInst_siu6                   <"bitsclr", int_hexagon_C2_bitsclri>;
2953 def Hexagon_C2_bitsset:
2954   qi_SInst_sisi                   <"bitsset", int_hexagon_C2_bitsset>;
2955
2956 // STYPE / BIT / Extract unsigned.
2957 // Rd[d][32/64]=extractu(Rs[s],Rt[t],[imm])
2958 def HEXAGON_S2_extractu:
2959   si_SInst_siu5u5                 <"extractu",int_hexagon_S2_extractu>;
2960 def HEXAGON_S2_extractu_rp:
2961   si_SInst_sidi                   <"extractu",int_hexagon_S2_extractu_rp>;
2962 def HEXAGON_S2_extractup:
2963   di_SInst_diu6u6                 <"extractu",int_hexagon_S2_extractup>;
2964 def HEXAGON_S2_extractup_rp:
2965   di_SInst_didi                   <"extractu",int_hexagon_S2_extractup_rp>;
2966
2967 // STYPE / BIT / Insert bitfield.
2968 def Hexagon_S2_insert:
2969   si_SInst_sisiu5u5               <"insert",  int_hexagon_S2_insert>;
2970 def Hexagon_S2_insert_rp:
2971   si_SInst_sisidi                 <"insert",  int_hexagon_S2_insert_rp>;
2972 def Hexagon_S2_insertp:
2973   di_SInst_didiu6u6               <"insert",  int_hexagon_S2_insertp>;
2974 def Hexagon_S2_insertp_rp:
2975   di_SInst_dididi                 <"insert",  int_hexagon_S2_insertp_rp>;
2976
2977 // STYPE / BIT / Innterleave/deinterleave.
2978 def Hexagon_S2_interleave:
2979   di_SInst_di                     <"interleave", int_hexagon_S2_interleave>;
2980 def Hexagon_S2_deinterleave:
2981   di_SInst_di                     <"deinterleave", int_hexagon_S2_deinterleave>;
2982
2983 // STYPE / BIT / Linear feedback-shift Iteration.
2984 def Hexagon_S2_lfsp:
2985   di_SInst_didi                   <"lfs",     int_hexagon_S2_lfsp>;
2986
2987 // STYPE / BIT / Bit reverse.
2988 def Hexagon_S2_brev:
2989   si_SInst_si                     <"brev",    int_hexagon_S2_brev>;
2990
2991 // STYPE / BIT / Set/Clear/Toggle Bit.
2992 def HEXAGON_S2_setbit_i:
2993   si_SInst_siu5                   <"setbit",  int_hexagon_S2_setbit_i>;
2994 def HEXAGON_S2_togglebit_i:
2995   si_SInst_siu5                   <"togglebit", int_hexagon_S2_togglebit_i>;
2996 def HEXAGON_S2_clrbit_i:
2997   si_SInst_siu5                   <"clrbit",  int_hexagon_S2_clrbit_i>;
2998 def HEXAGON_S2_setbit_r:
2999   si_SInst_sisi                   <"setbit",  int_hexagon_S2_setbit_r>;
3000 def HEXAGON_S2_togglebit_r:
3001   si_SInst_sisi                   <"togglebit", int_hexagon_S2_togglebit_r>;
3002 def HEXAGON_S2_clrbit_r:
3003   si_SInst_sisi                   <"clrbit",  int_hexagon_S2_clrbit_r>;
3004
3005 // STYPE / BIT / Test Bit.
3006 def HEXAGON_S2_tstbit_i:
3007   qi_SInst_siu5                   <"tstbit",  int_hexagon_S2_tstbit_i>;
3008 def HEXAGON_S2_tstbit_r:
3009   qi_SInst_sisi                   <"tstbit",  int_hexagon_S2_tstbit_r>;
3010
3011
3012 /********************************************************************
3013 *            STYPE/COMPLEX                                          *
3014 *********************************************************************/
3015
3016 // STYPE / COMPLEX / Vector Complex conjugate.
3017 def HEXAGON_A2_vconj:
3018   di_SInst_di_sat                 <"vconj",   int_hexagon_A2_vconj>;
3019
3020 // STYPE / COMPLEX / Vector Complex rotate.
3021 def HEXAGON_S2_vcrotate:
3022   di_SInst_disi                   <"vcrotate",int_hexagon_S2_vcrotate>;
3023
3024
3025 /********************************************************************
3026 *            STYPE/PERM                                             *
3027 *********************************************************************/
3028
3029 // STYPE / PERM / Saturate.
3030 def HEXAGON_A2_sat:
3031   si_SInst_di                     <"sat",     int_hexagon_A2_sat>;
3032 def HEXAGON_A2_satb:
3033   si_SInst_si                     <"satb",    int_hexagon_A2_satb>;
3034 def HEXAGON_A2_sath:
3035   si_SInst_si                     <"sath",    int_hexagon_A2_sath>;
3036 def HEXAGON_A2_satub:
3037   si_SInst_si                     <"satub",   int_hexagon_A2_satub>;
3038 def HEXAGON_A2_satuh:
3039   si_SInst_si                     <"satuh",   int_hexagon_A2_satuh>;
3040
3041 // STYPE / PERM / Swizzle bytes.
3042 def HEXAGON_A2_swiz:
3043   si_SInst_si                     <"swiz",    int_hexagon_A2_swiz>;
3044
3045 // STYPE / PERM / Vector align.
3046 // Need custom lowering
3047 def HEXAGON_S2_valignib:
3048   di_SInst_didiu3                 <"valignb", int_hexagon_S2_valignib>;
3049 def HEXAGON_S2_valignrb:
3050   di_SInst_didiqi                 <"valignb", int_hexagon_S2_valignrb>;
3051
3052 // STYPE / PERM / Vector round and pack.
3053 def HEXAGON_S2_vrndpackwh:
3054   si_SInst_di                     <"vrndwh",  int_hexagon_S2_vrndpackwh>;
3055 def HEXAGON_S2_vrndpackwhs:
3056   si_SInst_di_sat                 <"vrndwh",  int_hexagon_S2_vrndpackwhs>;
3057
3058 // STYPE / PERM / Vector saturate and pack.
3059 def HEXAGON_S2_svsathb:
3060   si_SInst_si                     <"vsathb",  int_hexagon_S2_svsathb>;
3061 def HEXAGON_S2_vsathb:
3062   si_SInst_di                     <"vsathb",  int_hexagon_S2_vsathb>;
3063 def HEXAGON_S2_svsathub:
3064   si_SInst_si                     <"vsathub", int_hexagon_S2_svsathub>;
3065 def HEXAGON_S2_vsathub:
3066   si_SInst_di                     <"vsathub", int_hexagon_S2_vsathub>;
3067 def HEXAGON_S2_vsatwh:
3068   si_SInst_di                     <"vsatwh",  int_hexagon_S2_vsatwh>;
3069 def HEXAGON_S2_vsatwuh:
3070   si_SInst_di                     <"vsatwuh", int_hexagon_S2_vsatwuh>;
3071
3072 // STYPE / PERM / Vector saturate without pack.
3073 def HEXAGON_S2_vsathb_nopack:
3074   di_SInst_di                     <"vsathb",  int_hexagon_S2_vsathb_nopack>;
3075 def HEXAGON_S2_vsathub_nopack:
3076   di_SInst_di                     <"vsathub", int_hexagon_S2_vsathub_nopack>;
3077 def HEXAGON_S2_vsatwh_nopack:
3078   di_SInst_di                     <"vsatwh",  int_hexagon_S2_vsatwh_nopack>;
3079 def HEXAGON_S2_vsatwuh_nopack:
3080   di_SInst_di                     <"vsatwuh", int_hexagon_S2_vsatwuh_nopack>;
3081
3082 // STYPE / PERM / Vector shuffle.
3083 def HEXAGON_S2_shuffeb:
3084   di_SInst_didi                   <"shuffeb", int_hexagon_S2_shuffeb>;
3085 def HEXAGON_S2_shuffeh:
3086   di_SInst_didi                   <"shuffeh", int_hexagon_S2_shuffeh>;
3087 def HEXAGON_S2_shuffob:
3088   di_SInst_didi                   <"shuffob", int_hexagon_S2_shuffob>;
3089 def HEXAGON_S2_shuffoh:
3090   di_SInst_didi                   <"shuffoh", int_hexagon_S2_shuffoh>;
3091
3092 // STYPE / PERM / Vector splat bytes.
3093 def HEXAGON_S2_vsplatrb:
3094   si_SInst_si                     <"vsplatb", int_hexagon_S2_vsplatrb>;
3095
3096 // STYPE / PERM / Vector splat halfwords.
3097 def HEXAGON_S2_vsplatrh:
3098   di_SInst_si                     <"vsplath", int_hexagon_S2_vsplatrh>;
3099
3100 // STYPE / PERM / Vector splice.
3101 def Hexagon_S2_vsplicerb:
3102   di_SInst_didiqi                 <"vspliceb",int_hexagon_S2_vsplicerb>;
3103 def Hexagon_S2_vspliceib:
3104   di_SInst_didiu3                 <"vspliceb",int_hexagon_S2_vspliceib>;
3105
3106 // STYPE / PERM / Sign extend.
3107 def HEXAGON_S2_vsxtbh:
3108   di_SInst_si                     <"vsxtbh",  int_hexagon_S2_vsxtbh>;
3109 def HEXAGON_S2_vsxthw:
3110   di_SInst_si                     <"vsxthw",  int_hexagon_S2_vsxthw>;
3111
3112 // STYPE / PERM / Truncate.
3113 def HEXAGON_S2_vtrunehb:
3114   si_SInst_di                     <"vtrunehb",int_hexagon_S2_vtrunehb>;
3115 def HEXAGON_S2_vtrunohb:
3116   si_SInst_di                     <"vtrunohb",int_hexagon_S2_vtrunohb>;
3117 def HEXAGON_S2_vtrunewh:
3118   di_SInst_didi                   <"vtrunewh",int_hexagon_S2_vtrunewh>;
3119 def HEXAGON_S2_vtrunowh:
3120   di_SInst_didi                   <"vtrunowh",int_hexagon_S2_vtrunowh>;
3121
3122 // STYPE / PERM / Zero extend.
3123 def HEXAGON_S2_vzxtbh:
3124   di_SInst_si                     <"vzxtbh",  int_hexagon_S2_vzxtbh>;
3125 def HEXAGON_S2_vzxthw:
3126   di_SInst_si                     <"vzxthw",  int_hexagon_S2_vzxthw>;
3127
3128
3129 /********************************************************************
3130 *            STYPE/PRED                                             *
3131 *********************************************************************/
3132
3133 // STYPE / PRED / Mask generate from predicate.
3134 def HEXAGON_C2_mask:
3135   di_SInst_qi                     <"mask",   int_hexagon_C2_mask>;
3136
3137 // STYPE / PRED / Predicate transfer.
3138 def HEXAGON_C2_tfrpr:
3139   si_SInst_qi                     <"",       int_hexagon_C2_tfrpr>;
3140 def HEXAGON_C2_tfrrp:
3141   qi_SInst_si                     <"",       int_hexagon_C2_tfrrp>;
3142
3143 // STYPE / PRED / Viterbi pack even and odd predicate bits.
3144 def HEXAGON_C2_vitpack:
3145   si_SInst_qiqi                   <"vitpack",int_hexagon_C2_vitpack>;
3146
3147
3148 /********************************************************************
3149 *            STYPE/SHIFT                                            *
3150 *********************************************************************/
3151
3152 // STYPE / SHIFT / Shift by immediate.
3153 def HEXAGON_S2_asl_i_r:
3154   si_SInst_siu5                   <"asl",     int_hexagon_S2_asl_i_r>;
3155 def HEXAGON_S2_asr_i_r:
3156   si_SInst_siu5                   <"asr",     int_hexagon_S2_asr_i_r>;
3157 def HEXAGON_S2_lsr_i_r:
3158   si_SInst_siu5                   <"lsr",     int_hexagon_S2_lsr_i_r>;
3159 def HEXAGON_S2_asl_i_p:
3160   di_SInst_diu6                   <"asl",     int_hexagon_S2_asl_i_p>;
3161 def HEXAGON_S2_asr_i_p:
3162   di_SInst_diu6                   <"asr",     int_hexagon_S2_asr_i_p>;
3163 def HEXAGON_S2_lsr_i_p:
3164   di_SInst_diu6                   <"lsr",     int_hexagon_S2_lsr_i_p>;
3165
3166 // STYPE / SHIFT / Shift by immediate and accumulate.
3167 def HEXAGON_S2_asl_i_r_acc:
3168   si_SInst_sisiu5_acc             <"asl",     int_hexagon_S2_asl_i_r_acc>;
3169 def HEXAGON_S2_asr_i_r_acc:
3170   si_SInst_sisiu5_acc             <"asr",     int_hexagon_S2_asr_i_r_acc>;
3171 def HEXAGON_S2_lsr_i_r_acc:
3172   si_SInst_sisiu5_acc             <"lsr",     int_hexagon_S2_lsr_i_r_acc>;
3173 def HEXAGON_S2_asl_i_r_nac:
3174   si_SInst_sisiu5_nac             <"asl",     int_hexagon_S2_asl_i_r_nac>;
3175 def HEXAGON_S2_asr_i_r_nac:
3176   si_SInst_sisiu5_nac             <"asr",     int_hexagon_S2_asr_i_r_nac>;
3177 def HEXAGON_S2_lsr_i_r_nac:
3178   si_SInst_sisiu5_nac             <"lsr",     int_hexagon_S2_lsr_i_r_nac>;
3179 def HEXAGON_S2_asl_i_p_acc:
3180   di_SInst_didiu6_acc             <"asl",     int_hexagon_S2_asl_i_p_acc>;
3181 def HEXAGON_S2_asr_i_p_acc:
3182   di_SInst_didiu6_acc             <"asr",     int_hexagon_S2_asr_i_p_acc>;
3183 def HEXAGON_S2_lsr_i_p_acc:
3184   di_SInst_didiu6_acc             <"lsr",     int_hexagon_S2_lsr_i_p_acc>;
3185 def HEXAGON_S2_asl_i_p_nac:
3186   di_SInst_didiu6_nac             <"asl",     int_hexagon_S2_asl_i_p_nac>;
3187 def HEXAGON_S2_asr_i_p_nac:
3188   di_SInst_didiu6_nac             <"asr",     int_hexagon_S2_asr_i_p_nac>;
3189 def HEXAGON_S2_lsr_i_p_nac:
3190   di_SInst_didiu6_nac             <"lsr",     int_hexagon_S2_lsr_i_p_nac>;
3191
3192 // STYPE / SHIFT / Shift by immediate and add.
3193 def HEXAGON_S2_addasl_rrri:
3194   si_SInst_sisiu3                 <"addasl",  int_hexagon_S2_addasl_rrri>;
3195
3196 // STYPE / SHIFT / Shift by immediate and logical.
3197 def HEXAGON_S2_asl_i_r_and:
3198   si_SInst_sisiu5_and             <"asl",     int_hexagon_S2_asl_i_r_and>;
3199 def HEXAGON_S2_asr_i_r_and:
3200   si_SInst_sisiu5_and             <"asr",     int_hexagon_S2_asr_i_r_and>;
3201 def HEXAGON_S2_lsr_i_r_and:
3202   si_SInst_sisiu5_and             <"lsr",     int_hexagon_S2_lsr_i_r_and>;
3203
3204 def HEXAGON_S2_asl_i_r_xacc:
3205   si_SInst_sisiu5_xor             <"asl",     int_hexagon_S2_asl_i_r_xacc>;
3206 def HEXAGON_S2_lsr_i_r_xacc:
3207   si_SInst_sisiu5_xor             <"lsr",     int_hexagon_S2_lsr_i_r_xacc>;
3208
3209 def HEXAGON_S2_asl_i_r_or:
3210   si_SInst_sisiu5_or              <"asl",     int_hexagon_S2_asl_i_r_or>;
3211 def HEXAGON_S2_asr_i_r_or:
3212   si_SInst_sisiu5_or              <"asr",     int_hexagon_S2_asr_i_r_or>;
3213 def HEXAGON_S2_lsr_i_r_or:
3214   si_SInst_sisiu5_or              <"lsr",     int_hexagon_S2_lsr_i_r_or>;
3215
3216 def HEXAGON_S2_asl_i_p_and:
3217   di_SInst_didiu6_and             <"asl",     int_hexagon_S2_asl_i_p_and>;
3218 def HEXAGON_S2_asr_i_p_and:
3219   di_SInst_didiu6_and             <"asr",     int_hexagon_S2_asr_i_p_and>;
3220 def HEXAGON_S2_lsr_i_p_and:
3221   di_SInst_didiu6_and             <"lsr",     int_hexagon_S2_lsr_i_p_and>;
3222
3223 def HEXAGON_S2_asl_i_p_xacc:
3224   di_SInst_didiu6_xor             <"asl",     int_hexagon_S2_asl_i_p_xacc>;
3225 def HEXAGON_S2_lsr_i_p_xacc:
3226   di_SInst_didiu6_xor             <"lsr",     int_hexagon_S2_lsr_i_p_xacc>;
3227
3228 def HEXAGON_S2_asl_i_p_or:
3229   di_SInst_didiu6_or              <"asl",     int_hexagon_S2_asl_i_p_or>;
3230 def HEXAGON_S2_asr_i_p_or:
3231   di_SInst_didiu6_or              <"asr",     int_hexagon_S2_asr_i_p_or>;
3232 def HEXAGON_S2_lsr_i_p_or:
3233   di_SInst_didiu6_or              <"lsr",     int_hexagon_S2_lsr_i_p_or>;
3234
3235 // STYPE / SHIFT / Shift right by immediate with rounding.
3236 def HEXAGON_S2_asr_i_r_rnd:
3237   si_SInst_siu5_rnd               <"asr",     int_hexagon_S2_asr_i_r_rnd>;
3238 def HEXAGON_S2_asr_i_r_rnd_goodsyntax:
3239   si_SInst_siu5              <"asrrnd",  int_hexagon_S2_asr_i_r_rnd_goodsyntax>;
3240
3241 // STYPE / SHIFT / Shift left by immediate with saturation.
3242 def HEXAGON_S2_asl_i_r_sat:
3243   si_SInst_sisi_sat               <"asl",     int_hexagon_S2_asl_i_r_sat>;
3244
3245 // STYPE / SHIFT / Shift by register.
3246 def HEXAGON_S2_asl_r_r:
3247   si_SInst_sisi                   <"asl",     int_hexagon_S2_asl_r_r>;
3248 def HEXAGON_S2_asr_r_r:
3249   si_SInst_sisi                   <"asr",     int_hexagon_S2_asr_r_r>;
3250 def HEXAGON_S2_lsl_r_r:
3251   si_SInst_sisi                   <"lsl",     int_hexagon_S2_lsl_r_r>;
3252 def HEXAGON_S2_lsr_r_r:
3253   si_SInst_sisi                   <"lsr",     int_hexagon_S2_lsr_r_r>;
3254 def HEXAGON_S2_asl_r_p:
3255   di_SInst_disi                   <"asl",     int_hexagon_S2_asl_r_p>;
3256 def HEXAGON_S2_asr_r_p:
3257   di_SInst_disi                   <"asr",     int_hexagon_S2_asr_r_p>;
3258 def HEXAGON_S2_lsl_r_p:
3259   di_SInst_disi                   <"lsl",     int_hexagon_S2_lsl_r_p>;
3260 def HEXAGON_S2_lsr_r_p:
3261   di_SInst_disi                   <"lsr",     int_hexagon_S2_lsr_r_p>;
3262
3263 // STYPE / SHIFT / Shift by register and accumulate.
3264 def HEXAGON_S2_asl_r_r_acc:
3265   si_SInst_sisisi_acc             <"asl",     int_hexagon_S2_asl_r_r_acc>;
3266 def HEXAGON_S2_asr_r_r_acc:
3267   si_SInst_sisisi_acc             <"asr",     int_hexagon_S2_asr_r_r_acc>;
3268 def HEXAGON_S2_lsl_r_r_acc:
3269   si_SInst_sisisi_acc             <"lsl",     int_hexagon_S2_lsl_r_r_acc>;
3270 def HEXAGON_S2_lsr_r_r_acc:
3271   si_SInst_sisisi_acc             <"lsr",     int_hexagon_S2_lsr_r_r_acc>;
3272 def HEXAGON_S2_asl_r_p_acc:
3273   di_SInst_didisi_acc             <"asl",     int_hexagon_S2_asl_r_p_acc>;
3274 def HEXAGON_S2_asr_r_p_acc:
3275   di_SInst_didisi_acc             <"asr",     int_hexagon_S2_asr_r_p_acc>;
3276 def HEXAGON_S2_lsl_r_p_acc:
3277   di_SInst_didisi_acc             <"lsl",     int_hexagon_S2_lsl_r_p_acc>;
3278 def HEXAGON_S2_lsr_r_p_acc:
3279   di_SInst_didisi_acc             <"lsr",     int_hexagon_S2_lsr_r_p_acc>;
3280
3281 def HEXAGON_S2_asl_r_r_nac:
3282   si_SInst_sisisi_nac             <"asl",     int_hexagon_S2_asl_r_r_nac>;
3283 def HEXAGON_S2_asr_r_r_nac:
3284   si_SInst_sisisi_nac             <"asr",     int_hexagon_S2_asr_r_r_nac>;
3285 def HEXAGON_S2_lsl_r_r_nac:
3286   si_SInst_sisisi_nac             <"lsl",     int_hexagon_S2_lsl_r_r_nac>;
3287 def HEXAGON_S2_lsr_r_r_nac:
3288   si_SInst_sisisi_nac             <"lsr",     int_hexagon_S2_lsr_r_r_nac>;
3289 def HEXAGON_S2_asl_r_p_nac:
3290   di_SInst_didisi_nac             <"asl",     int_hexagon_S2_asl_r_p_nac>;
3291 def HEXAGON_S2_asr_r_p_nac:
3292   di_SInst_didisi_nac             <"asr",     int_hexagon_S2_asr_r_p_nac>;
3293 def HEXAGON_S2_lsl_r_p_nac:
3294   di_SInst_didisi_nac             <"lsl",     int_hexagon_S2_lsl_r_p_nac>;
3295 def HEXAGON_S2_lsr_r_p_nac:
3296   di_SInst_didisi_nac             <"lsr",     int_hexagon_S2_lsr_r_p_nac>;
3297
3298 // STYPE / SHIFT / Shift by register and logical.
3299 def HEXAGON_S2_asl_r_r_and:
3300   si_SInst_sisisi_and             <"asl",     int_hexagon_S2_asl_r_r_and>;
3301 def HEXAGON_S2_asr_r_r_and:
3302   si_SInst_sisisi_and             <"asr",     int_hexagon_S2_asr_r_r_and>;
3303 def HEXAGON_S2_lsl_r_r_and:
3304   si_SInst_sisisi_and             <"lsl",     int_hexagon_S2_lsl_r_r_and>;
3305 def HEXAGON_S2_lsr_r_r_and:
3306   si_SInst_sisisi_and             <"lsr",     int_hexagon_S2_lsr_r_r_and>;
3307
3308 def HEXAGON_S2_asl_r_r_or:
3309   si_SInst_sisisi_or              <"asl",     int_hexagon_S2_asl_r_r_or>;
3310 def HEXAGON_S2_asr_r_r_or:
3311   si_SInst_sisisi_or              <"asr",     int_hexagon_S2_asr_r_r_or>;
3312 def HEXAGON_S2_lsl_r_r_or:
3313   si_SInst_sisisi_or              <"lsl",     int_hexagon_S2_lsl_r_r_or>;
3314 def HEXAGON_S2_lsr_r_r_or:
3315   si_SInst_sisisi_or              <"lsr",     int_hexagon_S2_lsr_r_r_or>;
3316
3317 def HEXAGON_S2_asl_r_p_and:
3318   di_SInst_didisi_and             <"asl",     int_hexagon_S2_asl_r_p_and>;
3319 def HEXAGON_S2_asr_r_p_and:
3320   di_SInst_didisi_and             <"asr",     int_hexagon_S2_asr_r_p_and>;
3321 def HEXAGON_S2_lsl_r_p_and:
3322   di_SInst_didisi_and             <"lsl",     int_hexagon_S2_lsl_r_p_and>;
3323 def HEXAGON_S2_lsr_r_p_and:
3324   di_SInst_didisi_and             <"lsr",     int_hexagon_S2_lsr_r_p_and>;
3325
3326 def HEXAGON_S2_asl_r_p_or:
3327   di_SInst_didisi_or              <"asl",     int_hexagon_S2_asl_r_p_or>;
3328 def HEXAGON_S2_asr_r_p_or:
3329   di_SInst_didisi_or              <"asr",     int_hexagon_S2_asr_r_p_or>;
3330 def HEXAGON_S2_lsl_r_p_or:
3331   di_SInst_didisi_or              <"lsl",     int_hexagon_S2_lsl_r_p_or>;
3332 def HEXAGON_S2_lsr_r_p_or:
3333   di_SInst_didisi_or              <"lsr",     int_hexagon_S2_lsr_r_p_or>;
3334
3335 // STYPE / SHIFT / Shift by register with saturation.
3336 def HEXAGON_S2_asl_r_r_sat:
3337   si_SInst_sisi_sat               <"asl",     int_hexagon_S2_asl_r_r_sat>;
3338 def HEXAGON_S2_asr_r_r_sat:
3339   si_SInst_sisi_sat               <"asr",     int_hexagon_S2_asr_r_r_sat>;
3340
3341 // STYPE / SHIFT / Table Index.
3342 def Hexagon_S2_tableidxb_goodsyntax:
3343   si_MInst_sisiu4u5          <"tableidxb",int_hexagon_S2_tableidxb_goodsyntax>;
3344 def Hexagon_S2_tableidxd_goodsyntax:
3345   si_MInst_sisiu4u5          <"tableidxd",int_hexagon_S2_tableidxd_goodsyntax>;
3346 def Hexagon_S2_tableidxh_goodsyntax:
3347   si_MInst_sisiu4u5          <"tableidxh",int_hexagon_S2_tableidxh_goodsyntax>;
3348 def Hexagon_S2_tableidxw_goodsyntax:
3349   si_MInst_sisiu4u5          <"tableidxw",int_hexagon_S2_tableidxw_goodsyntax>;
3350
3351
3352 /********************************************************************
3353 *            STYPE/VH                                               *
3354 *********************************************************************/
3355
3356 // STYPE / VH / Vector absolute value halfwords.
3357 // Rdd64=vabsh(Rss64)
3358 def HEXAGON_A2_vabsh:
3359   di_SInst_di                     <"vabsh",   int_hexagon_A2_vabsh>;
3360 def HEXAGON_A2_vabshsat:
3361   di_SInst_di_sat                 <"vabsh",   int_hexagon_A2_vabshsat>;
3362
3363 // STYPE / VH / Vector shift halfwords by immediate.
3364 // Rdd64=v[asl/asr/lsr]h(Rss64,Rt32)
3365 def HEXAGON_S2_asl_i_vh:
3366   di_SInst_disi                   <"vaslh",   int_hexagon_S2_asl_i_vh>;
3367 def HEXAGON_S2_asr_i_vh:
3368   di_SInst_disi                   <"vasrh",   int_hexagon_S2_asr_i_vh>;
3369 def HEXAGON_S2_lsr_i_vh:
3370   di_SInst_disi                   <"vlsrh",   int_hexagon_S2_lsr_i_vh>;
3371
3372 // STYPE / VH / Vector shift halfwords by register.
3373 // Rdd64=v[asl/asr/lsl/lsr]w(Rss64,Rt32)
3374 def HEXAGON_S2_asl_r_vh:
3375   di_SInst_disi                   <"vaslh",   int_hexagon_S2_asl_r_vh>;
3376 def HEXAGON_S2_asr_r_vh:
3377   di_SInst_disi                   <"vasrh",   int_hexagon_S2_asr_r_vh>;
3378 def HEXAGON_S2_lsl_r_vh:
3379   di_SInst_disi                   <"vlslh",   int_hexagon_S2_lsl_r_vh>;
3380 def HEXAGON_S2_lsr_r_vh:
3381   di_SInst_disi                   <"vlsrh",   int_hexagon_S2_lsr_r_vh>;
3382
3383
3384 /********************************************************************
3385 *            STYPE/VW                                               *
3386 *********************************************************************/
3387
3388 // STYPE / VW / Vector absolute value words.
3389 def HEXAGON_A2_vabsw:
3390   di_SInst_di                     <"vabsw",   int_hexagon_A2_vabsw>;
3391 def HEXAGON_A2_vabswsat:
3392   di_SInst_di_sat                 <"vabsw",   int_hexagon_A2_vabswsat>;
3393
3394 // STYPE / VW / Vector shift words by immediate.
3395 // Rdd64=v[asl/vsl]w(Rss64,Rt32)
3396 def HEXAGON_S2_asl_i_vw:
3397   di_SInst_disi                   <"vaslw",   int_hexagon_S2_asl_i_vw>;
3398 def HEXAGON_S2_asr_i_vw:
3399   di_SInst_disi                   <"vasrw",   int_hexagon_S2_asr_i_vw>;
3400 def HEXAGON_S2_lsr_i_vw:
3401   di_SInst_disi                   <"vlsrw",   int_hexagon_S2_lsr_i_vw>;
3402
3403 // STYPE / VW / Vector shift words by register.
3404 // Rdd64=v[asl/vsl]w(Rss64,Rt32)
3405 def HEXAGON_S2_asl_r_vw:
3406   di_SInst_disi                   <"vaslw",   int_hexagon_S2_asl_r_vw>;
3407 def HEXAGON_S2_asr_r_vw:
3408   di_SInst_disi                   <"vasrw",   int_hexagon_S2_asr_r_vw>;
3409 def HEXAGON_S2_lsl_r_vw:
3410   di_SInst_disi                   <"vlslw",   int_hexagon_S2_lsl_r_vw>;
3411 def HEXAGON_S2_lsr_r_vw:
3412   di_SInst_disi                   <"vlsrw",   int_hexagon_S2_lsr_r_vw>;
3413
3414 // STYPE / VW / Vector shift words with truncate and pack.
3415 def HEXAGON_S2_asr_r_svw_trun:
3416   si_SInst_disi                   <"vasrw",   int_hexagon_S2_asr_r_svw_trun>;
3417 def HEXAGON_S2_asr_i_svw_trun:
3418   si_SInst_diu5                   <"vasrw",   int_hexagon_S2_asr_i_svw_trun>;
3419
3420 // LD / Circular loads.
3421 def HEXAGON_circ_ldd:
3422   di_LDInstPI_diu4                <"circ_ldd", int_hexagon_circ_ldd>;
3423
3424 include "HexagonIntrinsicsV3.td"
3425 include "HexagonIntrinsicsV4.td"
3426 include "HexagonIntrinsicsV5.td"