1 //=- HexagonInstrInfoV5.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V5 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
18 let isCodeGenOnly = 0 in
19 def S2_asr_i_p_rnd : S_2OpInstImm<"asr", 0b110, 0b111, u6Imm,
21 (sra (i64 (add (i64 (sra I64:$src1, u6ImmPred:$src2)), 1)),
25 let Inst{13-8} = src2;
28 let isCodeGenOnly = 0 in
29 def C4_fastcorner9 : T_LOGICAL_2OP<"fastcorner9", 0b000, 0, 0>,
31 let Inst{13,7,4} = 0b111;
34 let isCodeGenOnly = 0 in
35 def C4_fastcorner9_not : T_LOGICAL_2OP<"!fastcorner9", 0b000, 0, 0>,
37 let Inst{20,13,7,4} = 0b1111;
40 def SDTHexagonFCONST32 : SDTypeProfile<1, 1, [
43 def HexagonFCONST32 : SDNode<"HexagonISD::FCONST32", SDTHexagonFCONST32>;
45 let isReMaterializable = 1, isMoveImm = 1 in
46 def FCONST32_nsdata : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
47 "$dst = CONST32(#$global)",
48 [(set (f32 IntRegs:$dst),
49 (HexagonFCONST32 tglobaladdr:$global))]>,
52 let isReMaterializable = 1, isMoveImm = 1 in
53 def CONST64_Float_Real : LDInst<(outs DoubleRegs:$dst), (ins f64imm:$src1),
54 "$dst = CONST64(#$src1)",
55 [(set DoubleRegs:$dst, fpimm:$src1)]>,
58 let isReMaterializable = 1, isMoveImm = 1 in
59 def CONST32_Float_Real : LDInst<(outs IntRegs:$dst), (ins f32imm:$src1),
60 "$dst = CONST32(#$src1)",
61 [(set IntRegs:$dst, fpimm:$src1)]>,
64 // Transfer immediate float.
65 // Only works with single precision fp value.
66 // For double precision, use CONST64_float_real, as 64bit transfer
67 // can only hold 40-bit values - 32 from const ext + 8 bit immediate.
68 // Make sure that complexity is more than the CONST32 pattern in
69 // HexagonInstrInfo.td patterns.
70 let isExtended = 1, opExtendable = 1, isMoveImm = 1, isReMaterializable = 1,
71 isPredicable = 1, AddedComplexity = 30, validSubTargets = HasV5SubT,
73 def TFRI_f : ALU32_ri<(outs IntRegs:$dst), (ins f32Ext:$src1),
75 [(set IntRegs:$dst, fpimm:$src1)]>,
78 let isExtended = 1, opExtendable = 2, isPredicated = 1,
79 hasSideEffects = 0, validSubTargets = HasV5SubT in
80 def TFRI_cPt_f : ALU32_ri<(outs IntRegs:$dst),
81 (ins PredRegs:$src1, f32Ext:$src2),
82 "if ($src1) $dst = #$src2",
86 let isExtended = 1, opExtendable = 2, isPredicated = 1, isPredicatedFalse = 1,
87 hasSideEffects = 0, validSubTargets = HasV5SubT in
88 def TFRI_cNotPt_f : ALU32_ri<(outs IntRegs:$dst),
89 (ins PredRegs:$src1, f32Ext:$src2),
90 "if (!$src1) $dst =#$src2",
94 def SDTHexagonI32I64: SDTypeProfile<1, 1, [SDTCisVT<0, i32>,
97 def HexagonPOPCOUNT: SDNode<"HexagonISD::POPCOUNT", SDTHexagonI32I64>;
99 let hasNewValue = 1, validSubTargets = HasV5SubT, isCodeGenOnly = 0 in
100 def S5_popcountp : ALU64_rr<(outs IntRegs:$Rd), (ins DoubleRegs:$Rss),
101 "$Rd = popcount($Rss)",
102 [(set I32:$Rd, (HexagonPOPCOUNT I64:$Rss))], "", S_2op_tc_2_SLOT23>,
109 let Inst{27-21} = 0b1000011;
110 let Inst{7-5} = 0b011;
112 let Inst{20-16} = Rss;
115 defm: Loadx_pat<load, f64, s11_3ExtPred, L2_loadrd_io>;
117 let isFP = 1, hasNewValue = 1, opNewValue = 0 in
118 class T_MInstFloat <string mnemonic, bits<3> MajOp, bits<3> MinOp>
119 : MInst<(outs IntRegs:$Rd),
120 (ins IntRegs:$Rs, IntRegs:$Rt),
121 "$Rd = "#mnemonic#"($Rs, $Rt)", [],
122 "" , M_tc_3or4x_SLOT23 > ,
130 let Inst{27-24} = 0b1011;
131 let Inst{23-21} = MajOp;
132 let Inst{20-16} = Rs;
135 let Inst{7-5} = MinOp;
139 let isCommutable = 1, isCodeGenOnly = 0 in {
140 def F2_sfadd : T_MInstFloat < "sfadd", 0b000, 0b000>;
141 def F2_sfmpy : T_MInstFloat < "sfmpy", 0b010, 0b000>;
144 let isCodeGenOnly = 0 in
145 def F2_sfsub : T_MInstFloat < "sfsub", 0b000, 0b001>;
147 let Itinerary = M_tc_3x_SLOT23, isCodeGenOnly = 0 in {
148 def F2_sfmax : T_MInstFloat < "sfmax", 0b100, 0b000>;
149 def F2_sfmin : T_MInstFloat < "sfmin", 0b100, 0b001>;
152 let isCodeGenOnly = 0 in {
153 def F2_sffixupn : T_MInstFloat < "sffixupn", 0b110, 0b000>;
154 def F2_sffixupd : T_MInstFloat < "sffixupd", 0b110, 0b001>;
157 // F2_sfrecipa: Reciprocal approximation for division.
158 let isPredicateLate = 1, isFP = 1,
159 hasSideEffects = 0, hasNewValue = 1, isCodeGenOnly = 0 in
160 def F2_sfrecipa: MInst <
161 (outs IntRegs:$Rd, PredRegs:$Pe),
162 (ins IntRegs:$Rs, IntRegs:$Rt),
163 "$Rd, $Pe = sfrecipa($Rs, $Rt)">,
171 let Inst{27-21} = 0b1011111;
172 let Inst{20-16} = Rs;
180 // F2_dfcmpeq: Floating point compare for equal.
181 let isCompare = 1, isFP = 1 in
182 class T_fcmp <string mnemonic, RegisterClass RC, bits<3> MinOp,
183 list<dag> pattern = [] >
184 : ALU64Inst <(outs PredRegs:$dst), (ins RC:$src1, RC:$src2),
185 "$dst = "#mnemonic#"($src1, $src2)", pattern,
186 "" , ALU64_tc_2early_SLOT23 > ,
194 let Inst{27-21} = 0b0010111;
195 let Inst{20-16} = src1;
196 let Inst{12-8} = src2;
197 let Inst{7-5} = MinOp;
201 class T_fcmp64 <string mnemonic, PatFrag OpNode, bits<3> MinOp>
202 : T_fcmp <mnemonic, DoubleRegs, MinOp,
203 [(set I1:$dst, (OpNode F64:$src1, F64:$src2))]> {
205 let Inst{27-21} = 0b0010111;
208 class T_fcmp32 <string mnemonic, PatFrag OpNode, bits<3> MinOp>
209 : T_fcmp <mnemonic, IntRegs, MinOp,
210 [(set I1:$dst, (OpNode F32:$src1, F32:$src2))]> {
212 let Inst{27-21} = 0b0111111;
215 let isCodeGenOnly = 0 in {
216 def F2_dfcmpeq : T_fcmp64<"dfcmp.eq", setoeq, 0b000>;
217 def F2_dfcmpgt : T_fcmp64<"dfcmp.gt", setogt, 0b001>;
218 def F2_dfcmpge : T_fcmp64<"dfcmp.ge", setoge, 0b010>;
219 def F2_dfcmpuo : T_fcmp64<"dfcmp.uo", setuo, 0b011>;
221 def F2_sfcmpge : T_fcmp32<"sfcmp.ge", setoge, 0b000>;
222 def F2_sfcmpuo : T_fcmp32<"sfcmp.uo", setuo, 0b001>;
223 def F2_sfcmpeq : T_fcmp32<"sfcmp.eq", setoeq, 0b011>;
224 def F2_sfcmpgt : T_fcmp32<"sfcmp.gt", setogt, 0b100>;
227 // F2 convert template classes:
229 class F2_RDD_RSS_CONVERT<string mnemonic, bits<3> MinOp,
230 SDNode Op, PatLeaf RCOut, PatLeaf RCIn,
232 : SInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss),
233 "$Rdd = "#mnemonic#"($Rss)"#chop,
234 [(set RCOut:$Rdd, (Op RCIn:$Rss))], "",
235 S_2op_tc_3or4x_SLOT23> {
241 let Inst{27-21} = 0b0000111;
242 let Inst{20-16} = Rss;
243 let Inst{7-5} = MinOp;
248 class F2_RDD_RS_CONVERT<string mnemonic, bits<3> MinOp,
249 SDNode Op, PatLeaf RCOut, PatLeaf RCIn,
251 : SInst <(outs DoubleRegs:$Rdd), (ins IntRegs:$Rs),
252 "$Rdd = "#mnemonic#"($Rs)"#chop,
253 [(set RCOut:$Rdd, (Op RCIn:$Rs))], "",
254 S_2op_tc_3or4x_SLOT23> {
260 let Inst{27-21} = 0b0100100;
261 let Inst{20-16} = Rs;
262 let Inst{7-5} = MinOp;
266 let isFP = 1, hasNewValue = 1 in
267 class F2_RD_RSS_CONVERT<string mnemonic, bits<3> MinOp,
268 SDNode Op, PatLeaf RCOut, PatLeaf RCIn,
270 : SInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss),
271 "$Rd = "#mnemonic#"($Rss)"#chop,
272 [(set RCOut:$Rd, (Op RCIn:$Rss))], "",
273 S_2op_tc_3or4x_SLOT23> {
279 let Inst{27-24} = 0b1000;
280 let Inst{23-21} = MinOp;
281 let Inst{20-16} = Rss;
282 let Inst{7-5} = 0b001;
286 let isFP = 1, hasNewValue = 1 in
287 class F2_RD_RS_CONVERT<string mnemonic, bits<3> MajOp, bits<3> MinOp,
288 SDNode Op, PatLeaf RCOut, PatLeaf RCIn,
290 : SInst <(outs IntRegs:$Rd), (ins IntRegs:$Rs),
291 "$Rd = "#mnemonic#"($Rs)"#chop,
292 [(set RCOut:$Rd, (Op RCIn:$Rs))], "",
293 S_2op_tc_3or4x_SLOT23> {
299 let Inst{27-24} = 0b1011;
300 let Inst{23-21} = MajOp;
301 let Inst{20-16} = Rs;
302 let Inst{7-5} = MinOp;
306 // Convert single precision to double precision and vice-versa.
307 let isCodeGenOnly = 0 in {
308 def F2_conv_sf2df : F2_RDD_RS_CONVERT <"convert_sf2df", 0b000,
311 def F2_conv_df2sf : F2_RD_RSS_CONVERT <"convert_df2sf", 0b000,
314 // Convert Integer to Floating Point.
315 def F2_conv_d2sf : F2_RD_RSS_CONVERT <"convert_d2sf", 0b010,
316 sint_to_fp, F32, I64>;
317 def F2_conv_ud2sf : F2_RD_RSS_CONVERT <"convert_ud2sf", 0b001,
318 uint_to_fp, F32, I64>;
319 def F2_conv_uw2sf : F2_RD_RS_CONVERT <"convert_uw2sf", 0b001, 0b000,
320 uint_to_fp, F32, I32>;
321 def F2_conv_w2sf : F2_RD_RS_CONVERT <"convert_w2sf", 0b010, 0b000,
322 sint_to_fp, F32, I32>;
323 def F2_conv_d2df : F2_RDD_RSS_CONVERT <"convert_d2df", 0b011,
324 sint_to_fp, F64, I64>;
325 def F2_conv_ud2df : F2_RDD_RSS_CONVERT <"convert_ud2df", 0b010,
326 uint_to_fp, F64, I64>;
327 def F2_conv_uw2df : F2_RDD_RS_CONVERT <"convert_uw2df", 0b001,
328 uint_to_fp, F64, I32>;
329 def F2_conv_w2df : F2_RDD_RS_CONVERT <"convert_w2df", 0b010,
330 sint_to_fp, F64, I32>;
332 // Convert Floating Point to Integer - default.
333 def F2_conv_df2uw_chop : F2_RD_RSS_CONVERT <"convert_df2uw", 0b101,
334 fp_to_uint, I32, F64, ":chop">;
335 def F2_conv_df2w_chop : F2_RD_RSS_CONVERT <"convert_df2w", 0b111,
336 fp_to_sint, I32, F64, ":chop">;
337 def F2_conv_sf2uw_chop : F2_RD_RS_CONVERT <"convert_sf2uw", 0b011, 0b001,
338 fp_to_uint, I32, F32, ":chop">;
339 def F2_conv_sf2w_chop : F2_RD_RS_CONVERT <"convert_sf2w", 0b100, 0b001,
340 fp_to_sint, I32, F32, ":chop">;
341 def F2_conv_df2d_chop : F2_RDD_RSS_CONVERT <"convert_df2d", 0b110,
342 fp_to_sint, I64, F64, ":chop">;
343 def F2_conv_df2ud_chop : F2_RDD_RSS_CONVERT <"convert_df2ud", 0b111,
344 fp_to_uint, I64, F64, ":chop">;
345 def F2_conv_sf2d_chop : F2_RDD_RS_CONVERT <"convert_sf2d", 0b110,
346 fp_to_sint, I64, F32, ":chop">;
347 def F2_conv_sf2ud_chop : F2_RDD_RS_CONVERT <"convert_sf2ud", 0b101,
348 fp_to_uint, I64, F32, ":chop">;
350 // Convert Floating Point to Integer: non-chopped.
351 let AddedComplexity = 20, Predicates = [HasV5T, IEEERndNearV5T] in {
352 def F2_conv_df2d : F2_RDD_RSS_CONVERT <"convert_df2d", 0b000,
353 fp_to_sint, I64, F64>;
354 def F2_conv_df2ud : F2_RDD_RSS_CONVERT <"convert_df2ud", 0b001,
355 fp_to_uint, I64, F64>;
356 def F2_conv_sf2ud : F2_RDD_RS_CONVERT <"convert_sf2ud", 0b011,
357 fp_to_uint, I64, F32>;
358 def F2_conv_sf2d : F2_RDD_RS_CONVERT <"convert_sf2d", 0b100,
359 fp_to_sint, I64, F32>;
360 def F2_conv_df2uw : F2_RD_RSS_CONVERT <"convert_df2uw", 0b011,
361 fp_to_uint, I32, F64>;
362 def F2_conv_df2w : F2_RD_RSS_CONVERT <"convert_df2w", 0b100,
363 fp_to_sint, I32, F64>;
364 def F2_conv_sf2uw : F2_RD_RS_CONVERT <"convert_sf2uw", 0b011, 0b000,
365 fp_to_uint, I32, F32>;
366 def F2_conv_sf2w : F2_RD_RS_CONVERT <"convert_sf2w", 0b100, 0b000,
367 fp_to_sint, I32, F32>;
372 let isFP = 1, hasNewValue = 1, isCodeGenOnly = 0 in
373 def F2_sffixupr: SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs),
374 "$Rd = sffixupr($Rs)",
375 [], "" , S_2op_tc_3or4x_SLOT23>, Requires<[HasV5T]> {
381 let Inst{27-21} = 0b1011101;
382 let Inst{20-16} = Rs;
383 let Inst{7-5} = 0b000;
387 // F2_sffma: Floating-point fused multiply add.
388 let isFP = 1, hasNewValue = 1 in
389 class T_sfmpy_acc <bit isSub, bit isLib>
390 : MInst<(outs IntRegs:$Rx),
391 (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
392 "$Rx "#!if(isSub, "-=","+=")#" sfmpy($Rs, $Rt)"#!if(isLib, ":lib",""),
393 [], "$dst2 = $Rx" , M_tc_3_SLOT23 > ,
401 let Inst{27-21} = 0b1111000;
402 let Inst{20-16} = Rs;
411 let isCodeGenOnly = 0 in {
412 def F2_sffma: T_sfmpy_acc <0, 0>;
413 def F2_sffms: T_sfmpy_acc <1, 0>;
414 def F2_sffma_lib: T_sfmpy_acc <0, 1>;
415 def F2_sffms_lib: T_sfmpy_acc <1, 1>;
418 // Floating-point fused multiply add w/ additional scaling (2**pu).
419 let isFP = 1, hasNewValue = 1, isCodeGenOnly = 0 in
420 def F2_sffma_sc: MInst <
422 (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt, PredRegs:$Pu),
423 "$Rx += sfmpy($Rs, $Rt, $Pu):scale" ,
424 [], "$dst2 = $Rx" , M_tc_3_SLOT23 > ,
433 let Inst{27-21} = 0b1111011;
434 let Inst{20-16} = Rs;
442 // Classify floating-point value
443 let isFP = 1, isCodeGenOnly = 0 in
444 def F2_sfclass : T_TEST_BIT_IMM<"sfclass", 0b111>;
446 let isFP = 1, isCodeGenOnly = 0 in
447 def F2_dfclass: ALU64Inst<(outs PredRegs:$Pd), (ins DoubleRegs:$Rss, u5Imm:$u5),
448 "$Pd = dfclass($Rss, #$u5)",
449 [], "" , ALU64_tc_2early_SLOT23 > , Requires<[HasV5T]> {
455 let Inst{27-21} = 0b1100100;
456 let Inst{20-16} = Rss;
457 let Inst{12-10} = 0b000;
459 let Inst{4-3} = 0b10;
463 // Instructions to create floating point constant
464 let hasNewValue = 1, opNewValue = 0 in
465 class T_fimm <string mnemonic, RegisterClass RC, bits<4> RegType, bit isNeg>
466 : ALU64Inst<(outs RC:$dst), (ins u10Imm:$src),
467 "$dst = "#mnemonic#"(#$src)"#!if(isNeg, ":neg", ":pos"),
468 [], "", ALU64_tc_3x_SLOT23>, Requires<[HasV5T]> {
473 let Inst{27-24} = RegType;
475 let Inst{22} = isNeg;
476 let Inst{21} = src{9};
477 let Inst{13-5} = src{8-0};
481 let isCodeGenOnly = 0 in {
482 def F2_sfimm_p : T_fimm <"sfmake", IntRegs, 0b0110, 0>;
483 def F2_sfimm_n : T_fimm <"sfmake", IntRegs, 0b0110, 1>;
484 def F2_dfimm_p : T_fimm <"dfmake", DoubleRegs, 0b1001, 0>;
485 def F2_dfimm_n : T_fimm <"dfmake", DoubleRegs, 0b1001, 1>;
488 let AddedComplexity = 20 in
489 def LDrid_indexed_f : LDInst<(outs DoubleRegs:$dst),
490 (ins IntRegs:$src1, s11_3Imm:$offset),
491 "$dst = memd($src1+#$offset)",
492 [(set DoubleRegs:$dst, (f64 (load (add IntRegs:$src1,
493 s11_3ImmPred:$offset))))]>,
496 def LDriw_f : LDInst<(outs IntRegs:$dst),
497 (ins MEMri:$addr), "$dst = memw($addr)",
498 [(set IntRegs:$dst, (f32 (load ADDRriS11_2:$addr)))]>,
502 let AddedComplexity = 20 in
503 def LDriw_indexed_f : LDInst<(outs IntRegs:$dst),
504 (ins IntRegs:$src1, s11_2Imm:$offset),
505 "$dst = memw($src1+#$offset)",
506 [(set IntRegs:$dst, (f32 (load (add IntRegs:$src1,
507 s11_2ImmPred:$offset))))]>,
511 def STriw_f : STInst<(outs),
512 (ins MEMri:$addr, IntRegs:$src1),
513 "memw($addr) = $src1",
514 [(store (f32 IntRegs:$src1), ADDRriS11_2:$addr)]>,
517 let AddedComplexity = 10 in
518 def STriw_indexed_f : STInst<(outs),
519 (ins IntRegs:$src1, s11_2Imm:$src2, IntRegs:$src3),
520 "memw($src1+#$src2) = $src3",
521 [(store (f32 IntRegs:$src3),
522 (add IntRegs:$src1, s11_2ImmPred:$src2))]>,
525 def STrid_f : STInst<(outs),
526 (ins MEMri:$addr, DoubleRegs:$src1),
527 "memd($addr) = $src1",
528 [(store (f64 DoubleRegs:$src1), ADDRriS11_2:$addr)]>,
531 // Indexed store double word.
532 let AddedComplexity = 10 in
533 def STrid_indexed_f : STInst<(outs),
534 (ins IntRegs:$src1, s11_3Imm:$src2, DoubleRegs:$src3),
535 "memd($src1+#$src2) = $src3",
536 [(store (f64 DoubleRegs:$src3),
537 (add IntRegs:$src1, s11_3ImmPred:$src2))]>,
542 let isCommutable = 1 in
543 def fADD_rr : ALU64_rr<(outs IntRegs:$dst),
544 (ins IntRegs:$src1, IntRegs:$src2),
545 "$dst = sfadd($src1, $src2)",
546 [(set IntRegs:$dst, (fadd IntRegs:$src1, IntRegs:$src2))]>,
549 let isCommutable = 1 in
550 def fADD64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
552 "$dst = dfadd($src1, $src2)",
553 [(set DoubleRegs:$dst, (fadd DoubleRegs:$src1,
554 DoubleRegs:$src2))]>,
557 def fSUB_rr : ALU64_rr<(outs IntRegs:$dst),
558 (ins IntRegs:$src1, IntRegs:$src2),
559 "$dst = sfsub($src1, $src2)",
560 [(set IntRegs:$dst, (fsub IntRegs:$src1, IntRegs:$src2))]>,
563 def fSUB64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
565 "$dst = dfsub($src1, $src2)",
566 [(set DoubleRegs:$dst, (fsub DoubleRegs:$src1,
567 DoubleRegs:$src2))]>,
570 let isCommutable = 1 in
571 def fMUL_rr : ALU64_rr<(outs IntRegs:$dst),
572 (ins IntRegs:$src1, IntRegs:$src2),
573 "$dst = sfmpy($src1, $src2)",
574 [(set IntRegs:$dst, (fmul IntRegs:$src1, IntRegs:$src2))]>,
577 let isCommutable = 1 in
578 def fMUL64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
580 "$dst = dfmpy($src1, $src2)",
581 [(set DoubleRegs:$dst, (fmul DoubleRegs:$src1,
582 DoubleRegs:$src2))]>,
586 let isCompare = 1 in {
587 multiclass FCMP64_rr<string OpcStr, PatFrag OpNode> {
588 def _rr : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$b, DoubleRegs:$c),
589 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
591 (OpNode (f64 DoubleRegs:$b), (f64 DoubleRegs:$c)))]>,
595 multiclass FCMP32_rr<string OpcStr, PatFrag OpNode> {
596 def _rr : ALU64_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
597 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
599 (OpNode (f32 IntRegs:$b), (f32 IntRegs:$c)))]>,
604 defm FCMPOEQ64 : FCMP64_rr<"dfcmp.eq", setoeq>;
605 defm FCMPUEQ64 : FCMP64_rr<"dfcmp.eq", setueq>;
606 defm FCMPOGT64 : FCMP64_rr<"dfcmp.gt", setogt>;
607 defm FCMPUGT64 : FCMP64_rr<"dfcmp.gt", setugt>;
608 defm FCMPOGE64 : FCMP64_rr<"dfcmp.ge", setoge>;
609 defm FCMPUGE64 : FCMP64_rr<"dfcmp.ge", setuge>;
611 defm FCMPOEQ32 : FCMP32_rr<"sfcmp.eq", setoeq>;
612 defm FCMPUEQ32 : FCMP32_rr<"sfcmp.eq", setueq>;
613 defm FCMPOGT32 : FCMP32_rr<"sfcmp.gt", setogt>;
614 defm FCMPUGT32 : FCMP32_rr<"sfcmp.gt", setugt>;
615 defm FCMPOGE32 : FCMP32_rr<"sfcmp.ge", setoge>;
616 defm FCMPUGE32 : FCMP32_rr<"sfcmp.ge", setuge>;
619 def : Pat <(i1 (setolt (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
620 (i1 (FCMPOGT32_rr IntRegs:$src2, IntRegs:$src1))>,
623 def : Pat <(i1 (setolt (f32 IntRegs:$src1), (fpimm:$src2))),
624 (i1 (FCMPOGT32_rr (f32 (TFRI_f fpimm:$src2)), (f32 IntRegs:$src1)))>,
627 def : Pat <(i1 (setolt (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
628 (i1 (FCMPOGT64_rr DoubleRegs:$src2, DoubleRegs:$src1))>,
631 def : Pat <(i1 (setolt (f64 DoubleRegs:$src1), (fpimm:$src2))),
632 (i1 (FCMPOGT64_rr (f64 (CONST64_Float_Real fpimm:$src2)),
633 (f64 DoubleRegs:$src1)))>,
637 def : Pat <(i1 (setugt (f64 DoubleRegs:$src1), (fpimm:$src2))),
638 (i1 (FCMPUGT64_rr (f64 DoubleRegs:$src1),
639 (f64 (CONST64_Float_Real fpimm:$src2))))>,
642 def : Pat <(i1 (setugt (f32 IntRegs:$src1), (fpimm:$src2))),
643 (i1 (FCMPUGT32_rr (f32 IntRegs:$src1), (f32 (TFRI_f fpimm:$src2))))>,
647 def : Pat <(i1 (setult (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
648 (i1 (FCMPUGT32_rr IntRegs:$src2, IntRegs:$src1))>,
651 def : Pat <(i1 (setult (f32 IntRegs:$src1), (fpimm:$src2))),
652 (i1 (FCMPUGT32_rr (f32 (TFRI_f fpimm:$src2)), (f32 IntRegs:$src1)))>,
655 def : Pat <(i1 (setult (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
656 (i1 (FCMPUGT64_rr DoubleRegs:$src2, DoubleRegs:$src1))>,
659 def : Pat <(i1 (setult (f64 DoubleRegs:$src1), (fpimm:$src2))),
660 (i1 (FCMPUGT64_rr (f64 (CONST64_Float_Real fpimm:$src2)),
661 (f64 DoubleRegs:$src1)))>,
665 // rs <= rt -> rt >= rs.
666 def : Pat<(i1 (setole (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
667 (i1 (FCMPOGE32_rr IntRegs:$src2, IntRegs:$src1))>,
670 def : Pat<(i1 (setole (f32 IntRegs:$src1), (fpimm:$src2))),
671 (i1 (FCMPOGE32_rr (f32 (TFRI_f fpimm:$src2)), IntRegs:$src1))>,
675 // Rss <= Rtt -> Rtt >= Rss.
676 def : Pat<(i1 (setole (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
677 (i1 (FCMPOGE64_rr DoubleRegs:$src2, DoubleRegs:$src1))>,
680 def : Pat<(i1 (setole (f64 DoubleRegs:$src1), (fpimm:$src2))),
681 (i1 (FCMPOGE64_rr (f64 (CONST64_Float_Real fpimm:$src2)),
685 // rs <= rt -> rt >= rs.
686 def : Pat<(i1 (setule (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
687 (i1 (FCMPUGE32_rr IntRegs:$src2, IntRegs:$src1))>,
690 def : Pat<(i1 (setule (f32 IntRegs:$src1), (fpimm:$src2))),
691 (i1 (FCMPUGE32_rr (f32 (TFRI_f fpimm:$src2)), IntRegs:$src1))>,
694 // Rss <= Rtt -> Rtt >= Rss.
695 def : Pat<(i1 (setule (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
696 (i1 (FCMPUGE64_rr DoubleRegs:$src2, DoubleRegs:$src1))>,
699 def : Pat<(i1 (setule (f64 DoubleRegs:$src1), (fpimm:$src2))),
700 (i1 (FCMPUGE64_rr (f64 (CONST64_Float_Real fpimm:$src2)),
705 def : Pat<(i1 (setone (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
706 (i1 (C2_not (FCMPOEQ32_rr IntRegs:$src1, IntRegs:$src2)))>,
709 def : Pat<(i1 (setone (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
710 (i1 (C2_not (FCMPOEQ64_rr DoubleRegs:$src1, DoubleRegs:$src2)))>,
713 def : Pat<(i1 (setune (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
714 (i1 (C2_not (FCMPUEQ32_rr IntRegs:$src1, IntRegs:$src2)))>,
717 def : Pat<(i1 (setune (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
718 (i1 (C2_not (FCMPUEQ64_rr DoubleRegs:$src1, DoubleRegs:$src2)))>,
721 def : Pat<(i1 (setone (f32 IntRegs:$src1), (fpimm:$src2))),
722 (i1 (C2_not (FCMPOEQ32_rr IntRegs:$src1, (f32 (TFRI_f fpimm:$src2)))))>,
725 def : Pat<(i1 (setone (f64 DoubleRegs:$src1), (fpimm:$src2))),
726 (i1 (C2_not (FCMPOEQ64_rr DoubleRegs:$src1,
727 (f64 (CONST64_Float_Real fpimm:$src2)))))>,
730 def : Pat<(i1 (setune (f32 IntRegs:$src1), (fpimm:$src2))),
731 (i1 (C2_not (FCMPUEQ32_rr IntRegs:$src1, (f32 (TFRI_f fpimm:$src2)))))>,
734 def : Pat<(i1 (setune (f64 DoubleRegs:$src1), (fpimm:$src2))),
735 (i1 (C2_not (FCMPUEQ64_rr DoubleRegs:$src1,
736 (f64 (CONST64_Float_Real fpimm:$src2)))))>,
739 // Convert Integer to Floating Point.
740 def CONVERT_d2sf : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
741 "$dst = convert_d2sf($src)",
742 [(set (f32 IntRegs:$dst), (sint_to_fp (i64 DoubleRegs:$src)))]>,
745 def CONVERT_ud2sf : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
746 "$dst = convert_ud2sf($src)",
747 [(set (f32 IntRegs:$dst), (uint_to_fp (i64 DoubleRegs:$src)))]>,
750 def CONVERT_uw2sf : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
751 "$dst = convert_uw2sf($src)",
752 [(set (f32 IntRegs:$dst), (uint_to_fp (i32 IntRegs:$src)))]>,
755 def CONVERT_w2sf : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
756 "$dst = convert_w2sf($src)",
757 [(set (f32 IntRegs:$dst), (sint_to_fp (i32 IntRegs:$src)))]>,
760 def CONVERT_d2df : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
761 "$dst = convert_d2df($src)",
762 [(set (f64 DoubleRegs:$dst), (sint_to_fp (i64 DoubleRegs:$src)))]>,
765 def CONVERT_ud2df : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
766 "$dst = convert_ud2df($src)",
767 [(set (f64 DoubleRegs:$dst), (uint_to_fp (i64 DoubleRegs:$src)))]>,
770 def CONVERT_uw2df : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
771 "$dst = convert_uw2df($src)",
772 [(set (f64 DoubleRegs:$dst), (uint_to_fp (i32 IntRegs:$src)))]>,
775 def CONVERT_w2df : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
776 "$dst = convert_w2df($src)",
777 [(set (f64 DoubleRegs:$dst), (sint_to_fp (i32 IntRegs:$src)))]>,
780 // Convert Floating Point to Integer - default.
781 def CONVERT_df2uw : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
782 "$dst = convert_df2uw($src):chop",
783 [(set (i32 IntRegs:$dst), (fp_to_uint (f64 DoubleRegs:$src)))]>,
786 def CONVERT_df2w : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
787 "$dst = convert_df2w($src):chop",
788 [(set (i32 IntRegs:$dst), (fp_to_sint (f64 DoubleRegs:$src)))]>,
791 def CONVERT_sf2uw : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
792 "$dst = convert_sf2uw($src):chop",
793 [(set (i32 IntRegs:$dst), (fp_to_uint (f32 IntRegs:$src)))]>,
796 def CONVERT_sf2w : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
797 "$dst = convert_sf2w($src):chop",
798 [(set (i32 IntRegs:$dst), (fp_to_sint (f32 IntRegs:$src)))]>,
801 def CONVERT_df2d : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
802 "$dst = convert_df2d($src):chop",
803 [(set (i64 DoubleRegs:$dst), (fp_to_sint (f64 DoubleRegs:$src)))]>,
806 def CONVERT_df2ud : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
807 "$dst = convert_df2ud($src):chop",
808 [(set (i64 DoubleRegs:$dst), (fp_to_uint (f64 DoubleRegs:$src)))]>,
811 def CONVERT_sf2d : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
812 "$dst = convert_sf2d($src):chop",
813 [(set (i64 DoubleRegs:$dst), (fp_to_sint (f32 IntRegs:$src)))]>,
816 def CONVERT_sf2ud : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
817 "$dst = convert_sf2ud($src):chop",
818 [(set (i64 DoubleRegs:$dst), (fp_to_uint (f32 IntRegs:$src)))]>,
821 // Convert Floating Point to Integer: non-chopped.
822 let AddedComplexity = 20 in
823 def CONVERT_df2uw_nchop : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
824 "$dst = convert_df2uw($src)",
825 [(set (i32 IntRegs:$dst), (fp_to_uint (f64 DoubleRegs:$src)))]>,
826 Requires<[HasV5T, IEEERndNearV5T]>;
828 let AddedComplexity = 20 in
829 def CONVERT_df2w_nchop : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
830 "$dst = convert_df2w($src)",
831 [(set (i32 IntRegs:$dst), (fp_to_sint (f64 DoubleRegs:$src)))]>,
832 Requires<[HasV5T, IEEERndNearV5T]>;
834 let AddedComplexity = 20 in
835 def CONVERT_sf2uw_nchop : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
836 "$dst = convert_sf2uw($src)",
837 [(set (i32 IntRegs:$dst), (fp_to_uint (f32 IntRegs:$src)))]>,
838 Requires<[HasV5T, IEEERndNearV5T]>;
840 let AddedComplexity = 20 in
841 def CONVERT_sf2w_nchop : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
842 "$dst = convert_sf2w($src)",
843 [(set (i32 IntRegs:$dst), (fp_to_sint (f32 IntRegs:$src)))]>,
844 Requires<[HasV5T, IEEERndNearV5T]>;
846 let AddedComplexity = 20 in
847 def CONVERT_df2d_nchop : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
848 "$dst = convert_df2d($src)",
849 [(set (i64 DoubleRegs:$dst), (fp_to_sint (f64 DoubleRegs:$src)))]>,
850 Requires<[HasV5T, IEEERndNearV5T]>;
852 let AddedComplexity = 20 in
853 def CONVERT_df2ud_nchop : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
854 "$dst = convert_df2ud($src)",
855 [(set (i64 DoubleRegs:$dst), (fp_to_uint (f64 DoubleRegs:$src)))]>,
856 Requires<[HasV5T, IEEERndNearV5T]>;
858 let AddedComplexity = 20 in
859 def CONVERT_sf2d_nchop : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
860 "$dst = convert_sf2d($src)",
861 [(set (i64 DoubleRegs:$dst), (fp_to_sint (f32 IntRegs:$src)))]>,
862 Requires<[HasV5T, IEEERndNearV5T]>;
864 let AddedComplexity = 20 in
865 def CONVERT_sf2ud_nchop : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
866 "$dst = convert_sf2ud($src)",
867 [(set (i64 DoubleRegs:$dst), (fp_to_uint (f32 IntRegs:$src)))]>,
868 Requires<[HasV5T, IEEERndNearV5T]>;
872 // Bitcast is different than [fp|sint|uint]_to_[sint|uint|fp].
873 def : Pat <(i32 (bitconvert (f32 IntRegs:$src))),
874 (i32 (A2_tfr IntRegs:$src))>,
877 def : Pat <(f32 (bitconvert (i32 IntRegs:$src))),
878 (f32 (A2_tfr IntRegs:$src))>,
881 def : Pat <(i64 (bitconvert (f64 DoubleRegs:$src))),
882 (i64 (A2_tfrp DoubleRegs:$src))>,
885 def : Pat <(f64 (bitconvert (i64 DoubleRegs:$src))),
886 (f64 (A2_tfrp DoubleRegs:$src))>,
889 def FMADD_sp : ALU64_acc<(outs IntRegs:$dst),
890 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
891 "$dst += sfmpy($src2, $src3)",
892 [(set (f32 IntRegs:$dst),
893 (fma IntRegs:$src2, IntRegs:$src3, IntRegs:$src1))],
898 // Floating point max/min.
900 let AddedComplexity = 100 in
901 def FMAX_sp : ALU64_rr<(outs IntRegs:$dst),
902 (ins IntRegs:$src1, IntRegs:$src2),
903 "$dst = sfmax($src1, $src2)",
904 [(set IntRegs:$dst, (f32 (select (i1 (setolt IntRegs:$src2,
910 let AddedComplexity = 100 in
911 def FMIN_sp : ALU64_rr<(outs IntRegs:$dst),
912 (ins IntRegs:$src1, IntRegs:$src2),
913 "$dst = sfmin($src1, $src2)",
914 [(set IntRegs:$dst, (f32 (select (i1 (setogt IntRegs:$src2,
920 // Pseudo instruction to encode a set of conditional transfers.
921 // This instruction is used instead of a mux and trades-off codesize
922 // for performance. We conduct this transformation optimistically in
923 // the hope that these instructions get promoted to dot-new transfers.
924 let AddedComplexity = 100, isPredicated = 1 in
925 def TFR_condset_rr_f : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
928 "Error; should not emit",
929 [(set IntRegs:$dst, (f32 (select PredRegs:$src1,
934 let AddedComplexity = 100, isPredicated = 1 in
935 def TFR_condset_rr64_f : ALU32_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
938 "Error; should not emit",
939 [(set DoubleRegs:$dst, (f64 (select PredRegs:$src1,
941 DoubleRegs:$src3)))]>,
946 let AddedComplexity = 100, isPredicated = 1 in
947 def TFR_condset_ri_f : ALU32_rr<(outs IntRegs:$dst),
948 (ins PredRegs:$src1, IntRegs:$src2, f32imm:$src3),
949 "Error; should not emit",
951 (f32 (select PredRegs:$src1, IntRegs:$src2, fpimm:$src3)))]>,
954 let AddedComplexity = 100, isPredicated = 1 in
955 def TFR_condset_ir_f : ALU32_rr<(outs IntRegs:$dst),
956 (ins PredRegs:$src1, f32imm:$src2, IntRegs:$src3),
957 "Error; should not emit",
959 (f32 (select PredRegs:$src1, fpimm:$src2, IntRegs:$src3)))]>,
962 let AddedComplexity = 100, isPredicated = 1 in
963 def TFR_condset_ii_f : ALU32_rr<(outs IntRegs:$dst),
964 (ins PredRegs:$src1, f32imm:$src2, f32imm:$src3),
965 "Error; should not emit",
966 [(set IntRegs:$dst, (f32 (select PredRegs:$src1,
972 def : Pat <(select (i1 (setult (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
974 (f32 IntRegs:$src4)),
975 (TFR_condset_rr_f (FCMPUGT32_rr IntRegs:$src2, IntRegs:$src1), IntRegs:$src4,
976 IntRegs:$src3)>, Requires<[HasV5T]>;
978 def : Pat <(select (i1 (setult (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
979 (f64 DoubleRegs:$src3),
980 (f64 DoubleRegs:$src4)),
981 (TFR_condset_rr64_f (FCMPUGT64_rr DoubleRegs:$src2, DoubleRegs:$src1),
982 DoubleRegs:$src4, DoubleRegs:$src3)>, Requires<[HasV5T]>;
984 // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
985 def : Pat <(select (not PredRegs:$src1), fpimm:$src2, fpimm:$src3),
986 (TFR_condset_ii_f PredRegs:$src1, fpimm:$src3, fpimm:$src2)>;
988 // Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
989 // => r0 = TFR_condset_ri(p0, r1, #i)
990 def : Pat <(select (not PredRegs:$src1), fpimm:$src2, IntRegs:$src3),
991 (TFR_condset_ri_f PredRegs:$src1, IntRegs:$src3, fpimm:$src2)>;
993 // Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
994 // => r0 = TFR_condset_ir(p0, #i, r1)
995 def : Pat <(select (not PredRegs:$src1), IntRegs:$src2, fpimm:$src3),
996 (TFR_condset_ir_f PredRegs:$src1, fpimm:$src3, IntRegs:$src2)>;
998 def : Pat <(i32 (fp_to_sint (f64 DoubleRegs:$src1))),
999 (i32 (EXTRACT_SUBREG (i64 (CONVERT_df2d (f64 DoubleRegs:$src1))), subreg_loreg))>,
1002 def : Pat <(fabs (f32 IntRegs:$src1)),
1003 (S2_clrbit_i (f32 IntRegs:$src1), 31)>,
1006 def : Pat <(fneg (f32 IntRegs:$src1)),
1007 (S2_togglebit_i (f32 IntRegs:$src1), 31)>,
1011 def : Pat <(fabs (f64 DoubleRegs:$src1)),
1012 (S2_clrbit_i (f32 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_hireg)), 31)>,
1015 def : Pat <(fabs (f64 DoubleRegs:$src1)),
1016 (S2_clrbit_i (f32 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_hireg)), 31)>,