1 //=- HexagonInstrInfoV5.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V5 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
18 let isCodeGenOnly = 0 in
19 def S2_asr_i_p_rnd : S_2OpInstImm<"asr", 0b110, 0b111, u6Imm,
21 (sra (i64 (add (i64 (sra I64:$src1, u6ImmPred:$src2)), 1)),
25 let Inst{13-8} = src2;
28 let isCodeGenOnly = 0 in
29 def C4_fastcorner9 : T_LOGICAL_2OP<"fastcorner9", 0b000, 0, 0>,
31 let Inst{13,7,4} = 0b111;
34 let isCodeGenOnly = 0 in
35 def C4_fastcorner9_not : T_LOGICAL_2OP<"!fastcorner9", 0b000, 0, 0>,
37 let Inst{20,13,7,4} = 0b1111;
40 def SDTHexagonFCONST32 : SDTypeProfile<1, 1, [
43 def HexagonFCONST32 : SDNode<"HexagonISD::FCONST32", SDTHexagonFCONST32>;
45 let isReMaterializable = 1, isMoveImm = 1 in
46 def FCONST32_nsdata : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
47 "$dst = CONST32(#$global)",
48 [(set (f32 IntRegs:$dst),
49 (HexagonFCONST32 tglobaladdr:$global))]>,
52 let isReMaterializable = 1, isMoveImm = 1 in
53 def CONST64_Float_Real : LDInst<(outs DoubleRegs:$dst), (ins f64imm:$src1),
54 "$dst = CONST64(#$src1)",
55 [(set DoubleRegs:$dst, fpimm:$src1)]>,
58 let isReMaterializable = 1, isMoveImm = 1 in
59 def CONST32_Float_Real : LDInst<(outs IntRegs:$dst), (ins f32imm:$src1),
60 "$dst = CONST32(#$src1)",
61 [(set IntRegs:$dst, fpimm:$src1)]>,
64 // Transfer immediate float.
65 // Only works with single precision fp value.
66 // For double precision, use CONST64_float_real, as 64bit transfer
67 // can only hold 40-bit values - 32 from const ext + 8 bit immediate.
68 // Make sure that complexity is more than the CONST32 pattern in
69 // HexagonInstrInfo.td patterns.
70 let isExtended = 1, opExtendable = 1, isMoveImm = 1, isReMaterializable = 1,
71 isPredicable = 1, AddedComplexity = 30, validSubTargets = HasV5SubT,
73 def TFRI_f : ALU32_ri<(outs IntRegs:$dst), (ins f32Ext:$src1),
75 [(set IntRegs:$dst, fpimm:$src1)]>,
78 let isExtended = 1, opExtendable = 2, isPredicated = 1,
79 hasSideEffects = 0, validSubTargets = HasV5SubT in
80 def TFRI_cPt_f : ALU32_ri<(outs IntRegs:$dst),
81 (ins PredRegs:$src1, f32Ext:$src2),
82 "if ($src1) $dst = #$src2",
86 let isExtended = 1, opExtendable = 2, isPredicated = 1, isPredicatedFalse = 1,
87 hasSideEffects = 0, validSubTargets = HasV5SubT in
88 def TFRI_cNotPt_f : ALU32_ri<(outs IntRegs:$dst),
89 (ins PredRegs:$src1, f32Ext:$src2),
90 "if (!$src1) $dst =#$src2",
94 def SDTHexagonI32I64: SDTypeProfile<1, 1, [SDTCisVT<0, i32>,
97 def HexagonPOPCOUNT: SDNode<"HexagonISD::POPCOUNT", SDTHexagonI32I64>;
99 let hasNewValue = 1, validSubTargets = HasV5SubT, isCodeGenOnly = 0 in
100 def S5_popcountp : ALU64_rr<(outs IntRegs:$Rd), (ins DoubleRegs:$Rss),
101 "$Rd = popcount($Rss)",
102 [(set I32:$Rd, (HexagonPOPCOUNT I64:$Rss))], "", S_2op_tc_2_SLOT23>,
109 let Inst{27-21} = 0b1000011;
110 let Inst{7-5} = 0b011;
112 let Inst{20-16} = Rss;
115 defm: Loadx_pat<load, f32, s11_2ExtPred, L2_loadri_io>;
116 defm: Loadx_pat<load, f64, s11_3ExtPred, L2_loadrd_io>;
118 defm: Storex_pat<store, F32, s11_2ExtPred, S2_storeri_io>;
119 defm: Storex_pat<store, F64, s11_3ExtPred, S2_storerd_io>;
121 let isFP = 1, hasNewValue = 1, opNewValue = 0 in
122 class T_MInstFloat <string mnemonic, bits<3> MajOp, bits<3> MinOp>
123 : MInst<(outs IntRegs:$Rd),
124 (ins IntRegs:$Rs, IntRegs:$Rt),
125 "$Rd = "#mnemonic#"($Rs, $Rt)", [],
126 "" , M_tc_3or4x_SLOT23 > ,
134 let Inst{27-24} = 0b1011;
135 let Inst{23-21} = MajOp;
136 let Inst{20-16} = Rs;
139 let Inst{7-5} = MinOp;
143 let isCommutable = 1, isCodeGenOnly = 0 in {
144 def F2_sfadd : T_MInstFloat < "sfadd", 0b000, 0b000>;
145 def F2_sfmpy : T_MInstFloat < "sfmpy", 0b010, 0b000>;
148 let isCodeGenOnly = 0 in
149 def F2_sfsub : T_MInstFloat < "sfsub", 0b000, 0b001>;
151 def: Pat<(f32 (fadd F32:$src1, F32:$src2)),
152 (F2_sfadd F32:$src1, F32:$src2)>;
154 def: Pat<(f32 (fsub F32:$src1, F32:$src2)),
155 (F2_sfsub F32:$src1, F32:$src2)>;
157 let Itinerary = M_tc_3x_SLOT23, isCodeGenOnly = 0 in {
158 def F2_sfmax : T_MInstFloat < "sfmax", 0b100, 0b000>;
159 def F2_sfmin : T_MInstFloat < "sfmin", 0b100, 0b001>;
162 let isCodeGenOnly = 0 in {
163 def F2_sffixupn : T_MInstFloat < "sffixupn", 0b110, 0b000>;
164 def F2_sffixupd : T_MInstFloat < "sffixupd", 0b110, 0b001>;
167 // F2_sfrecipa: Reciprocal approximation for division.
168 let isPredicateLate = 1, isFP = 1,
169 hasSideEffects = 0, hasNewValue = 1, isCodeGenOnly = 0 in
170 def F2_sfrecipa: MInst <
171 (outs IntRegs:$Rd, PredRegs:$Pe),
172 (ins IntRegs:$Rs, IntRegs:$Rt),
173 "$Rd, $Pe = sfrecipa($Rs, $Rt)">,
181 let Inst{27-21} = 0b1011111;
182 let Inst{20-16} = Rs;
190 // F2_dfcmpeq: Floating point compare for equal.
191 let isCompare = 1, isFP = 1 in
192 class T_fcmp <string mnemonic, RegisterClass RC, bits<3> MinOp,
193 list<dag> pattern = [] >
194 : ALU64Inst <(outs PredRegs:$dst), (ins RC:$src1, RC:$src2),
195 "$dst = "#mnemonic#"($src1, $src2)", pattern,
196 "" , ALU64_tc_2early_SLOT23 > ,
204 let Inst{27-21} = 0b0010111;
205 let Inst{20-16} = src1;
206 let Inst{12-8} = src2;
207 let Inst{7-5} = MinOp;
211 class T_fcmp64 <string mnemonic, PatFrag OpNode, bits<3> MinOp>
212 : T_fcmp <mnemonic, DoubleRegs, MinOp,
213 [(set I1:$dst, (OpNode F64:$src1, F64:$src2))]> {
215 let Inst{27-21} = 0b0010111;
218 class T_fcmp32 <string mnemonic, PatFrag OpNode, bits<3> MinOp>
219 : T_fcmp <mnemonic, IntRegs, MinOp,
220 [(set I1:$dst, (OpNode F32:$src1, F32:$src2))]> {
222 let Inst{27-21} = 0b0111111;
225 let isCodeGenOnly = 0 in {
226 def F2_dfcmpeq : T_fcmp64<"dfcmp.eq", setoeq, 0b000>;
227 def F2_dfcmpgt : T_fcmp64<"dfcmp.gt", setogt, 0b001>;
228 def F2_dfcmpge : T_fcmp64<"dfcmp.ge", setoge, 0b010>;
229 def F2_dfcmpuo : T_fcmp64<"dfcmp.uo", setuo, 0b011>;
231 def F2_sfcmpge : T_fcmp32<"sfcmp.ge", setoge, 0b000>;
232 def F2_sfcmpuo : T_fcmp32<"sfcmp.uo", setuo, 0b001>;
233 def F2_sfcmpeq : T_fcmp32<"sfcmp.eq", setoeq, 0b011>;
234 def F2_sfcmpgt : T_fcmp32<"sfcmp.gt", setogt, 0b100>;
237 // F2 convert template classes:
239 class F2_RDD_RSS_CONVERT<string mnemonic, bits<3> MinOp,
240 SDNode Op, PatLeaf RCOut, PatLeaf RCIn,
242 : SInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss),
243 "$Rdd = "#mnemonic#"($Rss)"#chop,
244 [(set RCOut:$Rdd, (Op RCIn:$Rss))], "",
245 S_2op_tc_3or4x_SLOT23> {
251 let Inst{27-21} = 0b0000111;
252 let Inst{20-16} = Rss;
253 let Inst{7-5} = MinOp;
258 class F2_RDD_RS_CONVERT<string mnemonic, bits<3> MinOp,
259 SDNode Op, PatLeaf RCOut, PatLeaf RCIn,
261 : SInst <(outs DoubleRegs:$Rdd), (ins IntRegs:$Rs),
262 "$Rdd = "#mnemonic#"($Rs)"#chop,
263 [(set RCOut:$Rdd, (Op RCIn:$Rs))], "",
264 S_2op_tc_3or4x_SLOT23> {
270 let Inst{27-21} = 0b0100100;
271 let Inst{20-16} = Rs;
272 let Inst{7-5} = MinOp;
276 let isFP = 1, hasNewValue = 1 in
277 class F2_RD_RSS_CONVERT<string mnemonic, bits<3> MinOp,
278 SDNode Op, PatLeaf RCOut, PatLeaf RCIn,
280 : SInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss),
281 "$Rd = "#mnemonic#"($Rss)"#chop,
282 [(set RCOut:$Rd, (Op RCIn:$Rss))], "",
283 S_2op_tc_3or4x_SLOT23> {
289 let Inst{27-24} = 0b1000;
290 let Inst{23-21} = MinOp;
291 let Inst{20-16} = Rss;
292 let Inst{7-5} = 0b001;
296 let isFP = 1, hasNewValue = 1 in
297 class F2_RD_RS_CONVERT<string mnemonic, bits<3> MajOp, bits<3> MinOp,
298 SDNode Op, PatLeaf RCOut, PatLeaf RCIn,
300 : SInst <(outs IntRegs:$Rd), (ins IntRegs:$Rs),
301 "$Rd = "#mnemonic#"($Rs)"#chop,
302 [(set RCOut:$Rd, (Op RCIn:$Rs))], "",
303 S_2op_tc_3or4x_SLOT23> {
309 let Inst{27-24} = 0b1011;
310 let Inst{23-21} = MajOp;
311 let Inst{20-16} = Rs;
312 let Inst{7-5} = MinOp;
316 // Convert single precision to double precision and vice-versa.
317 let isCodeGenOnly = 0 in {
318 def F2_conv_sf2df : F2_RDD_RS_CONVERT <"convert_sf2df", 0b000,
321 def F2_conv_df2sf : F2_RD_RSS_CONVERT <"convert_df2sf", 0b000,
324 // Convert Integer to Floating Point.
325 def F2_conv_d2sf : F2_RD_RSS_CONVERT <"convert_d2sf", 0b010,
326 sint_to_fp, F32, I64>;
327 def F2_conv_ud2sf : F2_RD_RSS_CONVERT <"convert_ud2sf", 0b001,
328 uint_to_fp, F32, I64>;
329 def F2_conv_uw2sf : F2_RD_RS_CONVERT <"convert_uw2sf", 0b001, 0b000,
330 uint_to_fp, F32, I32>;
331 def F2_conv_w2sf : F2_RD_RS_CONVERT <"convert_w2sf", 0b010, 0b000,
332 sint_to_fp, F32, I32>;
333 def F2_conv_d2df : F2_RDD_RSS_CONVERT <"convert_d2df", 0b011,
334 sint_to_fp, F64, I64>;
335 def F2_conv_ud2df : F2_RDD_RSS_CONVERT <"convert_ud2df", 0b010,
336 uint_to_fp, F64, I64>;
337 def F2_conv_uw2df : F2_RDD_RS_CONVERT <"convert_uw2df", 0b001,
338 uint_to_fp, F64, I32>;
339 def F2_conv_w2df : F2_RDD_RS_CONVERT <"convert_w2df", 0b010,
340 sint_to_fp, F64, I32>;
342 // Convert Floating Point to Integer - default.
343 def F2_conv_df2uw_chop : F2_RD_RSS_CONVERT <"convert_df2uw", 0b101,
344 fp_to_uint, I32, F64, ":chop">;
345 def F2_conv_df2w_chop : F2_RD_RSS_CONVERT <"convert_df2w", 0b111,
346 fp_to_sint, I32, F64, ":chop">;
347 def F2_conv_sf2uw_chop : F2_RD_RS_CONVERT <"convert_sf2uw", 0b011, 0b001,
348 fp_to_uint, I32, F32, ":chop">;
349 def F2_conv_sf2w_chop : F2_RD_RS_CONVERT <"convert_sf2w", 0b100, 0b001,
350 fp_to_sint, I32, F32, ":chop">;
351 def F2_conv_df2d_chop : F2_RDD_RSS_CONVERT <"convert_df2d", 0b110,
352 fp_to_sint, I64, F64, ":chop">;
353 def F2_conv_df2ud_chop : F2_RDD_RSS_CONVERT <"convert_df2ud", 0b111,
354 fp_to_uint, I64, F64, ":chop">;
355 def F2_conv_sf2d_chop : F2_RDD_RS_CONVERT <"convert_sf2d", 0b110,
356 fp_to_sint, I64, F32, ":chop">;
357 def F2_conv_sf2ud_chop : F2_RDD_RS_CONVERT <"convert_sf2ud", 0b101,
358 fp_to_uint, I64, F32, ":chop">;
360 // Convert Floating Point to Integer: non-chopped.
361 let AddedComplexity = 20, Predicates = [HasV5T, IEEERndNearV5T] in {
362 def F2_conv_df2d : F2_RDD_RSS_CONVERT <"convert_df2d", 0b000,
363 fp_to_sint, I64, F64>;
364 def F2_conv_df2ud : F2_RDD_RSS_CONVERT <"convert_df2ud", 0b001,
365 fp_to_uint, I64, F64>;
366 def F2_conv_sf2ud : F2_RDD_RS_CONVERT <"convert_sf2ud", 0b011,
367 fp_to_uint, I64, F32>;
368 def F2_conv_sf2d : F2_RDD_RS_CONVERT <"convert_sf2d", 0b100,
369 fp_to_sint, I64, F32>;
370 def F2_conv_df2uw : F2_RD_RSS_CONVERT <"convert_df2uw", 0b011,
371 fp_to_uint, I32, F64>;
372 def F2_conv_df2w : F2_RD_RSS_CONVERT <"convert_df2w", 0b100,
373 fp_to_sint, I32, F64>;
374 def F2_conv_sf2uw : F2_RD_RS_CONVERT <"convert_sf2uw", 0b011, 0b000,
375 fp_to_uint, I32, F32>;
376 def F2_conv_sf2w : F2_RD_RS_CONVERT <"convert_sf2w", 0b100, 0b000,
377 fp_to_sint, I32, F32>;
382 let isFP = 1, hasNewValue = 1, isCodeGenOnly = 0 in
383 def F2_sffixupr: SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs),
384 "$Rd = sffixupr($Rs)",
385 [], "" , S_2op_tc_3or4x_SLOT23>, Requires<[HasV5T]> {
391 let Inst{27-21} = 0b1011101;
392 let Inst{20-16} = Rs;
393 let Inst{7-5} = 0b000;
397 // F2_sffma: Floating-point fused multiply add.
398 let isFP = 1, hasNewValue = 1 in
399 class T_sfmpy_acc <bit isSub, bit isLib>
400 : MInst<(outs IntRegs:$Rx),
401 (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
402 "$Rx "#!if(isSub, "-=","+=")#" sfmpy($Rs, $Rt)"#!if(isLib, ":lib",""),
403 [], "$dst2 = $Rx" , M_tc_3_SLOT23 > ,
411 let Inst{27-21} = 0b1111000;
412 let Inst{20-16} = Rs;
421 let isCodeGenOnly = 0 in {
422 def F2_sffma: T_sfmpy_acc <0, 0>;
423 def F2_sffms: T_sfmpy_acc <1, 0>;
424 def F2_sffma_lib: T_sfmpy_acc <0, 1>;
425 def F2_sffms_lib: T_sfmpy_acc <1, 1>;
428 // Floating-point fused multiply add w/ additional scaling (2**pu).
429 let isFP = 1, hasNewValue = 1, isCodeGenOnly = 0 in
430 def F2_sffma_sc: MInst <
432 (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt, PredRegs:$Pu),
433 "$Rx += sfmpy($Rs, $Rt, $Pu):scale" ,
434 [], "$dst2 = $Rx" , M_tc_3_SLOT23 > ,
443 let Inst{27-21} = 0b1111011;
444 let Inst{20-16} = Rs;
452 // Classify floating-point value
453 let isFP = 1, isCodeGenOnly = 0 in
454 def F2_sfclass : T_TEST_BIT_IMM<"sfclass", 0b111>;
456 let isFP = 1, isCodeGenOnly = 0 in
457 def F2_dfclass: ALU64Inst<(outs PredRegs:$Pd), (ins DoubleRegs:$Rss, u5Imm:$u5),
458 "$Pd = dfclass($Rss, #$u5)",
459 [], "" , ALU64_tc_2early_SLOT23 > , Requires<[HasV5T]> {
465 let Inst{27-21} = 0b1100100;
466 let Inst{20-16} = Rss;
467 let Inst{12-10} = 0b000;
469 let Inst{4-3} = 0b10;
473 // Instructions to create floating point constant
474 let hasNewValue = 1, opNewValue = 0 in
475 class T_fimm <string mnemonic, RegisterClass RC, bits<4> RegType, bit isNeg>
476 : ALU64Inst<(outs RC:$dst), (ins u10Imm:$src),
477 "$dst = "#mnemonic#"(#$src)"#!if(isNeg, ":neg", ":pos"),
478 [], "", ALU64_tc_3x_SLOT23>, Requires<[HasV5T]> {
483 let Inst{27-24} = RegType;
485 let Inst{22} = isNeg;
486 let Inst{21} = src{9};
487 let Inst{13-5} = src{8-0};
491 let isCodeGenOnly = 0 in {
492 def F2_sfimm_p : T_fimm <"sfmake", IntRegs, 0b0110, 0>;
493 def F2_sfimm_n : T_fimm <"sfmake", IntRegs, 0b0110, 1>;
494 def F2_dfimm_p : T_fimm <"dfmake", DoubleRegs, 0b1001, 0>;
495 def F2_dfimm_n : T_fimm <"dfmake", DoubleRegs, 0b1001, 1>;
498 let isCommutable = 1 in
499 def fMUL_rr : ALU64_rr<(outs IntRegs:$dst),
500 (ins IntRegs:$src1, IntRegs:$src2),
501 "$dst = sfmpy($src1, $src2)",
502 [(set IntRegs:$dst, (fmul IntRegs:$src1, IntRegs:$src2))]>,
505 let isCommutable = 1 in
506 def fMUL64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
508 "$dst = dfmpy($src1, $src2)",
509 [(set DoubleRegs:$dst, (fmul DoubleRegs:$src1,
510 DoubleRegs:$src2))]>,
514 let isCompare = 1 in {
515 multiclass FCMP64_rr<string OpcStr, PatFrag OpNode> {
516 def _rr : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$b, DoubleRegs:$c),
517 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
519 (OpNode (f64 DoubleRegs:$b), (f64 DoubleRegs:$c)))]>,
523 multiclass FCMP32_rr<string OpcStr, PatFrag OpNode> {
524 def _rr : ALU64_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
525 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
527 (OpNode (f32 IntRegs:$b), (f32 IntRegs:$c)))]>,
532 defm FCMPOEQ64 : FCMP64_rr<"dfcmp.eq", setoeq>;
533 defm FCMPUEQ64 : FCMP64_rr<"dfcmp.eq", setueq>;
534 defm FCMPOGT64 : FCMP64_rr<"dfcmp.gt", setogt>;
535 defm FCMPUGT64 : FCMP64_rr<"dfcmp.gt", setugt>;
536 defm FCMPOGE64 : FCMP64_rr<"dfcmp.ge", setoge>;
537 defm FCMPUGE64 : FCMP64_rr<"dfcmp.ge", setuge>;
539 defm FCMPOEQ32 : FCMP32_rr<"sfcmp.eq", setoeq>;
540 defm FCMPUEQ32 : FCMP32_rr<"sfcmp.eq", setueq>;
541 defm FCMPOGT32 : FCMP32_rr<"sfcmp.gt", setogt>;
542 defm FCMPUGT32 : FCMP32_rr<"sfcmp.gt", setugt>;
543 defm FCMPOGE32 : FCMP32_rr<"sfcmp.ge", setoge>;
544 defm FCMPUGE32 : FCMP32_rr<"sfcmp.ge", setuge>;
547 def : Pat <(i1 (setolt (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
548 (i1 (FCMPOGT32_rr IntRegs:$src2, IntRegs:$src1))>,
551 def : Pat <(i1 (setolt (f32 IntRegs:$src1), (fpimm:$src2))),
552 (i1 (FCMPOGT32_rr (f32 (TFRI_f fpimm:$src2)), (f32 IntRegs:$src1)))>,
555 def : Pat <(i1 (setolt (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
556 (i1 (FCMPOGT64_rr DoubleRegs:$src2, DoubleRegs:$src1))>,
559 def : Pat <(i1 (setolt (f64 DoubleRegs:$src1), (fpimm:$src2))),
560 (i1 (FCMPOGT64_rr (f64 (CONST64_Float_Real fpimm:$src2)),
561 (f64 DoubleRegs:$src1)))>,
565 def : Pat <(i1 (setugt (f64 DoubleRegs:$src1), (fpimm:$src2))),
566 (i1 (FCMPUGT64_rr (f64 DoubleRegs:$src1),
567 (f64 (CONST64_Float_Real fpimm:$src2))))>,
570 def : Pat <(i1 (setugt (f32 IntRegs:$src1), (fpimm:$src2))),
571 (i1 (FCMPUGT32_rr (f32 IntRegs:$src1), (f32 (TFRI_f fpimm:$src2))))>,
575 def : Pat <(i1 (setult (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
576 (i1 (FCMPUGT32_rr IntRegs:$src2, IntRegs:$src1))>,
579 def : Pat <(i1 (setult (f32 IntRegs:$src1), (fpimm:$src2))),
580 (i1 (FCMPUGT32_rr (f32 (TFRI_f fpimm:$src2)), (f32 IntRegs:$src1)))>,
583 def : Pat <(i1 (setult (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
584 (i1 (FCMPUGT64_rr DoubleRegs:$src2, DoubleRegs:$src1))>,
587 def : Pat <(i1 (setult (f64 DoubleRegs:$src1), (fpimm:$src2))),
588 (i1 (FCMPUGT64_rr (f64 (CONST64_Float_Real fpimm:$src2)),
589 (f64 DoubleRegs:$src1)))>,
593 // rs <= rt -> rt >= rs.
594 def : Pat<(i1 (setole (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
595 (i1 (FCMPOGE32_rr IntRegs:$src2, IntRegs:$src1))>,
598 def : Pat<(i1 (setole (f32 IntRegs:$src1), (fpimm:$src2))),
599 (i1 (FCMPOGE32_rr (f32 (TFRI_f fpimm:$src2)), IntRegs:$src1))>,
603 // Rss <= Rtt -> Rtt >= Rss.
604 def : Pat<(i1 (setole (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
605 (i1 (FCMPOGE64_rr DoubleRegs:$src2, DoubleRegs:$src1))>,
608 def : Pat<(i1 (setole (f64 DoubleRegs:$src1), (fpimm:$src2))),
609 (i1 (FCMPOGE64_rr (f64 (CONST64_Float_Real fpimm:$src2)),
613 // rs <= rt -> rt >= rs.
614 def : Pat<(i1 (setule (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
615 (i1 (FCMPUGE32_rr IntRegs:$src2, IntRegs:$src1))>,
618 def : Pat<(i1 (setule (f32 IntRegs:$src1), (fpimm:$src2))),
619 (i1 (FCMPUGE32_rr (f32 (TFRI_f fpimm:$src2)), IntRegs:$src1))>,
622 // Rss <= Rtt -> Rtt >= Rss.
623 def : Pat<(i1 (setule (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
624 (i1 (FCMPUGE64_rr DoubleRegs:$src2, DoubleRegs:$src1))>,
627 def : Pat<(i1 (setule (f64 DoubleRegs:$src1), (fpimm:$src2))),
628 (i1 (FCMPUGE64_rr (f64 (CONST64_Float_Real fpimm:$src2)),
633 def : Pat<(i1 (setone (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
634 (i1 (C2_not (FCMPOEQ32_rr IntRegs:$src1, IntRegs:$src2)))>,
637 def : Pat<(i1 (setone (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
638 (i1 (C2_not (FCMPOEQ64_rr DoubleRegs:$src1, DoubleRegs:$src2)))>,
641 def : Pat<(i1 (setune (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
642 (i1 (C2_not (FCMPUEQ32_rr IntRegs:$src1, IntRegs:$src2)))>,
645 def : Pat<(i1 (setune (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
646 (i1 (C2_not (FCMPUEQ64_rr DoubleRegs:$src1, DoubleRegs:$src2)))>,
649 def : Pat<(i1 (setone (f32 IntRegs:$src1), (fpimm:$src2))),
650 (i1 (C2_not (FCMPOEQ32_rr IntRegs:$src1, (f32 (TFRI_f fpimm:$src2)))))>,
653 def : Pat<(i1 (setone (f64 DoubleRegs:$src1), (fpimm:$src2))),
654 (i1 (C2_not (FCMPOEQ64_rr DoubleRegs:$src1,
655 (f64 (CONST64_Float_Real fpimm:$src2)))))>,
658 def : Pat<(i1 (setune (f32 IntRegs:$src1), (fpimm:$src2))),
659 (i1 (C2_not (FCMPUEQ32_rr IntRegs:$src1, (f32 (TFRI_f fpimm:$src2)))))>,
662 def : Pat<(i1 (setune (f64 DoubleRegs:$src1), (fpimm:$src2))),
663 (i1 (C2_not (FCMPUEQ64_rr DoubleRegs:$src1,
664 (f64 (CONST64_Float_Real fpimm:$src2)))))>,
667 // Convert Integer to Floating Point.
668 def CONVERT_d2sf : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
669 "$dst = convert_d2sf($src)",
670 [(set (f32 IntRegs:$dst), (sint_to_fp (i64 DoubleRegs:$src)))]>,
673 def CONVERT_ud2sf : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
674 "$dst = convert_ud2sf($src)",
675 [(set (f32 IntRegs:$dst), (uint_to_fp (i64 DoubleRegs:$src)))]>,
678 def CONVERT_uw2sf : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
679 "$dst = convert_uw2sf($src)",
680 [(set (f32 IntRegs:$dst), (uint_to_fp (i32 IntRegs:$src)))]>,
683 def CONVERT_w2sf : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
684 "$dst = convert_w2sf($src)",
685 [(set (f32 IntRegs:$dst), (sint_to_fp (i32 IntRegs:$src)))]>,
688 def CONVERT_d2df : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
689 "$dst = convert_d2df($src)",
690 [(set (f64 DoubleRegs:$dst), (sint_to_fp (i64 DoubleRegs:$src)))]>,
693 def CONVERT_ud2df : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
694 "$dst = convert_ud2df($src)",
695 [(set (f64 DoubleRegs:$dst), (uint_to_fp (i64 DoubleRegs:$src)))]>,
698 def CONVERT_uw2df : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
699 "$dst = convert_uw2df($src)",
700 [(set (f64 DoubleRegs:$dst), (uint_to_fp (i32 IntRegs:$src)))]>,
703 def CONVERT_w2df : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
704 "$dst = convert_w2df($src)",
705 [(set (f64 DoubleRegs:$dst), (sint_to_fp (i32 IntRegs:$src)))]>,
708 // Convert Floating Point to Integer - default.
709 def CONVERT_df2uw : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
710 "$dst = convert_df2uw($src):chop",
711 [(set (i32 IntRegs:$dst), (fp_to_uint (f64 DoubleRegs:$src)))]>,
714 def CONVERT_df2w : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
715 "$dst = convert_df2w($src):chop",
716 [(set (i32 IntRegs:$dst), (fp_to_sint (f64 DoubleRegs:$src)))]>,
719 def CONVERT_sf2uw : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
720 "$dst = convert_sf2uw($src):chop",
721 [(set (i32 IntRegs:$dst), (fp_to_uint (f32 IntRegs:$src)))]>,
724 def CONVERT_sf2w : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
725 "$dst = convert_sf2w($src):chop",
726 [(set (i32 IntRegs:$dst), (fp_to_sint (f32 IntRegs:$src)))]>,
729 def CONVERT_df2d : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
730 "$dst = convert_df2d($src):chop",
731 [(set (i64 DoubleRegs:$dst), (fp_to_sint (f64 DoubleRegs:$src)))]>,
734 def CONVERT_df2ud : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
735 "$dst = convert_df2ud($src):chop",
736 [(set (i64 DoubleRegs:$dst), (fp_to_uint (f64 DoubleRegs:$src)))]>,
739 def CONVERT_sf2d : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
740 "$dst = convert_sf2d($src):chop",
741 [(set (i64 DoubleRegs:$dst), (fp_to_sint (f32 IntRegs:$src)))]>,
744 def CONVERT_sf2ud : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
745 "$dst = convert_sf2ud($src):chop",
746 [(set (i64 DoubleRegs:$dst), (fp_to_uint (f32 IntRegs:$src)))]>,
749 // Convert Floating Point to Integer: non-chopped.
750 let AddedComplexity = 20 in
751 def CONVERT_df2uw_nchop : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
752 "$dst = convert_df2uw($src)",
753 [(set (i32 IntRegs:$dst), (fp_to_uint (f64 DoubleRegs:$src)))]>,
754 Requires<[HasV5T, IEEERndNearV5T]>;
756 let AddedComplexity = 20 in
757 def CONVERT_df2w_nchop : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
758 "$dst = convert_df2w($src)",
759 [(set (i32 IntRegs:$dst), (fp_to_sint (f64 DoubleRegs:$src)))]>,
760 Requires<[HasV5T, IEEERndNearV5T]>;
762 let AddedComplexity = 20 in
763 def CONVERT_sf2uw_nchop : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
764 "$dst = convert_sf2uw($src)",
765 [(set (i32 IntRegs:$dst), (fp_to_uint (f32 IntRegs:$src)))]>,
766 Requires<[HasV5T, IEEERndNearV5T]>;
768 let AddedComplexity = 20 in
769 def CONVERT_sf2w_nchop : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
770 "$dst = convert_sf2w($src)",
771 [(set (i32 IntRegs:$dst), (fp_to_sint (f32 IntRegs:$src)))]>,
772 Requires<[HasV5T, IEEERndNearV5T]>;
774 let AddedComplexity = 20 in
775 def CONVERT_df2d_nchop : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
776 "$dst = convert_df2d($src)",
777 [(set (i64 DoubleRegs:$dst), (fp_to_sint (f64 DoubleRegs:$src)))]>,
778 Requires<[HasV5T, IEEERndNearV5T]>;
780 let AddedComplexity = 20 in
781 def CONVERT_df2ud_nchop : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
782 "$dst = convert_df2ud($src)",
783 [(set (i64 DoubleRegs:$dst), (fp_to_uint (f64 DoubleRegs:$src)))]>,
784 Requires<[HasV5T, IEEERndNearV5T]>;
786 let AddedComplexity = 20 in
787 def CONVERT_sf2d_nchop : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
788 "$dst = convert_sf2d($src)",
789 [(set (i64 DoubleRegs:$dst), (fp_to_sint (f32 IntRegs:$src)))]>,
790 Requires<[HasV5T, IEEERndNearV5T]>;
792 let AddedComplexity = 20 in
793 def CONVERT_sf2ud_nchop : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
794 "$dst = convert_sf2ud($src)",
795 [(set (i64 DoubleRegs:$dst), (fp_to_uint (f32 IntRegs:$src)))]>,
796 Requires<[HasV5T, IEEERndNearV5T]>;
800 // Bitcast is different than [fp|sint|uint]_to_[sint|uint|fp].
801 def : Pat <(i32 (bitconvert (f32 IntRegs:$src))),
802 (i32 (A2_tfr IntRegs:$src))>,
805 def : Pat <(f32 (bitconvert (i32 IntRegs:$src))),
806 (f32 (A2_tfr IntRegs:$src))>,
809 def : Pat <(i64 (bitconvert (f64 DoubleRegs:$src))),
810 (i64 (A2_tfrp DoubleRegs:$src))>,
813 def : Pat <(f64 (bitconvert (i64 DoubleRegs:$src))),
814 (f64 (A2_tfrp DoubleRegs:$src))>,
817 def FMADD_sp : ALU64_acc<(outs IntRegs:$dst),
818 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
819 "$dst += sfmpy($src2, $src3)",
820 [(set (f32 IntRegs:$dst),
821 (fma IntRegs:$src2, IntRegs:$src3, IntRegs:$src1))],
826 // Floating point max/min.
828 let AddedComplexity = 100 in
829 def FMAX_sp : ALU64_rr<(outs IntRegs:$dst),
830 (ins IntRegs:$src1, IntRegs:$src2),
831 "$dst = sfmax($src1, $src2)",
832 [(set IntRegs:$dst, (f32 (select (i1 (setolt IntRegs:$src2,
838 let AddedComplexity = 100 in
839 def FMIN_sp : ALU64_rr<(outs IntRegs:$dst),
840 (ins IntRegs:$src1, IntRegs:$src2),
841 "$dst = sfmin($src1, $src2)",
842 [(set IntRegs:$dst, (f32 (select (i1 (setogt IntRegs:$src2,
848 // Pseudo instruction to encode a set of conditional transfers.
849 // This instruction is used instead of a mux and trades-off codesize
850 // for performance. We conduct this transformation optimistically in
851 // the hope that these instructions get promoted to dot-new transfers.
852 let AddedComplexity = 100, isPredicated = 1 in
853 def TFR_condset_rr_f : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
856 "Error; should not emit",
857 [(set IntRegs:$dst, (f32 (select PredRegs:$src1,
862 let AddedComplexity = 100, isPredicated = 1 in
863 def TFR_condset_rr64_f : ALU32_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
866 "Error; should not emit",
867 [(set DoubleRegs:$dst, (f64 (select PredRegs:$src1,
869 DoubleRegs:$src3)))]>,
874 let AddedComplexity = 100, isPredicated = 1 in
875 def TFR_condset_ri_f : ALU32_rr<(outs IntRegs:$dst),
876 (ins PredRegs:$src1, IntRegs:$src2, f32imm:$src3),
877 "Error; should not emit",
879 (f32 (select PredRegs:$src1, IntRegs:$src2, fpimm:$src3)))]>,
882 let AddedComplexity = 100, isPredicated = 1 in
883 def TFR_condset_ir_f : ALU32_rr<(outs IntRegs:$dst),
884 (ins PredRegs:$src1, f32imm:$src2, IntRegs:$src3),
885 "Error; should not emit",
887 (f32 (select PredRegs:$src1, fpimm:$src2, IntRegs:$src3)))]>,
890 let AddedComplexity = 100, isPredicated = 1 in
891 def TFR_condset_ii_f : ALU32_rr<(outs IntRegs:$dst),
892 (ins PredRegs:$src1, f32imm:$src2, f32imm:$src3),
893 "Error; should not emit",
894 [(set IntRegs:$dst, (f32 (select PredRegs:$src1,
900 def : Pat <(select (i1 (setult (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
902 (f32 IntRegs:$src4)),
903 (TFR_condset_rr_f (FCMPUGT32_rr IntRegs:$src2, IntRegs:$src1), IntRegs:$src4,
904 IntRegs:$src3)>, Requires<[HasV5T]>;
906 def : Pat <(select (i1 (setult (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
907 (f64 DoubleRegs:$src3),
908 (f64 DoubleRegs:$src4)),
909 (TFR_condset_rr64_f (FCMPUGT64_rr DoubleRegs:$src2, DoubleRegs:$src1),
910 DoubleRegs:$src4, DoubleRegs:$src3)>, Requires<[HasV5T]>;
912 // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
913 def : Pat <(select (not PredRegs:$src1), fpimm:$src2, fpimm:$src3),
914 (TFR_condset_ii_f PredRegs:$src1, fpimm:$src3, fpimm:$src2)>;
916 // Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
917 // => r0 = TFR_condset_ri(p0, r1, #i)
918 def : Pat <(select (not PredRegs:$src1), fpimm:$src2, IntRegs:$src3),
919 (TFR_condset_ri_f PredRegs:$src1, IntRegs:$src3, fpimm:$src2)>;
921 // Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
922 // => r0 = TFR_condset_ir(p0, #i, r1)
923 def : Pat <(select (not PredRegs:$src1), IntRegs:$src2, fpimm:$src3),
924 (TFR_condset_ir_f PredRegs:$src1, fpimm:$src3, IntRegs:$src2)>;
926 def : Pat <(i32 (fp_to_sint (f64 DoubleRegs:$src1))),
927 (i32 (EXTRACT_SUBREG (i64 (CONVERT_df2d (f64 DoubleRegs:$src1))), subreg_loreg))>,
930 def : Pat <(fabs (f32 IntRegs:$src1)),
931 (S2_clrbit_i (f32 IntRegs:$src1), 31)>,
934 def : Pat <(fneg (f32 IntRegs:$src1)),
935 (S2_togglebit_i (f32 IntRegs:$src1), 31)>,
939 def : Pat <(fabs (f64 DoubleRegs:$src1)),
940 (S2_clrbit_i (f32 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_hireg)), 31)>,
943 def : Pat <(fabs (f64 DoubleRegs:$src1)),
944 (S2_clrbit_i (f32 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_hireg)), 31)>,