1 //=- HexagonInstrInfoV5.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V5 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
18 //Rdd[+]=vrmpybsu(Rss,Rtt)
19 let Predicates = [HasV5T] in {
20 def M5_vrmpybsu: T_XTYPE_Vect<"vrmpybsu", 0b110, 0b001, 0>;
21 def M5_vrmacbsu: T_XTYPE_Vect_acc<"vrmpybsu", 0b110, 0b001, 0>;
23 //Rdd[+]=vrmpybu(Rss,Rtt)
24 def M5_vrmpybuu: T_XTYPE_Vect<"vrmpybu", 0b100, 0b001, 0>;
25 def M5_vrmacbuu: T_XTYPE_Vect_acc<"vrmpybu", 0b100, 0b001, 0>;
27 def M5_vdmpybsu: T_M2_vmpy<"vdmpybsu", 0b101, 0b001, 0, 0, 1>;
28 def M5_vdmacbsu: T_M2_vmpy_acc_sat <"vdmpybsu", 0b001, 0b001, 0, 0>;
31 // Vector multiply bytes
32 // Rdd=vmpyb[s]u(Rs,Rt)
33 let Predicates = [HasV5T] in {
34 def M5_vmpybsu: T_XTYPE_mpy64 <"vmpybsu", 0b010, 0b001, 0, 0, 0>;
35 def M5_vmpybuu: T_XTYPE_mpy64 <"vmpybu", 0b100, 0b001, 0, 0, 0>;
37 // Rxx+=vmpyb[s]u(Rs,Rt)
38 def M5_vmacbsu: T_XTYPE_mpy64_acc <"vmpybsu", "+", 0b110, 0b001, 0, 0, 0>;
39 def M5_vmacbuu: T_XTYPE_mpy64_acc <"vmpybu", "+", 0b100, 0b001, 0, 0, 0>;
41 // Rd=vaddhub(Rss,Rtt):sat
42 let hasNewValue = 1, opNewValue = 0 in
43 def A5_vaddhubs: T_S3op_1 <"vaddhub", IntRegs, 0b01, 0b001, 0, 1>;
46 def S2_asr_i_p_rnd : S_2OpInstImm<"asr", 0b110, 0b111, u6Imm,
48 (sra (i64 (add (i64 (sra I64:$src1, u6ImmPred:$src2)), 1)),
52 let Inst{13-8} = src2;
55 let isAsmParserOnly = 1 in
56 def S2_asr_i_p_rnd_goodsyntax
57 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
58 "$dst = asrrnd($src1, #$src2)">;
60 def C4_fastcorner9 : T_LOGICAL_2OP<"fastcorner9", 0b000, 0, 0>,
62 let Inst{13,7,4} = 0b111;
65 def C4_fastcorner9_not : T_LOGICAL_2OP<"!fastcorner9", 0b000, 0, 0>,
67 let Inst{20,13,7,4} = 0b1111;
70 def SDTHexagonFCONST32 : SDTypeProfile<1, 1, [
73 def HexagonFCONST32 : SDNode<"HexagonISD::FCONST32", SDTHexagonFCONST32>;
75 let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
76 def FCONST32_nsdata : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
77 "$dst = CONST32(#$global)",
78 [(set (f32 IntRegs:$dst),
79 (HexagonFCONST32 tglobaladdr:$global))]>,
82 let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
83 def CONST64_Float_Real : LDInst<(outs DoubleRegs:$dst), (ins f64imm:$src1),
84 "$dst = CONST64(#$src1)",
85 [(set DoubleRegs:$dst, fpimm:$src1)]>,
88 let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
89 def CONST32_Float_Real : LDInst<(outs IntRegs:$dst), (ins f32imm:$src1),
90 "$dst = CONST32(#$src1)",
91 [(set IntRegs:$dst, fpimm:$src1)]>,
94 // Transfer immediate float.
95 // Only works with single precision fp value.
96 // For double precision, use CONST64_float_real, as 64bit transfer
97 // can only hold 40-bit values - 32 from const ext + 8 bit immediate.
98 // Make sure that complexity is more than the CONST32 pattern in
99 // HexagonInstrInfo.td patterns.
100 let isExtended = 1, opExtendable = 1, isMoveImm = 1, isReMaterializable = 1,
101 isPredicable = 1, AddedComplexity = 30, validSubTargets = HasV5SubT,
103 def TFRI_f : ALU32_ri<(outs IntRegs:$dst), (ins f32Ext:$src1),
105 [(set IntRegs:$dst, fpimm:$src1)]>,
108 let isExtended = 1, opExtendable = 2, isPredicated = 1,
109 hasSideEffects = 0, validSubTargets = HasV5SubT, isCodeGenOnly = 1 in
110 def TFRI_cPt_f : ALU32_ri<(outs IntRegs:$dst),
111 (ins PredRegs:$src1, f32Ext:$src2),
112 "if ($src1) $dst = #$src2",
116 let isExtended = 1, opExtendable = 2, isPredicated = 1, isPredicatedFalse = 1,
117 hasSideEffects = 0, validSubTargets = HasV5SubT in
118 def TFRI_cNotPt_f : ALU32_ri<(outs IntRegs:$dst),
119 (ins PredRegs:$src1, f32Ext:$src2),
120 "if (!$src1) $dst =#$src2",
124 def SDTHexagonI32I64: SDTypeProfile<1, 1, [SDTCisVT<0, i32>,
127 def HexagonPOPCOUNT: SDNode<"HexagonISD::POPCOUNT", SDTHexagonI32I64>;
129 let hasNewValue = 1, validSubTargets = HasV5SubT in
130 def S5_popcountp : ALU64_rr<(outs IntRegs:$Rd), (ins DoubleRegs:$Rss),
131 "$Rd = popcount($Rss)",
132 [(set I32:$Rd, (HexagonPOPCOUNT I64:$Rss))], "", S_2op_tc_2_SLOT23>,
139 let Inst{27-21} = 0b1000011;
140 let Inst{7-5} = 0b011;
142 let Inst{20-16} = Rss;
145 defm: Loadx_pat<load, f32, s11_2ExtPred, L2_loadri_io>;
146 defm: Loadx_pat<load, f64, s11_3ExtPred, L2_loadrd_io>;
148 defm: Storex_pat<store, F32, s11_2ExtPred, S2_storeri_io>;
149 defm: Storex_pat<store, F64, s11_3ExtPred, S2_storerd_io>;
151 let isFP = 1, hasNewValue = 1, opNewValue = 0 in
152 class T_MInstFloat <string mnemonic, bits<3> MajOp, bits<3> MinOp>
153 : MInst<(outs IntRegs:$Rd),
154 (ins IntRegs:$Rs, IntRegs:$Rt),
155 "$Rd = "#mnemonic#"($Rs, $Rt)", [],
156 "" , M_tc_3or4x_SLOT23 > ,
164 let Inst{27-24} = 0b1011;
165 let Inst{23-21} = MajOp;
166 let Inst{20-16} = Rs;
169 let Inst{7-5} = MinOp;
173 let isCommutable = 1 in {
174 def F2_sfadd : T_MInstFloat < "sfadd", 0b000, 0b000>;
175 def F2_sfmpy : T_MInstFloat < "sfmpy", 0b010, 0b000>;
178 def F2_sfsub : T_MInstFloat < "sfsub", 0b000, 0b001>;
180 def: Pat<(f32 (fadd F32:$src1, F32:$src2)),
181 (F2_sfadd F32:$src1, F32:$src2)>;
183 def: Pat<(f32 (fsub F32:$src1, F32:$src2)),
184 (F2_sfsub F32:$src1, F32:$src2)>;
186 def: Pat<(f32 (fmul F32:$src1, F32:$src2)),
187 (F2_sfmpy F32:$src1, F32:$src2)>;
189 let Itinerary = M_tc_3x_SLOT23 in {
190 def F2_sfmax : T_MInstFloat < "sfmax", 0b100, 0b000>;
191 def F2_sfmin : T_MInstFloat < "sfmin", 0b100, 0b001>;
194 def F2_sffixupn : T_MInstFloat < "sffixupn", 0b110, 0b000>;
195 def F2_sffixupd : T_MInstFloat < "sffixupd", 0b110, 0b001>;
197 // F2_sfrecipa: Reciprocal approximation for division.
198 let isPredicateLate = 1, isFP = 1,
199 hasSideEffects = 0, hasNewValue = 1 in
200 def F2_sfrecipa: MInst <
201 (outs IntRegs:$Rd, PredRegs:$Pe),
202 (ins IntRegs:$Rs, IntRegs:$Rt),
203 "$Rd, $Pe = sfrecipa($Rs, $Rt)">,
211 let Inst{27-21} = 0b1011111;
212 let Inst{20-16} = Rs;
220 // F2_dfcmpeq: Floating point compare for equal.
221 let isCompare = 1, isFP = 1 in
222 class T_fcmp <string mnemonic, RegisterClass RC, bits<3> MinOp,
223 list<dag> pattern = [] >
224 : ALU64Inst <(outs PredRegs:$dst), (ins RC:$src1, RC:$src2),
225 "$dst = "#mnemonic#"($src1, $src2)", pattern,
226 "" , ALU64_tc_2early_SLOT23 > ,
234 let Inst{27-21} = 0b0010111;
235 let Inst{20-16} = src1;
236 let Inst{12-8} = src2;
237 let Inst{7-5} = MinOp;
241 class T_fcmp64 <string mnemonic, PatFrag OpNode, bits<3> MinOp>
242 : T_fcmp <mnemonic, DoubleRegs, MinOp,
243 [(set I1:$dst, (OpNode F64:$src1, F64:$src2))]> {
245 let Inst{27-21} = 0b0010111;
248 class T_fcmp32 <string mnemonic, PatFrag OpNode, bits<3> MinOp>
249 : T_fcmp <mnemonic, IntRegs, MinOp,
250 [(set I1:$dst, (OpNode F32:$src1, F32:$src2))]> {
252 let Inst{27-21} = 0b0111111;
255 def F2_dfcmpeq : T_fcmp64<"dfcmp.eq", setoeq, 0b000>;
256 def F2_dfcmpgt : T_fcmp64<"dfcmp.gt", setogt, 0b001>;
257 def F2_dfcmpge : T_fcmp64<"dfcmp.ge", setoge, 0b010>;
258 def F2_dfcmpuo : T_fcmp64<"dfcmp.uo", setuo, 0b011>;
260 def F2_sfcmpge : T_fcmp32<"sfcmp.ge", setoge, 0b000>;
261 def F2_sfcmpuo : T_fcmp32<"sfcmp.uo", setuo, 0b001>;
262 def F2_sfcmpeq : T_fcmp32<"sfcmp.eq", setoeq, 0b011>;
263 def F2_sfcmpgt : T_fcmp32<"sfcmp.gt", setogt, 0b100>;
265 //===----------------------------------------------------------------------===//
266 // Multiclass to define 'Def Pats' for ordered gt, ge, eq operations.
267 //===----------------------------------------------------------------------===//
269 let Predicates = [HasV5T] in
270 multiclass T_fcmp_pats<PatFrag cmpOp, InstHexagon IntMI, InstHexagon DoubleMI> {
272 def: Pat<(i1 (cmpOp F32:$src1, F32:$src2)),
273 (IntMI F32:$src1, F32:$src2)>;
275 def: Pat<(i1 (cmpOp F64:$src1, F64:$src2)),
276 (DoubleMI F64:$src1, F64:$src2)>;
279 defm : T_fcmp_pats <seteq, F2_sfcmpeq, F2_dfcmpeq>;
280 defm : T_fcmp_pats <setgt, F2_sfcmpgt, F2_dfcmpgt>;
281 defm : T_fcmp_pats <setge, F2_sfcmpge, F2_dfcmpge>;
283 //===----------------------------------------------------------------------===//
284 // Multiclass to define 'Def Pats' for unordered gt, ge, eq operations.
285 //===----------------------------------------------------------------------===//
286 let Predicates = [HasV5T] in
287 multiclass unord_Pats <PatFrag cmpOp, InstHexagon IntMI, InstHexagon DoubleMI> {
289 def: Pat<(i1 (cmpOp F32:$src1, F32:$src2)),
290 (C2_or (F2_sfcmpuo F32:$src1, F32:$src2),
291 (IntMI F32:$src1, F32:$src2))>;
294 def: Pat<(i1 (cmpOp F64:$src1, F64:$src2)),
295 (C2_or (F2_dfcmpuo F64:$src1, F64:$src2),
296 (DoubleMI F64:$src1, F64:$src2))>;
299 defm : unord_Pats <setuge, F2_sfcmpge, F2_dfcmpge>;
300 defm : unord_Pats <setugt, F2_sfcmpgt, F2_dfcmpgt>;
301 defm : unord_Pats <setueq, F2_sfcmpeq, F2_dfcmpeq>;
303 //===----------------------------------------------------------------------===//
304 // Multiclass to define 'Def Pats' for the following dags:
305 // seteq(setoeq(op1, op2), 0) -> not(setoeq(op1, op2))
306 // seteq(setoeq(op1, op2), 1) -> setoeq(op1, op2)
307 // setne(setoeq(op1, op2), 0) -> setoeq(op1, op2)
308 // setne(setoeq(op1, op2), 1) -> not(setoeq(op1, op2))
309 //===----------------------------------------------------------------------===//
310 let Predicates = [HasV5T] in
311 multiclass eq_ordgePats <PatFrag cmpOp, InstHexagon IntMI,
312 InstHexagon DoubleMI> {
314 def: Pat<(i1 (seteq (i1 (cmpOp F32:$src1, F32:$src2)), 0)),
315 (C2_not (IntMI F32:$src1, F32:$src2))>;
316 def: Pat<(i1 (seteq (i1 (cmpOp F32:$src1, F32:$src2)), 1)),
317 (IntMI F32:$src1, F32:$src2)>;
318 def: Pat<(i1 (setne (i1 (cmpOp F32:$src1, F32:$src2)), 0)),
319 (IntMI F32:$src1, F32:$src2)>;
320 def: Pat<(i1 (setne (i1 (cmpOp F32:$src1, F32:$src2)), 1)),
321 (C2_not (IntMI F32:$src1, F32:$src2))>;
324 def : Pat<(i1 (seteq (i1 (cmpOp F64:$src1, F64:$src2)), 0)),
325 (C2_not (DoubleMI F64:$src1, F64:$src2))>;
326 def : Pat<(i1 (seteq (i1 (cmpOp F64:$src1, F64:$src2)), 1)),
327 (DoubleMI F64:$src1, F64:$src2)>;
328 def : Pat<(i1 (setne (i1 (cmpOp F64:$src1, F64:$src2)), 0)),
329 (DoubleMI F64:$src1, F64:$src2)>;
330 def : Pat<(i1 (setne (i1 (cmpOp F64:$src1, F64:$src2)), 1)),
331 (C2_not (DoubleMI F64:$src1, F64:$src2))>;
334 defm : eq_ordgePats<setoeq, F2_sfcmpeq, F2_dfcmpeq>;
335 defm : eq_ordgePats<setoge, F2_sfcmpge, F2_dfcmpge>;
336 defm : eq_ordgePats<setogt, F2_sfcmpgt, F2_dfcmpgt>;
338 //===----------------------------------------------------------------------===//
339 // Multiclass to define 'Def Pats' for the following dags:
340 // seteq(setolt(op1, op2), 0) -> not(setogt(op2, op1))
341 // seteq(setolt(op1, op2), 1) -> setogt(op2, op1)
342 // setne(setolt(op1, op2), 0) -> setogt(op2, op1)
343 // setne(setolt(op1, op2), 1) -> not(setogt(op2, op1))
344 //===----------------------------------------------------------------------===//
345 let Predicates = [HasV5T] in
346 multiclass eq_ordltPats <PatFrag cmpOp, InstHexagon IntMI,
347 InstHexagon DoubleMI> {
349 def: Pat<(i1 (seteq (i1 (cmpOp F32:$src1, F32:$src2)), 0)),
350 (C2_not (IntMI F32:$src2, F32:$src1))>;
351 def: Pat<(i1 (seteq (i1 (cmpOp F32:$src1, F32:$src2)), 1)),
352 (IntMI F32:$src2, F32:$src1)>;
353 def: Pat<(i1 (setne (i1 (cmpOp F32:$src1, F32:$src2)), 0)),
354 (IntMI F32:$src2, F32:$src1)>;
355 def: Pat<(i1 (setne (i1 (cmpOp F32:$src1, F32:$src2)), 1)),
356 (C2_not (IntMI F32:$src2, F32:$src1))>;
359 def: Pat<(i1 (seteq (i1 (cmpOp F64:$src1, F64:$src2)), 0)),
360 (C2_not (DoubleMI F64:$src2, F64:$src1))>;
361 def: Pat<(i1 (seteq (i1 (cmpOp F64:$src1, F64:$src2)), 1)),
362 (DoubleMI F64:$src2, F64:$src1)>;
363 def: Pat<(i1 (setne (i1 (cmpOp F64:$src1, F64:$src2)), 0)),
364 (DoubleMI F64:$src2, F64:$src1)>;
365 def: Pat<(i1 (setne (i1 (cmpOp F64:$src1, F64:$src2)), 0)),
366 (C2_not (DoubleMI F64:$src2, F64:$src1))>;
369 defm : eq_ordltPats<setole, F2_sfcmpge, F2_dfcmpge>;
370 defm : eq_ordltPats<setolt, F2_sfcmpgt, F2_dfcmpgt>;
373 // o. seto inverse of setuo. http://llvm.org/docs/LangRef.html#i_fcmp
374 let Predicates = [HasV5T] in {
375 def: Pat<(i1 (seto F32:$src1, F32:$src2)),
376 (C2_not (F2_sfcmpuo F32:$src2, F32:$src1))>;
377 def: Pat<(i1 (seto F32:$src1, fpimm:$src2)),
378 (C2_not (F2_sfcmpuo (TFRI_f fpimm:$src2), F32:$src1))>;
379 def: Pat<(i1 (seto F64:$src1, F64:$src2)),
380 (C2_not (F2_dfcmpuo F64:$src2, F64:$src1))>;
381 def: Pat<(i1 (seto F64:$src1, fpimm:$src2)),
382 (C2_not (F2_dfcmpuo (CONST64_Float_Real fpimm:$src2), F64:$src1))>;
386 let Predicates = [HasV5T] in {
387 def: Pat<(i1 (setolt F32:$src1, F32:$src2)),
388 (F2_sfcmpgt F32:$src2, F32:$src1)>;
389 def: Pat<(i1 (setolt F32:$src1, fpimm:$src2)),
390 (F2_sfcmpgt (f32 (TFRI_f fpimm:$src2)), F32:$src1)>;
391 def: Pat<(i1 (setolt F64:$src1, F64:$src2)),
392 (F2_dfcmpgt F64:$src2, F64:$src1)>;
393 def: Pat<(i1 (setolt F64:$src1, fpimm:$src2)),
394 (F2_dfcmpgt (CONST64_Float_Real fpimm:$src2), F64:$src1)>;
398 let Predicates = [HasV5T] in {
399 def: Pat<(i1 (setult F32:$src1, F32:$src2)),
400 (C2_or (F2_sfcmpuo F32:$src1, F32:$src2),
401 (F2_sfcmpgt F32:$src2, F32:$src1))>;
402 def: Pat<(i1 (setult F32:$src1, fpimm:$src2)),
403 (C2_or (F2_sfcmpuo F32:$src1, (TFRI_f fpimm:$src2)),
404 (F2_sfcmpgt (TFRI_f fpimm:$src2), F32:$src1))>;
405 def: Pat<(i1 (setult F64:$src1, F64:$src2)),
406 (C2_or (F2_dfcmpuo F64:$src1, F64:$src2),
407 (F2_dfcmpgt F64:$src2, F64:$src1))>;
408 def: Pat<(i1 (setult F64:$src1, fpimm:$src2)),
409 (C2_or (F2_dfcmpuo F64:$src1, (CONST64_Float_Real fpimm:$src2)),
410 (F2_dfcmpgt (CONST64_Float_Real fpimm:$src2), F64:$src1))>;
414 let Predicates = [HasV5T] in {
415 // rs <= rt -> rt >= rs.
416 def: Pat<(i1 (setole F32:$src1, F32:$src2)),
417 (F2_sfcmpge F32:$src2, F32:$src1)>;
418 def: Pat<(i1 (setole F32:$src1, fpimm:$src2)),
419 (F2_sfcmpge (TFRI_f fpimm:$src2), F32:$src1)>;
421 // Rss <= Rtt -> Rtt >= Rss.
422 def: Pat<(i1 (setole F64:$src1, F64:$src2)),
423 (F2_dfcmpge F64:$src2, F64:$src1)>;
424 def: Pat<(i1 (setole F64:$src1, fpimm:$src2)),
425 (F2_dfcmpge (CONST64_Float_Real fpimm:$src2), F64:$src1)>;
429 let Predicates = [HasV5T] in {
430 // rs <= rt -> rt >= rs.
431 def: Pat<(i1 (setule F32:$src1, F32:$src2)),
432 (C2_or (F2_sfcmpuo F32:$src1, F32:$src2),
433 (F2_sfcmpge F32:$src2, F32:$src1))>;
434 def: Pat<(i1 (setule F32:$src1, fpimm:$src2)),
435 (C2_or (F2_sfcmpuo F32:$src1, (TFRI_f fpimm:$src2)),
436 (F2_sfcmpge (TFRI_f fpimm:$src2), F32:$src1))>;
437 def: Pat<(i1 (setule F64:$src1, F64:$src2)),
438 (C2_or (F2_dfcmpuo F64:$src1, F64:$src2),
439 (F2_dfcmpge F64:$src2, F64:$src1))>;
440 def: Pat<(i1 (setule F64:$src1, fpimm:$src2)),
441 (C2_or (F2_dfcmpuo F64:$src1, (CONST64_Float_Real fpimm:$src2)),
442 (F2_dfcmpge (CONST64_Float_Real fpimm:$src2), F64:$src1))>;
446 let Predicates = [HasV5T] in {
447 def: Pat<(i1 (setone F32:$src1, F32:$src2)),
448 (C2_not (F2_sfcmpeq F32:$src1, F32:$src2))>;
449 def: Pat<(i1 (setone F64:$src1, F64:$src2)),
450 (C2_not (F2_dfcmpeq F64:$src1, F64:$src2))>;
451 def: Pat<(i1 (setone F32:$src1, fpimm:$src2)),
452 (C2_not (F2_sfcmpeq F32:$src1, (TFRI_f fpimm:$src2)))>;
453 def: Pat<(i1 (setone F64:$src1, fpimm:$src2)),
454 (C2_not (F2_dfcmpeq F64:$src1, (CONST64_Float_Real fpimm:$src2)))>;
458 let Predicates = [HasV5T] in {
459 def: Pat<(i1 (setune F32:$src1, F32:$src2)),
460 (C2_or (F2_sfcmpuo F32:$src1, F32:$src2),
461 (C2_not (F2_sfcmpeq F32:$src1, F32:$src2)))>;
462 def: Pat<(i1 (setune F64:$src1, F64:$src2)),
463 (C2_or (F2_dfcmpuo F64:$src1, F64:$src2),
464 (C2_not (F2_dfcmpeq F64:$src1, F64:$src2)))>;
465 def: Pat<(i1 (setune F32:$src1, fpimm:$src2)),
466 (C2_or (F2_sfcmpuo F32:$src1, (TFRI_f fpimm:$src2)),
467 (C2_not (F2_sfcmpeq F32:$src1, (TFRI_f fpimm:$src2))))>;
468 def: Pat<(i1 (setune F64:$src1, fpimm:$src2)),
469 (C2_or (F2_dfcmpuo F64:$src1, (CONST64_Float_Real fpimm:$src2)),
470 (C2_not (F2_dfcmpeq F64:$src1,
471 (CONST64_Float_Real fpimm:$src2))))>;
474 // Besides set[o|u][comparions], we also need set[comparisons].
475 let Predicates = [HasV5T] in {
477 def: Pat<(i1 (setlt F32:$src1, F32:$src2)),
478 (F2_sfcmpgt F32:$src2, F32:$src1)>;
479 def: Pat<(i1 (setlt F32:$src1, fpimm:$src2)),
480 (F2_sfcmpgt (TFRI_f fpimm:$src2), F32:$src1)>;
481 def: Pat<(i1 (setlt F64:$src1, F64:$src2)),
482 (F2_dfcmpgt F64:$src2, F64:$src1)>;
483 def: Pat<(i1 (setlt F64:$src1, fpimm:$src2)),
484 (F2_dfcmpgt (CONST64_Float_Real fpimm:$src2), F64:$src1)>;
487 // rs <= rt -> rt >= rs.
488 def: Pat<(i1 (setle F32:$src1, F32:$src2)),
489 (F2_sfcmpge F32:$src2, F32:$src1)>;
490 def: Pat<(i1 (setle F32:$src1, fpimm:$src2)),
491 (F2_sfcmpge (TFRI_f fpimm:$src2), F32:$src1)>;
493 // Rss <= Rtt -> Rtt >= Rss.
494 def: Pat<(i1 (setle F64:$src1, F64:$src2)),
495 (F2_dfcmpge F64:$src2, F64:$src1)>;
496 def: Pat<(i1 (setle F64:$src1, fpimm:$src2)),
497 (F2_dfcmpge (CONST64_Float_Real fpimm:$src2), F64:$src1)>;
500 def: Pat<(i1 (setne F32:$src1, F32:$src2)),
501 (C2_not (F2_sfcmpeq F32:$src1, F32:$src2))>;
502 def: Pat<(i1 (setne F64:$src1, F64:$src2)),
503 (C2_not (F2_dfcmpeq F64:$src1, F64:$src2))>;
504 def: Pat<(i1 (setne F32:$src1, fpimm:$src2)),
505 (C2_not (F2_sfcmpeq F32:$src1, (TFRI_f fpimm:$src2)))>;
506 def: Pat<(i1 (setne F64:$src1, fpimm:$src2)),
507 (C2_not (F2_dfcmpeq F64:$src1, (CONST64_Float_Real fpimm:$src2)))>;
510 // F2 convert template classes:
512 class F2_RDD_RSS_CONVERT<string mnemonic, bits<3> MinOp,
513 SDNode Op, PatLeaf RCOut, PatLeaf RCIn,
515 : SInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss),
516 "$Rdd = "#mnemonic#"($Rss)"#chop,
517 [(set RCOut:$Rdd, (Op RCIn:$Rss))], "",
518 S_2op_tc_3or4x_SLOT23> {
524 let Inst{27-21} = 0b0000111;
525 let Inst{20-16} = Rss;
526 let Inst{7-5} = MinOp;
531 class F2_RDD_RS_CONVERT<string mnemonic, bits<3> MinOp,
532 SDNode Op, PatLeaf RCOut, PatLeaf RCIn,
534 : SInst <(outs DoubleRegs:$Rdd), (ins IntRegs:$Rs),
535 "$Rdd = "#mnemonic#"($Rs)"#chop,
536 [(set RCOut:$Rdd, (Op RCIn:$Rs))], "",
537 S_2op_tc_3or4x_SLOT23> {
543 let Inst{27-21} = 0b0100100;
544 let Inst{20-16} = Rs;
545 let Inst{7-5} = MinOp;
549 let isFP = 1, hasNewValue = 1 in
550 class F2_RD_RSS_CONVERT<string mnemonic, bits<3> MinOp,
551 SDNode Op, PatLeaf RCOut, PatLeaf RCIn,
553 : SInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss),
554 "$Rd = "#mnemonic#"($Rss)"#chop,
555 [(set RCOut:$Rd, (Op RCIn:$Rss))], "",
556 S_2op_tc_3or4x_SLOT23> {
562 let Inst{27-24} = 0b1000;
563 let Inst{23-21} = MinOp;
564 let Inst{20-16} = Rss;
565 let Inst{7-5} = 0b001;
569 let isFP = 1, hasNewValue = 1 in
570 class F2_RD_RS_CONVERT<string mnemonic, bits<3> MajOp, bits<3> MinOp,
571 SDNode Op, PatLeaf RCOut, PatLeaf RCIn,
573 : SInst <(outs IntRegs:$Rd), (ins IntRegs:$Rs),
574 "$Rd = "#mnemonic#"($Rs)"#chop,
575 [(set RCOut:$Rd, (Op RCIn:$Rs))], "",
576 S_2op_tc_3or4x_SLOT23> {
582 let Inst{27-24} = 0b1011;
583 let Inst{23-21} = MajOp;
584 let Inst{20-16} = Rs;
585 let Inst{7-5} = MinOp;
589 // Convert single precision to double precision and vice-versa.
590 def F2_conv_sf2df : F2_RDD_RS_CONVERT <"convert_sf2df", 0b000,
593 def F2_conv_df2sf : F2_RD_RSS_CONVERT <"convert_df2sf", 0b000,
596 // Convert Integer to Floating Point.
597 def F2_conv_d2sf : F2_RD_RSS_CONVERT <"convert_d2sf", 0b010,
598 sint_to_fp, F32, I64>;
599 def F2_conv_ud2sf : F2_RD_RSS_CONVERT <"convert_ud2sf", 0b001,
600 uint_to_fp, F32, I64>;
601 def F2_conv_uw2sf : F2_RD_RS_CONVERT <"convert_uw2sf", 0b001, 0b000,
602 uint_to_fp, F32, I32>;
603 def F2_conv_w2sf : F2_RD_RS_CONVERT <"convert_w2sf", 0b010, 0b000,
604 sint_to_fp, F32, I32>;
605 def F2_conv_d2df : F2_RDD_RSS_CONVERT <"convert_d2df", 0b011,
606 sint_to_fp, F64, I64>;
607 def F2_conv_ud2df : F2_RDD_RSS_CONVERT <"convert_ud2df", 0b010,
608 uint_to_fp, F64, I64>;
609 def F2_conv_uw2df : F2_RDD_RS_CONVERT <"convert_uw2df", 0b001,
610 uint_to_fp, F64, I32>;
611 def F2_conv_w2df : F2_RDD_RS_CONVERT <"convert_w2df", 0b010,
612 sint_to_fp, F64, I32>;
614 // Convert Floating Point to Integer - default.
615 def F2_conv_df2uw_chop : F2_RD_RSS_CONVERT <"convert_df2uw", 0b101,
616 fp_to_uint, I32, F64, ":chop">;
617 def F2_conv_df2w_chop : F2_RD_RSS_CONVERT <"convert_df2w", 0b111,
618 fp_to_sint, I32, F64, ":chop">;
619 def F2_conv_sf2uw_chop : F2_RD_RS_CONVERT <"convert_sf2uw", 0b011, 0b001,
620 fp_to_uint, I32, F32, ":chop">;
621 def F2_conv_sf2w_chop : F2_RD_RS_CONVERT <"convert_sf2w", 0b100, 0b001,
622 fp_to_sint, I32, F32, ":chop">;
623 def F2_conv_df2d_chop : F2_RDD_RSS_CONVERT <"convert_df2d", 0b110,
624 fp_to_sint, I64, F64, ":chop">;
625 def F2_conv_df2ud_chop : F2_RDD_RSS_CONVERT <"convert_df2ud", 0b111,
626 fp_to_uint, I64, F64, ":chop">;
627 def F2_conv_sf2d_chop : F2_RDD_RS_CONVERT <"convert_sf2d", 0b110,
628 fp_to_sint, I64, F32, ":chop">;
629 def F2_conv_sf2ud_chop : F2_RDD_RS_CONVERT <"convert_sf2ud", 0b101,
630 fp_to_uint, I64, F32, ":chop">;
632 // Convert Floating Point to Integer: non-chopped.
633 let AddedComplexity = 20, Predicates = [HasV5T, IEEERndNearV5T] in {
634 def F2_conv_df2d : F2_RDD_RSS_CONVERT <"convert_df2d", 0b000,
635 fp_to_sint, I64, F64>;
636 def F2_conv_df2ud : F2_RDD_RSS_CONVERT <"convert_df2ud", 0b001,
637 fp_to_uint, I64, F64>;
638 def F2_conv_sf2ud : F2_RDD_RS_CONVERT <"convert_sf2ud", 0b011,
639 fp_to_uint, I64, F32>;
640 def F2_conv_sf2d : F2_RDD_RS_CONVERT <"convert_sf2d", 0b100,
641 fp_to_sint, I64, F32>;
642 def F2_conv_df2uw : F2_RD_RSS_CONVERT <"convert_df2uw", 0b011,
643 fp_to_uint, I32, F64>;
644 def F2_conv_df2w : F2_RD_RSS_CONVERT <"convert_df2w", 0b100,
645 fp_to_sint, I32, F64>;
646 def F2_conv_sf2uw : F2_RD_RS_CONVERT <"convert_sf2uw", 0b011, 0b000,
647 fp_to_uint, I32, F32>;
648 def F2_conv_sf2w : F2_RD_RS_CONVERT <"convert_sf2w", 0b100, 0b000,
649 fp_to_sint, I32, F32>;
653 let isFP = 1, hasNewValue = 1 in
654 def F2_sffixupr: SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs),
655 "$Rd = sffixupr($Rs)",
656 [], "" , S_2op_tc_3or4x_SLOT23>, Requires<[HasV5T]> {
662 let Inst{27-21} = 0b1011101;
663 let Inst{20-16} = Rs;
664 let Inst{7-5} = 0b000;
668 // Bitcast is different than [fp|sint|uint]_to_[sint|uint|fp].
669 let Predicates = [HasV5T] in {
670 def: Pat <(i32 (bitconvert F32:$src)), (I32:$src)>;
671 def: Pat <(f32 (bitconvert I32:$src)), (F32:$src)>;
672 def: Pat <(i64 (bitconvert F64:$src)), (I64:$src)>;
673 def: Pat <(f64 (bitconvert I64:$src)), (F64:$src)>;
676 // F2_sffma: Floating-point fused multiply add.
677 let isFP = 1, hasNewValue = 1 in
678 class T_sfmpy_acc <bit isSub, bit isLib>
679 : MInst<(outs IntRegs:$Rx),
680 (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
681 "$Rx "#!if(isSub, "-=","+=")#" sfmpy($Rs, $Rt)"#!if(isLib, ":lib",""),
682 [], "$dst2 = $Rx" , M_tc_3_SLOT23 > ,
690 let Inst{27-21} = 0b1111000;
691 let Inst{20-16} = Rs;
700 def F2_sffma: T_sfmpy_acc <0, 0>;
701 def F2_sffms: T_sfmpy_acc <1, 0>;
702 def F2_sffma_lib: T_sfmpy_acc <0, 1>;
703 def F2_sffms_lib: T_sfmpy_acc <1, 1>;
705 // Floating-point fused multiply add w/ additional scaling (2**pu).
706 let isFP = 1, hasNewValue = 1 in
707 def F2_sffma_sc: MInst <
709 (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt, PredRegs:$Pu),
710 "$Rx += sfmpy($Rs, $Rt, $Pu):scale" ,
711 [], "$dst2 = $Rx" , M_tc_3_SLOT23 > ,
720 let Inst{27-21} = 0b1111011;
721 let Inst{20-16} = Rs;
729 let isExtended = 1, isExtentSigned = 1, opExtentBits = 8, opExtendable = 3,
730 isPseudo = 1, InputType = "imm" in
731 def MUX_ir_f : ALU32_rr<(outs IntRegs:$dst),
732 (ins PredRegs:$src1, IntRegs:$src2, f32Ext:$src3),
733 "$dst = mux($src1, $src2, #$src3)",
734 [(set F32:$dst, (f32 (select I1:$src1, F32:$src2, fpimm:$src3)))]>,
737 let isExtended = 1, isExtentSigned = 1, opExtentBits = 8, opExtendable = 2,
738 isPseudo = 1, InputType = "imm" in
739 def MUX_ri_f : ALU32_rr<(outs IntRegs:$dst),
740 (ins PredRegs:$src1, f32Ext:$src2, IntRegs:$src3),
741 "$dst = mux($src1, #$src2, $src3)",
742 [(set F32:$dst, (f32 (select I1:$src1, fpimm:$src2, F32:$src3)))]>,
745 //===----------------------------------------------------------------------===//
746 // :natural forms of vasrh and vasrhub insns
747 //===----------------------------------------------------------------------===//
748 // S5_asrhub_rnd_sat: Vector arithmetic shift right by immediate with round,
749 // saturate, and pack.
750 let Defs = [USR_OVF], hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
751 class T_ASRHUB<bit isSat>
752 : SInst <(outs IntRegs:$Rd),
753 (ins DoubleRegs:$Rss, u4Imm:$u4),
754 "$Rd = vasrhub($Rss, #$u4):"#!if(isSat, "sat", "raw"),
755 [], "", S_2op_tc_2_SLOT23>,
763 let Inst{27-21} = 0b1000011;
764 let Inst{20-16} = Rss;
765 let Inst{13-12} = 0b00;
767 let Inst{7-6} = 0b10;
772 def S5_asrhub_rnd_sat : T_ASRHUB <0>;
773 def S5_asrhub_sat : T_ASRHUB <1>;
775 let isAsmParserOnly = 1 in
776 def S5_asrhub_rnd_sat_goodsyntax
777 : SInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss, u4Imm:$u4),
778 "$Rd = vasrhub($Rss, #$u4):rnd:sat">, Requires<[HasV5T]>;
780 // S5_vasrhrnd: Vector arithmetic shift right by immediate with round.
781 let hasSideEffects = 0 in
782 def S5_vasrhrnd : SInst <(outs DoubleRegs:$Rdd),
783 (ins DoubleRegs:$Rss, u4Imm:$u4),
784 "$Rdd = vasrh($Rss, #$u4):raw">,
792 let Inst{27-21} = 0b0000001;
793 let Inst{20-16} = Rss;
794 let Inst{13-12} = 0b00;
796 let Inst{7-5} = 0b000;
800 let isAsmParserOnly = 1 in
801 def S5_vasrhrnd_goodsyntax
802 : SInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, u4Imm:$u4),
803 "$Rdd = vasrh($Rss,#$u4):rnd">, Requires<[HasV5T]>;
805 // Floating point reciprocal square root approximation
806 let Uses = [USR], isPredicateLate = 1, isFP = 1,
807 hasSideEffects = 0, hasNewValue = 1, opNewValue = 0,
808 validSubTargets = HasV5SubT in
809 def F2_sfinvsqrta: SInst <
810 (outs IntRegs:$Rd, PredRegs:$Pe),
812 "$Rd, $Pe = sfinvsqrta($Rs)" > ,
820 let Inst{27-21} = 0b1011111;
821 let Inst{20-16} = Rs;
827 // Complex multiply 32x16
828 let Defs = [USR_OVF], Itinerary = S_3op_tc_3x_SLOT23 in {
829 def M4_cmpyi_whc : T_S3op_8<"cmpyiwh", 0b101, 1, 1, 1, 1>;
830 def M4_cmpyr_whc : T_S3op_8<"cmpyrwh", 0b111, 1, 1, 1, 1>;
833 // Classify floating-point value
835 def F2_sfclass : T_TEST_BIT_IMM<"sfclass", 0b111>;
838 def F2_dfclass: ALU64Inst<(outs PredRegs:$Pd), (ins DoubleRegs:$Rss, u5Imm:$u5),
839 "$Pd = dfclass($Rss, #$u5)",
840 [], "" , ALU64_tc_2early_SLOT23 > , Requires<[HasV5T]> {
846 let Inst{27-21} = 0b1100100;
847 let Inst{20-16} = Rss;
848 let Inst{12-10} = 0b000;
850 let Inst{4-3} = 0b10;
854 // Instructions to create floating point constant
855 let hasNewValue = 1, opNewValue = 0 in
856 class T_fimm <string mnemonic, RegisterClass RC, bits<4> RegType, bit isNeg>
857 : ALU64Inst<(outs RC:$dst), (ins u10Imm:$src),
858 "$dst = "#mnemonic#"(#$src)"#!if(isNeg, ":neg", ":pos"),
859 [], "", ALU64_tc_3x_SLOT23>, Requires<[HasV5T]> {
864 let Inst{27-24} = RegType;
866 let Inst{22} = isNeg;
867 let Inst{21} = src{9};
868 let Inst{13-5} = src{8-0};
872 def F2_sfimm_p : T_fimm <"sfmake", IntRegs, 0b0110, 0>;
873 def F2_sfimm_n : T_fimm <"sfmake", IntRegs, 0b0110, 1>;
874 def F2_dfimm_p : T_fimm <"dfmake", DoubleRegs, 0b1001, 0>;
875 def F2_dfimm_n : T_fimm <"dfmake", DoubleRegs, 0b1001, 1>;
877 def : Pat <(fabs (f32 IntRegs:$src1)),
878 (S2_clrbit_i (f32 IntRegs:$src1), 31)>,
881 def : Pat <(fneg (f32 IntRegs:$src1)),
882 (S2_togglebit_i (f32 IntRegs:$src1), 31)>,
886 def : Pat <(fabs (f64 DoubleRegs:$src1)),
887 (S2_clrbit_i (f32 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_hireg)), 31)>,
890 def : Pat <(fabs (f64 DoubleRegs:$src1)),
891 (S2_clrbit_i (f32 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_hireg)), 31)>,