lib/Target/Hexagon/HexagonInstrInfoV4.td

   1 //=- HexagonInstrInfoV4.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes the Hexagon V4 instructions in TableGen format.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 let neverHasSideEffects = 1 in
  15 def IMMEXT : Immext<(outs), (ins),
  16                     "/* immext #... */",
  17                     []>,
  18              Requires<[HasV4T]>;
  19
  20 // Hexagon V4 Architecture spec defines 8 instruction classes:
  21 // LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the
  22 // compiler)
  23
  24 // LD Instructions:
  25 // ========================================
  26 // Loads (8/16/32/64 bit)
  27 // Deallocframe
  28
  29 // ST Instructions:
  30 // ========================================
  31 // Stores (8/16/32/64 bit)
  32 // Allocframe
  33
  34 // ALU32 Instructions:
  35 // ========================================
  36 // Arithmetic / Logical (32 bit)
  37 // Vector Halfword
  38
  39 // XTYPE Instructions (32/64 bit):
  40 // ========================================
  41 // Arithmetic, Logical, Bit Manipulation
  42 // Multiply (Integer, Fractional, Complex)
  43 // Permute / Vector Permute Operations
  44 // Predicate Operations
  45 // Shift / Shift with Add/Sub/Logical
  46 // Vector Byte ALU
  47 // Vector Halfword (ALU, Shift, Multiply)
  48 // Vector Word (ALU, Shift)
  49
  50 // J Instructions:
  51 // ========================================
  52 // Jump/Call PC-relative
  53
  54 // JR Instructions:
  55 // ========================================
  56 // Jump/Call Register
  57
  58 // MEMOP Instructions:
  59 // ========================================
  60 // Operation on memory (8/16/32 bit)
  61
  62 // NV Instructions:
  63 // ========================================
  64 // New-value Jumps
  65 // New-value Stores
  66
  67 // CR Instructions:
  68 // ========================================
  69 // Control-Register Transfers
  70 // Hardware Loop Setup
  71 // Predicate Logicals & Reductions
  72
  73 // SYSTEM Instructions (not implemented in the compiler):
  74 // ========================================
  75 // Prefetch
  76 // Cache Maintenance
  77 // Bus Operations
  78
  79
  80 //===----------------------------------------------------------------------===//
  81 // ALU32 +
  82 //===----------------------------------------------------------------------===//
  83
  84 // Shift halfword.
  85
  86 let isPredicated = 1 in
  87 def ASLH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
  88             (ins PredRegs:$src1, IntRegs:$src2),
  89             "if ($src1) $dst = aslh($src2)",
  90             []>,
  91             Requires<[HasV4T]>;
  92
  93 let isPredicated = 1 in
  94 def ASLH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
  95             (ins PredRegs:$src1, IntRegs:$src2),
  96             "if (!$src1) $dst = aslh($src2)",
  97             []>,
  98             Requires<[HasV4T]>;
  99
 100 let isPredicated = 1 in
 101 def ASLH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 102             (ins PredRegs:$src1, IntRegs:$src2),
 103             "if ($src1.new) $dst = aslh($src2)",
 104             []>,
 105             Requires<[HasV4T]>;
 106
 107 let isPredicated = 1 in
 108 def ASLH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 109             (ins PredRegs:$src1, IntRegs:$src2),
 110             "if (!$src1.new) $dst = aslh($src2)",
 111             []>,
 112             Requires<[HasV4T]>;
 113
 114 let isPredicated = 1 in
 115 def ASRH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 116             (ins PredRegs:$src1, IntRegs:$src2),
 117             "if ($src1) $dst = asrh($src2)",
 118             []>,
 119             Requires<[HasV4T]>;
 120
 121 let isPredicated = 1 in
 122 def ASRH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 123             (ins PredRegs:$src1, IntRegs:$src2),
 124             "if (!$src1) $dst = asrh($src2)",
 125             []>,
 126             Requires<[HasV4T]>;
 127
 128 let isPredicated = 1 in
 129 def ASRH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 130             (ins PredRegs:$src1, IntRegs:$src2),
 131             "if ($src1.new) $dst = asrh($src2)",
 132             []>,
 133             Requires<[HasV4T]>;
 134
 135 let isPredicated = 1 in
 136 def ASRH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 137             (ins PredRegs:$src1, IntRegs:$src2),
 138             "if (!$src1.new) $dst = asrh($src2)",
 139             []>,
 140             Requires<[HasV4T]>;
 141
 142 // Sign extend.
 143
 144 let isPredicated = 1 in
 145 def SXTB_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 146             (ins PredRegs:$src1, IntRegs:$src2),
 147             "if ($src1) $dst = sxtb($src2)",
 148             []>,
 149             Requires<[HasV4T]>;
 150
 151 let isPredicated = 1 in
 152 def SXTB_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 153             (ins PredRegs:$src1, IntRegs:$src2),
 154             "if (!$src1) $dst = sxtb($src2)",
 155             []>,
 156             Requires<[HasV4T]>;
 157
 158 let isPredicated = 1 in
 159 def SXTB_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 160             (ins PredRegs:$src1, IntRegs:$src2),
 161             "if ($src1.new) $dst = sxtb($src2)",
 162             []>,
 163             Requires<[HasV4T]>;
 164
 165 let isPredicated = 1 in
 166 def SXTB_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 167             (ins PredRegs:$src1, IntRegs:$src2),
 168             "if (!$src1.new) $dst = sxtb($src2)",
 169             []>,
 170             Requires<[HasV4T]>;
 171
 172
 173 let isPredicated = 1 in
 174 def SXTH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 175             (ins PredRegs:$src1, IntRegs:$src2),
 176             "if ($src1) $dst = sxth($src2)",
 177             []>,
 178             Requires<[HasV4T]>;
 179
 180 let isPredicated = 1 in
 181 def SXTH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 182             (ins PredRegs:$src1, IntRegs:$src2),
 183             "if (!$src1) $dst = sxth($src2)",
 184             []>,
 185             Requires<[HasV4T]>;
 186
 187 let isPredicated = 1 in
 188 def SXTH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 189             (ins PredRegs:$src1, IntRegs:$src2),
 190             "if ($src1.new) $dst = sxth($src2)",
 191             []>,
 192             Requires<[HasV4T]>;
 193
 194 let isPredicated = 1 in
 195 def SXTH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 196             (ins PredRegs:$src1, IntRegs:$src2),
 197             "if (!$src1.new) $dst = sxth($src2)",
 198             []>,
 199             Requires<[HasV4T]>;
 200
 201 // Zero exten.
 202
 203 let neverHasSideEffects = 1, isPredicated = 1 in
 204 def ZXTB_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 205             (ins PredRegs:$src1, IntRegs:$src2),
 206             "if ($src1) $dst = zxtb($src2)",
 207             []>,
 208             Requires<[HasV4T]>;
 209
 210 let neverHasSideEffects = 1, isPredicated = 1 in
 211 def ZXTB_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 212             (ins PredRegs:$src1, IntRegs:$src2),
 213             "if (!$src1) $dst = zxtb($src2)",
 214             []>,
 215             Requires<[HasV4T]>;
 216
 217 let neverHasSideEffects = 1, isPredicated = 1 in
 218 def ZXTB_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 219             (ins PredRegs:$src1, IntRegs:$src2),
 220             "if ($src1.new) $dst = zxtb($src2)",
 221             []>,
 222             Requires<[HasV4T]>;
 223
 224 let neverHasSideEffects = 1, isPredicated = 1 in
 225 def ZXTB_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 226             (ins PredRegs:$src1, IntRegs:$src2),
 227             "if (!$src1.new) $dst = zxtb($src2)",
 228             []>,
 229             Requires<[HasV4T]>;
 230
 231 let neverHasSideEffects = 1, isPredicated = 1 in
 232 def ZXTH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 233             (ins PredRegs:$src1, IntRegs:$src2),
 234             "if ($src1) $dst = zxth($src2)",
 235             []>,
 236             Requires<[HasV4T]>;
 237
 238 let neverHasSideEffects = 1, isPredicated = 1 in
 239 def ZXTH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 240             (ins PredRegs:$src1, IntRegs:$src2),
 241             "if (!$src1) $dst = zxth($src2)",
 242             []>,
 243             Requires<[HasV4T]>;
 244
 245 let neverHasSideEffects = 1, isPredicated = 1 in
 246 def ZXTH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 247             (ins PredRegs:$src1, IntRegs:$src2),
 248             "if ($src1.new) $dst = zxth($src2)",
 249             []>,
 250             Requires<[HasV4T]>;
 251
 252 let neverHasSideEffects = 1, isPredicated = 1 in
 253 def ZXTH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 254             (ins PredRegs:$src1, IntRegs:$src2),
 255             "if (!$src1.new) $dst = zxth($src2)",
 256             []>,
 257             Requires<[HasV4T]>;
 258
 259 // Generate frame index addresses.
 260 let neverHasSideEffects = 1, isReMaterializable = 1 in
 261 def TFR_FI_immext_V4 : ALU32_ri<(outs IntRegs:$dst),
 262             (ins IntRegs:$src1, s32Imm:$offset),
 263             "$dst = add($src1, ##$offset)",
 264             []>,
 265             Requires<[HasV4T]>;
 266
 267
 268 //===----------------------------------------------------------------------===//
 269 // ALU32 -
 270 //===----------------------------------------------------------------------===//
 271
 272
 273 //===----------------------------------------------------------------------===//
 274 // ALU32/PERM +
 275 //===----------------------------------------------------------------------===//
 276
 277 // Combine
 278 // Rdd=combine(Rs, #s8)
 279 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8,
 280     neverHasSideEffects = 1, validSubTargets = HasV4SubT in
 281 def COMBINE_rI_V4 : ALU32_ri<(outs DoubleRegs:$dst),
 282             (ins IntRegs:$src1, s8Ext:$src2),
 283             "$dst = combine($src1, #$src2)",
 284             []>,
 285             Requires<[HasV4T]>;
 286
 287 // Rdd=combine(#s8, Rs)
 288 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 8,
 289     neverHasSideEffects = 1, validSubTargets = HasV4SubT in
 290 def COMBINE_Ir_V4 : ALU32_ir<(outs DoubleRegs:$dst),
 291             (ins s8Ext:$src1, IntRegs:$src2),
 292             "$dst = combine(#$src1, $src2)",
 293             []>,
 294             Requires<[HasV4T]>;
 295
 296 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 6,
 297     neverHasSideEffects = 1, validSubTargets = HasV4SubT in
 298 def COMBINE_iI_V4 : ALU32_ii<(outs DoubleRegs:$dst),
 299             (ins s8Imm:$src1, u6Ext:$src2),
 300             "$dst = combine(#$src1, #$src2)",
 301             []>,
 302             Requires<[HasV4T]>;
 303
 304 //===----------------------------------------------------------------------===//
 305 // ALU32/PERM +
 306 //===----------------------------------------------------------------------===//
 307
 308 //===----------------------------------------------------------------------===//
 309 // LD +
 310 //===----------------------------------------------------------------------===//
 311 //
 312 // These absolute set addressing mode instructions accept immediate as
 313 // an operand. We have duplicated these patterns to take global address.
 314
 315 let neverHasSideEffects = 1 in
 316 def LDrid_abs_setimm_V4 : LDInst2<(outs DoubleRegs:$dst1, IntRegs:$dst2),
 317             (ins u6Imm:$addr),
 318             "$dst1 = memd($dst2=#$addr)",
 319             []>,
 320             Requires<[HasV4T]>;
 321
 322 // Rd=memb(Re=#U6)
 323 let neverHasSideEffects = 1 in
 324 def LDrib_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 325             (ins u6Imm:$addr),
 326             "$dst1 = memb($dst2=#$addr)",
 327             []>,
 328             Requires<[HasV4T]>;
 329
 330 // Rd=memh(Re=#U6)
 331 let neverHasSideEffects = 1 in
 332 def LDrih_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 333             (ins u6Imm:$addr),
 334             "$dst1 = memh($dst2=#$addr)",
 335             []>,
 336             Requires<[HasV4T]>;
 337
 338 // Rd=memub(Re=#U6)
 339 let neverHasSideEffects = 1 in
 340 def LDriub_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 341             (ins u6Imm:$addr),
 342             "$dst1 = memub($dst2=#$addr)",
 343             []>,
 344             Requires<[HasV4T]>;
 345
 346 // Rd=memuh(Re=#U6)
 347 let neverHasSideEffects = 1 in
 348 def LDriuh_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 349             (ins u6Imm:$addr),
 350             "$dst1 = memuh($dst2=#$addr)",
 351             []>,
 352             Requires<[HasV4T]>;
 353
 354 // Rd=memw(Re=#U6)
 355 let neverHasSideEffects = 1 in
 356 def LDriw_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 357             (ins u6Imm:$addr),
 358             "$dst1 = memw($dst2=#$addr)",
 359             []>,
 360             Requires<[HasV4T]>;
 361
 362 // Following patterns are defined for absolute set addressing mode
 363 // instruction which take global address as operand.
 364 let neverHasSideEffects = 1 in
 365 def LDrid_abs_set_V4 : LDInst2<(outs DoubleRegs:$dst1, IntRegs:$dst2),
 366             (ins globaladdress:$addr),
 367             "$dst1 = memd($dst2=##$addr)",
 368             []>,
 369             Requires<[HasV4T]>;
 370
 371 // Rd=memb(Re=#U6)
 372 let neverHasSideEffects = 1 in
 373 def LDrib_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 374             (ins globaladdress:$addr),
 375             "$dst1 = memb($dst2=##$addr)",
 376             []>,
 377             Requires<[HasV4T]>;
 378
 379 // Rd=memh(Re=#U6)
 380 let neverHasSideEffects = 1 in
 381 def LDrih_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 382             (ins globaladdress:$addr),
 383             "$dst1 = memh($dst2=##$addr)",
 384             []>,
 385             Requires<[HasV4T]>;
 386
 387 // Rd=memub(Re=#U6)
 388 let neverHasSideEffects = 1 in
 389 def LDriub_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 390             (ins globaladdress:$addr),
 391             "$dst1 = memub($dst2=##$addr)",
 392             []>,
 393             Requires<[HasV4T]>;
 394
 395 // Rd=memuh(Re=#U6)
 396 let neverHasSideEffects = 1 in
 397 def LDriuh_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 398             (ins globaladdress:$addr),
 399             "$dst1 = memuh($dst2=##$addr)",
 400             []>,
 401             Requires<[HasV4T]>;
 402
 403 // Rd=memw(Re=#U6)
 404 let neverHasSideEffects = 1 in
 405 def LDriw_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 406             (ins globaladdress:$addr),
 407             "$dst1 = memw($dst2=##$addr)",
 408             []>,
 409             Requires<[HasV4T]>;
 410
 411 // Load doubleword.
 412 //
 413 // Make sure that in post increment load, the first operand is always the post
 414 // increment operand.
 415 //
 416 // Rdd=memd(Rs+Rt<<#u2)
 417 // Special case pattern for indexed load without offset which is easier to
 418 // match. AddedComplexity of this pattern should be lower than base+offset load
 419 // and lower yet than the more generic version with offset/shift below
 420 // Similar approach is taken for all other base+index loads.
 421 let AddedComplexity = 10, isPredicable = 1 in
 422 def LDrid_indexed_V4 : LDInst<(outs DoubleRegs:$dst),
 423                     (ins IntRegs:$src1, IntRegs:$src2),
 424                     "$dst=memd($src1+$src2<<#0)",
 425                     [(set (i64 DoubleRegs:$dst),
 426                           (i64 (load (add (i32 IntRegs:$src1),
 427                                           (i32 IntRegs:$src2)))))]>,
 428                     Requires<[HasV4T]>;
 429
 430 // multiclass for load instructions with base + register offset
 431 // addressing mode
 432 multiclass ld_idxd_shl_pbase<string mnemonic, RegisterClass RC, bit isNot,
 433                              bit isPredNew> {
 434   let PNewValue = #!if(isPredNew, "new", "") in
 435   def #NAME# : LDInst2<(outs RC:$dst),
 436             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset),
 437             !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
 438             ") ")#"$dst = "#mnemonic#"($src2+$src3<<#$offset)",
 439             []>, Requires<[HasV4T]>;
 440 }
 441
 442 multiclass ld_idxd_shl_pred<string mnemonic, RegisterClass RC, bit PredNot> {
 443   let PredSense = #!if(PredNot, "false", "true") in {
 444     defm _c#NAME# : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 0>;
 445     // Predicate new
 446     defm _cdn#NAME# : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 1>;
 447   }
 448 }
 449
 450 let neverHasSideEffects  = 1 in
 451 multiclass ld_idxd_shl<string mnemonic, string CextOp, RegisterClass RC> {
 452   let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
 453     let isPredicable = 1 in
 454     def #NAME#_V4 : LDInst2<(outs RC:$dst),
 455             (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
 456             "$dst = "#mnemonic#"($src1+$src2<<#$offset)",
 457             []>, Requires<[HasV4T]>;
 458
 459     let isPredicated = 1 in {
 460       defm Pt_V4 : ld_idxd_shl_pred<mnemonic, RC, 0 >;
 461       defm NotPt_V4 : ld_idxd_shl_pred<mnemonic, RC, 1>;
 462     }
 463   }
 464 }
 465
 466 let addrMode = BaseRegOffset in {
 467   defm LDrib_indexed_shl: ld_idxd_shl<"memb", "LDrib", IntRegs>, AddrModeRel;
 468   defm LDriub_indexed_shl: ld_idxd_shl<"memub", "LDriub", IntRegs>, AddrModeRel;
 469   defm LDrih_indexed_shl: ld_idxd_shl<"memh", "LDrih", IntRegs>, AddrModeRel;
 470   defm LDriuh_indexed_shl: ld_idxd_shl<"memuh", "LDriuh", IntRegs>, AddrModeRel;
 471   defm LDriw_indexed_shl: ld_idxd_shl<"memw", "LDriw", IntRegs>, AddrModeRel;
 472   defm LDrid_indexed_shl: ld_idxd_shl<"memd", "LDrid", DoubleRegs>, AddrModeRel;
 473 }
 474
 475 // 'def pats' for load instructions with base + register offset and non-zero
 476 // immediate value. Immediate value is used to left-shift the second
 477 // register operand.
 478 let AddedComplexity = 40 in {
 479 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1,
 480                                  (shl IntRegs:$src2, u2ImmPred:$offset)))),
 481            (LDrib_indexed_shl_V4 IntRegs:$src1,
 482             IntRegs:$src2, u2ImmPred:$offset)>,
 483             Requires<[HasV4T]>;
 484
 485 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1,
 486                                  (shl IntRegs:$src2, u2ImmPred:$offset)))),
 487            (LDriub_indexed_shl_V4 IntRegs:$src1,
 488             IntRegs:$src2, u2ImmPred:$offset)>,
 489             Requires<[HasV4T]>;
 490
 491 def : Pat <(i32 (extloadi8 (add IntRegs:$src1,
 492                                 (shl IntRegs:$src2, u2ImmPred:$offset)))),
 493            (LDriub_indexed_shl_V4 IntRegs:$src1,
 494             IntRegs:$src2, u2ImmPred:$offset)>,
 495             Requires<[HasV4T]>;
 496
 497 def : Pat <(i32 (sextloadi16 (add IntRegs:$src1,
 498                                   (shl IntRegs:$src2, u2ImmPred:$offset)))),
 499            (LDrih_indexed_shl_V4 IntRegs:$src1,
 500             IntRegs:$src2, u2ImmPred:$offset)>,
 501             Requires<[HasV4T]>;
 502
 503 def : Pat <(i32 (zextloadi16 (add IntRegs:$src1,
 504                                   (shl IntRegs:$src2, u2ImmPred:$offset)))),
 505            (LDriuh_indexed_shl_V4 IntRegs:$src1,
 506             IntRegs:$src2, u2ImmPred:$offset)>,
 507             Requires<[HasV4T]>;
 508
 509 def : Pat <(i32 (extloadi16 (add IntRegs:$src1,
 510                                  (shl IntRegs:$src2, u2ImmPred:$offset)))),
 511            (LDriuh_indexed_shl_V4 IntRegs:$src1,
 512             IntRegs:$src2, u2ImmPred:$offset)>,
 513             Requires<[HasV4T]>;
 514
 515 def : Pat <(i32 (load (add IntRegs:$src1,
 516                            (shl IntRegs:$src2, u2ImmPred:$offset)))),
 517            (LDriw_indexed_shl_V4 IntRegs:$src1,
 518             IntRegs:$src2, u2ImmPred:$offset)>,
 519             Requires<[HasV4T]>;
 520
 521 def : Pat <(i64 (load (add IntRegs:$src1,
 522                            (shl IntRegs:$src2, u2ImmPred:$offset)))),
 523            (LDrid_indexed_shl_V4 IntRegs:$src1,
 524             IntRegs:$src2, u2ImmPred:$offset)>,
 525             Requires<[HasV4T]>;
 526 }
 527
 528 //// Load doubleword conditionally.
 529 // if ([!]Pv[.new]) Rd=memd(Rs+Rt<<#u2)
 530 // if (Pv) Rd=memd(Rs+Rt<<#u2)
 531 let AddedComplexity = 15, isPredicated = 1 in
 532 def LDrid_indexed_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 533                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 534                     "if ($src1) $dst=memd($src2+$src3<<#0)",
 535                     []>,
 536                     Requires<[HasV4T]>;
 537
 538 // if (Pv.new) Rd=memd(Rs+Rt<<#u2)
 539 let AddedComplexity = 15, isPredicated = 1 in
 540 def LDrid_indexed_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 541                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 542                     "if ($src1.new) $dst=memd($src2+$src3<<#0)",
 543                     []>,
 544                     Requires<[HasV4T]>;
 545
 546 // if (!Pv) Rd=memd(Rs+Rt<<#u2)
 547 let AddedComplexity = 15, isPredicated = 1 in
 548 def LDrid_indexed_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 549                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 550                     "if (!$src1) $dst=memd($src2+$src3<<#0)",
 551                     []>,
 552                     Requires<[HasV4T]>;
 553
 554 // if (!Pv.new) Rd=memd(Rs+Rt<<#u2)
 555 let AddedComplexity = 15, isPredicated = 1 in
 556 def LDrid_indexed_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 557                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 558                     "if (!$src1.new) $dst=memd($src2+$src3<<#0)",
 559                     []>,
 560                     Requires<[HasV4T]>;
 561
 562 // Rdd=memd(Rt<<#u2+#U6)
 563
 564 //// Load byte.
 565 // Rd=memb(Rs+Rt<<#u2)
 566 let AddedComplexity = 10, isPredicable = 1 in
 567 def LDrib_indexed_V4 : LDInst<(outs IntRegs:$dst),
 568                     (ins IntRegs:$src1, IntRegs:$src2),
 569                     "$dst=memb($src1+$src2<<#0)",
 570                     [(set (i32 IntRegs:$dst),
 571                           (i32 (sextloadi8 (add (i32 IntRegs:$src1),
 572                                                 (i32 IntRegs:$src2)))))]>,
 573                     Requires<[HasV4T]>;
 574
 575 let AddedComplexity = 10, isPredicable = 1 in
 576 def LDriub_indexed_V4 : LDInst<(outs IntRegs:$dst),
 577                     (ins IntRegs:$src1, IntRegs:$src2),
 578                     "$dst=memub($src1+$src2<<#0)",
 579                     [(set (i32 IntRegs:$dst),
 580                           (i32 (zextloadi8 (add (i32 IntRegs:$src1),
 581                                                 (i32 IntRegs:$src2)))))]>,
 582                     Requires<[HasV4T]>;
 583
 584 let AddedComplexity = 10, isPredicable = 1 in
 585 def LDriub_ae_indexed_V4 : LDInst<(outs IntRegs:$dst),
 586                     (ins IntRegs:$src1, IntRegs:$src2),
 587                     "$dst=memub($src1+$src2<<#0)",
 588                     [(set (i32 IntRegs:$dst),
 589                           (i32 (extloadi8 (add (i32 IntRegs:$src1),
 590                                                (i32 IntRegs:$src2)))))]>,
 591                     Requires<[HasV4T]>;
 592
 593 let AddedComplexity = 40, isPredicable = 1 in
 594 def LDriub_ae_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
 595                     (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
 596                     "$dst=memub($src1+$src2<<#$offset)",
 597                     [(set (i32 IntRegs:$dst),
 598                           (i32 (extloadi8 (add (i32 IntRegs:$src1),
 599                                                (shl (i32 IntRegs:$src2),
 600                                                     u2ImmPred:$offset)))))]>,
 601                     Requires<[HasV4T]>;
 602
 603 //// Load byte conditionally.
 604 // if ([!]Pv[.new]) Rd=memb(Rs+Rt<<#u2)
 605 // if (Pv) Rd=memb(Rs+Rt<<#u2)
 606 let AddedComplexity = 15, isPredicated = 1 in
 607 def LDrib_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 608                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 609                     "if ($src1) $dst=memb($src2+$src3<<#0)",
 610                     []>,
 611                     Requires<[HasV4T]>;
 612
 613 // if (Pv.new) Rd=memb(Rs+Rt<<#u2)
 614 let AddedComplexity = 15, isPredicated = 1 in
 615 def LDrib_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 616                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 617                     "if ($src1.new) $dst=memb($src2+$src3<<#0)",
 618                     []>,
 619                     Requires<[HasV4T]>;
 620
 621 // if (!Pv) Rd=memb(Rs+Rt<<#u2)
 622 let AddedComplexity = 15, isPredicated = 1 in
 623 def LDrib_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 624                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 625                     "if (!$src1) $dst=memb($src2+$src3<<#0)",
 626                     []>,
 627                     Requires<[HasV4T]>;
 628
 629 // if (!Pv.new) Rd=memb(Rs+Rt<<#u2)
 630 let AddedComplexity = 15, isPredicated = 1 in
 631 def LDrib_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 632                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 633                     "if (!$src1.new) $dst=memb($src2+$src3<<#0)",
 634                     []>,
 635                     Requires<[HasV4T]>;
 636
 637 //// Load unsigned byte conditionally.
 638 // if ([!]Pv[.new]) Rd=memub(Rs+Rt<<#u2)
 639 // if (Pv) Rd=memub(Rs+Rt<<#u2)
 640 let AddedComplexity = 15, isPredicated = 1 in
 641 def LDriub_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 642                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 643                     "if ($src1) $dst=memub($src2+$src3<<#0)",
 644                     []>,
 645                     Requires<[HasV4T]>;
 646
 647 // if (Pv.new) Rd=memub(Rs+Rt<<#u2)
 648 let AddedComplexity = 15, isPredicated = 1 in
 649 def LDriub_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 650                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 651                     "if ($src1.new) $dst=memub($src2+$src3<<#0)",
 652                     []>,
 653                     Requires<[HasV4T]>;
 654
 655 // if (!Pv) Rd=memub(Rs+Rt<<#u2)
 656 let AddedComplexity = 15, isPredicated = 1 in
 657 def LDriub_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 658                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 659                     "if (!$src1) $dst=memub($src2+$src3<<#0)",
 660                     []>,
 661                     Requires<[HasV4T]>;
 662
 663 // if (!Pv.new) Rd=memub(Rs+Rt<<#u2)
 664 let AddedComplexity = 15, isPredicated = 1 in
 665 def LDriub_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 666                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 667                     "if (!$src1.new) $dst=memub($src2+$src3<<#0)",
 668                     []>,
 669                     Requires<[HasV4T]>;
 670
 671 // Rd=memb(Rt<<#u2+#U6)
 672
 673 //// Load halfword
 674 // Rd=memh(Rs+Rt<<#u2)
 675 let AddedComplexity = 10, isPredicable = 1 in
 676 def LDrih_indexed_V4 : LDInst<(outs IntRegs:$dst),
 677                     (ins IntRegs:$src1, IntRegs:$src2),
 678                     "$dst=memh($src1+$src2<<#0)",
 679                     [(set (i32 IntRegs:$dst),
 680                           (i32 (sextloadi16 (add (i32 IntRegs:$src1),
 681                                                  (i32 IntRegs:$src2)))))]>,
 682                     Requires<[HasV4T]>;
 683
 684 let AddedComplexity = 10, isPredicable = 1 in
 685 def LDriuh_indexed_V4 : LDInst<(outs IntRegs:$dst),
 686                     (ins IntRegs:$src1, IntRegs:$src2),
 687                     "$dst=memuh($src1+$src2<<#0)",
 688                     [(set (i32 IntRegs:$dst),
 689                           (i32 (zextloadi16 (add (i32 IntRegs:$src1),
 690                                                  (i32 IntRegs:$src2)))))]>,
 691                     Requires<[HasV4T]>;
 692
 693 let AddedComplexity = 10, isPredicable = 1 in
 694 def LDriuh_ae_indexed_V4 : LDInst<(outs IntRegs:$dst),
 695                     (ins IntRegs:$src1, IntRegs:$src2),
 696                     "$dst=memuh($src1+$src2<<#0)",
 697                     [(set (i32 IntRegs:$dst),
 698                           (i32 (extloadi16 (add (i32 IntRegs:$src1),
 699                                                 (i32 IntRegs:$src2)))))]>,
 700                     Requires<[HasV4T]>;
 701
 702 let AddedComplexity = 40, isPredicable = 1 in
 703 def LDriuh_ae_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
 704                     (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
 705                     "$dst=memuh($src1+$src2<<#$offset)",
 706                     [(set (i32 IntRegs:$dst),
 707                           (i32 (extloadi16 (add (i32 IntRegs:$src1),
 708                                                 (shl (i32 IntRegs:$src2),
 709                                                      u2ImmPred:$offset)))))]>,
 710                     Requires<[HasV4T]>;
 711
 712 //// Load halfword conditionally.
 713 // if ([!]Pv[.new]) Rd=memh(Rs+Rt<<#u2)
 714 // if (Pv) Rd=memh(Rs+Rt<<#u2)
 715 let AddedComplexity = 15, isPredicated = 1 in
 716 def LDrih_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 717                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 718                     "if ($src1) $dst=memh($src2+$src3<<#0)",
 719                     []>,
 720                     Requires<[HasV4T]>;
 721
 722 // if (Pv.new) Rd=memh(Rs+Rt<<#u2)
 723 let AddedComplexity = 15, isPredicated = 1 in
 724 def LDrih_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 725                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 726                     "if ($src1.new) $dst=memh($src2+$src3<<#0)",
 727                     []>,
 728                     Requires<[HasV4T]>;
 729
 730 // if (!Pv) Rd=memh(Rs+Rt<<#u2)
 731 let AddedComplexity = 15, isPredicated = 1 in
 732 def LDrih_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 733                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 734                     "if (!$src1) $dst=memh($src2+$src3<<#0)",
 735                     []>,
 736                     Requires<[HasV4T]>;
 737
 738 // if (!Pv.new) Rd=memh(Rs+Rt<<#u2)
 739 let AddedComplexity = 15, isPredicated = 1 in
 740 def LDrih_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 741                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 742                     "if (!$src1.new) $dst=memh($src2+$src3<<#0)",
 743                     []>,
 744                     Requires<[HasV4T]>;
 745
 746 //// Load unsigned halfword conditionally.
 747 // if ([!]Pv[.new]) Rd=memuh(Rs+Rt<<#u2)
 748 // if (Pv) Rd=memuh(Rs+Rt<<#u2)
 749 let AddedComplexity = 15, isPredicated = 1 in
 750 def LDriuh_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 751                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 752                     "if ($src1) $dst=memuh($src2+$src3<<#0)",
 753                     []>,
 754                     Requires<[HasV4T]>;
 755
 756 // if (Pv.new) Rd=memuh(Rs+Rt<<#u2)
 757 let AddedComplexity = 15, isPredicated = 1 in
 758 def LDriuh_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 759                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 760                     "if ($src1.new) $dst=memuh($src2+$src3<<#0)",
 761                     []>,
 762                     Requires<[HasV4T]>;
 763
 764 // if (!Pv) Rd=memuh(Rs+Rt<<#u2)
 765 let AddedComplexity = 15, isPredicated = 1 in
 766 def LDriuh_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 767                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 768                     "if (!$src1) $dst=memuh($src2+$src3<<#0)",
 769                     []>,
 770                     Requires<[HasV4T]>;
 771
 772 // if (!Pv.new) Rd=memuh(Rs+Rt<<#u2)
 773 let AddedComplexity = 15, isPredicated = 1 in
 774 def LDriuh_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 775                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 776                     "if (!$src1.new) $dst=memuh($src2+$src3<<#0)",
 777                     []>,
 778                     Requires<[HasV4T]>;
 779
 780 // Rd=memh(Rt<<#u2+#U6)
 781
 782 //// Load word.
 783 // Load predicate: Fix for bug 5279.
 784 let neverHasSideEffects = 1 in
 785 def LDriw_pred_V4 : LDInst2<(outs PredRegs:$dst),
 786             (ins MEMri:$addr),
 787             "Error; should not emit",
 788             []>,
 789             Requires<[HasV4T]>;
 790
 791 // Rd=memw(Re=#U6)
 792
 793 // Rd=memw(Rs+Rt<<#u2)
 794 let AddedComplexity = 10, isPredicable = 1 in
 795 def LDriw_indexed_V4 : LDInst<(outs IntRegs:$dst),
 796                     (ins IntRegs:$src1, IntRegs:$src2),
 797                     "$dst=memw($src1+$src2<<#0)",
 798                     [(set (i32 IntRegs:$dst),
 799                           (i32 (load (add (i32 IntRegs:$src1),
 800                                           (i32 IntRegs:$src2)))))]>,
 801                     Requires<[HasV4T]>;
 802
 803 //// Load word conditionally.
 804 // if ([!]Pv[.new]) Rd=memw(Rs+Rt<<#u2)
 805 // if (Pv) Rd=memw(Rs+Rt<<#u2)
 806 let AddedComplexity = 15, isPredicated = 1 in
 807 def LDriw_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 808                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 809                     "if ($src1) $dst=memw($src2+$src3<<#0)",
 810                     []>,
 811                     Requires<[HasV4T]>;
 812
 813 // if (Pv.new) Rd=memh(Rs+Rt<<#u2)
 814 let AddedComplexity = 15, isPredicated = 1 in
 815 def LDriw_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 816                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 817                     "if ($src1.new) $dst=memw($src2+$src3<<#0)",
 818                     []>,
 819                     Requires<[HasV4T]>;
 820
 821 // if (!Pv) Rd=memh(Rs+Rt<<#u2)
 822 let AddedComplexity = 15, isPredicated = 1 in
 823 def LDriw_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 824                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 825                     "if (!$src1) $dst=memw($src2+$src3<<#0)",
 826                     []>,
 827                     Requires<[HasV4T]>;
 828
 829 // if (!Pv.new) Rd=memh(Rs+Rt<<#u2)
 830 let AddedComplexity = 15, isPredicated = 1 in
 831 def LDriw_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 832                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 833                     "if (!$src1.new) $dst=memw($src2+$src3<<#0)",
 834                     []>,
 835                     Requires<[HasV4T]>;
 836
 837 /// Load from global offset
 838
 839 let isPredicable = 1, neverHasSideEffects = 1 in
 840 def LDrid_GP_V4 : LDInst2<(outs DoubleRegs:$dst),
 841             (ins globaladdress:$global, u16Imm:$offset),
 842             "$dst=memd(#$global+$offset)",
 843             []>,
 844             Requires<[HasV4T]>;
 845
 846 let neverHasSideEffects = 1, isPredicated = 1 in
 847 def LDrid_GP_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 848             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 849             "if ($src1) $dst=memd(##$global+$offset)",
 850             []>,
 851             Requires<[HasV4T]>;
 852
 853 let neverHasSideEffects = 1, isPredicated = 1 in
 854 def LDrid_GP_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 855             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 856             "if (!$src1) $dst=memd(##$global+$offset)",
 857             []>,
 858             Requires<[HasV4T]>;
 859
 860 let neverHasSideEffects = 1, isPredicated = 1 in
 861 def LDrid_GP_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 862             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 863             "if ($src1.new) $dst=memd(##$global+$offset)",
 864             []>,
 865             Requires<[HasV4T]>;
 866
 867 let neverHasSideEffects = 1, isPredicated = 1 in
 868 def LDrid_GP_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 869             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 870             "if (!$src1.new) $dst=memd(##$global+$offset)",
 871             []>,
 872             Requires<[HasV4T]>;
 873
 874 let isPredicable = 1, neverHasSideEffects = 1 in
 875 def LDrib_GP_V4 : LDInst2<(outs IntRegs:$dst),
 876             (ins globaladdress:$global, u16Imm:$offset),
 877             "$dst=memb(#$global+$offset)",
 878             []>,
 879             Requires<[HasV4T]>;
 880
 881 let neverHasSideEffects = 1, isPredicated = 1 in
 882 def LDrib_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 883             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 884             "if ($src1) $dst=memb(##$global+$offset)",
 885             []>,
 886             Requires<[HasV4T]>;
 887
 888 let neverHasSideEffects = 1, isPredicated = 1 in
 889 def LDrib_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 890             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 891             "if (!$src1) $dst=memb(##$global+$offset)",
 892             []>,
 893             Requires<[HasV4T]>;
 894
 895 let neverHasSideEffects = 1, isPredicated = 1 in
 896 def LDrib_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 897             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 898             "if ($src1.new) $dst=memb(##$global+$offset)",
 899             []>,
 900             Requires<[HasV4T]>;
 901
 902 let neverHasSideEffects = 1, isPredicated = 1 in
 903 def LDrib_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 904             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 905             "if (!$src1.new) $dst=memb(##$global+$offset)",
 906             []>,
 907             Requires<[HasV4T]>;
 908
 909
 910 let isPredicable = 1, neverHasSideEffects = 1 in
 911 def LDriub_GP_V4 : LDInst2<(outs IntRegs:$dst),
 912             (ins globaladdress:$global, u16Imm:$offset),
 913             "$dst=memub(#$global+$offset)",
 914             []>,
 915             Requires<[HasV4T]>;
 916
 917
 918 let neverHasSideEffects = 1, isPredicated = 1 in
 919 def LDriub_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 920             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 921             "if ($src1) $dst=memub(##$global+$offset)",
 922             []>,
 923             Requires<[HasV4T]>;
 924
 925 let neverHasSideEffects = 1, isPredicated = 1 in
 926 def LDriub_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 927             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 928             "if (!$src1) $dst=memub(##$global+$offset)",
 929             []>,
 930             Requires<[HasV4T]>;
 931
 932 let neverHasSideEffects = 1, isPredicated = 1 in
 933 def LDriub_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 934             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 935             "if ($src1.new) $dst=memub(##$global+$offset)",
 936             []>,
 937             Requires<[HasV4T]>;
 938
 939 let neverHasSideEffects = 1, isPredicated = 1 in
 940 def LDriub_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 941             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 942             "if (!$src1.new) $dst=memub(##$global+$offset)",
 943             []>,
 944             Requires<[HasV4T]>;
 945
 946
 947 let isPredicable = 1, neverHasSideEffects = 1 in
 948 def LDrih_GP_V4 : LDInst2<(outs IntRegs:$dst),
 949             (ins globaladdress:$global, u16Imm:$offset),
 950             "$dst=memh(#$global+$offset)",
 951             []>,
 952             Requires<[HasV4T]>;
 953
 954
 955 let neverHasSideEffects = 1, isPredicated = 1 in
 956 def LDrih_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 957             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 958             "if ($src1) $dst=memh(##$global+$offset)",
 959             []>,
 960             Requires<[HasV4T]>;
 961
 962 let neverHasSideEffects = 1, isPredicated = 1 in
 963 def LDrih_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 964             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 965             "if (!$src1) $dst=memh(##$global+$offset)",
 966             []>,
 967             Requires<[HasV4T]>;
 968
 969 let neverHasSideEffects = 1, isPredicated = 1 in
 970 def LDrih_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 971             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 972             "if ($src1.new) $dst=memh(##$global+$offset)",
 973             []>,
 974             Requires<[HasV4T]>;
 975
 976 let neverHasSideEffects = 1, isPredicated = 1 in
 977 def LDrih_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 978             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 979             "if (!$src1.new) $dst=memh(##$global+$offset)",
 980             []>,
 981             Requires<[HasV4T]>;
 982
 983
 984 let isPredicable = 1, neverHasSideEffects = 1 in
 985 def LDriuh_GP_V4 : LDInst2<(outs IntRegs:$dst),
 986             (ins globaladdress:$global, u16Imm:$offset),
 987             "$dst=memuh(#$global+$offset)",
 988             []>,
 989             Requires<[HasV4T]>;
 990
 991 let neverHasSideEffects = 1, isPredicated = 1 in
 992 def LDriuh_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 993             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 994             "if ($src1) $dst=memuh(##$global+$offset)",
 995             []>,
 996             Requires<[HasV4T]>;
 997
 998 let neverHasSideEffects = 1, isPredicated = 1 in
 999 def LDriuh_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1000             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1001             "if (!$src1) $dst=memuh(##$global+$offset)",
1002             []>,
1003             Requires<[HasV4T]>;
1004
1005 let neverHasSideEffects = 1, isPredicated = 1 in
1006 def LDriuh_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1007             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1008             "if ($src1.new) $dst=memuh(##$global+$offset)",
1009             []>,
1010             Requires<[HasV4T]>;
1011
1012 let neverHasSideEffects = 1, isPredicated = 1 in
1013 def LDriuh_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1014             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1015             "if (!$src1.new) $dst=memuh(##$global+$offset)",
1016             []>,
1017             Requires<[HasV4T]>;
1018
1019 let isPredicable = 1, neverHasSideEffects = 1 in
1020 def LDriw_GP_V4 : LDInst2<(outs IntRegs:$dst),
1021             (ins globaladdress:$global, u16Imm:$offset),
1022             "$dst=memw(#$global+$offset)",
1023             []>,
1024             Requires<[HasV4T]>;
1025
1026
1027 let neverHasSideEffects = 1, isPredicated = 1 in
1028 def LDriw_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1029             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1030             "if ($src1) $dst=memw(##$global+$offset)",
1031             []>,
1032             Requires<[HasV4T]>;
1033
1034 let neverHasSideEffects = 1, isPredicated = 1 in
1035 def LDriw_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1036             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1037             "if (!$src1) $dst=memw(##$global+$offset)",
1038             []>,
1039             Requires<[HasV4T]>;
1040
1041
1042 let neverHasSideEffects = 1, isPredicated = 1 in
1043 def LDriw_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1044             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1045             "if ($src1.new) $dst=memw(##$global+$offset)",
1046             []>,
1047             Requires<[HasV4T]>;
1048
1049 let neverHasSideEffects = 1, isPredicated = 1 in
1050 def LDriw_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1051             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1052             "if (!$src1.new) $dst=memw(##$global+$offset)",
1053             []>,
1054             Requires<[HasV4T]>;
1055
1056
1057 let isPredicable = 1, neverHasSideEffects = 1 in
1058 def LDd_GP_V4 : LDInst2<(outs DoubleRegs:$dst),
1059             (ins globaladdress:$global),
1060             "$dst=memd(#$global)",
1061             []>,
1062             Requires<[HasV4T]>;
1063
1064 // if (Pv) Rtt=memd(##global)
1065 let neverHasSideEffects = 1, isPredicated = 1 in
1066 def LDd_GP_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1067             (ins PredRegs:$src1, globaladdress:$global),
1068             "if ($src1) $dst=memd(##$global)",
1069             []>,
1070             Requires<[HasV4T]>;
1071
1072
1073 // if (!Pv) Rtt=memd(##global)
1074 let neverHasSideEffects = 1, isPredicated = 1 in
1075 def LDd_GP_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1076             (ins PredRegs:$src1, globaladdress:$global),
1077             "if (!$src1) $dst=memd(##$global)",
1078             []>,
1079             Requires<[HasV4T]>;
1080
1081 // if (Pv) Rtt=memd(##global)
1082 let neverHasSideEffects = 1, isPredicated = 1 in
1083 def LDd_GP_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1084             (ins PredRegs:$src1, globaladdress:$global),
1085             "if ($src1.new) $dst=memd(##$global)",
1086             []>,
1087             Requires<[HasV4T]>;
1088
1089
1090 // if (!Pv) Rtt=memd(##global)
1091 let neverHasSideEffects = 1, isPredicated = 1 in
1092 def LDd_GP_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1093             (ins PredRegs:$src1, globaladdress:$global),
1094             "if (!$src1.new) $dst=memd(##$global)",
1095             []>,
1096             Requires<[HasV4T]>;
1097
1098 let isPredicable = 1, neverHasSideEffects = 1 in
1099 def LDb_GP_V4 : LDInst2<(outs IntRegs:$dst),
1100             (ins globaladdress:$global),
1101             "$dst=memb(#$global)",
1102             []>,
1103             Requires<[HasV4T]>;
1104
1105 // if (Pv) Rt=memb(##global)
1106 let neverHasSideEffects = 1, isPredicated = 1 in
1107 def LDb_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1108             (ins PredRegs:$src1, globaladdress:$global),
1109             "if ($src1) $dst=memb(##$global)",
1110             []>,
1111             Requires<[HasV4T]>;
1112
1113 // if (!Pv) Rt=memb(##global)
1114 let neverHasSideEffects = 1, isPredicated = 1 in
1115 def LDb_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1116             (ins PredRegs:$src1, globaladdress:$global),
1117             "if (!$src1) $dst=memb(##$global)",
1118             []>,
1119             Requires<[HasV4T]>;
1120
1121 // if (Pv) Rt=memb(##global)
1122 let neverHasSideEffects = 1, isPredicated = 1 in
1123 def LDb_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1124             (ins PredRegs:$src1, globaladdress:$global),
1125             "if ($src1.new) $dst=memb(##$global)",
1126             []>,
1127             Requires<[HasV4T]>;
1128
1129 // if (!Pv) Rt=memb(##global)
1130 let neverHasSideEffects = 1, isPredicated = 1 in
1131 def LDb_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1132             (ins PredRegs:$src1, globaladdress:$global),
1133             "if (!$src1.new) $dst=memb(##$global)",
1134             []>,
1135             Requires<[HasV4T]>;
1136
1137 let isPredicable = 1, neverHasSideEffects = 1 in
1138 def LDub_GP_V4 : LDInst2<(outs IntRegs:$dst),
1139             (ins globaladdress:$global),
1140             "$dst=memub(#$global)",
1141             []>,
1142             Requires<[HasV4T]>;
1143
1144 // if (Pv) Rt=memub(##global)
1145 let neverHasSideEffects = 1, isPredicated = 1 in
1146 def LDub_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1147             (ins PredRegs:$src1, globaladdress:$global),
1148             "if ($src1) $dst=memub(##$global)",
1149             []>,
1150             Requires<[HasV4T]>;
1151
1152
1153 // if (!Pv) Rt=memub(##global)
1154 let neverHasSideEffects = 1, isPredicated = 1 in
1155 def LDub_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1156             (ins PredRegs:$src1, globaladdress:$global),
1157             "if (!$src1) $dst=memub(##$global)",
1158             []>,
1159             Requires<[HasV4T]>;
1160
1161 // if (Pv) Rt=memub(##global)
1162 let neverHasSideEffects = 1, isPredicated = 1 in
1163 def LDub_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1164             (ins PredRegs:$src1, globaladdress:$global),
1165             "if ($src1.new) $dst=memub(##$global)",
1166             []>,
1167             Requires<[HasV4T]>;
1168
1169
1170 // if (!Pv) Rt=memub(##global)
1171 let neverHasSideEffects = 1, isPredicated = 1 in
1172 def LDub_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1173             (ins PredRegs:$src1, globaladdress:$global),
1174             "if (!$src1.new) $dst=memub(##$global)",
1175             []>,
1176             Requires<[HasV4T]>;
1177
1178 let isPredicable = 1, neverHasSideEffects = 1 in
1179 def LDh_GP_V4 : LDInst2<(outs IntRegs:$dst),
1180             (ins globaladdress:$global),
1181             "$dst=memh(#$global)",
1182             []>,
1183             Requires<[HasV4T]>;
1184
1185 // if (Pv) Rt=memh(##global)
1186 let neverHasSideEffects = 1, isPredicated = 1 in
1187 def LDh_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1188             (ins PredRegs:$src1, globaladdress:$global),
1189             "if ($src1) $dst=memh(##$global)",
1190             []>,
1191             Requires<[HasV4T]>;
1192
1193 // if (!Pv) Rt=memh(##global)
1194 let neverHasSideEffects = 1, isPredicated = 1 in
1195 def LDh_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1196             (ins PredRegs:$src1, globaladdress:$global),
1197             "if (!$src1) $dst=memh(##$global)",
1198             []>,
1199             Requires<[HasV4T]>;
1200
1201 // if (Pv) Rt=memh(##global)
1202 let neverHasSideEffects = 1, isPredicated = 1 in
1203 def LDh_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1204             (ins PredRegs:$src1, globaladdress:$global),
1205             "if ($src1.new) $dst=memh(##$global)",
1206             []>,
1207             Requires<[HasV4T]>;
1208
1209 // if (!Pv) Rt=memh(##global)
1210 let neverHasSideEffects = 1, isPredicated = 1 in
1211 def LDh_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1212             (ins PredRegs:$src1, globaladdress:$global),
1213             "if (!$src1.new) $dst=memh(##$global)",
1214             []>,
1215             Requires<[HasV4T]>;
1216
1217 let isPredicable = 1, neverHasSideEffects = 1 in
1218 def LDuh_GP_V4 : LDInst2<(outs IntRegs:$dst),
1219             (ins globaladdress:$global),
1220             "$dst=memuh(#$global)",
1221             []>,
1222             Requires<[HasV4T]>;
1223
1224 // if (Pv) Rt=memuh(##global)
1225 let neverHasSideEffects = 1, isPredicated = 1 in
1226 def LDuh_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1227             (ins PredRegs:$src1, globaladdress:$global),
1228             "if ($src1) $dst=memuh(##$global)",
1229             []>,
1230             Requires<[HasV4T]>;
1231
1232 // if (!Pv) Rt=memuh(##global)
1233 let neverHasSideEffects = 1, isPredicated = 1 in
1234 def LDuh_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1235             (ins PredRegs:$src1, globaladdress:$global),
1236             "if (!$src1) $dst=memuh(##$global)",
1237             []>,
1238             Requires<[HasV4T]>;
1239
1240 // if (Pv) Rt=memuh(##global)
1241 let neverHasSideEffects = 1, isPredicated = 1 in
1242 def LDuh_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1243             (ins PredRegs:$src1, globaladdress:$global),
1244             "if ($src1.new) $dst=memuh(##$global)",
1245             []>,
1246             Requires<[HasV4T]>;
1247
1248 // if (!Pv) Rt=memuh(##global)
1249 let neverHasSideEffects = 1, isPredicated = 1 in
1250 def LDuh_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1251             (ins PredRegs:$src1, globaladdress:$global),
1252             "if (!$src1.new) $dst=memuh(##$global)",
1253             []>,
1254             Requires<[HasV4T]>;
1255
1256 let isPredicable = 1, neverHasSideEffects = 1 in
1257 def LDw_GP_V4 : LDInst2<(outs IntRegs:$dst),
1258             (ins globaladdress:$global),
1259             "$dst=memw(#$global)",
1260             []>,
1261             Requires<[HasV4T]>;
1262
1263 // if (Pv) Rt=memw(##global)
1264 let neverHasSideEffects = 1, isPredicated = 1 in
1265 def LDw_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1266             (ins PredRegs:$src1, globaladdress:$global),
1267             "if ($src1) $dst=memw(##$global)",
1268             []>,
1269             Requires<[HasV4T]>;
1270
1271
1272 // if (!Pv) Rt=memw(##global)
1273 let neverHasSideEffects = 1, isPredicated = 1 in
1274 def LDw_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1275             (ins PredRegs:$src1, globaladdress:$global),
1276             "if (!$src1) $dst=memw(##$global)",
1277             []>,
1278             Requires<[HasV4T]>;
1279
1280 // if (Pv) Rt=memw(##global)
1281 let neverHasSideEffects = 1, isPredicated = 1 in
1282 def LDw_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1283             (ins PredRegs:$src1, globaladdress:$global),
1284             "if ($src1.new) $dst=memw(##$global)",
1285             []>,
1286             Requires<[HasV4T]>;
1287
1288
1289 // if (!Pv) Rt=memw(##global)
1290 let neverHasSideEffects = 1, isPredicated = 1 in
1291 def LDw_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1292             (ins PredRegs:$src1, globaladdress:$global),
1293             "if (!$src1.new) $dst=memw(##$global)",
1294             []>,
1295             Requires<[HasV4T]>;
1296
1297
1298
1299 def : Pat <(atomic_load_64 (HexagonCONST32_GP tglobaladdr:$global)),
1300            (i64 (LDd_GP_V4 tglobaladdr:$global))>,
1301             Requires<[HasV4T]>;
1302
1303 def : Pat <(atomic_load_32 (HexagonCONST32_GP tglobaladdr:$global)),
1304            (i32 (LDw_GP_V4 tglobaladdr:$global))>,
1305             Requires<[HasV4T]>;
1306
1307 def : Pat <(atomic_load_16 (HexagonCONST32_GP tglobaladdr:$global)),
1308            (i32 (LDuh_GP_V4 tglobaladdr:$global))>,
1309             Requires<[HasV4T]>;
1310
1311 def : Pat <(atomic_load_8 (HexagonCONST32_GP tglobaladdr:$global)),
1312            (i32 (LDub_GP_V4 tglobaladdr:$global))>,
1313             Requires<[HasV4T]>;
1314
1315 // Map from load(globaladdress) -> memw(#foo + 0)
1316 let AddedComplexity = 100 in
1317 def : Pat <(i64 (load (HexagonCONST32_GP tglobaladdr:$global))),
1318            (i64 (LDd_GP_V4 tglobaladdr:$global))>,
1319             Requires<[HasV4T]>;
1320
1321 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd
1322 let AddedComplexity = 100 in
1323 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
1324            (i1 (TFR_PdRs (i32 (LDb_GP_V4 tglobaladdr:$global))))>,
1325            Requires<[HasV4T]>;
1326
1327 // When the Interprocedural Global Variable optimizer realizes that a certain
1328 // global variable takes only two constant values, it shrinks the global to
1329 // a boolean. Catch those loads here in the following 3 patterns.
1330 let AddedComplexity = 100 in
1331 def : Pat <(i32 (extloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
1332            (i32 (LDb_GP_V4 tglobaladdr:$global))>,
1333             Requires<[HasV4T]>;
1334
1335 let AddedComplexity = 100 in
1336 def : Pat <(i32 (sextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
1337            (i32 (LDb_GP_V4 tglobaladdr:$global))>,
1338             Requires<[HasV4T]>;
1339
1340 // Map from load(globaladdress) -> memb(#foo)
1341 let AddedComplexity = 100 in
1342 def : Pat <(i32 (extloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
1343            (i32 (LDb_GP_V4 tglobaladdr:$global))>,
1344             Requires<[HasV4T]>;
1345
1346 // Map from load(globaladdress) -> memb(#foo)
1347 let AddedComplexity = 100 in
1348 def : Pat <(i32 (sextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
1349            (i32 (LDb_GP_V4 tglobaladdr:$global))>,
1350             Requires<[HasV4T]>;
1351
1352 let AddedComplexity = 100 in
1353 def : Pat <(i32 (zextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
1354            (i32 (LDub_GP_V4 tglobaladdr:$global))>,
1355             Requires<[HasV4T]>;
1356
1357 // Map from load(globaladdress) -> memub(#foo)
1358 let AddedComplexity = 100 in
1359 def : Pat <(i32 (zextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
1360            (i32 (LDub_GP_V4 tglobaladdr:$global))>,
1361             Requires<[HasV4T]>;
1362
1363 // Map from load(globaladdress) -> memh(#foo)
1364 let AddedComplexity = 100 in
1365 def : Pat <(i32 (extloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
1366            (i32 (LDh_GP_V4 tglobaladdr:$global))>,
1367             Requires<[HasV4T]>;
1368
1369 // Map from load(globaladdress) -> memh(#foo)
1370 let AddedComplexity = 100 in
1371 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
1372            (i32 (LDh_GP_V4 tglobaladdr:$global))>,
1373             Requires<[HasV4T]>;
1374
1375 // Map from load(globaladdress) -> memuh(#foo)
1376 let AddedComplexity = 100 in
1377 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
1378            (i32 (LDuh_GP_V4 tglobaladdr:$global))>,
1379             Requires<[HasV4T]>;
1380
1381 // Map from load(globaladdress) -> memw(#foo)
1382 let AddedComplexity = 100 in
1383 def : Pat <(i32 (load (HexagonCONST32_GP tglobaladdr:$global))),
1384            (i32 (LDw_GP_V4 tglobaladdr:$global))>,
1385             Requires<[HasV4T]>;
1386
1387 def : Pat <(atomic_load_64 (add (HexagonCONST32_GP tglobaladdr:$global),
1388                                 u16ImmPred:$offset)),
1389            (i64 (LDrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1390            Requires<[HasV4T]>;
1391
1392 def : Pat <(atomic_load_32 (add (HexagonCONST32_GP tglobaladdr:$global),
1393                                 u16ImmPred:$offset)),
1394            (i32 (LDriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1395             Requires<[HasV4T]>;
1396
1397 def : Pat <(atomic_load_16 (add (HexagonCONST32_GP tglobaladdr:$global),
1398                                 u16ImmPred:$offset)),
1399            (i32 (LDriuh_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1400             Requires<[HasV4T]>;
1401
1402 def : Pat <(atomic_load_8 (add (HexagonCONST32_GP tglobaladdr:$global),
1403                                u16ImmPred:$offset)),
1404            (i32 (LDriub_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1405            Requires<[HasV4T]>;
1406
1407 // Map from load(globaladdress + x) -> memd(#foo + x)
1408 let AddedComplexity = 100 in
1409 def : Pat <(i64 (load (add (HexagonCONST32_GP tglobaladdr:$global),
1410                            u16ImmPred:$offset))),
1411            (i64 (LDrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1412            Requires<[HasV4T]>;
1413
1414 // Map from load(globaladdress + x) -> memb(#foo + x)
1415 let AddedComplexity = 100 in
1416 def : Pat <(i32 (extloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
1417                            u16ImmPred:$offset))),
1418            (i32 (LDrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1419            Requires<[HasV4T]>;
1420
1421 // Map from load(globaladdress + x) -> memb(#foo + x)
1422 let AddedComplexity = 100 in
1423 def : Pat <(i32 (sextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
1424                             u16ImmPred:$offset))),
1425            (i32 (LDrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1426            Requires<[HasV4T]>;
1427
1428 // Map from load(globaladdress + x) -> memub(#foo + x)
1429 let AddedComplexity = 100 in
1430 def : Pat <(i32 (zextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
1431                             u16ImmPred:$offset))),
1432            (i32 (LDriub_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1433            Requires<[HasV4T]>;
1434
1435 // Map from load(globaladdress + x) -> memuh(#foo + x)
1436 let AddedComplexity = 100 in
1437 def : Pat <(i32 (extloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
1438                             u16ImmPred:$offset))),
1439            (i32 (LDrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1440             Requires<[HasV4T]>;
1441
1442 // Map from load(globaladdress + x) -> memh(#foo + x)
1443 let AddedComplexity = 100 in
1444 def : Pat <(i32 (sextloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
1445                              u16ImmPred:$offset))),
1446            (i32 (LDrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1447            Requires<[HasV4T]>;
1448
1449
1450 // Map from load(globaladdress + x) -> memuh(#foo + x)
1451 let AddedComplexity = 100 in
1452 def : Pat <(i32 (zextloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
1453                              u16ImmPred:$offset))),
1454            (i32 (LDriuh_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1455             Requires<[HasV4T]>;
1456
1457 // Map from load(globaladdress + x) -> memw(#foo + x)
1458 let AddedComplexity = 100 in
1459 def : Pat <(i32 (load (add (HexagonCONST32_GP tglobaladdr:$global),
1460                       u16ImmPred:$offset))),
1461            (i32 (LDriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1462             Requires<[HasV4T]>;
1463
1464
1465 //===----------------------------------------------------------------------===//
1466 // LD -
1467 //===----------------------------------------------------------------------===//
1468
1469 //===----------------------------------------------------------------------===//
1470 // ST +
1471 //===----------------------------------------------------------------------===//
1472 ///
1473 /// Assumptions::: ****** DO NOT IGNORE ********
1474 /// 1. Make sure that in post increment store, the zero'th operand is always the
1475 ///    post increment operand.
1476 /// 2. Make sure that the store value operand(Rt/Rtt) in a store is always the
1477 ///    last operand.
1478 ///
1479
1480 // memd(Re=#U6)=Rtt
1481 def STrid_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1482             (ins DoubleRegs:$src1, u6Imm:$src2),
1483             "memd($dst1=#$src2) = $src1",
1484             []>,
1485             Requires<[HasV4T]>;
1486
1487 // memb(Re=#U6)=Rs
1488 def STrib_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1489             (ins IntRegs:$src1, u6Imm:$src2),
1490             "memb($dst1=#$src2) = $src1",
1491             []>,
1492             Requires<[HasV4T]>;
1493
1494 // memh(Re=#U6)=Rs
1495 def STrih_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1496             (ins IntRegs:$src1, u6Imm:$src2),
1497             "memh($dst1=#$src2) = $src1",
1498             []>,
1499             Requires<[HasV4T]>;
1500
1501 // memw(Re=#U6)=Rs
1502 def STriw_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1503             (ins IntRegs:$src1, u6Imm:$src2),
1504             "memw($dst1=#$src2) = $src1",
1505             []>,
1506             Requires<[HasV4T]>;
1507
1508 // memd(Re=#U6)=Rtt
1509 def STrid_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1510             (ins DoubleRegs:$src1, globaladdress:$src2),
1511             "memd($dst1=##$src2) = $src1",
1512             []>,
1513             Requires<[HasV4T]>;
1514
1515 // memb(Re=#U6)=Rs
1516 def STrib_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1517             (ins IntRegs:$src1, globaladdress:$src2),
1518             "memb($dst1=##$src2) = $src1",
1519             []>,
1520             Requires<[HasV4T]>;
1521
1522 // memh(Re=#U6)=Rs
1523 def STrih_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1524             (ins IntRegs:$src1, globaladdress:$src2),
1525             "memh($dst1=##$src2) = $src1",
1526             []>,
1527             Requires<[HasV4T]>;
1528
1529 // memw(Re=#U6)=Rs
1530 def STriw_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1531             (ins IntRegs:$src1, globaladdress:$src2),
1532             "memw($dst1=##$src2) = $src1",
1533             []>,
1534             Requires<[HasV4T]>;
1535
1536
1537 // multiclass for store instructions with base + register offset addressing
1538 // mode
1539 multiclass ST_Idxd_shl_Pbase<string mnemonic, RegisterClass RC, bit isNot,
1540                              bit isPredNew> {
1541   let PNewValue = #!if(isPredNew, "new", "") in
1542   def #NAME# : STInst2<(outs),
1543             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1544                  RC:$src5),
1545             !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1546             ") ")#mnemonic#"($src2+$src3<<#$src4) = $src5",
1547             []>,
1548             Requires<[HasV4T]>;
1549 }
1550
1551 multiclass ST_Idxd_shl_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
1552   let PredSense = #!if(PredNot, "false", "true") in {
1553     defm _c#NAME# : ST_Idxd_shl_Pbase<mnemonic, RC, PredNot, 0>;
1554     // Predicate new
1555     defm _cdn#NAME# : ST_Idxd_shl_Pbase<mnemonic, RC, PredNot, 1>;
1556   }
1557 }
1558
1559 let isNVStorable = 1 in
1560 multiclass ST_Idxd_shl<string mnemonic, string CextOp, RegisterClass RC> {
1561   let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
1562     let isPredicable = 1 in
1563     def #NAME#_V4 : STInst2<(outs),
1564             (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, RC:$src4),
1565             #mnemonic#"($src1+$src2<<#$src3) = $src4",
1566             []>,
1567             Requires<[HasV4T]>;
1568
1569     let isPredicated = 1 in {
1570       defm Pt_V4 : ST_Idxd_shl_Pred<mnemonic, RC, 0 >;
1571       defm NotPt_V4 : ST_Idxd_shl_Pred<mnemonic, RC, 1>;
1572     }
1573   }
1574 }
1575
1576 // multiclass for new-value store instructions with base + register offset
1577 // addressing mode.
1578 multiclass ST_Idxd_shl_Pbase_nv<string mnemonic, RegisterClass RC, bit isNot,
1579                              bit isPredNew> {
1580   let PNewValue = #!if(isPredNew, "new", "") in
1581   def #NAME#_nv_V4 : NVInst_V4<(outs),
1582             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1583                  RC:$src5),
1584             !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1585             ") ")#mnemonic#"($src2+$src3<<#$src4) = $src5.new",
1586             []>,
1587             Requires<[HasV4T]>;
1588 }
1589
1590 multiclass ST_Idxd_shl_Pred_nv<string mnemonic, RegisterClass RC, bit PredNot> {
1591   let PredSense = #!if(PredNot, "false", "true") in {
1592     defm _c#NAME# : ST_Idxd_shl_Pbase_nv<mnemonic, RC, PredNot, 0>;
1593     // Predicate new
1594     defm _cdn#NAME# : ST_Idxd_shl_Pbase_nv<mnemonic, RC, PredNot, 1>;
1595   }
1596 }
1597
1598 let mayStore = 1, isNVStore = 1 in
1599 multiclass ST_Idxd_shl_nv<string mnemonic, string CextOp, RegisterClass RC> {
1600   let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
1601     let isPredicable = 1 in
1602     def #NAME#_nv_V4 : NVInst_V4<(outs),
1603             (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, RC:$src4),
1604             #mnemonic#"($src1+$src2<<#$src3) = $src4.new",
1605             []>,
1606             Requires<[HasV4T]>;
1607
1608     let isPredicated = 1 in {
1609       defm Pt : ST_Idxd_shl_Pred_nv<mnemonic, RC, 0 >;
1610       defm NotPt : ST_Idxd_shl_Pred_nv<mnemonic, RC, 1>;
1611     }
1612   }
1613 }
1614
1615 let addrMode = BaseRegOffset, neverHasSideEffects = 1,
1616 validSubTargets = HasV4SubT in {
1617   defm STrib_indexed_shl: ST_Idxd_shl<"memb", "STrib", IntRegs>,
1618                           ST_Idxd_shl_nv<"memb", "STrib", IntRegs>, AddrModeRel;
1619
1620   defm STrih_indexed_shl: ST_Idxd_shl<"memh", "STrih", IntRegs>,
1621                           ST_Idxd_shl_nv<"memh", "STrih", IntRegs>, AddrModeRel;
1622
1623   defm STriw_indexed_shl: ST_Idxd_shl<"memw", "STriw", IntRegs>,
1624                           ST_Idxd_shl_nv<"memw", "STriw", IntRegs>, AddrModeRel;
1625
1626   let isNVStorable = 0 in
1627   defm STrid_indexed_shl: ST_Idxd_shl<"memd", "STrid", DoubleRegs>, AddrModeRel;
1628 }
1629
1630 let Predicates = [HasV4T], AddedComplexity = 10 in {
1631 def : Pat<(truncstorei8 (i32 IntRegs:$src4),
1632                        (add IntRegs:$src1, (shl IntRegs:$src2,
1633                                                 u2ImmPred:$src3))),
1634           (STrib_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
1635                                 u2ImmPred:$src3, IntRegs:$src4)>;
1636
1637 def : Pat<(truncstorei16 (i32 IntRegs:$src4),
1638                         (add IntRegs:$src1, (shl IntRegs:$src2,
1639                                                  u2ImmPred:$src3))),
1640           (STrih_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
1641                                 u2ImmPred:$src3, IntRegs:$src4)>;
1642
1643 def : Pat<(store (i32 IntRegs:$src4),
1644                  (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
1645           (STriw_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
1646                                 u2ImmPred:$src3, IntRegs:$src4)>;
1647
1648 def : Pat<(store (i64 DoubleRegs:$src4),
1649                 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
1650           (STrid_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
1651                                 u2ImmPred:$src3, DoubleRegs:$src4)>;
1652 }
1653
1654 // memd(Ru<<#u2+#U6)=Rtt
1655 let AddedComplexity = 10 in
1656 def STrid_shl_V4 : STInst<(outs),
1657             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, DoubleRegs:$src4),
1658             "memd($src1<<#$src2+#$src3) = $src4",
1659             [(store (i64 DoubleRegs:$src4),
1660                     (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
1661                          u6ImmPred:$src3))]>,
1662             Requires<[HasV4T]>;
1663
1664 // memd(Rx++#s4:3)=Rtt
1665 // memd(Rx++#s4:3:circ(Mu))=Rtt
1666 // memd(Rx++I:circ(Mu))=Rtt
1667 // memd(Rx++Mu)=Rtt
1668 // memd(Rx++Mu:brev)=Rtt
1669 // memd(gp+#u16:3)=Rtt
1670
1671 // Store doubleword conditionally.
1672 // if ([!]Pv[.new]) memd(#u6)=Rtt
1673 // TODO: needs to be implemented.
1674
1675 // if ([!]Pv[.new]) memd(Rx++#s4:3)=Rtt
1676 // if (Pv) memd(Rx++#s4:3)=Rtt
1677 // if (Pv.new) memd(Rx++#s4:3)=Rtt
1678 let AddedComplexity = 10, neverHasSideEffects = 1,
1679     isPredicated = 1 in
1680 def POST_STdri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst),
1681             (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1682                  s4_3Imm:$offset),
1683             "if ($src1.new) memd($src3++#$offset) = $src2",
1684             [],
1685             "$src3 = $dst">,
1686             Requires<[HasV4T]>;
1687
1688 // if (!Pv) memd(Rx++#s4:3)=Rtt
1689 // if (!Pv.new) memd(Rx++#s4:3)=Rtt
1690 let AddedComplexity = 10, neverHasSideEffects = 1,
1691     isPredicated = 1 in
1692 def POST_STdri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
1693             (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1694                  s4_3Imm:$offset),
1695             "if (!$src1.new) memd($src3++#$offset) = $src2",
1696             [],
1697             "$src3 = $dst">,
1698             Requires<[HasV4T]>;
1699
1700
1701 // multiclass for store instructions with base + immediate offset
1702 // addressing mode and immediate stored value.
1703 multiclass ST_Imm_Pbase<string mnemonic, Operand OffsetOp, bit isNot,
1704                         bit isPredNew> {
1705   let PNewValue = #!if(isPredNew, "new", "") in
1706   def #NAME# : STInst2<(outs),
1707             (ins PredRegs:$src1, IntRegs:$src2, OffsetOp:$src3, s6Ext:$src4),
1708             #!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1709             ") ")#mnemonic#"($src2+#$src3) = #$src4",
1710             []>,
1711             Requires<[HasV4T]>;
1712 }
1713
1714 multiclass ST_Imm_Pred<string mnemonic, Operand OffsetOp, bit PredNot> {
1715   let PredSense = #!if(PredNot, "false", "true") in {
1716     defm _c#NAME# : ST_Imm_Pbase<mnemonic, OffsetOp, PredNot, 0>;
1717     // Predicate new
1718     defm _cdn#NAME# : ST_Imm_Pbase<mnemonic, OffsetOp, PredNot, 1>;
1719   }
1720 }
1721
1722 let isExtendable = 1, isExtentSigned = 1, neverHasSideEffects = 1 in
1723 multiclass ST_Imm<string mnemonic, string CextOp, Operand OffsetOp> {
1724   let CextOpcode = CextOp, BaseOpcode = CextOp#_imm in {
1725     let opExtendable = 2, opExtentBits = 8, isPredicable = 1 in
1726     def #NAME#_V4 : STInst2<(outs),
1727             (ins IntRegs:$src1, OffsetOp:$src2, s8Ext:$src3),
1728             #mnemonic#"($src1+#$src2) = #$src3",
1729             []>,
1730             Requires<[HasV4T]>;
1731
1732     let opExtendable = 3, opExtentBits = 6, isPredicated = 1 in {
1733       defm Pt_V4 : ST_Imm_Pred<mnemonic, OffsetOp, 0>;
1734       defm NotPt_V4 : ST_Imm_Pred<mnemonic, OffsetOp, 1 >;
1735     }
1736   }
1737 }
1738
1739 let addrMode = BaseImmOffset, InputType = "imm",
1740     validSubTargets = HasV4SubT in {
1741   defm STrib_imm : ST_Imm<"memb", "STrib", u6_0Imm>, ImmRegRel;
1742   defm STrih_imm : ST_Imm<"memh", "STrih", u6_1Imm>, ImmRegRel;
1743   defm STriw_imm : ST_Imm<"memw", "STriw", u6_2Imm>, ImmRegRel;
1744 }
1745
1746 let Predicates = [HasV4T], AddedComplexity = 10 in {
1747 def: Pat<(truncstorei8 s8ExtPred:$src3, (add IntRegs:$src1, u6_0ImmPred:$src2)),
1748             (STrib_imm_V4 IntRegs:$src1, u6_0ImmPred:$src2, s8ExtPred:$src3)>;
1749
1750 def: Pat<(truncstorei16 s8ExtPred:$src3, (add IntRegs:$src1,
1751                                               u6_1ImmPred:$src2)),
1752             (STrih_imm_V4 IntRegs:$src1, u6_1ImmPred:$src2, s8ExtPred:$src3)>;
1753
1754 def: Pat<(store s8ExtPred:$src3, (add IntRegs:$src1, u6_2ImmPred:$src2)),
1755             (STriw_imm_V4 IntRegs:$src1, u6_2ImmPred:$src2, s8ExtPred:$src3)>;
1756 }
1757
1758 let AddedComplexity = 6 in
1759 def : Pat <(truncstorei8 s8ExtPred:$src2, (i32 IntRegs:$src1)),
1760            (STrib_imm_V4 IntRegs:$src1, 0, s8ExtPred:$src2)>,
1761            Requires<[HasV4T]>;
1762
1763 // memb(Ru<<#u2+#U6)=Rt
1764 let AddedComplexity = 10 in
1765 def STrib_shl_V4 : STInst<(outs),
1766             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
1767             "memb($src1<<#$src2+#$src3) = $src4",
1768             [(truncstorei8 (i32 IntRegs:$src4),
1769                            (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
1770                                 u6ImmPred:$src3))]>,
1771             Requires<[HasV4T]>;
1772
1773 // memb(Rx++#s4:0:circ(Mu))=Rt
1774 // memb(Rx++I:circ(Mu))=Rt
1775 // memb(Rx++Mu)=Rt
1776 // memb(Rx++Mu:brev)=Rt
1777 // memb(gp+#u16:0)=Rt
1778
1779
1780 // Store byte conditionally.
1781 // if ([!]Pv[.new]) memb(#u6)=Rt
1782 // if ([!]Pv[.new]) memb(Rx++#s4:0)=Rt
1783 // if (Pv) memb(Rx++#s4:0)=Rt
1784 // if (Pv.new) memb(Rx++#s4:0)=Rt
1785 let hasCtrlDep = 1,
1786     isPredicated = 1 in
1787 def POST_STbri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst),
1788             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1789             "if ($src1.new) memb($src3++#$offset) = $src2",
1790             [],"$src3 = $dst">,
1791             Requires<[HasV4T]>;
1792
1793 // if (!Pv) memb(Rx++#s4:0)=Rt
1794 // if (!Pv.new) memb(Rx++#s4:0)=Rt
1795 let hasCtrlDep = 1,
1796     isPredicated = 1 in
1797 def POST_STbri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
1798             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1799             "if (!$src1.new) memb($src3++#$offset) = $src2",
1800             [],"$src3 = $dst">,
1801             Requires<[HasV4T]>;
1802
1803
1804 // Store halfword.
1805 // TODO: needs to be implemented
1806 // memh(Re=#U6)=Rt.H
1807 // memh(Rs+#s11:1)=Rt.H
1808 let AddedComplexity = 6 in
1809 def : Pat <(truncstorei16 s8ExtPred:$src2, (i32 IntRegs:$src1)),
1810            (STrih_imm_V4 IntRegs:$src1, 0, s8ExtPred:$src2)>,
1811            Requires<[HasV4T]>;
1812
1813 // memh(Rs+Ru<<#u2)=Rt.H
1814 // TODO: needs to be implemented.
1815
1816 // memh(Ru<<#u2+#U6)=Rt.H
1817 // memh(Ru<<#u2+#U6)=Rt
1818 let AddedComplexity = 10 in
1819 def STrih_shl_V4 : STInst<(outs),
1820             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
1821             "memh($src1<<#$src2+#$src3) = $src4",
1822             [(truncstorei16 (i32 IntRegs:$src4),
1823                             (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
1824                                  u6ImmPred:$src3))]>,
1825             Requires<[HasV4T]>;
1826
1827 // memh(Rx++#s4:1:circ(Mu))=Rt.H
1828 // memh(Rx++#s4:1:circ(Mu))=Rt
1829 // memh(Rx++I:circ(Mu))=Rt.H
1830 // memh(Rx++I:circ(Mu))=Rt
1831 // memh(Rx++Mu)=Rt.H
1832 // memh(Rx++Mu)=Rt
1833 // memh(Rx++Mu:brev)=Rt.H
1834 // memh(Rx++Mu:brev)=Rt
1835 // memh(gp+#u16:1)=Rt
1836 // if ([!]Pv[.new]) memh(#u6)=Rt.H
1837 // if ([!]Pv[.new]) memh(#u6)=Rt
1838
1839
1840 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt.H
1841 // TODO: needs to be implemented.
1842
1843 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt.H
1844 // TODO: Needs to be implemented.
1845
1846 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt
1847 // if (Pv) memh(Rx++#s4:1)=Rt
1848 // if (Pv.new) memh(Rx++#s4:1)=Rt
1849 let hasCtrlDep = 1,
1850     isPredicated = 1 in
1851 def POST_SThri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst),
1852             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
1853             "if ($src1.new) memh($src3++#$offset) = $src2",
1854             [],"$src3 = $dst">,
1855             Requires<[HasV4T]>;
1856
1857 // if (!Pv) memh(Rx++#s4:1)=Rt
1858 // if (!Pv.new) memh(Rx++#s4:1)=Rt
1859 let hasCtrlDep = 1,
1860     isPredicated = 1 in
1861 def POST_SThri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
1862             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
1863             "if (!$src1.new) memh($src3++#$offset) = $src2",
1864             [],"$src3 = $dst">,
1865             Requires<[HasV4T]>;
1866
1867
1868 // Store word.
1869 // memw(Re=#U6)=Rt
1870 // TODO: Needs to be implemented.
1871
1872 // Store predicate:
1873 let neverHasSideEffects = 1 in
1874 def STriw_pred_V4 : STInst2<(outs),
1875             (ins MEMri:$addr, PredRegs:$src1),
1876             "Error; should not emit",
1877             []>,
1878             Requires<[HasV4T]>;
1879
1880 let AddedComplexity = 6 in
1881 def : Pat <(store s8ExtPred:$src2, (i32 IntRegs:$src1)),
1882            (STriw_imm_V4 IntRegs:$src1, 0, s8ExtPred:$src2)>,
1883            Requires<[HasV4T]>;
1884
1885 // memw(Ru<<#u2+#U6)=Rt
1886 let AddedComplexity = 10 in
1887 def STriw_shl_V4 : STInst<(outs),
1888             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
1889             "memw($src1<<#$src2+#$src3) = $src4",
1890             [(store (i32 IntRegs:$src4),
1891                     (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
1892                               u6ImmPred:$src3))]>,
1893             Requires<[HasV4T]>;
1894
1895 // memw(Rx++#s4:2)=Rt
1896 // memw(Rx++#s4:2:circ(Mu))=Rt
1897 // memw(Rx++I:circ(Mu))=Rt
1898 // memw(Rx++Mu)=Rt
1899 // memw(Rx++Mu:brev)=Rt
1900 // memw(gp+#u16:2)=Rt
1901
1902
1903 // if ([!]Pv[.new]) memw(Rx++#s4:2)=Rt
1904 // if (Pv) memw(Rx++#s4:2)=Rt
1905 // if (Pv.new) memw(Rx++#s4:2)=Rt
1906 let hasCtrlDep = 1,
1907     isPredicated = 1 in
1908 def POST_STwri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst),
1909             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
1910             "if ($src1.new) memw($src3++#$offset) = $src2",
1911             [],"$src3 = $dst">,
1912             Requires<[HasV4T]>;
1913
1914 // if (!Pv) memw(Rx++#s4:2)=Rt
1915 // if (!Pv.new) memw(Rx++#s4:2)=Rt
1916 let hasCtrlDep = 1,
1917     isPredicated = 1 in
1918 def POST_STwri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
1919             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
1920             "if (!$src1.new) memw($src3++#$offset) = $src2",
1921             [],"$src3 = $dst">,
1922             Requires<[HasV4T]>;
1923
1924
1925 /// store to global address
1926
1927 let isPredicable = 1, neverHasSideEffects = 1 in
1928 def STrid_GP_V4 : STInst2<(outs),
1929             (ins globaladdress:$global, u16Imm:$offset, DoubleRegs:$src),
1930             "memd(#$global+$offset) = $src",
1931             []>,
1932             Requires<[HasV4T]>;
1933
1934 let neverHasSideEffects = 1, isPredicated = 1 in
1935 def STrid_GP_cPt_V4 : STInst2<(outs),
1936             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1937                                                         DoubleRegs:$src2),
1938             "if ($src1) memd(##$global+$offset) = $src2",
1939             []>,
1940             Requires<[HasV4T]>;
1941
1942 let neverHasSideEffects = 1, isPredicated = 1 in
1943 def STrid_GP_cNotPt_V4 : STInst2<(outs),
1944             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1945                                                         DoubleRegs:$src2),
1946             "if (!$src1) memd(##$global+$offset) = $src2",
1947             []>,
1948             Requires<[HasV4T]>;
1949
1950 let neverHasSideEffects = 1, isPredicated = 1 in
1951 def STrid_GP_cdnPt_V4 : STInst2<(outs),
1952             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1953                                                         DoubleRegs:$src2),
1954             "if ($src1.new) memd(##$global+$offset) = $src2",
1955             []>,
1956             Requires<[HasV4T]>;
1957
1958 let neverHasSideEffects = 1, isPredicated = 1 in
1959 def STrid_GP_cdnNotPt_V4 : STInst2<(outs),
1960             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1961                                                         DoubleRegs:$src2),
1962             "if (!$src1.new) memd(##$global+$offset) = $src2",
1963             []>,
1964             Requires<[HasV4T]>;
1965
1966 let isPredicable = 1, neverHasSideEffects = 1 in
1967 def STrib_GP_V4 : STInst2<(outs),
1968             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1969             "memb(#$global+$offset) = $src",
1970             []>,
1971             Requires<[HasV4T]>;
1972
1973 let neverHasSideEffects = 1, isPredicated = 1 in
1974 def STrib_GP_cPt_V4 : STInst2<(outs),
1975             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1976                                                         IntRegs:$src2),
1977             "if ($src1) memb(##$global+$offset) = $src2",
1978             []>,
1979             Requires<[HasV4T]>;
1980
1981 let neverHasSideEffects = 1, isPredicated = 1 in
1982 def STrib_GP_cNotPt_V4 : STInst2<(outs),
1983             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1984                                                         IntRegs:$src2),
1985             "if (!$src1) memb(##$global+$offset) = $src2",
1986             []>,
1987             Requires<[HasV4T]>;
1988
1989 let neverHasSideEffects = 1, isPredicated = 1 in
1990 def STrib_GP_cdnPt_V4 : STInst2<(outs),
1991             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1992                                                         IntRegs:$src2),
1993             "if ($src1.new) memb(##$global+$offset) = $src2",
1994             []>,
1995             Requires<[HasV4T]>;
1996
1997 let neverHasSideEffects = 1, isPredicated = 1 in
1998 def STrib_GP_cdnNotPt_V4 : STInst2<(outs),
1999             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2000                                                         IntRegs:$src2),
2001             "if (!$src1.new) memb(##$global+$offset) = $src2",
2002             []>,
2003             Requires<[HasV4T]>;
2004
2005 let isPredicable = 1, neverHasSideEffects = 1 in
2006 def STrih_GP_V4 : STInst2<(outs),
2007             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2008             "memh(#$global+$offset) = $src",
2009             []>,
2010             Requires<[HasV4T]>;
2011
2012 let neverHasSideEffects = 1, isPredicated = 1 in
2013 def STrih_GP_cPt_V4 : STInst2<(outs),
2014             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2015                                                         IntRegs:$src2),
2016             "if ($src1) memh(##$global+$offset) = $src2",
2017             []>,
2018             Requires<[HasV4T]>;
2019
2020 let neverHasSideEffects = 1, isPredicated = 1 in
2021 def STrih_GP_cNotPt_V4 : STInst2<(outs),
2022             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2023                                                         IntRegs:$src2),
2024             "if (!$src1) memh(##$global+$offset) = $src2",
2025             []>,
2026             Requires<[HasV4T]>;
2027
2028 let neverHasSideEffects = 1, isPredicated = 1 in
2029 def STrih_GP_cdnPt_V4 : STInst2<(outs),
2030             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2031                                                         IntRegs:$src2),
2032             "if ($src1.new) memh(##$global+$offset) = $src2",
2033             []>,
2034             Requires<[HasV4T]>;
2035
2036 let neverHasSideEffects = 1, isPredicated = 1 in
2037 def STrih_GP_cdnNotPt_V4 : STInst2<(outs),
2038             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2039                                                         IntRegs:$src2),
2040             "if (!$src1.new) memh(##$global+$offset) = $src2",
2041             []>,
2042             Requires<[HasV4T]>;
2043
2044 let isPredicable = 1, neverHasSideEffects = 1 in
2045 def STriw_GP_V4 : STInst2<(outs),
2046             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2047             "memw(#$global+$offset) = $src",
2048             []>,
2049             Requires<[HasV4T]>;
2050
2051 let neverHasSideEffects = 1, isPredicated = 1 in
2052 def STriw_GP_cPt_V4 : STInst2<(outs),
2053             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2054                                                         IntRegs:$src2),
2055             "if ($src1) memw(##$global+$offset) = $src2",
2056             []>,
2057             Requires<[HasV4T]>;
2058
2059 let neverHasSideEffects = 1, isPredicated = 1 in
2060 def STriw_GP_cNotPt_V4 : STInst2<(outs),
2061             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2062                                                         IntRegs:$src2),
2063             "if (!$src1) memw(##$global+$offset) = $src2",
2064             []>,
2065             Requires<[HasV4T]>;
2066
2067 let neverHasSideEffects = 1, isPredicated = 1 in
2068 def STriw_GP_cdnPt_V4 : STInst2<(outs),
2069             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2070                                                         IntRegs:$src2),
2071             "if ($src1.new) memw(##$global+$offset) = $src2",
2072             []>,
2073             Requires<[HasV4T]>;
2074
2075 let neverHasSideEffects = 1, isPredicated = 1 in
2076 def STriw_GP_cdnNotPt_V4 : STInst2<(outs),
2077             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2078                                                         IntRegs:$src2),
2079             "if (!$src1.new) memw(##$global+$offset) = $src2",
2080             []>,
2081             Requires<[HasV4T]>;
2082
2083 // memd(#global)=Rtt
2084 let isPredicable = 1, neverHasSideEffects = 1 in
2085 def STd_GP_V4 : STInst2<(outs),
2086             (ins globaladdress:$global, DoubleRegs:$src),
2087             "memd(#$global) = $src",
2088             []>,
2089             Requires<[HasV4T]>;
2090
2091 // if (Pv) memd(##global) = Rtt
2092 let neverHasSideEffects = 1, isPredicated = 1 in
2093 def STd_GP_cPt_V4 : STInst2<(outs),
2094             (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
2095             "if ($src1) memd(##$global) = $src2",
2096             []>,
2097             Requires<[HasV4T]>;
2098
2099 // if (!Pv) memd(##global) = Rtt
2100 let neverHasSideEffects = 1, isPredicated = 1 in
2101 def STd_GP_cNotPt_V4 : STInst2<(outs),
2102             (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
2103             "if (!$src1) memd(##$global) = $src2",
2104             []>,
2105               Requires<[HasV4T]>;
2106
2107 // if (Pv) memd(##global) = Rtt
2108 let neverHasSideEffects = 1, isPredicated = 1 in
2109 def STd_GP_cdnPt_V4 : STInst2<(outs),
2110             (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
2111             "if ($src1.new) memd(##$global) = $src2",
2112             []>,
2113               Requires<[HasV4T]>;
2114
2115 // if (!Pv) memd(##global) = Rtt
2116 let neverHasSideEffects = 1, isPredicated = 1 in
2117 def STd_GP_cdnNotPt_V4 : STInst2<(outs),
2118             (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
2119             "if (!$src1.new) memd(##$global) = $src2",
2120             []>,
2121             Requires<[HasV4T]>;
2122
2123 // memb(#global)=Rt
2124 let isPredicable = 1, neverHasSideEffects = 1 in
2125 def STb_GP_V4 : STInst2<(outs),
2126             (ins globaladdress:$global, IntRegs:$src),
2127             "memb(#$global) = $src",
2128             []>,
2129             Requires<[HasV4T]>;
2130
2131 // if (Pv) memb(##global) = Rt
2132 let neverHasSideEffects = 1, isPredicated = 1 in
2133 def STb_GP_cPt_V4 : STInst2<(outs),
2134             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2135             "if ($src1) memb(##$global) = $src2",
2136               []>,
2137               Requires<[HasV4T]>;
2138
2139 // if (!Pv) memb(##global) = Rt
2140 let neverHasSideEffects = 1, isPredicated = 1 in
2141 def STb_GP_cNotPt_V4 : STInst2<(outs),
2142             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2143             "if (!$src1) memb(##$global) = $src2",
2144               []>,
2145               Requires<[HasV4T]>;
2146
2147 // if (Pv) memb(##global) = Rt
2148 let neverHasSideEffects = 1, isPredicated = 1 in
2149 def STb_GP_cdnPt_V4 : STInst2<(outs),
2150             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2151             "if ($src1.new) memb(##$global) = $src2",
2152               []>,
2153               Requires<[HasV4T]>;
2154
2155 // if (!Pv) memb(##global) = Rt
2156 let neverHasSideEffects = 1, isPredicated = 1 in
2157 def STb_GP_cdnNotPt_V4 : STInst2<(outs),
2158             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2159             "if (!$src1.new) memb(##$global) = $src2",
2160               []>,
2161               Requires<[HasV4T]>;
2162
2163 // memh(#global)=Rt
2164 let isPredicable = 1, neverHasSideEffects = 1 in
2165 def STh_GP_V4 : STInst2<(outs),
2166             (ins globaladdress:$global, IntRegs:$src),
2167             "memh(#$global) = $src",
2168             []>,
2169             Requires<[HasV4T]>;
2170
2171 // if (Pv) memh(##global) = Rt
2172 let neverHasSideEffects = 1, isPredicated = 1 in
2173 def STh_GP_cPt_V4 : STInst2<(outs),
2174             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2175             "if ($src1) memh(##$global) = $src2",
2176               []>,
2177               Requires<[HasV4T]>;
2178
2179 // if (!Pv) memh(##global) = Rt
2180 let neverHasSideEffects = 1, isPredicated = 1 in
2181 def STh_GP_cNotPt_V4 : STInst2<(outs),
2182             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2183             "if (!$src1) memh(##$global) = $src2",
2184               []>,
2185               Requires<[HasV4T]>;
2186
2187 // if (Pv) memh(##global) = Rt
2188 let neverHasSideEffects = 1, isPredicated = 1 in
2189 def STh_GP_cdnPt_V4 : STInst2<(outs),
2190             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2191             "if ($src1.new) memh(##$global) = $src2",
2192               []>,
2193               Requires<[HasV4T]>;
2194
2195 // if (!Pv) memh(##global) = Rt
2196 let neverHasSideEffects = 1, isPredicated = 1 in
2197 def STh_GP_cdnNotPt_V4 : STInst2<(outs),
2198             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2199             "if (!$src1.new) memh(##$global) = $src2",
2200               []>,
2201               Requires<[HasV4T]>;
2202
2203 // memw(#global)=Rt
2204 let isPredicable = 1, neverHasSideEffects = 1 in
2205 def STw_GP_V4 : STInst2<(outs),
2206             (ins globaladdress:$global, IntRegs:$src),
2207             "memw(#$global) = $src",
2208               []>,
2209               Requires<[HasV4T]>;
2210
2211 // if (Pv) memw(##global) = Rt
2212 let neverHasSideEffects = 1, isPredicated = 1 in
2213 def STw_GP_cPt_V4 : STInst2<(outs),
2214             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2215             "if ($src1) memw(##$global) = $src2",
2216               []>,
2217               Requires<[HasV4T]>;
2218
2219 // if (!Pv) memw(##global) = Rt
2220 let neverHasSideEffects = 1, isPredicated = 1 in
2221 def STw_GP_cNotPt_V4 : STInst2<(outs),
2222             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2223             "if (!$src1) memw(##$global) = $src2",
2224               []>,
2225               Requires<[HasV4T]>;
2226
2227 // if (Pv) memw(##global) = Rt
2228 let neverHasSideEffects = 1, isPredicated = 1 in
2229 def STw_GP_cdnPt_V4 : STInst2<(outs),
2230             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2231             "if ($src1.new) memw(##$global) = $src2",
2232               []>,
2233               Requires<[HasV4T]>;
2234
2235 // if (!Pv) memw(##global) = Rt
2236 let neverHasSideEffects = 1, isPredicated = 1 in
2237 def STw_GP_cdnNotPt_V4 : STInst2<(outs),
2238             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2239             "if (!$src1.new) memw(##$global) = $src2",
2240             []>,
2241               Requires<[HasV4T]>;
2242
2243 // 64 bit atomic store
2244 def : Pat <(atomic_store_64 (HexagonCONST32_GP tglobaladdr:$global),
2245                             (i64 DoubleRegs:$src1)),
2246            (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2247            Requires<[HasV4T]>;
2248
2249 // Map from store(globaladdress) -> memd(#foo)
2250 let AddedComplexity = 100 in
2251 def : Pat <(store (i64 DoubleRegs:$src1),
2252                   (HexagonCONST32_GP tglobaladdr:$global)),
2253            (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2254            Requires<[HasV4T]>;
2255
2256 // 8 bit atomic store
2257 def : Pat < (atomic_store_8 (HexagonCONST32_GP tglobaladdr:$global),
2258                             (i32 IntRegs:$src1)),
2259             (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2260               Requires<[HasV4T]>;
2261
2262 // Map from store(globaladdress) -> memb(#foo)
2263 let AddedComplexity = 100 in
2264 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
2265           (HexagonCONST32_GP tglobaladdr:$global)),
2266           (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2267           Requires<[HasV4T]>;
2268
2269 // Map from "i1 = constant<-1>; memw(CONST32(#foo)) = i1"
2270 //       to "r0 = 1; memw(#foo) = r0"
2271 let AddedComplexity = 100 in
2272 def : Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
2273           (STb_GP_V4 tglobaladdr:$global, (TFRI 1))>,
2274           Requires<[HasV4T]>;
2275
2276 def : Pat<(atomic_store_16 (HexagonCONST32_GP tglobaladdr:$global),
2277                            (i32 IntRegs:$src1)),
2278           (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2279           Requires<[HasV4T]>;
2280
2281 // Map from store(globaladdress) -> memh(#foo)
2282 let AddedComplexity = 100 in
2283 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
2284                          (HexagonCONST32_GP tglobaladdr:$global)),
2285           (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2286           Requires<[HasV4T]>;
2287
2288 // 32 bit atomic store
2289 def : Pat<(atomic_store_32 (HexagonCONST32_GP tglobaladdr:$global),
2290                            (i32 IntRegs:$src1)),
2291           (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2292           Requires<[HasV4T]>;
2293
2294 // Map from store(globaladdress) -> memw(#foo)
2295 let AddedComplexity = 100 in
2296 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
2297           (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2298           Requires<[HasV4T]>;
2299
2300 def : Pat<(atomic_store_64 (add (HexagonCONST32_GP tglobaladdr:$global),
2301                                 u16ImmPred:$offset),
2302                            (i64 DoubleRegs:$src1)),
2303           (STrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2304                                             (i64 DoubleRegs:$src1))>,
2305           Requires<[HasV4T]>;
2306
2307 def : Pat<(atomic_store_32 (add (HexagonCONST32_GP tglobaladdr:$global),
2308                                 u16ImmPred:$offset),
2309                            (i32 IntRegs:$src1)),
2310           (STriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2311                                             (i32 IntRegs:$src1))>,
2312           Requires<[HasV4T]>;
2313
2314 def : Pat<(atomic_store_16 (add (HexagonCONST32_GP tglobaladdr:$global),
2315                                 u16ImmPred:$offset),
2316                            (i32 IntRegs:$src1)),
2317           (STrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2318                                             (i32 IntRegs:$src1))>,
2319           Requires<[HasV4T]>;
2320
2321 def : Pat<(atomic_store_8 (add (HexagonCONST32_GP tglobaladdr:$global),
2322                                u16ImmPred:$offset),
2323                           (i32 IntRegs:$src1)),
2324           (STrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2325                                             (i32 IntRegs:$src1))>,
2326           Requires<[HasV4T]>;
2327
2328 // Map from store(globaladdress + x) -> memd(#foo + x)
2329 let AddedComplexity = 100 in
2330 def : Pat<(store (i64 DoubleRegs:$src1),
2331                     (add (HexagonCONST32_GP tglobaladdr:$global),
2332                                         u16ImmPred:$offset)),
2333           (STrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2334                                             (i64 DoubleRegs:$src1))>,
2335           Requires<[HasV4T]>;
2336
2337 // Map from store(globaladdress + x) -> memb(#foo + x)
2338 let AddedComplexity = 100 in
2339 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
2340                         (add (HexagonCONST32_GP tglobaladdr:$global),
2341                              u16ImmPred:$offset)),
2342           (STrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2343                                             (i32 IntRegs:$src1))>,
2344           Requires<[HasV4T]>;
2345
2346 // Map from store(globaladdress + x) -> memh(#foo + x)
2347 let AddedComplexity = 100 in
2348 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
2349                          (add (HexagonCONST32_GP tglobaladdr:$global),
2350                               u16ImmPred:$offset)),
2351           (STrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2352                                             (i32 IntRegs:$src1))>,
2353           Requires<[HasV4T]>;
2354
2355 // Map from store(globaladdress + x) -> memw(#foo + x)
2356 let AddedComplexity = 100 in
2357 def : Pat<(store (i32 IntRegs:$src1),
2358                  (add (HexagonCONST32_GP tglobaladdr:$global),
2359                                 u16ImmPred:$offset)),
2360           (STriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2361                                             (i32 IntRegs:$src1))>,
2362           Requires<[HasV4T]>;
2363
2364
2365
2366 //===----------------------------------------------------------------------===
2367 // ST -
2368 //===----------------------------------------------------------------------===
2369
2370
2371 //===----------------------------------------------------------------------===//
2372 // NV/ST +
2373 //===----------------------------------------------------------------------===//
2374
2375 // Store new-value byte.
2376
2377 // memb(Re=#U6)=Nt.new
2378 // memb(Rs+#s11:0)=Nt.new
2379 let mayStore = 1, isPredicable = 1 in
2380 def STrib_nv_V4 : NVInst_V4<(outs), (ins MEMri:$addr, IntRegs:$src1),
2381             "memb($addr) = $src1.new",
2382             []>,
2383             Requires<[HasV4T]>;
2384
2385 let mayStore = 1, isPredicable = 1 in
2386 def STrib_indexed_nv_V4 : NVInst_V4<(outs),
2387             (ins IntRegs:$src1, s11_0Imm:$src2, IntRegs:$src3),
2388             "memb($src1+#$src2) = $src3.new",
2389             []>,
2390             Requires<[HasV4T]>;
2391 // memb(Ru<<#u2+#U6)=Nt.new
2392 let mayStore = 1, AddedComplexity = 10 in
2393 def STrib_shl_nv_V4 : NVInst_V4<(outs),
2394             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
2395             "memb($src1<<#$src2+#$src3) = $src4.new",
2396             []>,
2397             Requires<[HasV4T]>;
2398
2399 // memb(Rx++#s4:0)=Nt.new
2400 let mayStore = 1, hasCtrlDep = 1, isPredicable = 1  in
2401 def POST_STbri_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2402             (ins IntRegs:$src1, IntRegs:$src2, s4_0Imm:$offset),
2403             "memb($src2++#$offset) = $src1.new",
2404             [],
2405             "$src2 = $dst">,
2406             Requires<[HasV4T]>;
2407
2408 // memb(Rx++#s4:0:circ(Mu))=Nt.new
2409 // memb(Rx++I:circ(Mu))=Nt.new
2410 // memb(Rx++Mu)=Nt.new
2411 // memb(Rx++Mu:brev)=Nt.new
2412
2413 // memb(gp+#u16:0)=Nt.new
2414 let mayStore = 1, neverHasSideEffects = 1 in
2415 def STrib_GP_nv_V4 : NVInst_V4<(outs),
2416             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2417             "memb(#$global+$offset) = $src.new",
2418             []>,
2419             Requires<[HasV4T]>;
2420
2421 // memb(#global)=Nt.new
2422 let mayStore = 1, neverHasSideEffects = 1 in
2423 def STb_GP_nv_V4 : NVInst_V4<(outs),
2424             (ins globaladdress:$global, IntRegs:$src),
2425             "memb(#$global) = $src.new",
2426             []>,
2427             Requires<[HasV4T]>;
2428
2429 // Store new-value byte conditionally.
2430 // if ([!]Pv[.new]) memb(#u6)=Nt.new
2431 // if (Pv) memb(Rs+#u6:0)=Nt.new
2432 let mayStore = 1, neverHasSideEffects = 1,
2433     isPredicated = 1 in
2434 def STrib_cPt_nv_V4 : NVInst_V4<(outs),
2435             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2436             "if ($src1) memb($addr) = $src2.new",
2437             []>,
2438             Requires<[HasV4T]>;
2439
2440 // if (Pv.new) memb(Rs+#u6:0)=Nt.new
2441 let mayStore = 1, neverHasSideEffects = 1,
2442     isPredicated = 1 in
2443 def STrib_cdnPt_nv_V4 : NVInst_V4<(outs),
2444             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2445             "if ($src1.new) memb($addr) = $src2.new",
2446             []>,
2447             Requires<[HasV4T]>;
2448
2449 // if (!Pv) memb(Rs+#u6:0)=Nt.new
2450 let mayStore = 1, neverHasSideEffects = 1,
2451     isPredicated = 1 in
2452 def STrib_cNotPt_nv_V4 : NVInst_V4<(outs),
2453             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2454             "if (!$src1) memb($addr) = $src2.new",
2455             []>,
2456             Requires<[HasV4T]>;
2457
2458 // if (!Pv.new) memb(Rs+#u6:0)=Nt.new
2459 let mayStore = 1, neverHasSideEffects = 1,
2460     isPredicated = 1 in
2461 def STrib_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2462             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2463             "if (!$src1.new) memb($addr) = $src2.new",
2464             []>,
2465             Requires<[HasV4T]>;
2466
2467 // if (Pv) memb(Rs+#u6:0)=Nt.new
2468 let mayStore = 1, neverHasSideEffects = 1,
2469     isPredicated = 1 in
2470 def STrib_indexed_cPt_nv_V4 : NVInst_V4<(outs),
2471             (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
2472             "if ($src1) memb($src2+#$src3) = $src4.new",
2473             []>,
2474             Requires<[HasV4T]>;
2475
2476 // if (Pv.new) memb(Rs+#u6:0)=Nt.new
2477 let mayStore = 1, neverHasSideEffects = 1,
2478     isPredicated = 1 in
2479 def STrib_indexed_cdnPt_nv_V4 : NVInst_V4<(outs),
2480             (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
2481             "if ($src1.new) memb($src2+#$src3) = $src4.new",
2482             []>,
2483             Requires<[HasV4T]>;
2484
2485 // if (!Pv) memb(Rs+#u6:0)=Nt.new
2486 let mayStore = 1, neverHasSideEffects = 1,
2487     isPredicated = 1 in
2488 def STrib_indexed_cNotPt_nv_V4 : NVInst_V4<(outs),
2489             (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
2490             "if (!$src1) memb($src2+#$src3) = $src4.new",
2491             []>,
2492             Requires<[HasV4T]>;
2493
2494 // if (!Pv.new) memb(Rs+#u6:0)=Nt.new
2495 let mayStore = 1, neverHasSideEffects = 1,
2496     isPredicated = 1 in
2497 def STrib_indexed_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2498             (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
2499             "if (!$src1.new) memb($src2+#$src3) = $src4.new",
2500             []>,
2501             Requires<[HasV4T]>;
2502
2503 // if ([!]Pv[.new]) memb(Rx++#s4:0)=Nt.new
2504 // if (Pv) memb(Rx++#s4:0)=Nt.new
2505 let mayStore = 1, hasCtrlDep = 1,
2506     isPredicated = 1 in
2507 def POST_STbri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2508             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
2509             "if ($src1) memb($src3++#$offset) = $src2.new",
2510             [],"$src3 = $dst">,
2511             Requires<[HasV4T]>;
2512
2513 // if (Pv.new) memb(Rx++#s4:0)=Nt.new
2514 let mayStore = 1, hasCtrlDep = 1,
2515     isPredicated = 1 in
2516 def POST_STbri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2517             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
2518             "if ($src1.new) memb($src3++#$offset) = $src2.new",
2519             [],"$src3 = $dst">,
2520             Requires<[HasV4T]>;
2521
2522 // if (!Pv) memb(Rx++#s4:0)=Nt.new
2523 let mayStore = 1, hasCtrlDep = 1,
2524     isPredicated = 1 in
2525 def POST_STbri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2526             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
2527             "if (!$src1) memb($src3++#$offset) = $src2.new",
2528             [],"$src3 = $dst">,
2529             Requires<[HasV4T]>;
2530
2531 // if (!Pv.new) memb(Rx++#s4:0)=Nt.new
2532 let mayStore = 1, hasCtrlDep = 1,
2533     isPredicated = 1 in
2534 def POST_STbri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2535             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
2536             "if (!$src1.new) memb($src3++#$offset) = $src2.new",
2537             [],"$src3 = $dst">,
2538             Requires<[HasV4T]>;
2539
2540
2541 // Store new-value halfword.
2542 // memh(Re=#U6)=Nt.new
2543 // memh(Rs+#s11:1)=Nt.new
2544 let mayStore = 1, isPredicable = 1 in
2545 def STrih_nv_V4 : NVInst_V4<(outs), (ins MEMri:$addr, IntRegs:$src1),
2546             "memh($addr) = $src1.new",
2547             []>,
2548             Requires<[HasV4T]>;
2549
2550 let mayStore = 1, isPredicable = 1 in
2551 def STrih_indexed_nv_V4 : NVInst_V4<(outs),
2552             (ins IntRegs:$src1, s11_1Imm:$src2, IntRegs:$src3),
2553             "memh($src1+#$src2) = $src3.new",
2554             []>,
2555             Requires<[HasV4T]>;
2556
2557 // memh(Ru<<#u2+#U6)=Nt.new
2558 let mayStore = 1, AddedComplexity = 10 in
2559 def STrih_shl_nv_V4 : NVInst_V4<(outs),
2560             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
2561             "memh($src1<<#$src2+#$src3) = $src4.new",
2562             []>,
2563             Requires<[HasV4T]>;
2564
2565 // memh(Rx++#s4:1)=Nt.new
2566 let mayStore = 1, hasCtrlDep = 1, isPredicable = 1  in
2567 def POST_SThri_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2568             (ins IntRegs:$src1, IntRegs:$src2, s4_1Imm:$offset),
2569             "memh($src2++#$offset) = $src1.new",
2570             [],
2571             "$src2 = $dst">,
2572             Requires<[HasV4T]>;
2573
2574 // memh(Rx++#s4:1:circ(Mu))=Nt.new
2575 // memh(Rx++I:circ(Mu))=Nt.new
2576 // memh(Rx++Mu)=Nt.new
2577 // memh(Rx++Mu:brev)=Nt.new
2578
2579 // memh(gp+#u16:1)=Nt.new
2580 let mayStore = 1, neverHasSideEffects = 1 in
2581 def STrih_GP_nv_V4 : NVInst_V4<(outs),
2582             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2583             "memh(#$global+$offset) = $src.new",
2584             []>,
2585             Requires<[HasV4T]>;
2586
2587 // memh(#global)=Nt.new
2588 let mayStore = 1, neverHasSideEffects = 1 in
2589 def STh_GP_nv_V4 : NVInst_V4<(outs),
2590             (ins globaladdress:$global, IntRegs:$src),
2591             "memh(#$global) = $src.new",
2592             []>,
2593             Requires<[HasV4T]>;
2594
2595
2596 // Store new-value halfword conditionally.
2597
2598 // if ([!]Pv[.new]) memh(#u6)=Nt.new
2599
2600 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Nt.new
2601 // if (Pv) memh(Rs+#u6:1)=Nt.new
2602 let mayStore = 1, neverHasSideEffects = 1,
2603     isPredicated = 1 in
2604 def STrih_cPt_nv_V4 : NVInst_V4<(outs),
2605             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2606             "if ($src1) memh($addr) = $src2.new",
2607             []>,
2608             Requires<[HasV4T]>;
2609
2610 // if (Pv.new) memh(Rs+#u6:1)=Nt.new
2611 let mayStore = 1, neverHasSideEffects = 1,
2612     isPredicated = 1 in
2613 def STrih_cdnPt_nv_V4 : NVInst_V4<(outs),
2614             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2615             "if ($src1.new) memh($addr) = $src2.new",
2616             []>,
2617             Requires<[HasV4T]>;
2618
2619 // if (!Pv) memh(Rs+#u6:1)=Nt.new
2620 let mayStore = 1, neverHasSideEffects = 1,
2621     isPredicated = 1 in
2622 def STrih_cNotPt_nv_V4 : NVInst_V4<(outs),
2623             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2624             "if (!$src1) memh($addr) = $src2.new",
2625             []>,
2626             Requires<[HasV4T]>;
2627
2628 // if (!Pv.new) memh(Rs+#u6:1)=Nt.new
2629 let mayStore = 1, neverHasSideEffects = 1,
2630     isPredicated = 1 in
2631 def STrih_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2632             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2633             "if (!$src1.new) memh($addr) = $src2.new",
2634             []>,
2635             Requires<[HasV4T]>;
2636
2637 // if (Pv) memh(Rs+#u6:1)=Nt.new
2638 let mayStore = 1, neverHasSideEffects = 1,
2639     isPredicated = 1 in
2640 def STrih_indexed_cPt_nv_V4 : NVInst_V4<(outs),
2641             (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
2642             "if ($src1) memh($src2+#$src3) = $src4.new",
2643             []>,
2644             Requires<[HasV4T]>;
2645
2646 // if (Pv.new) memh(Rs+#u6:1)=Nt.new
2647 let mayStore = 1, neverHasSideEffects = 1,
2648     isPredicated = 1 in
2649 def STrih_indexed_cdnPt_nv_V4 : NVInst_V4<(outs),
2650             (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
2651             "if ($src1.new) memh($src2+#$src3) = $src4.new",
2652             []>,
2653             Requires<[HasV4T]>;
2654
2655 // if (!Pv) memh(Rs+#u6:1)=Nt.new
2656 let mayStore = 1, neverHasSideEffects = 1,
2657     isPredicated = 1 in
2658 def STrih_indexed_cNotPt_nv_V4 : NVInst_V4<(outs),
2659             (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
2660             "if (!$src1) memh($src2+#$src3) = $src4.new",
2661             []>,
2662             Requires<[HasV4T]>;
2663
2664 // if (!Pv.new) memh(Rs+#u6:1)=Nt.new
2665 let mayStore = 1, neverHasSideEffects = 1,
2666     isPredicated = 1 in
2667 def STrih_indexed_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2668             (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
2669             "if (!$src1.new) memh($src2+#$src3) = $src4.new",
2670             []>,
2671             Requires<[HasV4T]>;
2672
2673 // if ([!]Pv[]) memh(Rx++#s4:1)=Nt.new
2674 // if (Pv) memh(Rx++#s4:1)=Nt.new
2675 let mayStore = 1, hasCtrlDep = 1,
2676     isPredicated = 1 in
2677 def POST_SThri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2678             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2679             "if ($src1) memh($src3++#$offset) = $src2.new",
2680             [],"$src3 = $dst">,
2681             Requires<[HasV4T]>;
2682
2683 // if (Pv.new) memh(Rx++#s4:1)=Nt.new
2684 let mayStore = 1, hasCtrlDep = 1,
2685     isPredicated = 1 in
2686 def POST_SThri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2687             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2688             "if ($src1.new) memh($src3++#$offset) = $src2.new",
2689             [],"$src3 = $dst">,
2690             Requires<[HasV4T]>;
2691
2692 // if (!Pv) memh(Rx++#s4:1)=Nt.new
2693 let mayStore = 1, hasCtrlDep = 1,
2694     isPredicated = 1 in
2695 def POST_SThri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2696             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2697             "if (!$src1) memh($src3++#$offset) = $src2.new",
2698             [],"$src3 = $dst">,
2699             Requires<[HasV4T]>;
2700
2701 // if (!Pv.new) memh(Rx++#s4:1)=Nt.new
2702 let mayStore = 1, hasCtrlDep = 1,
2703     isPredicated = 1 in
2704 def POST_SThri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2705             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2706             "if (!$src1.new) memh($src3++#$offset) = $src2.new",
2707             [],"$src3 = $dst">,
2708             Requires<[HasV4T]>;
2709
2710
2711 // Store new-value word.
2712
2713 // memw(Re=#U6)=Nt.new
2714 // memw(Rs+#s11:2)=Nt.new
2715 let mayStore = 1, isPredicable = 1 in
2716 def STriw_nv_V4 : NVInst_V4<(outs),
2717             (ins MEMri:$addr, IntRegs:$src1),
2718             "memw($addr) = $src1.new",
2719             []>,
2720             Requires<[HasV4T]>;
2721
2722 let mayStore = 1, isPredicable = 1 in
2723 def STriw_indexed_nv_V4 : NVInst_V4<(outs),
2724             (ins IntRegs:$src1, s11_2Imm:$src2, IntRegs:$src3),
2725             "memw($src1+#$src2) = $src3.new",
2726             []>,
2727             Requires<[HasV4T]>;
2728
2729 // memw(Ru<<#u2+#U6)=Nt.new
2730 let mayStore = 1, AddedComplexity = 10 in
2731 def STriw_shl_nv_V4 : NVInst_V4<(outs),
2732             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
2733             "memw($src1<<#$src2+#$src3) = $src4.new",
2734             []>,
2735             Requires<[HasV4T]>;
2736
2737 // memw(Rx++#s4:2)=Nt.new
2738 let mayStore = 1, hasCtrlDep = 1, isPredicable = 1  in
2739 def POST_STwri_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2740             (ins IntRegs:$src1, IntRegs:$src2, s4_2Imm:$offset),
2741             "memw($src2++#$offset) = $src1.new",
2742             [],
2743             "$src2 = $dst">,
2744             Requires<[HasV4T]>;
2745
2746 // memw(Rx++#s4:2:circ(Mu))=Nt.new
2747 // memw(Rx++I:circ(Mu))=Nt.new
2748 // memw(Rx++Mu)=Nt.new
2749 // memw(Rx++Mu:brev)=Nt.new
2750 // memw(gp+#u16:2)=Nt.new
2751 let mayStore = 1, neverHasSideEffects = 1 in
2752 def STriw_GP_nv_V4 : NVInst_V4<(outs),
2753             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2754             "memw(#$global+$offset) = $src.new",
2755             []>,
2756             Requires<[HasV4T]>;
2757
2758 let mayStore = 1, neverHasSideEffects = 1 in
2759 def STw_GP_nv_V4 : NVInst_V4<(outs),
2760             (ins globaladdress:$global, IntRegs:$src),
2761             "memw(#$global) = $src.new",
2762             []>,
2763             Requires<[HasV4T]>;
2764
2765 // Store new-value word conditionally.
2766
2767 // if ([!]Pv[.new]) memw(#u6)=Nt.new
2768
2769 // if ([!]Pv[.new]) memw(Rs+#u6:2)=Nt.new
2770 // if (Pv) memw(Rs+#u6:2)=Nt.new
2771 let mayStore = 1, neverHasSideEffects = 1,
2772     isPredicated = 1 in
2773 def STriw_cPt_nv_V4 : NVInst_V4<(outs),
2774             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2775             "if ($src1) memw($addr) = $src2.new",
2776             []>,
2777             Requires<[HasV4T]>;
2778
2779 // if (Pv.new) memw(Rs+#u6:2)=Nt.new
2780 let mayStore = 1, neverHasSideEffects = 1,
2781     isPredicated = 1 in
2782 def STriw_cdnPt_nv_V4 : NVInst_V4<(outs),
2783             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2784             "if ($src1.new) memw($addr) = $src2.new",
2785             []>,
2786             Requires<[HasV4T]>;
2787
2788 // if (!Pv) memw(Rs+#u6:2)=Nt.new
2789 let mayStore = 1, neverHasSideEffects = 1,
2790     isPredicated = 1 in
2791 def STriw_cNotPt_nv_V4 : NVInst_V4<(outs),
2792             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2793             "if (!$src1) memw($addr) = $src2.new",
2794             []>,
2795             Requires<[HasV4T]>;
2796
2797 // if (!Pv.new) memw(Rs+#u6:2)=Nt.new
2798 let mayStore = 1, neverHasSideEffects = 1,
2799     isPredicated = 1 in
2800 def STriw_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2801             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2802             "if (!$src1.new) memw($addr) = $src2.new",
2803             []>,
2804             Requires<[HasV4T]>;
2805
2806 // if (Pv) memw(Rs+#u6:2)=Nt.new
2807 let mayStore = 1, neverHasSideEffects = 1,
2808     isPredicated = 1 in
2809 def STriw_indexed_cPt_nv_V4 : NVInst_V4<(outs),
2810             (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
2811             "if ($src1) memw($src2+#$src3) = $src4.new",
2812             []>,
2813             Requires<[HasV4T]>;
2814
2815 // if (Pv.new) memw(Rs+#u6:2)=Nt.new
2816 let mayStore = 1, neverHasSideEffects = 1,
2817     isPredicated = 1 in
2818 def STriw_indexed_cdnPt_nv_V4 : NVInst_V4<(outs),
2819             (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
2820             "if ($src1.new) memw($src2+#$src3) = $src4.new",
2821             []>,
2822             Requires<[HasV4T]>;
2823
2824 // if (!Pv) memw(Rs+#u6:2)=Nt.new
2825 let mayStore = 1, neverHasSideEffects = 1,
2826     isPredicated = 1 in
2827 def STriw_indexed_cNotPt_nv_V4 : NVInst_V4<(outs),
2828             (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
2829             "if (!$src1) memw($src2+#$src3) = $src4.new",
2830             []>,
2831             Requires<[HasV4T]>;
2832
2833 // if (!Pv.new) memw(Rs+#u6:2)=Nt.new
2834 let mayStore = 1, neverHasSideEffects = 1,
2835     isPredicated = 1 in
2836 def STriw_indexed_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2837             (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
2838             "if (!$src1.new) memw($src2+#$src3) = $src4.new",
2839             []>,
2840             Requires<[HasV4T]>;
2841
2842 // if ([!]Pv[.new]) memw(Rx++#s4:2)=Nt.new
2843 // if (Pv) memw(Rx++#s4:2)=Nt.new
2844 let mayStore = 1, hasCtrlDep = 1,
2845     isPredicated = 1 in
2846 def POST_STwri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2847             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2848             "if ($src1) memw($src3++#$offset) = $src2.new",
2849             [],"$src3 = $dst">,
2850             Requires<[HasV4T]>;
2851
2852 // if (Pv.new) memw(Rx++#s4:2)=Nt.new
2853 let mayStore = 1, hasCtrlDep = 1,
2854     isPredicated = 1 in
2855 def POST_STwri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2856             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2857             "if ($src1.new) memw($src3++#$offset) = $src2.new",
2858             [],"$src3 = $dst">,
2859             Requires<[HasV4T]>;
2860
2861 // if (!Pv) memw(Rx++#s4:2)=Nt.new
2862 let mayStore = 1, hasCtrlDep = 1,
2863     isPredicated = 1 in
2864 def POST_STwri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2865             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2866             "if (!$src1) memw($src3++#$offset) = $src2.new",
2867             [],"$src3 = $dst">,
2868             Requires<[HasV4T]>;
2869
2870 // if (!Pv.new) memw(Rx++#s4:2)=Nt.new
2871 let mayStore = 1, hasCtrlDep = 1,
2872     isPredicated = 1 in
2873 def POST_STwri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2874             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2875             "if (!$src1.new) memw($src3++#$offset) = $src2.new",
2876             [],"$src3 = $dst">,
2877             Requires<[HasV4T]>;
2878
2879
2880
2881 // if (Pv) memb(##global) = Rt
2882 let mayStore = 1, neverHasSideEffects = 1 in
2883 def STb_GP_cPt_nv_V4 : NVInst_V4<(outs),
2884             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2885             "if ($src1) memb(##$global) = $src2.new",
2886             []>,
2887             Requires<[HasV4T]>;
2888
2889 // if (!Pv) memb(##global) = Rt
2890 let mayStore = 1, neverHasSideEffects = 1 in
2891 def STb_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
2892             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2893             "if (!$src1) memb(##$global) = $src2.new",
2894             []>,
2895             Requires<[HasV4T]>;
2896
2897 // if (Pv) memb(##global) = Rt
2898 let mayStore = 1, neverHasSideEffects = 1 in
2899 def STb_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
2900             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2901             "if ($src1.new) memb(##$global) = $src2.new",
2902             []>,
2903             Requires<[HasV4T]>;
2904
2905 // if (!Pv) memb(##global) = Rt
2906 let mayStore = 1, neverHasSideEffects = 1 in
2907 def STb_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2908             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2909             "if (!$src1.new) memb(##$global) = $src2.new",
2910             []>,
2911             Requires<[HasV4T]>;
2912
2913 // if (Pv) memh(##global) = Rt
2914 let mayStore = 1, neverHasSideEffects = 1 in
2915 def STh_GP_cPt_nv_V4 : NVInst_V4<(outs),
2916             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2917             "if ($src1) memh(##$global) = $src2.new",
2918             []>,
2919             Requires<[HasV4T]>;
2920
2921 // if (!Pv) memh(##global) = Rt
2922 let mayStore = 1, neverHasSideEffects = 1 in
2923 def STh_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
2924             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2925             "if (!$src1) memh(##$global) = $src2.new",
2926             []>,
2927             Requires<[HasV4T]>;
2928
2929 // if (Pv) memh(##global) = Rt
2930 let mayStore = 1, neverHasSideEffects = 1 in
2931 def STh_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
2932             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2933             "if ($src1.new) memh(##$global) = $src2.new",
2934             []>,
2935             Requires<[HasV4T]>;
2936
2937 // if (!Pv) memh(##global) = Rt
2938 let mayStore = 1, neverHasSideEffects = 1 in
2939 def STh_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2940             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2941             "if (!$src1.new) memh(##$global) = $src2.new",
2942             []>,
2943             Requires<[HasV4T]>;
2944
2945 // if (Pv) memw(##global) = Rt
2946 let mayStore = 1, neverHasSideEffects = 1 in
2947 def STw_GP_cPt_nv_V4 : NVInst_V4<(outs),
2948             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2949             "if ($src1) memw(##$global) = $src2.new",
2950             []>,
2951             Requires<[HasV4T]>;
2952
2953 // if (!Pv) memw(##global) = Rt
2954 let mayStore = 1, neverHasSideEffects = 1 in
2955 def STw_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
2956             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2957             "if (!$src1) memw(##$global) = $src2.new",
2958             []>,
2959             Requires<[HasV4T]>;
2960
2961 // if (Pv) memw(##global) = Rt
2962 let mayStore = 1, neverHasSideEffects = 1 in
2963 def STw_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
2964             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2965             "if ($src1.new) memw(##$global) = $src2.new",
2966             []>,
2967             Requires<[HasV4T]>;
2968
2969 // if (!Pv) memw(##global) = Rt
2970 let mayStore = 1, neverHasSideEffects = 1 in
2971 def STw_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2972             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2973             "if (!$src1.new) memw(##$global) = $src2.new",
2974             []>,
2975             Requires<[HasV4T]>;
2976
2977 let mayStore = 1, neverHasSideEffects = 1 in
2978 def STrib_GP_cPt_nv_V4 : NVInst_V4<(outs),
2979             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2980                                                         IntRegs:$src2),
2981             "if ($src1) memb(##$global+$offset) = $src2.new",
2982             []>,
2983             Requires<[HasV4T]>;
2984
2985 let mayStore = 1, neverHasSideEffects = 1 in
2986 def STrib_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
2987             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2988                                                         IntRegs:$src2),
2989             "if (!$src1) memb(##$global+$offset) = $src2.new",
2990             []>,
2991             Requires<[HasV4T]>;
2992
2993 let mayStore = 1, neverHasSideEffects = 1 in
2994 def STrib_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
2995             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2996                                                         IntRegs:$src2),
2997             "if ($src1.new) memb(##$global+$offset) = $src2.new",
2998             []>,
2999             Requires<[HasV4T]>;
3000
3001 let mayStore = 1, neverHasSideEffects = 1 in
3002 def STrib_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3003             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3004                                                         IntRegs:$src2),
3005             "if (!$src1.new) memb(##$global+$offset) = $src2.new",
3006             []>,
3007             Requires<[HasV4T]>;
3008
3009 let mayStore = 1, neverHasSideEffects = 1 in
3010 def STrih_GP_cPt_nv_V4 : NVInst_V4<(outs),
3011             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3012                                                         IntRegs:$src2),
3013             "if ($src1) memh(##$global+$offset) = $src2.new",
3014             []>,
3015             Requires<[HasV4T]>;
3016
3017 let mayStore = 1, neverHasSideEffects = 1 in
3018 def STrih_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
3019             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3020                                                         IntRegs:$src2),
3021             "if (!$src1) memh(##$global+$offset) = $src2.new",
3022             []>,
3023             Requires<[HasV4T]>;
3024
3025 let mayStore = 1, neverHasSideEffects = 1 in
3026 def STrih_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
3027             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3028                                                         IntRegs:$src2),
3029             "if ($src1.new) memh(##$global+$offset) = $src2.new",
3030             []>,
3031             Requires<[HasV4T]>;
3032
3033 let mayStore = 1, neverHasSideEffects = 1 in
3034 def STrih_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3035             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3036                                                         IntRegs:$src2),
3037             "if (!$src1.new) memh(##$global+$offset) = $src2.new",
3038             []>,
3039             Requires<[HasV4T]>;
3040
3041 let mayStore = 1, neverHasSideEffects = 1 in
3042 def STriw_GP_cPt_nv_V4 : NVInst_V4<(outs),
3043             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3044                                                         IntRegs:$src2),
3045             "if ($src1) memw(##$global+$offset) = $src2.new",
3046             []>,
3047             Requires<[HasV4T]>;
3048
3049 let mayStore = 1, neverHasSideEffects = 1 in
3050 def STriw_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
3051             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3052                                                         IntRegs:$src2),
3053             "if (!$src1) memw(##$global+$offset) = $src2.new",
3054             []>,
3055             Requires<[HasV4T]>;
3056
3057 let mayStore = 1, neverHasSideEffects = 1 in
3058 def STriw_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
3059             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3060                                                         IntRegs:$src2),
3061             "if ($src1.new) memw(##$global+$offset) = $src2.new",
3062             []>,
3063             Requires<[HasV4T]>;
3064
3065 let mayStore = 1, neverHasSideEffects = 1 in
3066 def STriw_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3067             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3068                                                         IntRegs:$src2),
3069             "if (!$src1.new) memw(##$global+$offset) = $src2.new",
3070             []>,
3071             Requires<[HasV4T]>;
3072
3073 //===----------------------------------------------------------------------===//
3074 // NV/ST -
3075 //===----------------------------------------------------------------------===//
3076
3077 //===----------------------------------------------------------------------===//
3078 // NV/J +
3079 //===----------------------------------------------------------------------===//
3080
3081 multiclass NVJ_type_basic_reg<string NotStr, string OpcStr, string TakenStr> {
3082   def _ie_nv_V4 : NVInst_V4<(outs),
3083             (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
3084             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3085             !strconcat("($src1.new, $src2)) jump:",
3086             !strconcat(TakenStr, " $offset"))))),
3087             []>,
3088             Requires<[HasV4T]>;
3089
3090   def _nv_V4 : NVInst_V4<(outs),
3091             (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
3092             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3093             !strconcat("($src1.new, $src2)) jump:",
3094             !strconcat(TakenStr, " $offset"))))),
3095             []>,
3096             Requires<[HasV4T]>;
3097 }
3098
3099 multiclass NVJ_type_basic_2ndDotNew<string NotStr, string OpcStr,
3100                                                    string TakenStr> {
3101   def _ie_nv_V4 : NVInst_V4<(outs),
3102             (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
3103             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3104             !strconcat("($src1, $src2.new)) jump:",
3105             !strconcat(TakenStr, " $offset"))))),
3106             []>,
3107             Requires<[HasV4T]>;
3108
3109   def _nv_V4 : NVInst_V4<(outs),
3110             (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
3111             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3112             !strconcat("($src1, $src2.new)) jump:",
3113             !strconcat(TakenStr, " $offset"))))),
3114             []>,
3115             Requires<[HasV4T]>;
3116 }
3117
3118 multiclass NVJ_type_basic_imm<string NotStr, string OpcStr, string TakenStr> {
3119   def _ie_nv_V4 : NVInst_V4<(outs),
3120             (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
3121             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3122             !strconcat("($src1.new, #$src2)) jump:",
3123             !strconcat(TakenStr, " $offset"))))),
3124             []>,
3125             Requires<[HasV4T]>;
3126
3127   def _nv_V4 : NVInst_V4<(outs),
3128             (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
3129             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3130             !strconcat("($src1.new, #$src2)) jump:",
3131             !strconcat(TakenStr, " $offset"))))),
3132             []>,
3133             Requires<[HasV4T]>;
3134 }
3135
3136 multiclass NVJ_type_basic_neg<string NotStr, string OpcStr, string TakenStr> {
3137   def _ie_nv_V4 : NVInst_V4<(outs),
3138             (ins IntRegs:$src1, nOneImm:$src2, brtarget:$offset),
3139             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3140             !strconcat("($src1.new, #$src2)) jump:",
3141             !strconcat(TakenStr, " $offset"))))),
3142             []>,
3143             Requires<[HasV4T]>;
3144
3145   def _nv_V4 : NVInst_V4<(outs),
3146             (ins IntRegs:$src1, nOneImm:$src2, brtarget:$offset),
3147             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3148             !strconcat("($src1.new, #$src2)) jump:",
3149             !strconcat(TakenStr, " $offset"))))),
3150             []>,
3151             Requires<[HasV4T]>;
3152 }
3153
3154 multiclass NVJ_type_basic_tstbit<string NotStr, string OpcStr,
3155                                                 string TakenStr> {
3156   def _ie_nv_V4 : NVInst_V4<(outs),
3157             (ins IntRegs:$src1, u1Imm:$src2, brtarget:$offset),
3158             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3159             !strconcat("($src1.new, #$src2)) jump:",
3160             !strconcat(TakenStr, " $offset"))))),
3161             []>,
3162             Requires<[HasV4T]>;
3163
3164   def _nv_V4 : NVInst_V4<(outs),
3165             (ins IntRegs:$src1, u1Imm:$src2, brtarget:$offset),
3166             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3167             !strconcat("($src1.new, #$src2)) jump:",
3168             !strconcat(TakenStr, " $offset"))))),
3169             []>,
3170             Requires<[HasV4T]>;
3171 }
3172
3173 // Multiclass for regular dot new of Ist operand register.
3174 multiclass NVJ_type_br_pred_reg<string NotStr, string OpcStr> {
3175   defm Pt  : NVJ_type_basic_reg<NotStr, OpcStr, "t">;
3176   defm Pnt : NVJ_type_basic_reg<NotStr, OpcStr, "nt">;
3177 }
3178
3179 // Multiclass for dot new of 2nd operand register.
3180 multiclass NVJ_type_br_pred_2ndDotNew<string NotStr, string OpcStr> {
3181   defm Pt  : NVJ_type_basic_2ndDotNew<NotStr, OpcStr, "t">;
3182   defm Pnt : NVJ_type_basic_2ndDotNew<NotStr, OpcStr, "nt">;
3183 }
3184
3185 // Multiclass for 2nd operand immediate, including -1.
3186 multiclass NVJ_type_br_pred_imm<string NotStr, string OpcStr> {
3187   defm Pt     : NVJ_type_basic_imm<NotStr, OpcStr, "t">;
3188   defm Pnt    : NVJ_type_basic_imm<NotStr, OpcStr, "nt">;
3189   defm Ptneg  : NVJ_type_basic_neg<NotStr, OpcStr, "t">;
3190   defm Pntneg : NVJ_type_basic_neg<NotStr, OpcStr, "nt">;
3191 }
3192
3193 // Multiclass for 2nd operand immediate, excluding -1.
3194 multiclass NVJ_type_br_pred_imm_only<string NotStr, string OpcStr> {
3195   defm Pt     : NVJ_type_basic_imm<NotStr, OpcStr, "t">;
3196   defm Pnt    : NVJ_type_basic_imm<NotStr, OpcStr, "nt">;
3197 }
3198
3199 // Multiclass for tstbit, where 2nd operand is always #0.
3200 multiclass NVJ_type_br_pred_tstbit<string NotStr, string OpcStr> {
3201   defm Pt     : NVJ_type_basic_tstbit<NotStr, OpcStr, "t">;
3202   defm Pnt    : NVJ_type_basic_tstbit<NotStr, OpcStr, "nt">;
3203 }
3204
3205 // Multiclass for GT.
3206 multiclass NVJ_type_rr_ri<string OpcStr> {
3207   defm rrNot   : NVJ_type_br_pred_reg<"!", OpcStr>;
3208   defm rr      : NVJ_type_br_pred_reg<"",  OpcStr>;
3209   defm rrdnNot : NVJ_type_br_pred_2ndDotNew<"!", OpcStr>;
3210   defm rrdn    : NVJ_type_br_pred_2ndDotNew<"",  OpcStr>;
3211   defm riNot   : NVJ_type_br_pred_imm<"!", OpcStr>;
3212   defm ri      : NVJ_type_br_pred_imm<"",  OpcStr>;
3213 }
3214
3215 // Multiclass for EQ.
3216 multiclass NVJ_type_rr_ri_no_2ndDotNew<string OpcStr> {
3217   defm rrNot   : NVJ_type_br_pred_reg<"!", OpcStr>;
3218   defm rr      : NVJ_type_br_pred_reg<"",  OpcStr>;
3219   defm riNot   : NVJ_type_br_pred_imm<"!", OpcStr>;
3220   defm ri      : NVJ_type_br_pred_imm<"",  OpcStr>;
3221 }
3222
3223 // Multiclass for GTU.
3224 multiclass NVJ_type_rr_ri_no_nOne<string OpcStr> {
3225   defm rrNot   : NVJ_type_br_pred_reg<"!", OpcStr>;
3226   defm rr      : NVJ_type_br_pred_reg<"",  OpcStr>;
3227   defm rrdnNot : NVJ_type_br_pred_2ndDotNew<"!", OpcStr>;
3228   defm rrdn    : NVJ_type_br_pred_2ndDotNew<"",  OpcStr>;
3229   defm riNot   : NVJ_type_br_pred_imm_only<"!", OpcStr>;
3230   defm ri      : NVJ_type_br_pred_imm_only<"",  OpcStr>;
3231 }
3232
3233 // Multiclass for tstbit.
3234 multiclass NVJ_type_r0<string OpcStr> {
3235   defm r0Not : NVJ_type_br_pred_tstbit<"!", OpcStr>;
3236   defm r0    : NVJ_type_br_pred_tstbit<"",  OpcStr>;
3237  }
3238
3239 // Base Multiclass for New Value Jump.
3240 multiclass NVJ_type {
3241   defm GT     : NVJ_type_rr_ri<"cmp.gt">;
3242   defm EQ     : NVJ_type_rr_ri_no_2ndDotNew<"cmp.eq">;
3243   defm GTU    : NVJ_type_rr_ri_no_nOne<"cmp.gtu">;
3244   defm TSTBIT : NVJ_type_r0<"tstbit">;
3245 }
3246
3247 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC] in {
3248   defm JMP_ : NVJ_type;
3249 }
3250
3251 //===----------------------------------------------------------------------===//
3252 // NV/J -
3253 //===----------------------------------------------------------------------===//
3254
3255 //===----------------------------------------------------------------------===//
3256 // XTYPE/ALU +
3257 //===----------------------------------------------------------------------===//
3258
3259 //  Add and accumulate.
3260 //  Rd=add(Rs,add(Ru,#s6))
3261 def ADDr_ADDri_V4 : MInst<(outs IntRegs:$dst),
3262           (ins IntRegs:$src1, IntRegs:$src2, s6Imm:$src3),
3263           "$dst = add($src1, add($src2, #$src3))",
3264           [(set (i32 IntRegs:$dst),
3265            (add (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),
3266                                           s6ImmPred:$src3)))]>,
3267           Requires<[HasV4T]>;
3268
3269 //  Rd=add(Rs,sub(#s6,Ru))
3270 def ADDr_SUBri_V4 : MInst<(outs IntRegs:$dst),
3271           (ins IntRegs:$src1, s6Imm:$src2, IntRegs:$src3),
3272           "$dst = add($src1, sub(#$src2, $src3))",
3273           [(set (i32 IntRegs:$dst),
3274            (add (i32 IntRegs:$src1), (sub s6ImmPred:$src2,
3275                                           (i32 IntRegs:$src3))))]>,
3276           Requires<[HasV4T]>;
3277
3278 // Generates the same instruction as ADDr_SUBri_V4 but matches different
3279 // pattern.
3280 //  Rd=add(Rs,sub(#s6,Ru))
3281 def ADDri_SUBr_V4 : MInst<(outs IntRegs:$dst),
3282           (ins IntRegs:$src1, s6Imm:$src2, IntRegs:$src3),
3283           "$dst = add($src1, sub(#$src2, $src3))",
3284           [(set (i32 IntRegs:$dst),
3285                 (sub (add (i32 IntRegs:$src1), s6ImmPred:$src2),
3286                      (i32 IntRegs:$src3)))]>,
3287           Requires<[HasV4T]>;
3288
3289
3290 //  Add or subtract doublewords with carry.
3291 //TODO:
3292 //  Rdd=add(Rss,Rtt,Px):carry
3293 //TODO:
3294 //  Rdd=sub(Rss,Rtt,Px):carry
3295
3296
3297 //  Logical doublewords.
3298 //  Rdd=and(Rtt,~Rss)
3299 def ANDd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),
3300           (ins DoubleRegs:$src1, DoubleRegs:$src2),
3301           "$dst = and($src1, ~$src2)",
3302           [(set (i64 DoubleRegs:$dst), (and (i64 DoubleRegs:$src1),
3303                                       (not (i64 DoubleRegs:$src2))))]>,
3304           Requires<[HasV4T]>;
3305
3306 //  Rdd=or(Rtt,~Rss)
3307 def ORd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),
3308           (ins DoubleRegs:$src1, DoubleRegs:$src2),
3309           "$dst = or($src1, ~$src2)",
3310           [(set (i64 DoubleRegs:$dst),
3311            (or (i64 DoubleRegs:$src1), (not (i64 DoubleRegs:$src2))))]>,
3312           Requires<[HasV4T]>;
3313
3314
3315 //  Logical-logical doublewords.
3316 //  Rxx^=xor(Rss,Rtt)
3317 def XORd_XORdd: MInst_acc<(outs DoubleRegs:$dst),
3318           (ins DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
3319           "$dst ^= xor($src2, $src3)",
3320           [(set (i64 DoubleRegs:$dst),
3321            (xor (i64 DoubleRegs:$src1), (xor (i64 DoubleRegs:$src2),
3322                                              (i64 DoubleRegs:$src3))))],
3323           "$src1 = $dst">,
3324           Requires<[HasV4T]>;
3325
3326
3327 // Logical-logical words.
3328 // Rx=or(Ru,and(Rx,#s10))
3329 def ORr_ANDri_V4 : MInst_acc<(outs IntRegs:$dst),
3330             (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),
3331             "$dst = or($src1, and($src2, #$src3))",
3332             [(set (i32 IntRegs:$dst),
3333                   (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3334                                                 s10ImmPred:$src3)))],
3335             "$src2 = $dst">,
3336             Requires<[HasV4T]>;
3337
3338 // Rx[&|^]=and(Rs,Rt)
3339 // Rx&=and(Rs,Rt)
3340 def ANDr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
3341             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3342             "$dst &= and($src2, $src3)",
3343             [(set (i32 IntRegs:$dst),
3344                   (and (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3345                                                  (i32 IntRegs:$src3))))],
3346             "$src1 = $dst">,
3347             Requires<[HasV4T]>;
3348
3349 // Rx|=and(Rs,Rt)
3350 def ORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
3351             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3352             "$dst |= and($src2, $src3)",
3353             [(set (i32 IntRegs:$dst),
3354                   (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3355                                                 (i32 IntRegs:$src3))))],
3356             "$src1 = $dst">,
3357             Requires<[HasV4T]>;
3358
3359 // Rx^=and(Rs,Rt)
3360 def XORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
3361             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3362             "$dst ^= and($src2, $src3)",
3363             [(set (i32 IntRegs:$dst),
3364              (xor (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3365                                             (i32 IntRegs:$src3))))],
3366             "$src1 = $dst">,
3367             Requires<[HasV4T]>;
3368
3369 // Rx[&|^]=and(Rs,~Rt)
3370 // Rx&=and(Rs,~Rt)
3371 def ANDr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
3372             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3373             "$dst &= and($src2, ~$src3)",
3374             [(set (i32 IntRegs:$dst),
3375                   (and (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3376                                                  (not (i32 IntRegs:$src3)))))],
3377             "$src1 = $dst">,
3378             Requires<[HasV4T]>;
3379
3380 // Rx|=and(Rs,~Rt)
3381 def ORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
3382             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3383             "$dst |= and($src2, ~$src3)",
3384             [(set (i32 IntRegs:$dst),
3385              (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3386                                            (not (i32 IntRegs:$src3)))))],
3387             "$src1 = $dst">,
3388             Requires<[HasV4T]>;
3389
3390 // Rx^=and(Rs,~Rt)
3391 def XORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
3392             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3393             "$dst ^= and($src2, ~$src3)",
3394             [(set (i32 IntRegs:$dst),
3395              (xor (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3396                                             (not (i32 IntRegs:$src3)))))],
3397             "$src1 = $dst">,
3398             Requires<[HasV4T]>;
3399
3400 // Rx[&|^]=or(Rs,Rt)
3401 // Rx&=or(Rs,Rt)
3402 def ANDr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3403             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3404             "$dst &= or($src2, $src3)",
3405             [(set (i32 IntRegs:$dst),
3406                   (and (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
3407                                                 (i32 IntRegs:$src3))))],
3408             "$src1 = $dst">,
3409             Requires<[HasV4T]>;
3410
3411 // Rx|=or(Rs,Rt)
3412 def ORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3413             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3414             "$dst |= or($src2, $src3)",
3415             [(set (i32 IntRegs:$dst),
3416                   (or (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
3417                                                (i32 IntRegs:$src3))))],
3418             "$src1 = $dst">,
3419             Requires<[HasV4T]>;
3420
3421 // Rx^=or(Rs,Rt)
3422 def XORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3423             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3424             "$dst ^= or($src2, $src3)",
3425             [(set (i32 IntRegs:$dst),
3426              (xor (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
3427                                            (i32 IntRegs:$src3))))],
3428             "$src1 = $dst">,
3429             Requires<[HasV4T]>;
3430
3431 // Rx[&|^]=xor(Rs,Rt)
3432 // Rx&=xor(Rs,Rt)
3433 def ANDr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3434             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3435             "$dst &= xor($src2, $src3)",
3436             [(set (i32 IntRegs:$dst),
3437                   (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
3438                                                  (i32 IntRegs:$src3))))],
3439             "$src1 = $dst">,
3440             Requires<[HasV4T]>;
3441
3442 // Rx|=xor(Rs,Rt)
3443 def ORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3444             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3445             "$dst |= xor($src2, $src3)",
3446             [(set (i32 IntRegs:$dst),
3447                   (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
3448                                                  (i32 IntRegs:$src3))))],
3449             "$src1 = $dst">,
3450             Requires<[HasV4T]>;
3451
3452 // Rx^=xor(Rs,Rt)
3453 def XORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3454             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3455             "$dst ^= xor($src2, $src3)",
3456             [(set (i32 IntRegs:$dst),
3457              (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
3458                                             (i32 IntRegs:$src3))))],
3459             "$src1 = $dst">,
3460             Requires<[HasV4T]>;
3461
3462 // Rx|=and(Rs,#s10)
3463 def ORr_ANDri2_V4 : MInst_acc<(outs IntRegs:$dst),
3464             (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),
3465             "$dst |= and($src2, #$src3)",
3466             [(set (i32 IntRegs:$dst),
3467                   (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3468                                                 s10ImmPred:$src3)))],
3469             "$src1 = $dst">,
3470             Requires<[HasV4T]>;
3471
3472 // Rx|=or(Rs,#s10)
3473 def ORr_ORri_V4 : MInst_acc<(outs IntRegs:$dst),
3474             (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),
3475             "$dst |= or($src2, #$src3)",
3476             [(set (i32 IntRegs:$dst),
3477                   (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3478                                                 s10ImmPred:$src3)))],
3479             "$src1 = $dst">,
3480             Requires<[HasV4T]>;
3481
3482
3483 //    Modulo wrap
3484 //        Rd=modwrap(Rs,Rt)
3485 //    Round
3486 //        Rd=cround(Rs,#u5)
3487 //        Rd=cround(Rs,Rt)
3488 //        Rd=round(Rs,#u5)[:sat]
3489 //        Rd=round(Rs,Rt)[:sat]
3490 //    Vector reduce add unsigned halfwords
3491 //        Rd=vraddh(Rss,Rtt)
3492 //    Vector add bytes
3493 //        Rdd=vaddb(Rss,Rtt)
3494 //    Vector conditional negate
3495 //        Rdd=vcnegh(Rss,Rt)
3496 //        Rxx+=vrcnegh(Rss,Rt)
3497 //    Vector maximum bytes
3498 //        Rdd=vmaxb(Rtt,Rss)
3499 //    Vector reduce maximum halfwords
3500 //        Rxx=vrmaxh(Rss,Ru)
3501 //        Rxx=vrmaxuh(Rss,Ru)
3502 //    Vector reduce maximum words
3503 //        Rxx=vrmaxuw(Rss,Ru)
3504 //        Rxx=vrmaxw(Rss,Ru)
3505 //    Vector minimum bytes
3506 //        Rdd=vminb(Rtt,Rss)
3507 //    Vector reduce minimum halfwords
3508 //        Rxx=vrminh(Rss,Ru)
3509 //        Rxx=vrminuh(Rss,Ru)
3510 //    Vector reduce minimum words
3511 //        Rxx=vrminuw(Rss,Ru)
3512 //        Rxx=vrminw(Rss,Ru)
3513 //    Vector subtract bytes
3514 //        Rdd=vsubb(Rss,Rtt)
3515
3516 //===----------------------------------------------------------------------===//
3517 // XTYPE/ALU -
3518 //===----------------------------------------------------------------------===//
3519
3520
3521 //===----------------------------------------------------------------------===//
3522 // XTYPE/MPY +
3523 //===----------------------------------------------------------------------===//
3524
3525 // Multiply and user lower result.
3526 // Rd=add(#u6,mpyi(Rs,#U6))
3527 def ADDi_MPYri_V4 : MInst<(outs IntRegs:$dst),
3528             (ins u6Imm:$src1, IntRegs:$src2, u6Imm:$src3),
3529             "$dst = add(#$src1, mpyi($src2, #$src3))",
3530             [(set (i32 IntRegs:$dst),
3531                   (add (mul (i32 IntRegs:$src2), u6ImmPred:$src3),
3532                        u6ImmPred:$src1))]>,
3533             Requires<[HasV4T]>;
3534
3535 // Rd=add(#u6,mpyi(Rs,Rt))
3536
3537 def ADDi_MPYrr_V4 : MInst<(outs IntRegs:$dst),
3538             (ins u6Imm:$src1, IntRegs:$src2, IntRegs:$src3),
3539             "$dst = add(#$src1, mpyi($src2, $src3))",
3540             [(set (i32 IntRegs:$dst),
3541                   (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
3542                        u6ImmPred:$src1))]>,
3543             Requires<[HasV4T]>;
3544
3545 // Rd=add(Ru,mpyi(#u6:2,Rs))
3546 def ADDr_MPYir_V4 : MInst<(outs IntRegs:$dst),
3547             (ins IntRegs:$src1, u6Imm:$src2, IntRegs:$src3),
3548             "$dst = add($src1, mpyi(#$src2, $src3))",
3549             [(set (i32 IntRegs:$dst),
3550              (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src3),
3551                                             u6_2ImmPred:$src2)))]>,
3552             Requires<[HasV4T]>;
3553
3554 // Rd=add(Ru,mpyi(Rs,#u6))
3555 def ADDr_MPYri_V4 : MInst<(outs IntRegs:$dst),
3556             (ins IntRegs:$src1, IntRegs:$src2, u6Imm:$src3),
3557             "$dst = add($src1, mpyi($src2, #$src3))",
3558             [(set (i32 IntRegs:$dst),
3559                   (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
3560                                                  u6ImmPred:$src3)))]>,
3561             Requires<[HasV4T]>;
3562
3563 // Rx=add(Ru,mpyi(Rx,Rs))
3564 def ADDr_MPYrr_V4 : MInst_acc<(outs IntRegs:$dst),
3565             (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
3566             "$dst = add($src1, mpyi($src2, $src3))",
3567             [(set (i32 IntRegs:$dst),
3568              (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
3569                                             (i32 IntRegs:$src3))))],
3570             "$src2 = $dst">,
3571             Requires<[HasV4T]>;
3572
3573
3574 // Polynomial multiply words
3575 // Rdd=pmpyw(Rs,Rt)
3576 // Rxx^=pmpyw(Rs,Rt)
3577
3578 // Vector reduce multiply word by signed half (32x16)
3579 // Rdd=vrmpyweh(Rss,Rtt)[:<<1]
3580 // Rdd=vrmpywoh(Rss,Rtt)[:<<1]
3581 // Rxx+=vrmpyweh(Rss,Rtt)[:<<1]
3582 // Rxx+=vrmpywoh(Rss,Rtt)[:<<1]
3583
3584 // Multiply and use upper result
3585 // Rd=mpy(Rs,Rt.H):<<1:sat
3586 // Rd=mpy(Rs,Rt.L):<<1:sat
3587 // Rd=mpy(Rs,Rt):<<1
3588 // Rd=mpy(Rs,Rt):<<1:sat
3589 // Rd=mpysu(Rs,Rt)
3590 // Rx+=mpy(Rs,Rt):<<1:sat
3591 // Rx-=mpy(Rs,Rt):<<1:sat
3592
3593 // Vector multiply bytes
3594 // Rdd=vmpybsu(Rs,Rt)
3595 // Rdd=vmpybu(Rs,Rt)
3596 // Rxx+=vmpybsu(Rs,Rt)
3597 // Rxx+=vmpybu(Rs,Rt)
3598
3599 // Vector polynomial multiply halfwords
3600 // Rdd=vpmpyh(Rs,Rt)
3601 // Rxx^=vpmpyh(Rs,Rt)
3602
3603 //===----------------------------------------------------------------------===//
3604 // XTYPE/MPY -
3605 //===----------------------------------------------------------------------===//
3606
3607
3608 //===----------------------------------------------------------------------===//
3609 // XTYPE/SHIFT +
3610 //===----------------------------------------------------------------------===//
3611
3612 // Shift by immediate and accumulate.
3613 // Rx=add(#u8,asl(Rx,#U5))
3614 def ADDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
3615             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3616             "$dst = add(#$src1, asl($src2, #$src3))",
3617             [(set (i32 IntRegs:$dst),
3618                   (add (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
3619                        u8ImmPred:$src1))],
3620             "$src2 = $dst">,
3621             Requires<[HasV4T]>;
3622
3623 // Rx=add(#u8,lsr(Rx,#U5))
3624 def ADDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
3625             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3626             "$dst = add(#$src1, lsr($src2, #$src3))",
3627             [(set (i32 IntRegs:$dst),
3628                   (add (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
3629                        u8ImmPred:$src1))],
3630             "$src2 = $dst">,
3631             Requires<[HasV4T]>;
3632
3633 // Rx=sub(#u8,asl(Rx,#U5))
3634 def SUBi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
3635             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3636             "$dst = sub(#$src1, asl($src2, #$src3))",
3637             [(set (i32 IntRegs:$dst),
3638                   (sub (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
3639                        u8ImmPred:$src1))],
3640             "$src2 = $dst">,
3641             Requires<[HasV4T]>;
3642
3643 // Rx=sub(#u8,lsr(Rx,#U5))
3644 def SUBi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
3645             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3646             "$dst = sub(#$src1, lsr($src2, #$src3))",
3647             [(set (i32 IntRegs:$dst),
3648                   (sub (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
3649                        u8ImmPred:$src1))],
3650             "$src2 = $dst">,
3651             Requires<[HasV4T]>;
3652
3653
3654 //Shift by immediate and logical.
3655 //Rx=and(#u8,asl(Rx,#U5))
3656 def ANDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
3657             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3658             "$dst = and(#$src1, asl($src2, #$src3))",
3659             [(set (i32 IntRegs:$dst),
3660                   (and (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
3661                        u8ImmPred:$src1))],
3662             "$src2 = $dst">,
3663             Requires<[HasV4T]>;
3664
3665 //Rx=and(#u8,lsr(Rx,#U5))
3666 def ANDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
3667             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3668             "$dst = and(#$src1, lsr($src2, #$src3))",
3669             [(set (i32 IntRegs:$dst),
3670                   (and (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
3671                        u8ImmPred:$src1))],
3672             "$src2 = $dst">,
3673             Requires<[HasV4T]>;
3674
3675 //Rx=or(#u8,asl(Rx,#U5))
3676 let AddedComplexity = 30 in
3677 def ORi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
3678             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3679             "$dst = or(#$src1, asl($src2, #$src3))",
3680             [(set (i32 IntRegs:$dst),
3681                   (or (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
3682                       u8ImmPred:$src1))],
3683             "$src2 = $dst">,
3684             Requires<[HasV4T]>;
3685
3686 //Rx=or(#u8,lsr(Rx,#U5))
3687 let AddedComplexity = 30 in
3688 def ORi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
3689             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3690             "$dst = or(#$src1, lsr($src2, #$src3))",
3691             [(set (i32 IntRegs:$dst),
3692                   (or (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
3693                       u8ImmPred:$src1))],
3694             "$src2 = $dst">,
3695             Requires<[HasV4T]>;
3696
3697
3698 //Shift by register.
3699 //Rd=lsl(#s6,Rt)
3700 def LSLi_V4 : MInst<(outs IntRegs:$dst), (ins s6Imm:$src1, IntRegs:$src2),
3701             "$dst = lsl(#$src1, $src2)",
3702             [(set (i32 IntRegs:$dst), (shl s6ImmPred:$src1,
3703                                            (i32 IntRegs:$src2)))]>,
3704             Requires<[HasV4T]>;
3705
3706
3707 //Shift by register and logical.
3708 //Rxx^=asl(Rss,Rt)
3709 def ASLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
3710             (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
3711             "$dst ^= asl($src2, $src3)",
3712             [(set (i64 DoubleRegs:$dst),
3713                   (xor (i64 DoubleRegs:$src1), (shl (i64 DoubleRegs:$src2),
3714                                                     (i32 IntRegs:$src3))))],
3715             "$src1 = $dst">,
3716             Requires<[HasV4T]>;
3717
3718 //Rxx^=asr(Rss,Rt)
3719 def ASRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
3720             (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
3721             "$dst ^= asr($src2, $src3)",
3722             [(set (i64 DoubleRegs:$dst),
3723                   (xor (i64 DoubleRegs:$src1), (sra (i64 DoubleRegs:$src2),
3724                                                     (i32 IntRegs:$src3))))],
3725             "$src1 = $dst">,
3726             Requires<[HasV4T]>;
3727
3728 //Rxx^=lsl(Rss,Rt)
3729 def LSLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
3730             (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
3731             "$dst ^= lsl($src2, $src3)",
3732             [(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1),
3733                                               (shl (i64 DoubleRegs:$src2),
3734                                                    (i32 IntRegs:$src3))))],
3735             "$src1 = $dst">,
3736             Requires<[HasV4T]>;
3737
3738 //Rxx^=lsr(Rss,Rt)
3739 def LSRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
3740             (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
3741             "$dst ^= lsr($src2, $src3)",
3742             [(set (i64 DoubleRegs:$dst),
3743                   (xor (i64 DoubleRegs:$src1), (srl (i64 DoubleRegs:$src2),
3744                                                     (i32 IntRegs:$src3))))],
3745             "$src1 = $dst">,
3746             Requires<[HasV4T]>;
3747
3748
3749 //===----------------------------------------------------------------------===//
3750 // XTYPE/SHIFT -
3751 //===----------------------------------------------------------------------===//
3752
3753 //===----------------------------------------------------------------------===//
3754 // MEMOP: Word, Half, Byte
3755 //===----------------------------------------------------------------------===//
3756
3757 //===----------------------------------------------------------------------===//
3758 // MEMOP: Word
3759 //
3760 //  Implemented:
3761 //     MEMw_ADDi_indexed_V4  : memw(Rs+#u6:2)+=#U5
3762 //     MEMw_SUBi_indexed_V4  : memw(Rs+#u6:2)-=#U5
3763 //     MEMw_ADDr_indexed_V4  : memw(Rs+#u6:2)+=Rt
3764 //     MEMw_SUBr_indexed_V4  : memw(Rs+#u6:2)-=Rt
3765 //     MEMw_CLRr_indexed_V4  : memw(Rs+#u6:2)&=Rt
3766 //     MEMw_SETr_indexed_V4  : memw(Rs+#u6:2)|=Rt
3767 //     MEMw_ADDi_V4          : memw(Rs+#u6:2)+=#U5
3768 //     MEMw_SUBi_V4          : memw(Rs+#u6:2)-=#U5
3769 //     MEMw_ADDr_V4          : memw(Rs+#u6:2)+=Rt
3770 //     MEMw_SUBr_V4          : memw(Rs+#u6:2)-=Rt
3771 //     MEMw_CLRr_V4          : memw(Rs+#u6:2)&=Rt
3772 //     MEMw_SETr_V4          : memw(Rs+#u6:2)|=Rt
3773 //
3774 //   Not implemented:
3775 //     MEMw_CLRi_indexed_V4  : memw(Rs+#u6:2)=clrbit(#U5)
3776 //     MEMw_SETi_indexed_V4  : memw(Rs+#u6:2)=setbit(#U5)
3777 //     MEMw_CLRi_V4          : memw(Rs+#u6:2)=clrbit(#U5)
3778 //     MEMw_SETi_V4          : memw(Rs+#u6:2)=setbit(#U5)
3779 //===----------------------------------------------------------------------===//
3780
3781
3782
3783 // memw(Rs+#u6:2) += #U5
3784 let AddedComplexity = 30 in
3785 def MEMw_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
3786             (ins IntRegs:$base, u6_2Imm:$offset, u5Imm:$addend),
3787             "memw($base+#$offset) += #$addend",
3788             []>,
3789             Requires<[HasV4T, UseMEMOP]>;
3790
3791 // memw(Rs+#u6:2) -= #U5
3792 let AddedComplexity = 30 in
3793 def MEMw_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
3794             (ins IntRegs:$base, u6_2Imm:$offset, u5Imm:$subend),
3795             "memw($base+#$offset) -= #$subend",
3796             []>,
3797             Requires<[HasV4T, UseMEMOP]>;
3798
3799 // memw(Rs+#u6:2) += Rt
3800 let AddedComplexity = 30 in
3801 def MEMw_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),
3802             (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$addend),
3803             "memw($base+#$offset) += $addend",
3804             [(store (add (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
3805                          (i32 IntRegs:$addend)),
3806                     (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
3807             Requires<[HasV4T, UseMEMOP]>;
3808
3809 // memw(Rs+#u6:2) -= Rt
3810 let AddedComplexity = 30 in
3811 def MEMw_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),
3812             (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$subend),
3813             "memw($base+#$offset) -= $subend",
3814             [(store (sub (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
3815                          (i32 IntRegs:$subend)),
3816                     (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
3817             Requires<[HasV4T, UseMEMOP]>;
3818
3819 // memw(Rs+#u6:2) &= Rt
3820 let AddedComplexity = 30 in
3821 def MEMw_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),
3822             (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$andend),
3823             "memw($base+#$offset) &= $andend",
3824             [(store (and (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
3825                          (i32 IntRegs:$andend)),
3826                     (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
3827             Requires<[HasV4T, UseMEMOP]>;
3828
3829 // memw(Rs+#u6:2) |= Rt
3830 let AddedComplexity = 30 in
3831 def MEMw_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
3832             (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$orend),
3833             "memw($base+#$offset) |= $orend",
3834             [(store (or (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
3835                         (i32 IntRegs:$orend)),
3836                     (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
3837             Requires<[HasV4T, UseMEMOP]>;
3838
3839 // memw(Rs+#u6:2) += #U5
3840 let AddedComplexity = 30 in
3841 def MEMw_ADDi_MEM_V4 : MEMInst_V4<(outs),
3842             (ins MEMri:$addr, u5Imm:$addend),
3843             "memw($addr) += $addend",
3844             []>,
3845             Requires<[HasV4T, UseMEMOP]>;
3846
3847 // memw(Rs+#u6:2) -= #U5
3848 let AddedComplexity = 30 in
3849 def MEMw_SUBi_MEM_V4 : MEMInst_V4<(outs),
3850             (ins MEMri:$addr, u5Imm:$subend),
3851             "memw($addr) -= $subend",
3852             []>,
3853             Requires<[HasV4T, UseMEMOP]>;
3854
3855 // memw(Rs+#u6:2) += Rt
3856 let AddedComplexity = 30 in
3857 def MEMw_ADDr_MEM_V4 : MEMInst_V4<(outs),
3858             (ins MEMri:$addr, IntRegs:$addend),
3859             "memw($addr) += $addend",
3860             [(store (add (load ADDRriU6_2:$addr), (i32 IntRegs:$addend)),
3861                     ADDRriU6_2:$addr)]>,
3862             Requires<[HasV4T, UseMEMOP]>;
3863
3864 // memw(Rs+#u6:2) -= Rt
3865 let AddedComplexity = 30 in
3866 def MEMw_SUBr_MEM_V4 : MEMInst_V4<(outs),
3867             (ins MEMri:$addr, IntRegs:$subend),
3868             "memw($addr) -= $subend",
3869             [(store (sub (load ADDRriU6_2:$addr), (i32 IntRegs:$subend)),
3870                     ADDRriU6_2:$addr)]>,
3871             Requires<[HasV4T, UseMEMOP]>;
3872
3873 // memw(Rs+#u6:2) &= Rt
3874 let AddedComplexity = 30 in
3875 def MEMw_ANDr_MEM_V4 : MEMInst_V4<(outs),
3876             (ins MEMri:$addr, IntRegs:$andend),
3877             "memw($addr) &= $andend",
3878             [(store (and (load ADDRriU6_2:$addr), (i32 IntRegs:$andend)),
3879                     ADDRriU6_2:$addr)]>,
3880             Requires<[HasV4T, UseMEMOP]>;
3881
3882 // memw(Rs+#u6:2) |= Rt
3883 let AddedComplexity = 30 in
3884 def MEMw_ORr_MEM_V4 : MEMInst_V4<(outs),
3885             (ins MEMri:$addr, IntRegs:$orend),
3886             "memw($addr) |= $orend",
3887             [(store (or (load ADDRriU6_2:$addr), (i32 IntRegs:$orend)),
3888                     ADDRriU6_2:$addr)]>,
3889             Requires<[HasV4T, UseMEMOP]>;
3890
3891 //===----------------------------------------------------------------------===//
3892 // MEMOP: Halfword
3893 //
3894 //  Implemented:
3895 //     MEMh_ADDi_indexed_V4  : memw(Rs+#u6:2)+=#U5
3896 //     MEMh_SUBi_indexed_V4  : memw(Rs+#u6:2)-=#U5
3897 //     MEMh_ADDr_indexed_V4  : memw(Rs+#u6:2)+=Rt
3898 //     MEMh_SUBr_indexed_V4  : memw(Rs+#u6:2)-=Rt
3899 //     MEMh_CLRr_indexed_V4  : memw(Rs+#u6:2)&=Rt
3900 //     MEMh_SETr_indexed_V4  : memw(Rs+#u6:2)|=Rt
3901 //     MEMh_ADDi_V4          : memw(Rs+#u6:2)+=#U5
3902 //     MEMh_SUBi_V4          : memw(Rs+#u6:2)-=#U5
3903 //     MEMh_ADDr_V4          : memw(Rs+#u6:2)+=Rt
3904 //     MEMh_SUBr_V4          : memw(Rs+#u6:2)-=Rt
3905 //     MEMh_CLRr_V4          : memw(Rs+#u6:2)&=Rt
3906 //     MEMh_SETr_V4          : memw(Rs+#u6:2)|=Rt
3907 //
3908 //   Not implemented:
3909 //     MEMh_CLRi_indexed_V4  : memw(Rs+#u6:2)=clrbit(#U5)
3910 //     MEMh_SETi_indexed_V4  : memw(Rs+#u6:2)=setbit(#U5)
3911 //     MEMh_CLRi_V4          : memw(Rs+#u6:2)=clrbit(#U5)
3912 //     MEMh_SETi_V4          : memw(Rs+#u6:2)=setbit(#U5)
3913 //===----------------------------------------------------------------------===//
3914
3915
3916 // memh(Rs+#u6:1) += #U5
3917 let AddedComplexity = 30 in
3918 def MEMh_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
3919             (ins IntRegs:$base, u6_1Imm:$offset, u5Imm:$addend),
3920             "memh($base+#$offset) += $addend",
3921             []>,
3922             Requires<[HasV4T, UseMEMOP]>;
3923
3924 // memh(Rs+#u6:1) -= #U5
3925 let AddedComplexity = 30 in
3926 def MEMh_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
3927             (ins IntRegs:$base, u6_1Imm:$offset, u5Imm:$subend),
3928             "memh($base+#$offset) -= $subend",
3929             []>,
3930             Requires<[HasV4T, UseMEMOP]>;
3931
3932 // memh(Rs+#u6:1) += Rt
3933 let AddedComplexity = 30 in
3934 def MEMh_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),
3935             (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$addend),
3936             "memh($base+#$offset) += $addend",
3937             [(truncstorei16 (add (sextloadi16 (add (i32 IntRegs:$base),
3938                                                    u6_1ImmPred:$offset)),
3939                                  (i32 IntRegs:$addend)),
3940                             (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
3941             Requires<[HasV4T, UseMEMOP]>;
3942
3943 // memh(Rs+#u6:1) -= Rt
3944 let AddedComplexity = 30 in
3945 def MEMh_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),
3946             (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$subend),
3947             "memh($base+#$offset) -= $subend",
3948             [(truncstorei16 (sub (sextloadi16 (add (i32 IntRegs:$base),
3949                                                    u6_1ImmPred:$offset)),
3950                                  (i32 IntRegs:$subend)),
3951                             (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
3952             Requires<[HasV4T, UseMEMOP]>;
3953
3954 // memh(Rs+#u6:1) &= Rt
3955 let AddedComplexity = 30 in
3956 def MEMh_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),
3957             (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$andend),
3958             "memh($base+#$offset) += $andend",
3959             [(truncstorei16 (and (sextloadi16 (add (i32 IntRegs:$base),
3960                                                    u6_1ImmPred:$offset)),
3961                                  (i32 IntRegs:$andend)),
3962                             (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
3963             Requires<[HasV4T, UseMEMOP]>;
3964
3965 // memh(Rs+#u6:1) |= Rt
3966 let AddedComplexity = 30 in
3967 def MEMh_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
3968             (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$orend),
3969             "memh($base+#$offset) |= $orend",
3970             [(truncstorei16 (or (sextloadi16 (add (i32 IntRegs:$base),
3971                                               u6_1ImmPred:$offset)),
3972                              (i32 IntRegs:$orend)),
3973                             (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
3974             Requires<[HasV4T, UseMEMOP]>;
3975
3976 // memh(Rs+#u6:1) += #U5
3977 let AddedComplexity = 30 in
3978 def MEMh_ADDi_MEM_V4 : MEMInst_V4<(outs),
3979             (ins MEMri:$addr, u5Imm:$addend),
3980             "memh($addr) += $addend",
3981             []>,
3982             Requires<[HasV4T, UseMEMOP]>;
3983
3984 // memh(Rs+#u6:1) -= #U5
3985 let AddedComplexity = 30 in
3986 def MEMh_SUBi_MEM_V4 : MEMInst_V4<(outs),
3987             (ins MEMri:$addr, u5Imm:$subend),
3988             "memh($addr) -= $subend",
3989             []>,
3990             Requires<[HasV4T, UseMEMOP]>;
3991
3992 // memh(Rs+#u6:1) += Rt
3993 let AddedComplexity = 30 in
3994 def MEMh_ADDr_MEM_V4 : MEMInst_V4<(outs),
3995             (ins MEMri:$addr, IntRegs:$addend),
3996             "memh($addr) += $addend",
3997             [(truncstorei16 (add (sextloadi16 ADDRriU6_1:$addr),
3998                                  (i32 IntRegs:$addend)), ADDRriU6_1:$addr)]>,
3999             Requires<[HasV4T, UseMEMOP]>;
4000
4001 // memh(Rs+#u6:1) -= Rt
4002 let AddedComplexity = 30 in
4003 def MEMh_SUBr_MEM_V4 : MEMInst_V4<(outs),
4004             (ins MEMri:$addr, IntRegs:$subend),
4005             "memh($addr) -= $subend",
4006             [(truncstorei16 (sub (sextloadi16 ADDRriU6_1:$addr),
4007                                  (i32 IntRegs:$subend)), ADDRriU6_1:$addr)]>,
4008             Requires<[HasV4T, UseMEMOP]>;
4009
4010 // memh(Rs+#u6:1) &= Rt
4011 let AddedComplexity = 30 in
4012 def MEMh_ANDr_MEM_V4 : MEMInst_V4<(outs),
4013             (ins MEMri:$addr, IntRegs:$andend),
4014             "memh($addr) &= $andend",
4015             [(truncstorei16 (and (sextloadi16 ADDRriU6_1:$addr),
4016                                  (i32 IntRegs:$andend)), ADDRriU6_1:$addr)]>,
4017             Requires<[HasV4T, UseMEMOP]>;
4018
4019 // memh(Rs+#u6:1) |= Rt
4020 let AddedComplexity = 30 in
4021 def MEMh_ORr_MEM_V4 : MEMInst_V4<(outs),
4022             (ins MEMri:$addr, IntRegs:$orend),
4023             "memh($addr) |= $orend",
4024             [(truncstorei16 (or (sextloadi16 ADDRriU6_1:$addr),
4025                                 (i32 IntRegs:$orend)), ADDRriU6_1:$addr)]>,
4026             Requires<[HasV4T, UseMEMOP]>;
4027
4028
4029 //===----------------------------------------------------------------------===//
4030 // MEMOP: Byte
4031 //
4032 //  Implemented:
4033 //     MEMb_ADDi_indexed_V4  : memb(Rs+#u6:0)+=#U5
4034 //     MEMb_SUBi_indexed_V4  : memb(Rs+#u6:0)-=#U5
4035 //     MEMb_ADDr_indexed_V4  : memb(Rs+#u6:0)+=Rt
4036 //     MEMb_SUBr_indexed_V4  : memb(Rs+#u6:0)-=Rt
4037 //     MEMb_CLRr_indexed_V4  : memb(Rs+#u6:0)&=Rt
4038 //     MEMb_SETr_indexed_V4  : memb(Rs+#u6:0)|=Rt
4039 //     MEMb_ADDi_V4          : memb(Rs+#u6:0)+=#U5
4040 //     MEMb_SUBi_V4          : memb(Rs+#u6:0)-=#U5
4041 //     MEMb_ADDr_V4          : memb(Rs+#u6:0)+=Rt
4042 //     MEMb_SUBr_V4          : memb(Rs+#u6:0)-=Rt
4043 //     MEMb_CLRr_V4          : memb(Rs+#u6:0)&=Rt
4044 //     MEMb_SETr_V4          : memb(Rs+#u6:0)|=Rt
4045 //
4046 //   Not implemented:
4047 //     MEMb_CLRi_indexed_V4  : memb(Rs+#u6:0)=clrbit(#U5)
4048 //     MEMb_SETi_indexed_V4  : memb(Rs+#u6:0)=setbit(#U5)
4049 //     MEMb_CLRi_V4          : memb(Rs+#u6:0)=clrbit(#U5)
4050 //     MEMb_SETi_V4          : memb(Rs+#u6:0)=setbit(#U5)
4051 //===----------------------------------------------------------------------===//
4052
4053 // memb(Rs+#u6:0) += #U5
4054 let AddedComplexity = 30 in
4055 def MEMb_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
4056             (ins IntRegs:$base, u6_0Imm:$offset, u5Imm:$addend),
4057             "memb($base+#$offset) += $addend",
4058             []>,
4059             Requires<[HasV4T, UseMEMOP]>;
4060
4061 // memb(Rs+#u6:0) -= #U5
4062 let AddedComplexity = 30 in
4063 def MEMb_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
4064             (ins IntRegs:$base, u6_0Imm:$offset, u5Imm:$subend),
4065             "memb($base+#$offset) -= $subend",
4066             []>,
4067             Requires<[HasV4T, UseMEMOP]>;
4068
4069 // memb(Rs+#u6:0) += Rt
4070 let AddedComplexity = 30 in
4071 def MEMb_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),
4072             (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$addend),
4073             "memb($base+#$offset) += $addend",
4074             [(truncstorei8 (add (sextloadi8 (add (i32 IntRegs:$base),
4075                                                  u6_0ImmPred:$offset)),
4076                                 (i32 IntRegs:$addend)),
4077                            (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
4078             Requires<[HasV4T, UseMEMOP]>;
4079
4080 // memb(Rs+#u6:0) -= Rt
4081 let AddedComplexity = 30 in
4082 def MEMb_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),
4083             (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$subend),
4084             "memb($base+#$offset) -= $subend",
4085             [(truncstorei8 (sub (sextloadi8 (add (i32 IntRegs:$base),
4086                                                  u6_0ImmPred:$offset)),
4087                                 (i32 IntRegs:$subend)),
4088                            (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
4089             Requires<[HasV4T, UseMEMOP]>;
4090
4091 // memb(Rs+#u6:0) &= Rt
4092 let AddedComplexity = 30 in
4093 def MEMb_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),
4094             (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$andend),
4095             "memb($base+#$offset) += $andend",
4096             [(truncstorei8 (and (sextloadi8 (add (i32 IntRegs:$base),
4097                                                  u6_0ImmPred:$offset)),
4098                                 (i32 IntRegs:$andend)),
4099                            (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
4100             Requires<[HasV4T, UseMEMOP]>;
4101
4102 // memb(Rs+#u6:0) |= Rt
4103 let AddedComplexity = 30 in
4104 def MEMb_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
4105             (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$orend),
4106             "memb($base+#$offset) |= $orend",
4107             [(truncstorei8 (or (sextloadi8 (add (i32 IntRegs:$base),
4108                                                 u6_0ImmPred:$offset)),
4109                                (i32 IntRegs:$orend)),
4110                            (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
4111             Requires<[HasV4T, UseMEMOP]>;
4112
4113 // memb(Rs+#u6:0) += #U5
4114 let AddedComplexity = 30 in
4115 def MEMb_ADDi_MEM_V4 : MEMInst_V4<(outs),
4116             (ins MEMri:$addr, u5Imm:$addend),
4117             "memb($addr) += $addend",
4118             []>,
4119             Requires<[HasV4T, UseMEMOP]>;
4120
4121 // memb(Rs+#u6:0) -= #U5
4122 let AddedComplexity = 30 in
4123 def MEMb_SUBi_MEM_V4 : MEMInst_V4<(outs),
4124             (ins MEMri:$addr, u5Imm:$subend),
4125             "memb($addr) -= $subend",
4126             []>,
4127             Requires<[HasV4T, UseMEMOP]>;
4128
4129 // memb(Rs+#u6:0) += Rt
4130 let AddedComplexity = 30 in
4131 def MEMb_ADDr_MEM_V4 : MEMInst_V4<(outs),
4132             (ins MEMri:$addr, IntRegs:$addend),
4133             "memb($addr) += $addend",
4134             [(truncstorei8 (add (sextloadi8 ADDRriU6_0:$addr),
4135                                 (i32 IntRegs:$addend)), ADDRriU6_0:$addr)]>,
4136             Requires<[HasV4T, UseMEMOP]>;
4137
4138 // memb(Rs+#u6:0) -= Rt
4139 let AddedComplexity = 30 in
4140 def MEMb_SUBr_MEM_V4 : MEMInst_V4<(outs),
4141             (ins MEMri:$addr, IntRegs:$subend),
4142             "memb($addr) -= $subend",
4143             [(truncstorei8 (sub (sextloadi8 ADDRriU6_0:$addr),
4144                                 (i32 IntRegs:$subend)), ADDRriU6_0:$addr)]>,
4145             Requires<[HasV4T, UseMEMOP]>;
4146
4147 // memb(Rs+#u6:0) &= Rt
4148 let AddedComplexity = 30 in
4149 def MEMb_ANDr_MEM_V4 : MEMInst_V4<(outs),
4150             (ins MEMri:$addr, IntRegs:$andend),
4151             "memb($addr) &= $andend",
4152             [(truncstorei8 (and (sextloadi8 ADDRriU6_0:$addr),
4153                                 (i32 IntRegs:$andend)), ADDRriU6_0:$addr)]>,
4154             Requires<[HasV4T, UseMEMOP]>;
4155
4156 // memb(Rs+#u6:0) |= Rt
4157 let AddedComplexity = 30 in
4158 def MEMb_ORr_MEM_V4 : MEMInst_V4<(outs),
4159             (ins MEMri:$addr, IntRegs:$orend),
4160             "memb($addr) |= $orend",
4161             [(truncstorei8 (or (sextloadi8 ADDRriU6_0:$addr),
4162                                (i32 IntRegs:$orend)), ADDRriU6_0:$addr)]>,
4163             Requires<[HasV4T, UseMEMOP]>;
4164
4165
4166 //===----------------------------------------------------------------------===//
4167 // XTYPE/PRED +
4168 //===----------------------------------------------------------------------===//
4169
4170 // Hexagon V4 only supports these flavors of byte/half compare instructions:
4171 // EQ/GT/GTU. Other flavors like GE/GEU/LT/LTU/LE/LEU are not supported by
4172 // hardware. However, compiler can still implement these patterns through
4173 // appropriate patterns combinations based on current implemented patterns.
4174 // The implemented patterns are: EQ/GT/GTU.
4175 // Missing patterns are: GE/GEU/LT/LTU/LE/LEU.
4176
4177 // Following instruction is not being extended as it results into the
4178 // incorrect code for negative numbers.
4179 // Pd=cmpb.eq(Rs,#u8)
4180
4181 let isCompare = 1 in
4182 def CMPbEQri_V4 : MInst<(outs PredRegs:$dst),
4183             (ins IntRegs:$src1, u8Imm:$src2),
4184             "$dst = cmpb.eq($src1, #$src2)",
4185             [(set (i1 PredRegs:$dst),
4186                   (seteq (and (i32 IntRegs:$src1), 255), u8ImmPred:$src2))]>,
4187             Requires<[HasV4T]>;
4188
4189 // Pd=cmpb.eq(Rs,Rt)
4190 let isCompare = 1 in
4191 def CMPbEQrr_ubub_V4 : MInst<(outs PredRegs:$dst),
4192             (ins IntRegs:$src1, IntRegs:$src2),
4193             "$dst = cmpb.eq($src1, $src2)",
4194             [(set (i1 PredRegs:$dst),
4195                   (seteq (and (xor (i32 IntRegs:$src1),
4196                                    (i32 IntRegs:$src2)), 255), 0))]>,
4197             Requires<[HasV4T]>;
4198
4199 // Pd=cmpb.eq(Rs,Rt)
4200 let isCompare = 1 in
4201 def CMPbEQrr_sbsb_V4 : MInst<(outs PredRegs:$dst),
4202             (ins IntRegs:$src1, IntRegs:$src2),
4203             "$dst = cmpb.eq($src1, $src2)",
4204             [(set (i1 PredRegs:$dst),
4205                   (seteq (shl (i32 IntRegs:$src1), (i32 24)),
4206                          (shl (i32 IntRegs:$src2), (i32 24))))]>,
4207             Requires<[HasV4T]>;
4208
4209 // Pd=cmpb.gt(Rs,Rt)
4210 let isCompare = 1 in
4211 def CMPbGTrr_V4 : MInst<(outs PredRegs:$dst),
4212             (ins IntRegs:$src1, IntRegs:$src2),
4213             "$dst = cmpb.gt($src1, $src2)",
4214             [(set (i1 PredRegs:$dst),
4215                   (setgt (shl (i32 IntRegs:$src1), (i32 24)),
4216                          (shl (i32 IntRegs:$src2), (i32 24))))]>,
4217             Requires<[HasV4T]>;
4218
4219 // Pd=cmpb.gtu(Rs,#u7)
4220 let isCompare = 1 in
4221 def CMPbGTUri_V4 : MInst<(outs PredRegs:$dst),
4222             (ins IntRegs:$src1, u7Imm:$src2),
4223             "$dst = cmpb.gtu($src1, #$src2)",
4224             [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),
4225                                               u7ImmPred:$src2))]>,
4226             Requires<[HasV4T]>;
4227
4228 // Pd=cmpb.gtu(Rs,Rt)
4229 let isCompare = 1 in
4230 def CMPbGTUrr_V4 : MInst<(outs PredRegs:$dst),
4231             (ins IntRegs:$src1, IntRegs:$src2),
4232             "$dst = cmpb.gtu($src1, $src2)",
4233             [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),
4234                                              (and (i32 IntRegs:$src2), 255)))]>,
4235             Requires<[HasV4T]>;
4236
4237 // Following instruction is not being extended as it results into the incorrect
4238 // code for negative numbers.
4239
4240 // Signed half compare(.eq) ri.
4241 // Pd=cmph.eq(Rs,#s8)
4242 let isCompare = 1 in
4243 def CMPhEQri_V4 : MInst<(outs PredRegs:$dst),
4244             (ins IntRegs:$src1, s8Imm:$src2),
4245             "$dst = cmph.eq($src1, #$src2)",
4246             [(set (i1 PredRegs:$dst), (seteq (and (i32 IntRegs:$src1), 65535),
4247                                              s8ImmPred:$src2))]>,
4248             Requires<[HasV4T]>;
4249
4250 // Signed half compare(.eq) rr.
4251 // Case 1: xor + and, then compare:
4252 //   r0=xor(r0,r1)
4253 //   r0=and(r0,#0xffff)
4254 //   p0=cmp.eq(r0,#0)
4255 // Pd=cmph.eq(Rs,Rt)
4256 let isCompare = 1 in
4257 def CMPhEQrr_xor_V4 : MInst<(outs PredRegs:$dst),
4258             (ins IntRegs:$src1, IntRegs:$src2),
4259             "$dst = cmph.eq($src1, $src2)",
4260             [(set (i1 PredRegs:$dst), (seteq (and (xor (i32 IntRegs:$src1),
4261                                                        (i32 IntRegs:$src2)),
4262                                                   65535), 0))]>,
4263             Requires<[HasV4T]>;
4264
4265 // Signed half compare(.eq) rr.
4266 // Case 2: shift left 16 bits then compare:
4267 //   r0=asl(r0,16)
4268 //   r1=asl(r1,16)
4269 //   p0=cmp.eq(r0,r1)
4270 // Pd=cmph.eq(Rs,Rt)
4271 let isCompare = 1 in
4272 def CMPhEQrr_shl_V4 : MInst<(outs PredRegs:$dst),
4273             (ins IntRegs:$src1, IntRegs:$src2),
4274             "$dst = cmph.eq($src1, $src2)",
4275             [(set (i1 PredRegs:$dst),
4276                   (seteq (shl (i32 IntRegs:$src1), (i32 16)),
4277                          (shl (i32 IntRegs:$src2), (i32 16))))]>,
4278             Requires<[HasV4T]>;
4279
4280 /* Incorrect Pattern -- immediate should be right shifted before being
4281 used in the cmph.gt instruction.
4282 // Signed half compare(.gt) ri.
4283 // Pd=cmph.gt(Rs,#s8)
4284
4285 let isCompare = 1 in
4286 def CMPhGTri_V4 : MInst<(outs PredRegs:$dst),
4287             (ins IntRegs:$src1, s8Imm:$src2),
4288             "$dst = cmph.gt($src1, #$src2)",
4289             [(set (i1 PredRegs:$dst),
4290                   (setgt (shl (i32 IntRegs:$src1), (i32 16)),
4291                          s8ImmPred:$src2))]>,
4292             Requires<[HasV4T]>;
4293 */
4294
4295 // Signed half compare(.gt) rr.
4296 // Pd=cmph.gt(Rs,Rt)
4297 let isCompare = 1 in
4298 def CMPhGTrr_shl_V4 : MInst<(outs PredRegs:$dst),
4299             (ins IntRegs:$src1, IntRegs:$src2),
4300             "$dst = cmph.gt($src1, $src2)",
4301             [(set (i1 PredRegs:$dst),
4302                   (setgt (shl (i32 IntRegs:$src1), (i32 16)),
4303                          (shl (i32 IntRegs:$src2), (i32 16))))]>,
4304             Requires<[HasV4T]>;
4305
4306 // Unsigned half compare rr (.gtu).
4307 // Pd=cmph.gtu(Rs,Rt)
4308 let isCompare = 1 in
4309 def CMPhGTUrr_V4 : MInst<(outs PredRegs:$dst),
4310             (ins IntRegs:$src1, IntRegs:$src2),
4311             "$dst = cmph.gtu($src1, $src2)",
4312             [(set (i1 PredRegs:$dst),
4313                   (setugt (and (i32 IntRegs:$src1), 65535),
4314                           (and (i32 IntRegs:$src2), 65535)))]>,
4315             Requires<[HasV4T]>;
4316
4317 // Unsigned half compare ri (.gtu).
4318 // Pd=cmph.gtu(Rs,#u7)
4319 let isCompare = 1 in
4320 def CMPhGTUri_V4 : MInst<(outs PredRegs:$dst),
4321             (ins IntRegs:$src1, u7Imm:$src2),
4322             "$dst = cmph.gtu($src1, #$src2)",
4323             [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 65535),
4324                                               u7ImmPred:$src2))]>,
4325             Requires<[HasV4T]>;
4326
4327 //===----------------------------------------------------------------------===//
4328 // XTYPE/PRED -
4329 //===----------------------------------------------------------------------===//
4330
4331 //Deallocate frame and return.
4332 //    dealloc_return
4333 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicable = 1,
4334   Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1 in {
4335   def DEALLOC_RET_V4 : NVInst_V4<(outs), (ins i32imm:$amt1),
4336             "dealloc_return",
4337             []>,
4338             Requires<[HasV4T]>;
4339 }
4340
4341 // Restore registers and dealloc return function call.
4342 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
4343   Defs = [R29, R30, R31, PC] in {
4344   def RESTORE_DEALLOC_RET_JMP_V4 : JInst<(outs),
4345                                    (ins calltarget:$dst),
4346              "jump $dst // Restore_and_dealloc_return",
4347              []>,
4348              Requires<[HasV4T]>;
4349 }
4350
4351 // Restore registers and dealloc frame before a tail call.
4352 let isCall = 1, isBarrier = 1,
4353   Defs = [R29, R30, R31, PC] in {
4354   def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : JInst<(outs),
4355                                            (ins calltarget:$dst),
4356              "call $dst // Restore_and_dealloc_before_tailcall",
4357              []>,
4358              Requires<[HasV4T]>;
4359 }
4360
4361 // Save registers function call.
4362 let isCall = 1, isBarrier = 1,
4363   Uses = [R29, R31] in {
4364   def SAVE_REGISTERS_CALL_V4 : JInst<(outs),
4365                                (ins calltarget:$dst),
4366              "call $dst // Save_calle_saved_registers",
4367              []>,
4368              Requires<[HasV4T]>;
4369 }
4370
4371 //    if (Ps) dealloc_return
4372 let isReturn = 1, isTerminator = 1,
4373     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4374     isPredicated = 1 in {
4375   def DEALLOC_RET_cPt_V4 : NVInst_V4<(outs),
4376                            (ins PredRegs:$src1, i32imm:$amt1),
4377             "if ($src1) dealloc_return",
4378             []>,
4379             Requires<[HasV4T]>;
4380 }
4381
4382 //    if (!Ps) dealloc_return
4383 let isReturn = 1, isTerminator = 1,
4384     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4385     isPredicated = 1 in {
4386   def DEALLOC_RET_cNotPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4387                                                      i32imm:$amt1),
4388             "if (!$src1) dealloc_return",
4389             []>,
4390             Requires<[HasV4T]>;
4391 }
4392
4393 //    if (Ps.new) dealloc_return:nt
4394 let isReturn = 1, isTerminator = 1,
4395     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4396     isPredicated = 1 in {
4397   def DEALLOC_RET_cdnPnt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4398                                                      i32imm:$amt1),
4399             "if ($src1.new) dealloc_return:nt",
4400             []>,
4401             Requires<[HasV4T]>;
4402 }
4403
4404 //    if (!Ps.new) dealloc_return:nt
4405 let isReturn = 1, isTerminator = 1,
4406     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4407     isPredicated = 1 in {
4408   def DEALLOC_RET_cNotdnPnt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4409                                                         i32imm:$amt1),
4410             "if (!$src1.new) dealloc_return:nt",
4411             []>,
4412             Requires<[HasV4T]>;
4413 }
4414
4415 //    if (Ps.new) dealloc_return:t
4416 let isReturn = 1, isTerminator = 1,
4417     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4418     isPredicated = 1 in {
4419   def DEALLOC_RET_cdnPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4420                                                     i32imm:$amt1),
4421             "if ($src1.new) dealloc_return:t",
4422             []>,
4423             Requires<[HasV4T]>;
4424 }
4425
4426 //    if (!Ps.new) dealloc_return:nt
4427 let isReturn = 1, isTerminator = 1,
4428     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4429     isPredicated = 1 in {
4430   def DEALLOC_RET_cNotdnPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4431                                                        i32imm:$amt1),
4432             "if (!$src1.new) dealloc_return:t",
4433             []>,
4434             Requires<[HasV4T]>;
4435 }
4436
4437
4438 // Load/Store with absolute addressing mode
4439 // memw(#u6)=Rt
4440
4441 multiclass ST_abs<string OpcStr> {
4442   let isPredicable = 1 in
4443   def _abs_V4 : STInst2<(outs),
4444             (ins globaladdress:$absaddr, IntRegs:$src),
4445             !strconcat(OpcStr, "(##$absaddr) = $src"),
4446             []>,
4447             Requires<[HasV4T]>;
4448
4449   let isPredicated = 1 in
4450   def _abs_cPt_V4 : STInst2<(outs),
4451             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4452             !strconcat("if ($src1)",
4453             !strconcat(OpcStr, "(##$absaddr) = $src2")),
4454             []>,
4455             Requires<[HasV4T]>;
4456
4457   let isPredicated = 1 in
4458   def _abs_cNotPt_V4 : STInst2<(outs),
4459             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4460             !strconcat("if (!$src1)",
4461             !strconcat(OpcStr, "(##$absaddr) = $src2")),
4462             []>,
4463             Requires<[HasV4T]>;
4464
4465   let isPredicated = 1 in
4466   def _abs_cdnPt_V4 : STInst2<(outs),
4467             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4468             !strconcat("if ($src1.new)",
4469             !strconcat(OpcStr, "(##$absaddr) = $src2")),
4470             []>,
4471             Requires<[HasV4T]>;
4472
4473   let isPredicated = 1 in
4474   def _abs_cdnNotPt_V4 : STInst2<(outs),
4475             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4476             !strconcat("if (!$src1.new)",
4477             !strconcat(OpcStr, "(##$absaddr) = $src2")),
4478             []>,
4479             Requires<[HasV4T]>;
4480
4481   def _abs_nv_V4 : STInst2<(outs),
4482             (ins globaladdress:$absaddr, IntRegs:$src),
4483             !strconcat(OpcStr, "(##$absaddr) = $src.new"),
4484             []>,
4485             Requires<[HasV4T]>;
4486
4487   let isPredicated = 1 in
4488   def _abs_cPt_nv_V4 : STInst2<(outs),
4489             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4490             !strconcat("if ($src1)",
4491             !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
4492             []>,
4493             Requires<[HasV4T]>;
4494
4495   let isPredicated = 1 in
4496   def _abs_cNotPt_nv_V4 : STInst2<(outs),
4497             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4498             !strconcat("if (!$src1)",
4499             !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
4500             []>,
4501             Requires<[HasV4T]>;
4502
4503   let isPredicated = 1 in
4504   def _abs_cdnPt_nv_V4 : STInst2<(outs),
4505             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4506             !strconcat("if ($src1.new)",
4507             !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
4508             []>,
4509             Requires<[HasV4T]>;
4510
4511   let isPredicated = 1 in
4512   def _abs_cdnNotPt_nv_V4 : STInst2<(outs),
4513             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4514             !strconcat("if (!$src1.new)",
4515             !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
4516             []>,
4517             Requires<[HasV4T]>;
4518 }
4519
4520 let AddedComplexity = 30, isPredicable = 1 in
4521 def STrid_abs_V4 : STInst<(outs),
4522           (ins globaladdress:$absaddr, DoubleRegs:$src),
4523            "memd(##$absaddr) = $src",
4524           [(store (i64 DoubleRegs:$src),
4525                   (HexagonCONST32 tglobaladdr:$absaddr))]>,
4526           Requires<[HasV4T]>;
4527
4528 let AddedComplexity = 30, isPredicated = 1 in
4529 def STrid_abs_cPt_V4 : STInst2<(outs),
4530           (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
4531           "if ($src1) memd(##$absaddr) = $src2",
4532           []>,
4533           Requires<[HasV4T]>;
4534
4535 let AddedComplexity = 30, isPredicated = 1 in
4536 def STrid_abs_cNotPt_V4 : STInst2<(outs),
4537           (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
4538           "if (!$src1) memd(##$absaddr) = $src2",
4539           []>,
4540           Requires<[HasV4T]>;
4541
4542 let AddedComplexity = 30, isPredicated = 1 in
4543 def STrid_abs_cdnPt_V4 : STInst2<(outs),
4544           (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
4545           "if ($src1.new) memd(##$absaddr) = $src2",
4546           []>,
4547           Requires<[HasV4T]>;
4548
4549 let AddedComplexity = 30, isPredicated = 1 in
4550 def STrid_abs_cdnNotPt_V4 : STInst2<(outs),
4551           (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
4552           "if (!$src1.new) memd(##$absaddr) = $src2",
4553           []>,
4554           Requires<[HasV4T]>;
4555
4556 defm STrib : ST_abs<"memb">;
4557 defm STrih : ST_abs<"memh">;
4558 defm STriw : ST_abs<"memw">;
4559
4560 let Predicates = [HasV4T], AddedComplexity  = 30 in
4561 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
4562                         (HexagonCONST32 tglobaladdr:$absaddr)),
4563           (STrib_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
4564
4565 let Predicates = [HasV4T], AddedComplexity  = 30 in
4566 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
4567                           (HexagonCONST32 tglobaladdr:$absaddr)),
4568           (STrih_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
4569
4570 let Predicates = [HasV4T], AddedComplexity  = 30 in
4571 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32 tglobaladdr:$absaddr)),
4572           (STriw_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
4573
4574
4575 multiclass LD_abs<string OpcStr> {
4576   let isPredicable = 1 in
4577   def _abs_V4 : LDInst2<(outs IntRegs:$dst),
4578             (ins globaladdress:$absaddr),
4579             !strconcat("$dst = ", !strconcat(OpcStr, "(##$absaddr)")),
4580             []>,
4581             Requires<[HasV4T]>;
4582
4583   let isPredicated = 1 in
4584   def _abs_cPt_V4 : LDInst2<(outs IntRegs:$dst),
4585             (ins PredRegs:$src1, globaladdress:$absaddr),
4586             !strconcat("if ($src1) $dst = ",
4587             !strconcat(OpcStr, "(##$absaddr)")),
4588             []>,
4589             Requires<[HasV4T]>;
4590
4591   let isPredicated = 1 in
4592   def _abs_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
4593             (ins PredRegs:$src1, globaladdress:$absaddr),
4594             !strconcat("if (!$src1) $dst = ",
4595             !strconcat(OpcStr, "(##$absaddr)")),
4596             []>,
4597             Requires<[HasV4T]>;
4598
4599   let isPredicated = 1 in
4600   def _abs_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
4601             (ins PredRegs:$src1, globaladdress:$absaddr),
4602             !strconcat("if ($src1.new) $dst = ",
4603             !strconcat(OpcStr, "(##$absaddr)")),
4604             []>,
4605             Requires<[HasV4T]>;
4606
4607   let isPredicated = 1 in
4608   def _abs_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
4609             (ins PredRegs:$src1, globaladdress:$absaddr),
4610             !strconcat("if (!$src1.new) $dst = ",
4611             !strconcat(OpcStr, "(##$absaddr)")),
4612             []>,
4613             Requires<[HasV4T]>;
4614 }
4615
4616 let AddedComplexity = 30 in
4617 def LDrid_abs_V4 : LDInst<(outs DoubleRegs:$dst),
4618           (ins globaladdress:$absaddr),
4619           "$dst = memd(##$absaddr)",
4620           [(set (i64 DoubleRegs:$dst),
4621                 (load (HexagonCONST32 tglobaladdr:$absaddr)))]>,
4622           Requires<[HasV4T]>;
4623
4624 let AddedComplexity = 30, isPredicated = 1 in
4625 def LDrid_abs_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
4626           (ins PredRegs:$src1, globaladdress:$absaddr),
4627           "if ($src1) $dst = memd(##$absaddr)",
4628           []>,
4629           Requires<[HasV4T]>;
4630
4631 let AddedComplexity = 30, isPredicated = 1 in
4632 def LDrid_abs_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
4633           (ins PredRegs:$src1, globaladdress:$absaddr),
4634           "if (!$src1) $dst = memd(##$absaddr)",
4635           []>,
4636           Requires<[HasV4T]>;
4637
4638 let AddedComplexity = 30, isPredicated = 1 in
4639 def LDrid_abs_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
4640           (ins PredRegs:$src1, globaladdress:$absaddr),
4641           "if ($src1.new) $dst = memd(##$absaddr)",
4642           []>,
4643           Requires<[HasV4T]>;
4644
4645 let AddedComplexity = 30, isPredicated = 1 in
4646 def LDrid_abs_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
4647           (ins PredRegs:$src1, globaladdress:$absaddr),
4648           "if (!$src1.new) $dst = memd(##$absaddr)",
4649           []>,
4650           Requires<[HasV4T]>;
4651
4652 defm LDrib : LD_abs<"memb">;
4653 defm LDriub : LD_abs<"memub">;
4654 defm LDrih : LD_abs<"memh">;
4655 defm LDriuh : LD_abs<"memuh">;
4656 defm LDriw : LD_abs<"memw">;
4657
4658
4659 let Predicates = [HasV4T], AddedComplexity  = 30 in
4660 def : Pat<(i32 (load (HexagonCONST32 tglobaladdr:$absaddr))),
4661           (LDriw_abs_V4 tglobaladdr: $absaddr)>;
4662
4663 let Predicates = [HasV4T], AddedComplexity=30 in
4664 def : Pat<(i32 (sextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
4665           (LDrib_abs_V4 tglobaladdr:$absaddr)>;
4666
4667 let Predicates = [HasV4T], AddedComplexity=30 in
4668 def : Pat<(i32 (zextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
4669           (LDriub_abs_V4 tglobaladdr:$absaddr)>;
4670
4671 let Predicates = [HasV4T], AddedComplexity=30 in
4672 def : Pat<(i32 (sextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
4673           (LDrih_abs_V4 tglobaladdr:$absaddr)>;
4674
4675 let Predicates = [HasV4T], AddedComplexity=30 in
4676 def : Pat<(i32 (zextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
4677           (LDriuh_abs_V4 tglobaladdr:$absaddr)>;
4678
4679 // Transfer global address into a register
4680 let AddedComplexity=50, isMoveImm = 1, isReMaterializable = 1 in
4681 def TFRI_V4 : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$src1),
4682            "$dst = ##$src1",
4683            [(set IntRegs:$dst, (HexagonCONST32 tglobaladdr:$src1))]>,
4684            Requires<[HasV4T]>;
4685
4686 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
4687 def TFRI_cPt_V4 : ALU32_ri<(outs IntRegs:$dst),
4688                            (ins PredRegs:$src1, globaladdress:$src2),
4689            "if($src1) $dst = ##$src2",
4690            []>,
4691            Requires<[HasV4T]>;
4692
4693 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
4694 def TFRI_cNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
4695                               (ins PredRegs:$src1, globaladdress:$src2),
4696            "if(!$src1) $dst = ##$src2",
4697            []>,
4698            Requires<[HasV4T]>;
4699
4700 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
4701 def TFRI_cdnPt_V4 : ALU32_ri<(outs IntRegs:$dst),
4702                              (ins PredRegs:$src1, globaladdress:$src2),
4703            "if($src1.new) $dst = ##$src2",
4704            []>,
4705            Requires<[HasV4T]>;
4706
4707 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
4708 def TFRI_cdnNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
4709                                 (ins PredRegs:$src1, globaladdress:$src2),
4710            "if(!$src1.new) $dst = ##$src2",
4711            []>,
4712            Requires<[HasV4T]>;
4713
4714 let AddedComplexity = 50, Predicates = [HasV4T] in
4715 def : Pat<(HexagonCONST32_GP tglobaladdr:$src1),
4716            (TFRI_V4 tglobaladdr:$src1)>;
4717
4718
4719 // Load - Indirect with long offset: These instructions take global address
4720 // as an operand
4721 let AddedComplexity = 10 in
4722 def LDrid_ind_lo_V4 : LDInst<(outs DoubleRegs:$dst),
4723             (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$offset),
4724             "$dst=memd($src1<<#$src2+##$offset)",
4725             [(set (i64 DoubleRegs:$dst),
4726                   (load (add (shl IntRegs:$src1, u2ImmPred:$src2),
4727                         (HexagonCONST32 tglobaladdr:$offset))))]>,
4728             Requires<[HasV4T]>;
4729
4730 let AddedComplexity = 10 in
4731 multiclass LD_indirect_lo<string OpcStr, PatFrag OpNode> {
4732   def _lo_V4 : LDInst<(outs IntRegs:$dst),
4733             (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$offset),
4734             !strconcat("$dst = ",
4735             !strconcat(OpcStr, "($src1<<#$src2+##$offset)")),
4736             [(set IntRegs:$dst,
4737                   (i32 (OpNode (add (shl IntRegs:$src1, u2ImmPred:$src2),
4738                           (HexagonCONST32 tglobaladdr:$offset)))))]>,
4739             Requires<[HasV4T]>;
4740 }
4741
4742 defm LDrib_ind : LD_indirect_lo<"memb", sextloadi8>;
4743 defm LDriub_ind : LD_indirect_lo<"memub", zextloadi8>;
4744 defm LDrih_ind : LD_indirect_lo<"memh", sextloadi16>;
4745 defm LDriuh_ind : LD_indirect_lo<"memuh", zextloadi16>;
4746 defm LDriw_ind : LD_indirect_lo<"memw", load>;
4747
4748 // Store - Indirect with long offset: These instructions take global address
4749 // as an operand
4750 let AddedComplexity = 10 in
4751 def STrid_ind_lo_V4 : STInst<(outs),
4752             (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$src3,
4753                  DoubleRegs:$src4),
4754             "memd($src1<<#$src2+#$src3) = $src4",
4755             [(store (i64 DoubleRegs:$src4),
4756                  (add (shl IntRegs:$src1, u2ImmPred:$src2),
4757                       (HexagonCONST32 tglobaladdr:$src3)))]>,
4758              Requires<[HasV4T]>;
4759
4760 let AddedComplexity = 10 in
4761 multiclass ST_indirect_lo<string OpcStr, PatFrag OpNode> {
4762   def _lo_V4 : STInst<(outs),
4763             (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$src3,
4764                  IntRegs:$src4),
4765             !strconcat(OpcStr, "($src1<<#$src2+##$src3) = $src4"),
4766             [(OpNode (i32 IntRegs:$src4),
4767                  (add (shl IntRegs:$src1, u2ImmPred:$src2),
4768                       (HexagonCONST32 tglobaladdr:$src3)))]>,
4769              Requires<[HasV4T]>;
4770 }
4771
4772 defm STrib_ind : ST_indirect_lo<"memb", truncstorei8>;
4773 defm STrih_ind : ST_indirect_lo<"memh", truncstorei16>;
4774 defm STriw_ind : ST_indirect_lo<"memw", store>;
4775
4776 // Store - absolute addressing mode: These instruction take constant
4777 // value as the extended operand
4778 multiclass ST_absimm<string OpcStr> {
4779   let isPredicable = 1 in
4780   def _abs_V4 : STInst2<(outs),
4781             (ins u6Imm:$src1, IntRegs:$src2),
4782             !strconcat(OpcStr, "(#$src1) = $src2"),
4783             []>,
4784             Requires<[HasV4T]>;
4785
4786   let isPredicated = 1 in
4787   def _abs_cPt_V4 : STInst2<(outs),
4788             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
4789             !strconcat("if ($src1)", !strconcat(OpcStr, "(#$src2) = $src3")),
4790             []>,
4791             Requires<[HasV4T]>;
4792
4793   let isPredicated = 1 in
4794   def _abs_cNotPt_V4 : STInst2<(outs),
4795             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
4796             !strconcat("if (!$src1)", !strconcat(OpcStr, "(#$src2) = $src3")),
4797             []>,
4798             Requires<[HasV4T]>;
4799
4800   let isPredicated = 1 in
4801   def _abs_cdnPt_V4 : STInst2<(outs),
4802             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
4803             !strconcat("if ($src1.new)",
4804             !strconcat(OpcStr, "(#$src2) = $src3")),
4805             []>,
4806             Requires<[HasV4T]>;
4807
4808   let isPredicated = 1 in
4809   def _abs_cdnNotPt_V4 : STInst2<(outs),
4810             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
4811             !strconcat("if (!$src1.new)",
4812             !strconcat(OpcStr, "(#$src2) = $src3")),
4813             []>,
4814             Requires<[HasV4T]>;
4815
4816   def _abs_nv_V4 : STInst2<(outs),
4817             (ins u6Imm:$src1, IntRegs:$src2),
4818             !strconcat(OpcStr, "(#$src1) = $src2.new"),
4819             []>,
4820             Requires<[HasV4T]>;
4821
4822   let isPredicated = 1 in
4823   def _abs_cPt_nv_V4 : STInst2<(outs),
4824             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
4825             !strconcat("if ($src1)",
4826             !strconcat(OpcStr, "(#$src2) = $src3.new")),
4827             []>,
4828             Requires<[HasV4T]>;
4829
4830   let isPredicated = 1 in
4831   def _abs_cNotPt_nv_V4 : STInst2<(outs),
4832             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
4833             !strconcat("if (!$src1)",
4834             !strconcat(OpcStr, "(#$src2) = $src3.new")),
4835             []>,
4836             Requires<[HasV4T]>;
4837
4838   let isPredicated = 1 in
4839   def _abs_cdnPt_nv_V4 : STInst2<(outs),
4840             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
4841             !strconcat("if ($src1.new)",
4842             !strconcat(OpcStr, "(#$src2) = $src3.new")),
4843             []>,
4844             Requires<[HasV4T]>;
4845
4846   let isPredicated = 1 in
4847   def _abs_cdnNotPt_nv_V4 : STInst2<(outs),
4848             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
4849             !strconcat("if (!$src1.new)",
4850             !strconcat(OpcStr, "(#$src2) = $src3.new")),
4851             []>,
4852             Requires<[HasV4T]>;
4853 }
4854
4855 defm STrib_imm : ST_absimm<"memb">;
4856 defm STrih_imm : ST_absimm<"memh">;
4857 defm STriw_imm : ST_absimm<"memw">;
4858
4859 let Predicates = [HasV4T], AddedComplexity  = 30 in
4860 def : Pat<(truncstorei8 (i32 IntRegs:$src1), u6ImmPred:$src2),
4861           (STrib_imm_abs_V4 u6ImmPred:$src2, IntRegs: $src1)>;
4862
4863 let Predicates = [HasV4T], AddedComplexity  = 30 in
4864 def : Pat<(truncstorei16 (i32 IntRegs:$src1), u6ImmPred:$src2),
4865           (STrih_imm_abs_V4 u6ImmPred:$src2, IntRegs: $src1)>;
4866
4867 let Predicates = [HasV4T], AddedComplexity  = 30 in
4868 def : Pat<(store (i32 IntRegs:$src1), u6ImmPred:$src2),
4869           (STriw_imm_abs_V4 u6ImmPred:$src2, IntRegs: $src1)>;
4870
4871
4872 // Load - absolute addressing mode: These instruction take constant
4873 // value as the extended operand
4874
4875 multiclass LD_absimm<string OpcStr> {
4876   let isPredicable = 1 in
4877   def _abs_V4 : LDInst2<(outs IntRegs:$dst),
4878             (ins u6Imm:$src),
4879             !strconcat("$dst = ",
4880             !strconcat(OpcStr, "(#$src)")),
4881             []>,
4882             Requires<[HasV4T]>;
4883
4884   let isPredicated = 1 in
4885   def _abs_cPt_V4 : LDInst2<(outs IntRegs:$dst),
4886             (ins PredRegs:$src1, u6Imm:$src2),
4887             !strconcat("if ($src1) $dst = ",
4888             !strconcat(OpcStr, "(#$src2)")),
4889             []>,
4890             Requires<[HasV4T]>;
4891
4892   let isPredicated = 1 in
4893   def _abs_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
4894             (ins PredRegs:$src1, u6Imm:$src2),
4895             !strconcat("if (!$src1) $dst = ",
4896             !strconcat(OpcStr, "(#$src2)")),
4897             []>,
4898             Requires<[HasV4T]>;
4899
4900   let isPredicated = 1 in
4901   def _abs_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
4902             (ins PredRegs:$src1, u6Imm:$src2),
4903             !strconcat("if ($src1.new) $dst = ",
4904             !strconcat(OpcStr, "(#$src2)")),
4905             []>,
4906             Requires<[HasV4T]>;
4907
4908   let isPredicated = 1 in
4909   def _abs_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
4910             (ins PredRegs:$src1, u6Imm:$src2),
4911             !strconcat("if (!$src1.new) $dst = ",
4912             !strconcat(OpcStr, "(#$src2)")),
4913             []>,
4914             Requires<[HasV4T]>;
4915 }
4916
4917 defm LDrib_imm : LD_absimm<"memb">;
4918 defm LDriub_imm : LD_absimm<"memub">;
4919 defm LDrih_imm : LD_absimm<"memh">;
4920 defm LDriuh_imm : LD_absimm<"memuh">;
4921 defm LDriw_imm : LD_absimm<"memw">;
4922
4923 let Predicates = [HasV4T], AddedComplexity  = 30 in
4924 def : Pat<(i32 (load u6ImmPred:$src)),
4925           (LDriw_imm_abs_V4 u6ImmPred:$src)>;
4926
4927 let Predicates = [HasV4T], AddedComplexity=30 in
4928 def : Pat<(i32 (sextloadi8 u6ImmPred:$src)),
4929           (LDrib_imm_abs_V4 u6ImmPred:$src)>;
4930
4931 let Predicates = [HasV4T], AddedComplexity=30 in
4932 def : Pat<(i32 (zextloadi8 u6ImmPred:$src)),
4933           (LDriub_imm_abs_V4 u6ImmPred:$src)>;
4934
4935 let Predicates = [HasV4T], AddedComplexity=30 in
4936 def : Pat<(i32 (sextloadi16 u6ImmPred:$src)),
4937           (LDrih_imm_abs_V4 u6ImmPred:$src)>;
4938
4939 let Predicates = [HasV4T], AddedComplexity=30 in
4940 def : Pat<(i32 (zextloadi16 u6ImmPred:$src)),
4941           (LDriuh_imm_abs_V4 u6ImmPred:$src)>;
4942
4943
4944 // Indexed store double word - global address.
4945 // memw(Rs+#u6:2)=#S8
4946 let AddedComplexity = 10 in
4947 def STriw_offset_ext_V4 : STInst<(outs),
4948             (ins IntRegs:$src1, u6_2Imm:$src2, globaladdress:$src3),
4949             "memw($src1+#$src2) = ##$src3",
4950             [(store (HexagonCONST32 tglobaladdr:$src3),
4951                     (add IntRegs:$src1, u6_2ImmPred:$src2))]>,
4952             Requires<[HasV4T]>;
4953
4954
4955 // Indexed store double word - global address.
4956 // memw(Rs+#u6:2)=#S8
4957 let AddedComplexity = 10 in
4958 def STrih_offset_ext_V4 : STInst<(outs),
4959             (ins IntRegs:$src1, u6_1Imm:$src2, globaladdress:$src3),
4960             "memh($src1+#$src2) = ##$src3",
4961             [(truncstorei16 (HexagonCONST32 tglobaladdr:$src3),
4962                     (add IntRegs:$src1, u6_1ImmPred:$src2))]>,
4963             Requires<[HasV4T]>;