1 //=- HexagonInstrInfoV4.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V4 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 let neverHasSideEffects = 1 in
15 class T_Immext<dag ins> :
16 EXTENDERInst<(outs), ins, "immext(#$imm)", []>,
19 def IMMEXT_b : T_Immext<(ins brtarget:$imm)>;
20 def IMMEXT_c : T_Immext<(ins calltarget:$imm)>;
21 def IMMEXT_g : T_Immext<(ins globaladdress:$imm)>;
22 def IMMEXT_i : T_Immext<(ins u26_6Imm:$imm)>;
24 // Fold (add (CONST32 tglobaladdr:$addr) <offset>) into a global address.
25 def FoldGlobalAddr : ComplexPattern<i32, 1, "foldGlobalAddress", [], []>;
27 // Fold (add (CONST32_GP tglobaladdr:$addr) <offset>) into a global address.
28 def FoldGlobalAddrGP : ComplexPattern<i32, 1, "foldGlobalAddressGP", [], []>;
30 def NumUsesBelowThresCONST32 : PatFrag<(ops node:$addr),
31 (HexagonCONST32 node:$addr), [{
32 return hasNumUsesBelowThresGA(N->getOperand(0).getNode());
35 // Hexagon V4 Architecture spec defines 8 instruction classes:
36 // LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the
40 // ========================================
41 // Loads (8/16/32/64 bit)
45 // ========================================
46 // Stores (8/16/32/64 bit)
49 // ALU32 Instructions:
50 // ========================================
51 // Arithmetic / Logical (32 bit)
54 // XTYPE Instructions (32/64 bit):
55 // ========================================
56 // Arithmetic, Logical, Bit Manipulation
57 // Multiply (Integer, Fractional, Complex)
58 // Permute / Vector Permute Operations
59 // Predicate Operations
60 // Shift / Shift with Add/Sub/Logical
62 // Vector Halfword (ALU, Shift, Multiply)
63 // Vector Word (ALU, Shift)
66 // ========================================
67 // Jump/Call PC-relative
70 // ========================================
73 // MEMOP Instructions:
74 // ========================================
75 // Operation on memory (8/16/32 bit)
78 // ========================================
83 // ========================================
84 // Control-Register Transfers
85 // Hardware Loop Setup
86 // Predicate Logicals & Reductions
88 // SYSTEM Instructions (not implemented in the compiler):
89 // ========================================
95 //===----------------------------------------------------------------------===//
97 //===----------------------------------------------------------------------===//
98 // Generate frame index addresses.
99 let neverHasSideEffects = 1, isReMaterializable = 1,
100 isExtended = 1, opExtendable = 2, validSubTargets = HasV4SubT in
101 def TFR_FI_immext_V4 : ALU32_ri<(outs IntRegs:$dst),
102 (ins IntRegs:$src1, s32Imm:$offset),
103 "$dst = add($src1, ##$offset)",
108 let validSubTargets = HasV4SubT, isExtendable = 1, opExtendable = 2,
109 isExtentSigned = 1, opExtentBits = 8 in
110 def V4_A4_rcmpeqi : ALU32_ri<(outs IntRegs:$Rd),
111 (ins IntRegs:$Rs, s8Ext:$s8),
112 "$Rd = cmp.eq($Rs, #$s8)",
113 [(set (i32 IntRegs:$Rd),
114 (i32 (zext (i1 (seteq (i32 IntRegs:$Rs),
115 s8ExtPred:$s8)))))]>,
118 // Preserve the TSTBIT generation
119 def : Pat <(i32 (zext (i1 (setne (i32 (and (i32 (shl 1, (i32 IntRegs:$src2))),
120 (i32 IntRegs:$src1))), 0)))),
121 (i32 (MUX_ii (i1 (TSTBIT_rr (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
124 // Interfered with tstbit generation, above pattern preserves, see : tstbit.ll
126 let validSubTargets = HasV4SubT, isExtendable = 1, opExtendable = 2,
127 isExtentSigned = 1, opExtentBits = 8 in
128 def V4_A4_rcmpneqi : ALU32_ri<(outs IntRegs:$Rd),
129 (ins IntRegs:$Rs, s8Ext:$s8),
130 "$Rd = !cmp.eq($Rs, #$s8)",
131 [(set (i32 IntRegs:$Rd),
132 (i32 (zext (i1 (setne (i32 IntRegs:$Rs),
133 s8ExtPred:$s8)))))]>,
137 let validSubTargets = HasV4SubT in
138 def V4_A4_rcmpeq : ALU32_ri<(outs IntRegs:$Rd),
139 (ins IntRegs:$Rs, IntRegs:$Rt),
140 "$Rd = cmp.eq($Rs, $Rt)",
141 [(set (i32 IntRegs:$Rd),
142 (i32 (zext (i1 (seteq (i32 IntRegs:$Rs),
147 let validSubTargets = HasV4SubT in
148 def V4_A4_rcmpneq : ALU32_ri<(outs IntRegs:$Rd),
149 (ins IntRegs:$Rs, IntRegs:$Rt),
150 "$Rd = !cmp.eq($Rs, $Rt)",
151 [(set (i32 IntRegs:$Rd),
152 (i32 (zext (i1 (setne (i32 IntRegs:$Rs),
156 //===----------------------------------------------------------------------===//
158 //===----------------------------------------------------------------------===//
161 //===----------------------------------------------------------------------===//
163 //===----------------------------------------------------------------------===//
166 // Rdd=combine(Rs, #s8)
167 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8,
168 neverHasSideEffects = 1, validSubTargets = HasV4SubT in
169 def COMBINE_rI_V4 : ALU32_ri<(outs DoubleRegs:$dst),
170 (ins IntRegs:$src1, s8Ext:$src2),
171 "$dst = combine($src1, #$src2)",
175 // Rdd=combine(#s8, Rs)
176 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 8,
177 neverHasSideEffects = 1, validSubTargets = HasV4SubT in
178 def COMBINE_Ir_V4 : ALU32_ir<(outs DoubleRegs:$dst),
179 (ins s8Ext:$src1, IntRegs:$src2),
180 "$dst = combine(#$src1, $src2)",
184 def HexagonWrapperCombineRI_V4 :
185 SDNode<"HexagonISD::WrapperCombineRI_V4", SDTHexagonI64I32I32>;
186 def HexagonWrapperCombineIR_V4 :
187 SDNode<"HexagonISD::WrapperCombineIR_V4", SDTHexagonI64I32I32>;
189 def : Pat <(HexagonWrapperCombineRI_V4 IntRegs:$r, s8ExtPred:$i),
190 (COMBINE_rI_V4 IntRegs:$r, s8ExtPred:$i)>,
193 def : Pat <(HexagonWrapperCombineIR_V4 s8ExtPred:$i, IntRegs:$r),
194 (COMBINE_Ir_V4 s8ExtPred:$i, IntRegs:$r)>,
197 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 6,
198 neverHasSideEffects = 1, validSubTargets = HasV4SubT in
199 def COMBINE_iI_V4 : ALU32_ii<(outs DoubleRegs:$dst),
200 (ins s8Imm:$src1, u6Ext:$src2),
201 "$dst = combine(#$src1, #$src2)",
205 //===----------------------------------------------------------------------===//
207 //===----------------------------------------------------------------------===//
209 //===----------------------------------------------------------------------===//
211 //===----------------------------------------------------------------------===//
212 //===----------------------------------------------------------------------===//
213 // Template class for load instructions with Absolute set addressing mode.
214 //===----------------------------------------------------------------------===//
215 let isExtended = 1, opExtendable = 2, neverHasSideEffects = 1,
216 validSubTargets = HasV4SubT in
217 class T_LD_abs_set<string mnemonic, RegisterClass RC>:
218 LDInst2<(outs RC:$dst1, IntRegs:$dst2),
219 (ins u0AlwaysExt:$addr),
220 "$dst1 = "#mnemonic#"($dst2=##$addr)",
224 def LDrid_abs_set_V4 : T_LD_abs_set <"memd", DoubleRegs>;
225 def LDrib_abs_set_V4 : T_LD_abs_set <"memb", IntRegs>;
226 def LDriub_abs_set_V4 : T_LD_abs_set <"memub", IntRegs>;
227 def LDrih_abs_set_V4 : T_LD_abs_set <"memh", IntRegs>;
228 def LDriw_abs_set_V4 : T_LD_abs_set <"memw", IntRegs>;
229 def LDriuh_abs_set_V4 : T_LD_abs_set <"memuh", IntRegs>;
232 // multiclass for load instructions with base + register offset
234 multiclass ld_idxd_shl_pbase<string mnemonic, RegisterClass RC, bit isNot,
236 let isPredicatedNew = isPredNew in
237 def NAME : LDInst2<(outs RC:$dst),
238 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset),
239 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
240 ") ")#"$dst = "#mnemonic#"($src2+$src3<<#$offset)",
241 []>, Requires<[HasV4T]>;
244 multiclass ld_idxd_shl_pred<string mnemonic, RegisterClass RC, bit PredNot> {
245 let isPredicatedFalse = PredNot in {
246 defm _c#NAME : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 0>;
248 defm _cdn#NAME : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 1>;
252 let neverHasSideEffects = 1 in
253 multiclass ld_idxd_shl<string mnemonic, string CextOp, RegisterClass RC> {
254 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
255 let isPredicable = 1 in
256 def NAME#_V4 : LDInst2<(outs RC:$dst),
257 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
258 "$dst = "#mnemonic#"($src1+$src2<<#$offset)",
259 []>, Requires<[HasV4T]>;
261 let isPredicated = 1 in {
262 defm Pt_V4 : ld_idxd_shl_pred<mnemonic, RC, 0 >;
263 defm NotPt_V4 : ld_idxd_shl_pred<mnemonic, RC, 1>;
268 let addrMode = BaseRegOffset in {
269 defm LDrib_indexed_shl: ld_idxd_shl<"memb", "LDrib", IntRegs>, AddrModeRel;
270 defm LDriub_indexed_shl: ld_idxd_shl<"memub", "LDriub", IntRegs>, AddrModeRel;
271 defm LDrih_indexed_shl: ld_idxd_shl<"memh", "LDrih", IntRegs>, AddrModeRel;
272 defm LDriuh_indexed_shl: ld_idxd_shl<"memuh", "LDriuh", IntRegs>, AddrModeRel;
273 defm LDriw_indexed_shl: ld_idxd_shl<"memw", "LDriw", IntRegs>, AddrModeRel;
274 defm LDrid_indexed_shl: ld_idxd_shl<"memd", "LDrid", DoubleRegs>, AddrModeRel;
277 // 'def pats' for load instructions with base + register offset and non-zero
278 // immediate value. Immediate value is used to left-shift the second
280 let AddedComplexity = 40 in {
281 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1,
282 (shl IntRegs:$src2, u2ImmPred:$offset)))),
283 (LDrib_indexed_shl_V4 IntRegs:$src1,
284 IntRegs:$src2, u2ImmPred:$offset)>,
287 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1,
288 (shl IntRegs:$src2, u2ImmPred:$offset)))),
289 (LDriub_indexed_shl_V4 IntRegs:$src1,
290 IntRegs:$src2, u2ImmPred:$offset)>,
293 def : Pat <(i32 (extloadi8 (add IntRegs:$src1,
294 (shl IntRegs:$src2, u2ImmPred:$offset)))),
295 (LDriub_indexed_shl_V4 IntRegs:$src1,
296 IntRegs:$src2, u2ImmPred:$offset)>,
299 def : Pat <(i32 (sextloadi16 (add IntRegs:$src1,
300 (shl IntRegs:$src2, u2ImmPred:$offset)))),
301 (LDrih_indexed_shl_V4 IntRegs:$src1,
302 IntRegs:$src2, u2ImmPred:$offset)>,
305 def : Pat <(i32 (zextloadi16 (add IntRegs:$src1,
306 (shl IntRegs:$src2, u2ImmPred:$offset)))),
307 (LDriuh_indexed_shl_V4 IntRegs:$src1,
308 IntRegs:$src2, u2ImmPred:$offset)>,
311 def : Pat <(i32 (extloadi16 (add IntRegs:$src1,
312 (shl IntRegs:$src2, u2ImmPred:$offset)))),
313 (LDriuh_indexed_shl_V4 IntRegs:$src1,
314 IntRegs:$src2, u2ImmPred:$offset)>,
317 def : Pat <(i32 (load (add IntRegs:$src1,
318 (shl IntRegs:$src2, u2ImmPred:$offset)))),
319 (LDriw_indexed_shl_V4 IntRegs:$src1,
320 IntRegs:$src2, u2ImmPred:$offset)>,
323 def : Pat <(i64 (load (add IntRegs:$src1,
324 (shl IntRegs:$src2, u2ImmPred:$offset)))),
325 (LDrid_indexed_shl_V4 IntRegs:$src1,
326 IntRegs:$src2, u2ImmPred:$offset)>,
331 // 'def pats' for load instruction base + register offset and
332 // zero immediate value.
333 let AddedComplexity = 10 in {
334 def : Pat <(i64 (load (add IntRegs:$src1, IntRegs:$src2))),
335 (LDrid_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
338 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1, IntRegs:$src2))),
339 (LDrib_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
342 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1, IntRegs:$src2))),
343 (LDriub_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
346 def : Pat <(i32 (extloadi8 (add IntRegs:$src1, IntRegs:$src2))),
347 (LDriub_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
350 def : Pat <(i32 (sextloadi16 (add IntRegs:$src1, IntRegs:$src2))),
351 (LDrih_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
354 def : Pat <(i32 (zextloadi16 (add IntRegs:$src1, IntRegs:$src2))),
355 (LDriuh_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
358 def : Pat <(i32 (extloadi16 (add IntRegs:$src1, IntRegs:$src2))),
359 (LDriuh_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
362 def : Pat <(i32 (load (add IntRegs:$src1, IntRegs:$src2))),
363 (LDriw_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
368 def : Pat <(i64 (zext (i1 PredRegs:$src1))),
369 (i64 (COMBINE_Ir_V4 0, (MUX_ii (i1 PredRegs:$src1), 1, 0)))>,
373 def : Pat <(i64 (zext (i32 IntRegs:$src1))),
374 (i64 (COMBINE_Ir_V4 0, (i32 IntRegs:$src1)))>,
377 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
378 (i64 (COMBINE_Ir_V4 0, (LDriub ADDRriS11_0:$src1)))>,
381 let AddedComplexity = 20 in
382 def: Pat <(i64 (zextloadi8 (add (i32 IntRegs:$src1),
383 s11_0ExtPred:$offset))),
384 (i64 (COMBINE_Ir_V4 0, (LDriub_indexed IntRegs:$src1,
385 s11_0ExtPred:$offset)))>,
389 def: Pat <(i64 (zextloadi1 ADDRriS11_0:$src1)),
390 (i64 (COMBINE_Ir_V4 0, (LDriub ADDRriS11_0:$src1)))>,
393 let AddedComplexity = 20 in
394 def: Pat <(i64 (zextloadi1 (add (i32 IntRegs:$src1),
395 s11_0ExtPred:$offset))),
396 (i64 (COMBINE_Ir_V4 0, (LDriub_indexed IntRegs:$src1,
397 s11_0ExtPred:$offset)))>,
401 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
402 (i64 (COMBINE_Ir_V4 0, (LDriuh ADDRriS11_1:$src1)))>,
405 let AddedComplexity = 20 in
406 def: Pat <(i64 (zextloadi16 (add (i32 IntRegs:$src1),
407 s11_1ExtPred:$offset))),
408 (i64 (COMBINE_Ir_V4 0, (LDriuh_indexed IntRegs:$src1,
409 s11_1ExtPred:$offset)))>,
413 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
414 (i64 (COMBINE_Ir_V4 0, (LDrih ADDRriS11_2:$src1)))>,
417 let AddedComplexity = 20 in
418 def: Pat <(i64 (extloadi16 (add (i32 IntRegs:$src1),
419 s11_1ExtPred:$offset))),
420 (i64 (COMBINE_Ir_V4 0, (LDrih_indexed IntRegs:$src1,
421 s11_1ExtPred:$offset)))>,
425 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
426 (i64 (COMBINE_Ir_V4 0, (LDriw ADDRriS11_2:$src1)))>,
429 let AddedComplexity = 100 in
430 def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
431 (i64 (COMBINE_Ir_V4 0, (LDriw_indexed IntRegs:$src1,
432 s11_2ExtPred:$offset)))>,
436 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
437 (i64 (COMBINE_Ir_V4 0, (LDriw ADDRriS11_2:$src1)))>,
440 let AddedComplexity = 100 in
441 def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
442 (i64 (COMBINE_Ir_V4 0, (LDriw_indexed IntRegs:$src1,
443 s11_2ExtPred:$offset)))>,
448 //===----------------------------------------------------------------------===//
450 //===----------------------------------------------------------------------===//
452 //===----------------------------------------------------------------------===//
454 //===----------------------------------------------------------------------===//
456 //===----------------------------------------------------------------------===//
457 // Template class for store instructions with Absolute set addressing mode.
458 //===----------------------------------------------------------------------===//
459 let isExtended = 1, opExtendable = 2, validSubTargets = HasV4SubT in
460 class T_ST_abs_set<string mnemonic, RegisterClass RC>:
461 STInst2<(outs IntRegs:$dst1),
462 (ins RC:$src1, u0AlwaysExt:$src2),
463 mnemonic#"($dst1=##$src2) = $src1",
467 def STrid_abs_set_V4 : T_ST_abs_set <"memd", DoubleRegs>;
468 def STrib_abs_set_V4 : T_ST_abs_set <"memb", IntRegs>;
469 def STrih_abs_set_V4 : T_ST_abs_set <"memh", IntRegs>;
470 def STriw_abs_set_V4 : T_ST_abs_set <"memw", IntRegs>;
472 //===----------------------------------------------------------------------===//
473 // multiclass for store instructions with base + register offset addressing
475 //===----------------------------------------------------------------------===//
476 multiclass ST_Idxd_shl_Pbase<string mnemonic, RegisterClass RC, bit isNot,
478 let isPredicatedNew = isPredNew in
479 def NAME : STInst2<(outs),
480 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
482 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
483 ") ")#mnemonic#"($src2+$src3<<#$src4) = $src5",
488 multiclass ST_Idxd_shl_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
489 let isPredicatedFalse = PredNot in {
490 defm _c#NAME : ST_Idxd_shl_Pbase<mnemonic, RC, PredNot, 0>;
492 defm _cdn#NAME : ST_Idxd_shl_Pbase<mnemonic, RC, PredNot, 1>;
496 let isNVStorable = 1 in
497 multiclass ST_Idxd_shl<string mnemonic, string CextOp, RegisterClass RC> {
498 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
499 let isPredicable = 1 in
500 def NAME#_V4 : STInst2<(outs),
501 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, RC:$src4),
502 mnemonic#"($src1+$src2<<#$src3) = $src4",
506 let isPredicated = 1 in {
507 defm Pt_V4 : ST_Idxd_shl_Pred<mnemonic, RC, 0 >;
508 defm NotPt_V4 : ST_Idxd_shl_Pred<mnemonic, RC, 1>;
513 // multiclass for new-value store instructions with base + register offset
515 multiclass ST_Idxd_shl_Pbase_nv<string mnemonic, RegisterClass RC, bit isNot,
517 let isPredicatedNew = isPredNew in
518 def NAME#_nv_V4 : NVInst_V4<(outs),
519 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
521 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
522 ") ")#mnemonic#"($src2+$src3<<#$src4) = $src5.new",
527 multiclass ST_Idxd_shl_Pred_nv<string mnemonic, RegisterClass RC, bit PredNot> {
528 let isPredicatedFalse = PredNot in {
529 defm _c#NAME : ST_Idxd_shl_Pbase_nv<mnemonic, RC, PredNot, 0>;
531 defm _cdn#NAME : ST_Idxd_shl_Pbase_nv<mnemonic, RC, PredNot, 1>;
535 let mayStore = 1, isNVStore = 1 in
536 multiclass ST_Idxd_shl_nv<string mnemonic, string CextOp, RegisterClass RC> {
537 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
538 let isPredicable = 1 in
539 def NAME#_nv_V4 : NVInst_V4<(outs),
540 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, RC:$src4),
541 mnemonic#"($src1+$src2<<#$src3) = $src4.new",
545 let isPredicated = 1 in {
546 defm Pt : ST_Idxd_shl_Pred_nv<mnemonic, RC, 0 >;
547 defm NotPt : ST_Idxd_shl_Pred_nv<mnemonic, RC, 1>;
552 let addrMode = BaseRegOffset, neverHasSideEffects = 1,
553 validSubTargets = HasV4SubT in {
554 defm STrib_indexed_shl: ST_Idxd_shl<"memb", "STrib", IntRegs>,
555 ST_Idxd_shl_nv<"memb", "STrib", IntRegs>, AddrModeRel;
557 defm STrih_indexed_shl: ST_Idxd_shl<"memh", "STrih", IntRegs>,
558 ST_Idxd_shl_nv<"memh", "STrih", IntRegs>, AddrModeRel;
560 defm STriw_indexed_shl: ST_Idxd_shl<"memw", "STriw", IntRegs>,
561 ST_Idxd_shl_nv<"memw", "STriw", IntRegs>, AddrModeRel;
563 let isNVStorable = 0 in
564 defm STrid_indexed_shl: ST_Idxd_shl<"memd", "STrid", DoubleRegs>, AddrModeRel;
567 let Predicates = [HasV4T], AddedComplexity = 10 in {
568 def : Pat<(truncstorei8 (i32 IntRegs:$src4),
569 (add IntRegs:$src1, (shl IntRegs:$src2,
571 (STrib_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
572 u2ImmPred:$src3, IntRegs:$src4)>;
574 def : Pat<(truncstorei16 (i32 IntRegs:$src4),
575 (add IntRegs:$src1, (shl IntRegs:$src2,
577 (STrih_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
578 u2ImmPred:$src3, IntRegs:$src4)>;
580 def : Pat<(store (i32 IntRegs:$src4),
581 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
582 (STriw_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
583 u2ImmPred:$src3, IntRegs:$src4)>;
585 def : Pat<(store (i64 DoubleRegs:$src4),
586 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
587 (STrid_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
588 u2ImmPred:$src3, DoubleRegs:$src4)>;
591 let isExtended = 1, opExtendable = 2 in
592 class T_ST_LongOff <string mnemonic, PatFrag stOp, RegisterClass RC, ValueType VT> :
594 (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, RC:$src4),
595 mnemonic#"($src1<<#$src2+##$src3) = $src4",
596 [(stOp (VT RC:$src4),
597 (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
598 u0AlwaysExtPred:$src3))]>,
601 let isExtended = 1, opExtendable = 2, mayStore = 1, isNVStore = 1 in
602 class T_ST_LongOff_nv <string mnemonic> :
604 (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, IntRegs:$src4),
605 mnemonic#"($src1<<#$src2+##$src3) = $src4.new",
609 multiclass ST_LongOff <string mnemonic, string BaseOp, PatFrag stOp> {
610 let BaseOpcode = BaseOp#"_shl" in {
611 let isNVStorable = 1 in
612 def NAME#_V4 : T_ST_LongOff<mnemonic, stOp, IntRegs, i32>;
614 def NAME#_nv_V4 : T_ST_LongOff_nv<mnemonic>;
618 let AddedComplexity = 10, validSubTargets = HasV4SubT in {
619 def STrid_shl_V4 : T_ST_LongOff<"memd", store, DoubleRegs, i64>;
620 defm STrib_shl : ST_LongOff <"memb", "STrib", truncstorei8>, NewValueRel;
621 defm STrih_shl : ST_LongOff <"memh", "Strih", truncstorei16>, NewValueRel;
622 defm STriw_shl : ST_LongOff <"memw", "STriw", store>, NewValueRel;
625 let AddedComplexity = 40 in
626 multiclass T_ST_LOff_Pats <InstHexagon I, RegisterClass RC, ValueType VT,
628 def : Pat<(stOp (VT RC:$src4),
629 (add (shl IntRegs:$src1, u2ImmPred:$src2),
630 (NumUsesBelowThresCONST32 tglobaladdr:$src3))),
631 (I IntRegs:$src1, u2ImmPred:$src2, tglobaladdr:$src3, RC:$src4)>;
633 def : Pat<(stOp (VT RC:$src4),
635 (NumUsesBelowThresCONST32 tglobaladdr:$src3))),
636 (I IntRegs:$src1, 0, tglobaladdr:$src3, RC:$src4)>;
639 defm : T_ST_LOff_Pats<STrid_shl_V4, DoubleRegs, i64, store>;
640 defm : T_ST_LOff_Pats<STriw_shl_V4, IntRegs, i32, store>;
641 defm : T_ST_LOff_Pats<STrib_shl_V4, IntRegs, i32, truncstorei8>;
642 defm : T_ST_LOff_Pats<STrih_shl_V4, IntRegs, i32, truncstorei16>;
644 // memd(Rx++#s4:3)=Rtt
645 // memd(Rx++#s4:3:circ(Mu))=Rtt
646 // memd(Rx++I:circ(Mu))=Rtt
648 // memd(Rx++Mu:brev)=Rtt
649 // memd(gp+#u16:3)=Rtt
651 // Store doubleword conditionally.
652 // if ([!]Pv[.new]) memd(#u6)=Rtt
653 // TODO: needs to be implemented.
655 //===----------------------------------------------------------------------===//
656 // multiclass for store instructions with base + immediate offset
657 // addressing mode and immediate stored value.
658 // mem[bhw](Rx++#s4:3)=#s8
659 // if ([!]Pv[.new]) mem[bhw](Rx++#s4:3)=#s6
660 //===----------------------------------------------------------------------===//
661 multiclass ST_Imm_Pbase<string mnemonic, Operand OffsetOp, bit isNot,
663 let isPredicatedNew = isPredNew in
664 def NAME : STInst2<(outs),
665 (ins PredRegs:$src1, IntRegs:$src2, OffsetOp:$src3, s6Ext:$src4),
666 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
667 ") ")#mnemonic#"($src2+#$src3) = #$src4",
672 multiclass ST_Imm_Pred<string mnemonic, Operand OffsetOp, bit PredNot> {
673 let isPredicatedFalse = PredNot in {
674 defm _c#NAME : ST_Imm_Pbase<mnemonic, OffsetOp, PredNot, 0>;
676 defm _cdn#NAME : ST_Imm_Pbase<mnemonic, OffsetOp, PredNot, 1>;
680 let isExtendable = 1, isExtentSigned = 1, neverHasSideEffects = 1 in
681 multiclass ST_Imm<string mnemonic, string CextOp, Operand OffsetOp> {
682 let CextOpcode = CextOp, BaseOpcode = CextOp#_imm in {
683 let opExtendable = 2, opExtentBits = 8, isPredicable = 1 in
684 def NAME#_V4 : STInst2<(outs),
685 (ins IntRegs:$src1, OffsetOp:$src2, s8Ext:$src3),
686 mnemonic#"($src1+#$src2) = #$src3",
690 let opExtendable = 3, opExtentBits = 6, isPredicated = 1 in {
691 defm Pt_V4 : ST_Imm_Pred<mnemonic, OffsetOp, 0>;
692 defm NotPt_V4 : ST_Imm_Pred<mnemonic, OffsetOp, 1 >;
697 let addrMode = BaseImmOffset, InputType = "imm",
698 validSubTargets = HasV4SubT in {
699 defm STrib_imm : ST_Imm<"memb", "STrib", u6_0Imm>, ImmRegRel, PredNewRel;
700 defm STrih_imm : ST_Imm<"memh", "STrih", u6_1Imm>, ImmRegRel, PredNewRel;
701 defm STriw_imm : ST_Imm<"memw", "STriw", u6_2Imm>, ImmRegRel, PredNewRel;
704 let Predicates = [HasV4T], AddedComplexity = 10 in {
705 def: Pat<(truncstorei8 s8ExtPred:$src3, (add IntRegs:$src1, u6_0ImmPred:$src2)),
706 (STrib_imm_V4 IntRegs:$src1, u6_0ImmPred:$src2, s8ExtPred:$src3)>;
708 def: Pat<(truncstorei16 s8ExtPred:$src3, (add IntRegs:$src1,
710 (STrih_imm_V4 IntRegs:$src1, u6_1ImmPred:$src2, s8ExtPred:$src3)>;
712 def: Pat<(store s8ExtPred:$src3, (add IntRegs:$src1, u6_2ImmPred:$src2)),
713 (STriw_imm_V4 IntRegs:$src1, u6_2ImmPred:$src2, s8ExtPred:$src3)>;
716 let AddedComplexity = 6 in
717 def : Pat <(truncstorei8 s8ExtPred:$src2, (i32 IntRegs:$src1)),
718 (STrib_imm_V4 IntRegs:$src1, 0, s8ExtPred:$src2)>,
721 // memb(Rx++#s4:0:circ(Mu))=Rt
722 // memb(Rx++I:circ(Mu))=Rt
724 // memb(Rx++Mu:brev)=Rt
725 // memb(gp+#u16:0)=Rt
729 // TODO: needs to be implemented
731 // memh(Rs+#s11:1)=Rt.H
732 let AddedComplexity = 6 in
733 def : Pat <(truncstorei16 s8ExtPred:$src2, (i32 IntRegs:$src1)),
734 (STrih_imm_V4 IntRegs:$src1, 0, s8ExtPred:$src2)>,
737 // memh(Rs+Ru<<#u2)=Rt.H
738 // TODO: needs to be implemented.
740 // memh(Ru<<#u2+#U6)=Rt.H
741 // memh(Rx++#s4:1:circ(Mu))=Rt.H
742 // memh(Rx++#s4:1:circ(Mu))=Rt
743 // memh(Rx++I:circ(Mu))=Rt.H
744 // memh(Rx++I:circ(Mu))=Rt
747 // memh(Rx++Mu:brev)=Rt.H
748 // memh(Rx++Mu:brev)=Rt
749 // memh(gp+#u16:1)=Rt
750 // if ([!]Pv[.new]) memh(#u6)=Rt.H
751 // if ([!]Pv[.new]) memh(#u6)=Rt
754 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt.H
755 // TODO: needs to be implemented.
757 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt.H
758 // TODO: Needs to be implemented.
762 // TODO: Needs to be implemented.
765 let neverHasSideEffects = 1 in
766 def STriw_pred_V4 : STInst2<(outs),
767 (ins MEMri:$addr, PredRegs:$src1),
768 "Error; should not emit",
772 let AddedComplexity = 6 in
773 def : Pat <(store s8ExtPred:$src2, (i32 IntRegs:$src1)),
774 (STriw_imm_V4 IntRegs:$src1, 0, s8ExtPred:$src2)>,
777 // memw(Rx++#s4:2)=Rt
778 // memw(Rx++#s4:2:circ(Mu))=Rt
779 // memw(Rx++I:circ(Mu))=Rt
781 // memw(Rx++Mu:brev)=Rt
783 //===----------------------------------------------------------------------===
785 //===----------------------------------------------------------------------===
788 //===----------------------------------------------------------------------===//
790 //===----------------------------------------------------------------------===//
792 // multiclass for new-value store instructions with base + immediate offset.
794 multiclass ST_Idxd_Pbase_nv<string mnemonic, RegisterClass RC,
795 Operand predImmOp, bit isNot, bit isPredNew> {
796 let isPredicatedNew = isPredNew in
797 def NAME#_nv_V4 : NVInst_V4<(outs),
798 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4),
799 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
800 ") ")#mnemonic#"($src2+#$src3) = $src4.new",
805 multiclass ST_Idxd_Pred_nv<string mnemonic, RegisterClass RC, Operand predImmOp,
807 let isPredicatedFalse = PredNot in {
808 defm _c#NAME : ST_Idxd_Pbase_nv<mnemonic, RC, predImmOp, PredNot, 0>;
810 defm _cdn#NAME : ST_Idxd_Pbase_nv<mnemonic, RC, predImmOp, PredNot, 1>;
814 let mayStore = 1, isNVStore = 1, neverHasSideEffects = 1, isExtendable = 1 in
815 multiclass ST_Idxd_nv<string mnemonic, string CextOp, RegisterClass RC,
816 Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
817 bits<5> PredImmBits> {
819 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
820 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
822 def NAME#_nv_V4 : NVInst_V4<(outs),
823 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
824 mnemonic#"($src1+#$src2) = $src3.new",
828 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits,
829 isPredicated = 1 in {
830 defm Pt : ST_Idxd_Pred_nv<mnemonic, RC, predImmOp, 0>;
831 defm NotPt : ST_Idxd_Pred_nv<mnemonic, RC, predImmOp, 1>;
836 let addrMode = BaseImmOffset, validSubTargets = HasV4SubT in {
837 defm STrib_indexed: ST_Idxd_nv<"memb", "STrib", IntRegs, s11_0Ext,
838 u6_0Ext, 11, 6>, AddrModeRel;
839 defm STrih_indexed: ST_Idxd_nv<"memh", "STrih", IntRegs, s11_1Ext,
840 u6_1Ext, 12, 7>, AddrModeRel;
841 defm STriw_indexed: ST_Idxd_nv<"memw", "STriw", IntRegs, s11_2Ext,
842 u6_2Ext, 13, 8>, AddrModeRel;
845 // multiclass for new-value store instructions with base + immediate offset.
846 // and MEMri operand.
847 multiclass ST_MEMri_Pbase_nv<string mnemonic, RegisterClass RC, bit isNot,
849 let isPredicatedNew = isPredNew in
850 def NAME#_nv_V4 : NVInst_V4<(outs),
851 (ins PredRegs:$src1, MEMri:$addr, RC: $src2),
852 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
853 ") ")#mnemonic#"($addr) = $src2.new",
858 multiclass ST_MEMri_Pred_nv<string mnemonic, RegisterClass RC, bit PredNot> {
859 let isPredicatedFalse = PredNot in {
860 defm _c#NAME : ST_MEMri_Pbase_nv<mnemonic, RC, PredNot, 0>;
863 defm _cdn#NAME : ST_MEMri_Pbase_nv<mnemonic, RC, PredNot, 1>;
867 let mayStore = 1, isNVStore = 1, isExtendable = 1, neverHasSideEffects = 1 in
868 multiclass ST_MEMri_nv<string mnemonic, string CextOp, RegisterClass RC,
869 bits<5> ImmBits, bits<5> PredImmBits> {
871 let CextOpcode = CextOp, BaseOpcode = CextOp in {
872 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
874 def NAME#_nv_V4 : NVInst_V4<(outs),
875 (ins MEMri:$addr, RC:$src),
876 mnemonic#"($addr) = $src.new",
880 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits,
881 neverHasSideEffects = 1, isPredicated = 1 in {
882 defm Pt : ST_MEMri_Pred_nv<mnemonic, RC, 0>;
883 defm NotPt : ST_MEMri_Pred_nv<mnemonic, RC, 1>;
888 let addrMode = BaseImmOffset, isMEMri = "true", validSubTargets = HasV4SubT,
890 defm STrib: ST_MEMri_nv<"memb", "STrib", IntRegs, 11, 6>, AddrModeRel;
891 defm STrih: ST_MEMri_nv<"memh", "STrih", IntRegs, 12, 7>, AddrModeRel;
892 defm STriw: ST_MEMri_nv<"memw", "STriw", IntRegs, 13, 8>, AddrModeRel;
895 //===----------------------------------------------------------------------===//
896 // Post increment store
897 // mem[bhwd](Rx++#s4:[0123])=Nt.new
898 //===----------------------------------------------------------------------===//
900 multiclass ST_PostInc_Pbase_nv<string mnemonic, RegisterClass RC, Operand ImmOp,
901 bit isNot, bit isPredNew> {
902 let isPredicatedNew = isPredNew in
903 def NAME#_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
904 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3),
905 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
906 ") ")#mnemonic#"($src2++#$offset) = $src3.new",
912 multiclass ST_PostInc_Pred_nv<string mnemonic, RegisterClass RC,
913 Operand ImmOp, bit PredNot> {
914 let isPredicatedFalse = PredNot in {
915 defm _c#NAME : ST_PostInc_Pbase_nv<mnemonic, RC, ImmOp, PredNot, 0>;
917 let Predicates = [HasV4T], validSubTargets = HasV4SubT in
918 defm _cdn#NAME : ST_PostInc_Pbase_nv<mnemonic, RC, ImmOp, PredNot, 1>;
922 let hasCtrlDep = 1, isNVStore = 1, neverHasSideEffects = 1 in
923 multiclass ST_PostInc_nv<string mnemonic, string BaseOp, RegisterClass RC,
926 let BaseOpcode = "POST_"#BaseOp in {
927 let isPredicable = 1 in
928 def NAME#_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
929 (ins IntRegs:$src1, ImmOp:$offset, RC:$src2),
930 mnemonic#"($src1++#$offset) = $src2.new",
935 let isPredicated = 1 in {
936 defm Pt : ST_PostInc_Pred_nv<mnemonic, RC, ImmOp, 0 >;
937 defm NotPt : ST_PostInc_Pred_nv<mnemonic, RC, ImmOp, 1 >;
942 let validSubTargets = HasV4SubT in {
943 defm POST_STbri: ST_PostInc_nv <"memb", "STrib", IntRegs, s4_0Imm>, AddrModeRel;
944 defm POST_SThri: ST_PostInc_nv <"memh", "STrih", IntRegs, s4_1Imm>, AddrModeRel;
945 defm POST_STwri: ST_PostInc_nv <"memw", "STriw", IntRegs, s4_2Imm>, AddrModeRel;
948 // memb(Rx++#s4:0:circ(Mu))=Nt.new
949 // memb(Rx++I:circ(Mu))=Nt.new
950 // memb(Rx++Mu)=Nt.new
951 // memb(Rx++Mu:brev)=Nt.new
952 // memh(Rx++#s4:1:circ(Mu))=Nt.new
953 // memh(Rx++I:circ(Mu))=Nt.new
954 // memh(Rx++Mu)=Nt.new
955 // memh(Rx++Mu:brev)=Nt.new
957 // memw(Rx++#s4:2:circ(Mu))=Nt.new
958 // memw(Rx++I:circ(Mu))=Nt.new
959 // memw(Rx++Mu)=Nt.new
960 // memw(Rx++Mu:brev)=Nt.new
962 //===----------------------------------------------------------------------===//
964 //===----------------------------------------------------------------------===//
966 //===----------------------------------------------------------------------===//
968 //===----------------------------------------------------------------------===//
970 //===----------------------------------------------------------------------===//
971 // multiclass/template class for the new-value compare jumps with the register
973 //===----------------------------------------------------------------------===//
975 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11 in
976 class NVJrr_template<string mnemonic, bits<3> majOp, bit NvOpNum,
977 bit isNegCond, bit isTaken>
979 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
980 "if ("#!if(isNegCond, "!","")#mnemonic#
981 "($src1"#!if(!eq(NvOpNum, 0),".new, ",", ")#
982 "$src2"#!if(!eq(NvOpNum, 1),".new))","))")#" jump:"
983 #!if(isTaken, "t","nt")#" $offset",
984 []>, Requires<[HasV4T]> {
988 bits<3> Ns; // New-Value Operand
989 bits<5> RegOp; // Non New-Value Operand
992 let isBrTaken = !if(isTaken, "true", "false");
993 let isPredicatedFalse = isNegCond;
995 let Ns = !if(!eq(NvOpNum, 0), src1{2-0}, src2{2-0});
996 let RegOp = !if(!eq(NvOpNum, 0), src2, src1);
1000 let Inst{25-23} = majOp;
1001 let Inst{22} = isNegCond;
1002 let Inst{18-16} = Ns;
1003 let Inst{13} = isTaken;
1004 let Inst{12-8} = RegOp;
1005 let Inst{21-20} = offset{10-9};
1006 let Inst{7-1} = offset{8-2};
1010 multiclass NVJrr_cond<string mnemonic, bits<3> majOp, bit NvOpNum,
1012 // Branch not taken:
1013 def _nt_V4: NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 0>;
1015 def _t_V4: NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 1>;
1018 // NvOpNum = 0 -> First Operand is a new-value Register
1019 // NvOpNum = 1 -> Second Operand is a new-value Register
1021 multiclass NVJrr_base<string mnemonic, string BaseOp, bits<3> majOp,
1023 let BaseOpcode = BaseOp#_NVJ in {
1024 defm _t_Jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 0>; // True cond
1025 defm _f_Jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 1>; // False cond
1029 // if ([!]cmp.eq(Ns.new,Rt)) jump:[n]t #r9:2
1030 // if ([!]cmp.gt(Ns.new,Rt)) jump:[n]t #r9:2
1031 // if ([!]cmp.gtu(Ns.new,Rt)) jump:[n]t #r9:2
1032 // if ([!]cmp.gt(Rt,Ns.new)) jump:[n]t #r9:2
1033 // if ([!]cmp.gtu(Rt,Ns.new)) jump:[n]t #r9:2
1035 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
1036 Defs = [PC], neverHasSideEffects = 1, validSubTargets = HasV4SubT in {
1037 defm CMPEQrr : NVJrr_base<"cmp.eq", "CMPEQ", 0b000, 0>, PredRel;
1038 defm CMPGTrr : NVJrr_base<"cmp.gt", "CMPGT", 0b001, 0>, PredRel;
1039 defm CMPGTUrr : NVJrr_base<"cmp.gtu", "CMPGTU", 0b010, 0>, PredRel;
1040 defm CMPLTrr : NVJrr_base<"cmp.gt", "CMPLT", 0b011, 1>, PredRel;
1041 defm CMPLTUrr : NVJrr_base<"cmp.gtu", "CMPLTU", 0b100, 1>, PredRel;
1044 //===----------------------------------------------------------------------===//
1045 // multiclass/template class for the new-value compare jumps instruction
1046 // with a register and an unsigned immediate (U5) operand.
1047 //===----------------------------------------------------------------------===//
1049 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11 in
1050 class NVJri_template<string mnemonic, bits<3> majOp, bit isNegCond,
1053 (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
1054 "if ("#!if(isNegCond, "!","")#mnemonic#"($src1.new, #$src2)) jump:"
1055 #!if(isTaken, "t","nt")#" $offset",
1056 []>, Requires<[HasV4T]> {
1058 let isPredicatedFalse = isNegCond;
1059 let isBrTaken = !if(isTaken, "true", "false");
1065 let IClass = 0b0010;
1067 let Inst{25-23} = majOp;
1068 let Inst{22} = isNegCond;
1069 let Inst{18-16} = src1;
1070 let Inst{13} = isTaken;
1071 let Inst{12-8} = src2;
1072 let Inst{21-20} = offset{10-9};
1073 let Inst{7-1} = offset{8-2};
1076 multiclass NVJri_cond<string mnemonic, bits<3> majOp, bit isNegCond> {
1077 // Branch not taken:
1078 def _nt_V4: NVJri_template<mnemonic, majOp, isNegCond, 0>;
1080 def _t_V4: NVJri_template<mnemonic, majOp, isNegCond, 1>;
1083 multiclass NVJri_base<string mnemonic, string BaseOp, bits<3> majOp> {
1084 let BaseOpcode = BaseOp#_NVJri in {
1085 defm _t_Jumpnv : NVJri_cond<mnemonic, majOp, 0>; // True Cond
1086 defm _f_Jumpnv : NVJri_cond<mnemonic, majOp, 1>; // False cond
1090 // if ([!]cmp.eq(Ns.new,#U5)) jump:[n]t #r9:2
1091 // if ([!]cmp.gt(Ns.new,#U5)) jump:[n]t #r9:2
1092 // if ([!]cmp.gtu(Ns.new,#U5)) jump:[n]t #r9:2
1094 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
1095 Defs = [PC], neverHasSideEffects = 1, validSubTargets = HasV4SubT in {
1096 defm CMPEQri : NVJri_base<"cmp.eq", "CMPEQ", 0b000>, PredRel;
1097 defm CMPGTri : NVJri_base<"cmp.gt", "CMPGT", 0b001>, PredRel;
1098 defm CMPGTUri : NVJri_base<"cmp.gtu", "CMPGTU", 0b010>, PredRel;
1101 //===----------------------------------------------------------------------===//
1102 // multiclass/template class for the new-value compare jumps instruction
1103 // with a register and an hardcoded 0/-1 immediate value.
1104 //===----------------------------------------------------------------------===//
1106 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 11 in
1107 class NVJ_ConstImm_template<string mnemonic, bits<3> majOp, string ImmVal,
1108 bit isNegCond, bit isTaken>
1110 (ins IntRegs:$src1, brtarget:$offset),
1111 "if ("#!if(isNegCond, "!","")#mnemonic
1112 #"($src1.new, #"#ImmVal#")) jump:"
1113 #!if(isTaken, "t","nt")#" $offset",
1114 []>, Requires<[HasV4T]> {
1116 let isPredicatedFalse = isNegCond;
1117 let isBrTaken = !if(isTaken, "true", "false");
1121 let IClass = 0b0010;
1123 let Inst{25-23} = majOp;
1124 let Inst{22} = isNegCond;
1125 let Inst{18-16} = src1;
1126 let Inst{13} = isTaken;
1127 let Inst{21-20} = offset{10-9};
1128 let Inst{7-1} = offset{8-2};
1131 multiclass NVJ_ConstImm_cond<string mnemonic, bits<3> majOp, string ImmVal,
1133 // Branch not taken:
1134 def _nt_V4: NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 0>;
1136 def _t_V4: NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 1>;
1139 multiclass NVJ_ConstImm_base<string mnemonic, string BaseOp, bits<3> majOp,
1141 let BaseOpcode = BaseOp#_NVJ_ConstImm in {
1142 defm _t_Jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 0>; // True cond
1143 defm _f_Jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 1>; // False Cond
1147 // if ([!]tstbit(Ns.new,#0)) jump:[n]t #r9:2
1148 // if ([!]cmp.eq(Ns.new,#-1)) jump:[n]t #r9:2
1149 // if ([!]cmp.gt(Ns.new,#-1)) jump:[n]t #r9:2
1151 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator=1,
1152 Defs = [PC], neverHasSideEffects = 1 in {
1153 defm TSTBIT0 : NVJ_ConstImm_base<"tstbit", "TSTBIT", 0b011, "0">, PredRel;
1154 defm CMPEQn1 : NVJ_ConstImm_base<"cmp.eq", "CMPEQ", 0b100, "-1">, PredRel;
1155 defm CMPGTn1 : NVJ_ConstImm_base<"cmp.gt", "CMPGT", 0b101, "-1">, PredRel;
1158 //===----------------------------------------------------------------------===//
1160 //===----------------------------------------------------------------------===//
1162 // Add and accumulate.
1163 // Rd=add(Rs,add(Ru,#s6))
1164 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 6,
1165 validSubTargets = HasV4SubT in
1166 def ADDr_ADDri_V4 : MInst<(outs IntRegs:$dst),
1167 (ins IntRegs:$src1, IntRegs:$src2, s6Ext:$src3),
1168 "$dst = add($src1, add($src2, #$src3))",
1169 [(set (i32 IntRegs:$dst),
1170 (add (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),
1171 s6_16ExtPred:$src3)))]>,
1174 // Rd=add(Rs,sub(#s6,Ru))
1175 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 6,
1176 validSubTargets = HasV4SubT in
1177 def ADDr_SUBri_V4 : MInst<(outs IntRegs:$dst),
1178 (ins IntRegs:$src1, s6Ext:$src2, IntRegs:$src3),
1179 "$dst = add($src1, sub(#$src2, $src3))",
1180 [(set (i32 IntRegs:$dst),
1181 (add (i32 IntRegs:$src1), (sub s6_10ExtPred:$src2,
1182 (i32 IntRegs:$src3))))]>,
1185 // Generates the same instruction as ADDr_SUBri_V4 but matches different
1187 // Rd=add(Rs,sub(#s6,Ru))
1188 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 6,
1189 validSubTargets = HasV4SubT in
1190 def ADDri_SUBr_V4 : MInst<(outs IntRegs:$dst),
1191 (ins IntRegs:$src1, s6Ext:$src2, IntRegs:$src3),
1192 "$dst = add($src1, sub(#$src2, $src3))",
1193 [(set (i32 IntRegs:$dst),
1194 (sub (add (i32 IntRegs:$src1), s6_10ExtPred:$src2),
1195 (i32 IntRegs:$src3)))]>,
1199 // Add or subtract doublewords with carry.
1201 // Rdd=add(Rss,Rtt,Px):carry
1203 // Rdd=sub(Rss,Rtt,Px):carry
1206 // Logical doublewords.
1207 // Rdd=and(Rtt,~Rss)
1208 let validSubTargets = HasV4SubT in
1209 def ANDd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),
1210 (ins DoubleRegs:$src1, DoubleRegs:$src2),
1211 "$dst = and($src1, ~$src2)",
1212 [(set (i64 DoubleRegs:$dst), (and (i64 DoubleRegs:$src1),
1213 (not (i64 DoubleRegs:$src2))))]>,
1217 let validSubTargets = HasV4SubT in
1218 def ORd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),
1219 (ins DoubleRegs:$src1, DoubleRegs:$src2),
1220 "$dst = or($src1, ~$src2)",
1221 [(set (i64 DoubleRegs:$dst),
1222 (or (i64 DoubleRegs:$src1), (not (i64 DoubleRegs:$src2))))]>,
1226 // Logical-logical doublewords.
1227 // Rxx^=xor(Rss,Rtt)
1228 let validSubTargets = HasV4SubT in
1229 def XORd_XORdd: MInst_acc<(outs DoubleRegs:$dst),
1230 (ins DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
1231 "$dst ^= xor($src2, $src3)",
1232 [(set (i64 DoubleRegs:$dst),
1233 (xor (i64 DoubleRegs:$src1), (xor (i64 DoubleRegs:$src2),
1234 (i64 DoubleRegs:$src3))))],
1239 // Logical-logical words.
1240 // Rx=or(Ru,and(Rx,#s10))
1241 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 10,
1242 validSubTargets = HasV4SubT in
1243 def ORr_ANDri_V4 : MInst_acc<(outs IntRegs:$dst),
1244 (ins IntRegs:$src1, IntRegs: $src2, s10Ext:$src3),
1245 "$dst = or($src1, and($src2, #$src3))",
1246 [(set (i32 IntRegs:$dst),
1247 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1248 s10ExtPred:$src3)))],
1252 // Rx[&|^]=and(Rs,Rt)
1254 let validSubTargets = HasV4SubT in
1255 def ANDr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
1256 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1257 "$dst &= and($src2, $src3)",
1258 [(set (i32 IntRegs:$dst),
1259 (and (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1260 (i32 IntRegs:$src3))))],
1265 let validSubTargets = HasV4SubT, CextOpcode = "ORr_ANDr", InputType = "reg" in
1266 def ORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
1267 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1268 "$dst |= and($src2, $src3)",
1269 [(set (i32 IntRegs:$dst),
1270 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1271 (i32 IntRegs:$src3))))],
1273 Requires<[HasV4T]>, ImmRegRel;
1276 let validSubTargets = HasV4SubT in
1277 def XORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
1278 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1279 "$dst ^= and($src2, $src3)",
1280 [(set (i32 IntRegs:$dst),
1281 (xor (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1282 (i32 IntRegs:$src3))))],
1286 // Rx[&|^]=and(Rs,~Rt)
1288 let validSubTargets = HasV4SubT in
1289 def ANDr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
1290 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1291 "$dst &= and($src2, ~$src3)",
1292 [(set (i32 IntRegs:$dst),
1293 (and (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1294 (not (i32 IntRegs:$src3)))))],
1299 let validSubTargets = HasV4SubT in
1300 def ORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
1301 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1302 "$dst |= and($src2, ~$src3)",
1303 [(set (i32 IntRegs:$dst),
1304 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1305 (not (i32 IntRegs:$src3)))))],
1310 let validSubTargets = HasV4SubT in
1311 def XORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
1312 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1313 "$dst ^= and($src2, ~$src3)",
1314 [(set (i32 IntRegs:$dst),
1315 (xor (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1316 (not (i32 IntRegs:$src3)))))],
1320 // Rx[&|^]=or(Rs,Rt)
1322 let validSubTargets = HasV4SubT in
1323 def ANDr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1324 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1325 "$dst &= or($src2, $src3)",
1326 [(set (i32 IntRegs:$dst),
1327 (and (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
1328 (i32 IntRegs:$src3))))],
1333 let validSubTargets = HasV4SubT, CextOpcode = "ORr_ORr", InputType = "reg" in
1334 def ORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1335 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1336 "$dst |= or($src2, $src3)",
1337 [(set (i32 IntRegs:$dst),
1338 (or (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
1339 (i32 IntRegs:$src3))))],
1341 Requires<[HasV4T]>, ImmRegRel;
1344 let validSubTargets = HasV4SubT in
1345 def XORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1346 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1347 "$dst ^= or($src2, $src3)",
1348 [(set (i32 IntRegs:$dst),
1349 (xor (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
1350 (i32 IntRegs:$src3))))],
1354 // Rx[&|^]=xor(Rs,Rt)
1356 let validSubTargets = HasV4SubT in
1357 def ANDr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1358 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1359 "$dst &= xor($src2, $src3)",
1360 [(set (i32 IntRegs:$dst),
1361 (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
1362 (i32 IntRegs:$src3))))],
1367 let validSubTargets = HasV4SubT in
1368 def ORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1369 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1370 "$dst |= xor($src2, $src3)",
1371 [(set (i32 IntRegs:$dst),
1372 (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
1373 (i32 IntRegs:$src3))))],
1378 let validSubTargets = HasV4SubT in
1379 def XORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1380 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1381 "$dst ^= xor($src2, $src3)",
1382 [(set (i32 IntRegs:$dst),
1383 (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
1384 (i32 IntRegs:$src3))))],
1389 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 10,
1390 validSubTargets = HasV4SubT, CextOpcode = "ORr_ANDr", InputType = "imm" in
1391 def ORr_ANDri2_V4 : MInst_acc<(outs IntRegs:$dst),
1392 (ins IntRegs:$src1, IntRegs: $src2, s10Ext:$src3),
1393 "$dst |= and($src2, #$src3)",
1394 [(set (i32 IntRegs:$dst),
1395 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1396 s10ExtPred:$src3)))],
1398 Requires<[HasV4T]>, ImmRegRel;
1401 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 10,
1402 validSubTargets = HasV4SubT, CextOpcode = "ORr_ORr", InputType = "imm" in
1403 def ORr_ORri_V4 : MInst_acc<(outs IntRegs:$dst),
1404 (ins IntRegs:$src1, IntRegs: $src2, s10Ext:$src3),
1405 "$dst |= or($src2, #$src3)",
1406 [(set (i32 IntRegs:$dst),
1407 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1408 s10ExtPred:$src3)))],
1410 Requires<[HasV4T]>, ImmRegRel;
1414 // Rd=modwrap(Rs,Rt)
1416 // Rd=cround(Rs,#u5)
1418 // Rd=round(Rs,#u5)[:sat]
1419 // Rd=round(Rs,Rt)[:sat]
1420 // Vector reduce add unsigned halfwords
1421 // Rd=vraddh(Rss,Rtt)
1423 // Rdd=vaddb(Rss,Rtt)
1424 // Vector conditional negate
1425 // Rdd=vcnegh(Rss,Rt)
1426 // Rxx+=vrcnegh(Rss,Rt)
1427 // Vector maximum bytes
1428 // Rdd=vmaxb(Rtt,Rss)
1429 // Vector reduce maximum halfwords
1430 // Rxx=vrmaxh(Rss,Ru)
1431 // Rxx=vrmaxuh(Rss,Ru)
1432 // Vector reduce maximum words
1433 // Rxx=vrmaxuw(Rss,Ru)
1434 // Rxx=vrmaxw(Rss,Ru)
1435 // Vector minimum bytes
1436 // Rdd=vminb(Rtt,Rss)
1437 // Vector reduce minimum halfwords
1438 // Rxx=vrminh(Rss,Ru)
1439 // Rxx=vrminuh(Rss,Ru)
1440 // Vector reduce minimum words
1441 // Rxx=vrminuw(Rss,Ru)
1442 // Rxx=vrminw(Rss,Ru)
1443 // Vector subtract bytes
1444 // Rdd=vsubb(Rss,Rtt)
1446 //===----------------------------------------------------------------------===//
1448 //===----------------------------------------------------------------------===//
1451 //===----------------------------------------------------------------------===//
1453 //===----------------------------------------------------------------------===//
1455 // Multiply and user lower result.
1456 // Rd=add(#u6,mpyi(Rs,#U6))
1457 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 6,
1458 validSubTargets = HasV4SubT in
1459 def ADDi_MPYri_V4 : MInst<(outs IntRegs:$dst),
1460 (ins u6Ext:$src1, IntRegs:$src2, u6Imm:$src3),
1461 "$dst = add(#$src1, mpyi($src2, #$src3))",
1462 [(set (i32 IntRegs:$dst),
1463 (add (mul (i32 IntRegs:$src2), u6ImmPred:$src3),
1464 u6ExtPred:$src1))]>,
1467 // Rd=add(##,mpyi(Rs,#U6))
1468 def : Pat <(add (mul (i32 IntRegs:$src2), u6ImmPred:$src3),
1469 (HexagonCONST32 tglobaladdr:$src1)),
1470 (i32 (ADDi_MPYri_V4 tglobaladdr:$src1, IntRegs:$src2,
1473 // Rd=add(#u6,mpyi(Rs,Rt))
1474 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 6,
1475 validSubTargets = HasV4SubT, InputType = "imm", CextOpcode = "ADD_MPY" in
1476 def ADDi_MPYrr_V4 : MInst<(outs IntRegs:$dst),
1477 (ins u6Ext:$src1, IntRegs:$src2, IntRegs:$src3),
1478 "$dst = add(#$src1, mpyi($src2, $src3))",
1479 [(set (i32 IntRegs:$dst),
1480 (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
1481 u6ExtPred:$src1))]>,
1482 Requires<[HasV4T]>, ImmRegRel;
1484 // Rd=add(##,mpyi(Rs,Rt))
1485 def : Pat <(add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
1486 (HexagonCONST32 tglobaladdr:$src1)),
1487 (i32 (ADDi_MPYrr_V4 tglobaladdr:$src1, IntRegs:$src2,
1490 // Rd=add(Ru,mpyi(#u6:2,Rs))
1491 let validSubTargets = HasV4SubT in
1492 def ADDr_MPYir_V4 : MInst<(outs IntRegs:$dst),
1493 (ins IntRegs:$src1, u6Imm:$src2, IntRegs:$src3),
1494 "$dst = add($src1, mpyi(#$src2, $src3))",
1495 [(set (i32 IntRegs:$dst),
1496 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src3),
1497 u6_2ImmPred:$src2)))]>,
1500 // Rd=add(Ru,mpyi(Rs,#u6))
1501 let isExtendable = 1, opExtendable = 3, isExtentSigned = 0, opExtentBits = 6,
1502 validSubTargets = HasV4SubT, InputType = "imm", CextOpcode = "ADD_MPY" in
1503 def ADDr_MPYri_V4 : MInst<(outs IntRegs:$dst),
1504 (ins IntRegs:$src1, IntRegs:$src2, u6Ext:$src3),
1505 "$dst = add($src1, mpyi($src2, #$src3))",
1506 [(set (i32 IntRegs:$dst),
1507 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
1508 u6ExtPred:$src3)))]>,
1509 Requires<[HasV4T]>, ImmRegRel;
1511 // Rx=add(Ru,mpyi(Rx,Rs))
1512 let validSubTargets = HasV4SubT, InputType = "reg", CextOpcode = "ADD_MPY" in
1513 def ADDr_MPYrr_V4 : MInst_acc<(outs IntRegs:$dst),
1514 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1515 "$dst = add($src1, mpyi($src2, $src3))",
1516 [(set (i32 IntRegs:$dst),
1517 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
1518 (i32 IntRegs:$src3))))],
1520 Requires<[HasV4T]>, ImmRegRel;
1523 // Polynomial multiply words
1525 // Rxx^=pmpyw(Rs,Rt)
1527 // Vector reduce multiply word by signed half (32x16)
1528 // Rdd=vrmpyweh(Rss,Rtt)[:<<1]
1529 // Rdd=vrmpywoh(Rss,Rtt)[:<<1]
1530 // Rxx+=vrmpyweh(Rss,Rtt)[:<<1]
1531 // Rxx+=vrmpywoh(Rss,Rtt)[:<<1]
1533 // Multiply and use upper result
1534 // Rd=mpy(Rs,Rt.H):<<1:sat
1535 // Rd=mpy(Rs,Rt.L):<<1:sat
1536 // Rd=mpy(Rs,Rt):<<1
1537 // Rd=mpy(Rs,Rt):<<1:sat
1539 // Rx+=mpy(Rs,Rt):<<1:sat
1540 // Rx-=mpy(Rs,Rt):<<1:sat
1542 // Vector multiply bytes
1543 // Rdd=vmpybsu(Rs,Rt)
1544 // Rdd=vmpybu(Rs,Rt)
1545 // Rxx+=vmpybsu(Rs,Rt)
1546 // Rxx+=vmpybu(Rs,Rt)
1548 // Vector polynomial multiply halfwords
1549 // Rdd=vpmpyh(Rs,Rt)
1550 // Rxx^=vpmpyh(Rs,Rt)
1552 //===----------------------------------------------------------------------===//
1554 //===----------------------------------------------------------------------===//
1557 //===----------------------------------------------------------------------===//
1559 //===----------------------------------------------------------------------===//
1561 // Shift by immediate and accumulate.
1562 // Rx=add(#u8,asl(Rx,#U5))
1563 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1564 validSubTargets = HasV4SubT in
1565 def ADDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
1566 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1567 "$dst = add(#$src1, asl($src2, #$src3))",
1568 [(set (i32 IntRegs:$dst),
1569 (add (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
1574 // Rx=add(#u8,lsr(Rx,#U5))
1575 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1576 validSubTargets = HasV4SubT in
1577 def ADDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
1578 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1579 "$dst = add(#$src1, lsr($src2, #$src3))",
1580 [(set (i32 IntRegs:$dst),
1581 (add (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
1586 // Rx=sub(#u8,asl(Rx,#U5))
1587 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1588 validSubTargets = HasV4SubT in
1589 def SUBi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
1590 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1591 "$dst = sub(#$src1, asl($src2, #$src3))",
1592 [(set (i32 IntRegs:$dst),
1593 (sub (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
1598 // Rx=sub(#u8,lsr(Rx,#U5))
1599 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1600 validSubTargets = HasV4SubT in
1601 def SUBi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
1602 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1603 "$dst = sub(#$src1, lsr($src2, #$src3))",
1604 [(set (i32 IntRegs:$dst),
1605 (sub (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
1611 //Shift by immediate and logical.
1612 //Rx=and(#u8,asl(Rx,#U5))
1613 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1614 validSubTargets = HasV4SubT in
1615 def ANDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
1616 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1617 "$dst = and(#$src1, asl($src2, #$src3))",
1618 [(set (i32 IntRegs:$dst),
1619 (and (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
1624 //Rx=and(#u8,lsr(Rx,#U5))
1625 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1626 validSubTargets = HasV4SubT in
1627 def ANDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
1628 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1629 "$dst = and(#$src1, lsr($src2, #$src3))",
1630 [(set (i32 IntRegs:$dst),
1631 (and (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
1636 //Rx=or(#u8,asl(Rx,#U5))
1637 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1638 AddedComplexity = 30, validSubTargets = HasV4SubT in
1639 def ORi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
1640 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1641 "$dst = or(#$src1, asl($src2, #$src3))",
1642 [(set (i32 IntRegs:$dst),
1643 (or (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
1648 //Rx=or(#u8,lsr(Rx,#U5))
1649 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1650 AddedComplexity = 30, validSubTargets = HasV4SubT in
1651 def ORi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
1652 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1653 "$dst = or(#$src1, lsr($src2, #$src3))",
1654 [(set (i32 IntRegs:$dst),
1655 (or (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
1661 //Shift by register.
1663 let validSubTargets = HasV4SubT in {
1664 def LSLi_V4 : MInst<(outs IntRegs:$dst), (ins s6Imm:$src1, IntRegs:$src2),
1665 "$dst = lsl(#$src1, $src2)",
1666 [(set (i32 IntRegs:$dst), (shl s6ImmPred:$src1,
1667 (i32 IntRegs:$src2)))]>,
1671 //Shift by register and logical.
1673 def ASLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
1674 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
1675 "$dst ^= asl($src2, $src3)",
1676 [(set (i64 DoubleRegs:$dst),
1677 (xor (i64 DoubleRegs:$src1), (shl (i64 DoubleRegs:$src2),
1678 (i32 IntRegs:$src3))))],
1683 def ASRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
1684 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
1685 "$dst ^= asr($src2, $src3)",
1686 [(set (i64 DoubleRegs:$dst),
1687 (xor (i64 DoubleRegs:$src1), (sra (i64 DoubleRegs:$src2),
1688 (i32 IntRegs:$src3))))],
1693 def LSLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
1694 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
1695 "$dst ^= lsl($src2, $src3)",
1696 [(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1),
1697 (shl (i64 DoubleRegs:$src2),
1698 (i32 IntRegs:$src3))))],
1703 def LSRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
1704 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
1705 "$dst ^= lsr($src2, $src3)",
1706 [(set (i64 DoubleRegs:$dst),
1707 (xor (i64 DoubleRegs:$src1), (srl (i64 DoubleRegs:$src2),
1708 (i32 IntRegs:$src3))))],
1713 //===----------------------------------------------------------------------===//
1715 //===----------------------------------------------------------------------===//
1717 //===----------------------------------------------------------------------===//
1718 // MEMOP: Word, Half, Byte
1719 //===----------------------------------------------------------------------===//
1721 def MEMOPIMM : SDNodeXForm<imm, [{
1722 // Call the transformation function XformM5ToU5Imm to get the negative
1723 // immediate's positive counterpart.
1724 int32_t imm = N->getSExtValue();
1725 return XformM5ToU5Imm(imm);
1728 def MEMOPIMM_HALF : SDNodeXForm<imm, [{
1729 // -1 .. -31 represented as 65535..65515
1730 // assigning to a short restores our desired signed value.
1731 // Call the transformation function XformM5ToU5Imm to get the negative
1732 // immediate's positive counterpart.
1733 int16_t imm = N->getSExtValue();
1734 return XformM5ToU5Imm(imm);
1737 def MEMOPIMM_BYTE : SDNodeXForm<imm, [{
1738 // -1 .. -31 represented as 255..235
1739 // assigning to a char restores our desired signed value.
1740 // Call the transformation function XformM5ToU5Imm to get the negative
1741 // immediate's positive counterpart.
1742 int8_t imm = N->getSExtValue();
1743 return XformM5ToU5Imm(imm);
1746 def SETMEMIMM : SDNodeXForm<imm, [{
1747 // Return the bit position we will set [0-31].
1749 int32_t imm = N->getSExtValue();
1750 return XformMskToBitPosU5Imm(imm);
1753 def CLRMEMIMM : SDNodeXForm<imm, [{
1754 // Return the bit position we will clear [0-31].
1756 // we bit negate the value first
1757 int32_t imm = ~(N->getSExtValue());
1758 return XformMskToBitPosU5Imm(imm);
1761 def SETMEMIMM_SHORT : SDNodeXForm<imm, [{
1762 // Return the bit position we will set [0-15].
1764 int16_t imm = N->getSExtValue();
1765 return XformMskToBitPosU4Imm(imm);
1768 def CLRMEMIMM_SHORT : SDNodeXForm<imm, [{
1769 // Return the bit position we will clear [0-15].
1771 // we bit negate the value first
1772 int16_t imm = ~(N->getSExtValue());
1773 return XformMskToBitPosU4Imm(imm);
1776 def SETMEMIMM_BYTE : SDNodeXForm<imm, [{
1777 // Return the bit position we will set [0-7].
1779 int8_t imm = N->getSExtValue();
1780 return XformMskToBitPosU3Imm(imm);
1783 def CLRMEMIMM_BYTE : SDNodeXForm<imm, [{
1784 // Return the bit position we will clear [0-7].
1786 // we bit negate the value first
1787 int8_t imm = ~(N->getSExtValue());
1788 return XformMskToBitPosU3Imm(imm);
1791 //===----------------------------------------------------------------------===//
1792 // Template class for MemOp instructions with the register value.
1793 //===----------------------------------------------------------------------===//
1794 class MemOp_rr_base <string opc, bits<2> opcBits, Operand ImmOp,
1795 string memOp, bits<2> memOpBits> :
1797 (ins IntRegs:$base, ImmOp:$offset, IntRegs:$delta),
1798 opc#"($base+#$offset)"#memOp#"$delta",
1800 Requires<[HasV4T, UseMEMOP]> {
1805 bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
1807 let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
1808 !if (!eq(opcBits, 0b01), offset{6-1},
1809 !if (!eq(opcBits, 0b10), offset{7-2},0)));
1811 let IClass = 0b0011;
1812 let Inst{27-24} = 0b1110;
1813 let Inst{22-21} = opcBits;
1814 let Inst{20-16} = base;
1816 let Inst{12-7} = offsetBits;
1817 let Inst{6-5} = memOpBits;
1818 let Inst{4-0} = delta;
1821 //===----------------------------------------------------------------------===//
1822 // Template class for MemOp instructions with the immediate value.
1823 //===----------------------------------------------------------------------===//
1824 class MemOp_ri_base <string opc, bits<2> opcBits, Operand ImmOp,
1825 string memOp, bits<2> memOpBits> :
1827 (ins IntRegs:$base, ImmOp:$offset, u5Imm:$delta),
1828 opc#"($base+#$offset)"#memOp#"#$delta"
1829 #!if(memOpBits{1},")", ""), // clrbit, setbit - include ')'
1831 Requires<[HasV4T, UseMEMOP]> {
1836 bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
1838 let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
1839 !if (!eq(opcBits, 0b01), offset{6-1},
1840 !if (!eq(opcBits, 0b10), offset{7-2},0)));
1842 let IClass = 0b0011;
1843 let Inst{27-24} = 0b1111;
1844 let Inst{22-21} = opcBits;
1845 let Inst{20-16} = base;
1847 let Inst{12-7} = offsetBits;
1848 let Inst{6-5} = memOpBits;
1849 let Inst{4-0} = delta;
1852 // multiclass to define MemOp instructions with register operand.
1853 multiclass MemOp_rr<string opc, bits<2> opcBits, Operand ImmOp> {
1854 def _ADD#NAME#_V4 : MemOp_rr_base <opc, opcBits, ImmOp, " += ", 0b00>; // add
1855 def _SUB#NAME#_V4 : MemOp_rr_base <opc, opcBits, ImmOp, " -= ", 0b01>; // sub
1856 def _AND#NAME#_V4 : MemOp_rr_base <opc, opcBits, ImmOp, " &= ", 0b10>; // and
1857 def _OR#NAME#_V4 : MemOp_rr_base <opc, opcBits, ImmOp, " |= ", 0b11>; // or
1860 // multiclass to define MemOp instructions with immediate Operand.
1861 multiclass MemOp_ri<string opc, bits<2> opcBits, Operand ImmOp> {
1862 def _ADD#NAME#_V4 : MemOp_ri_base <opc, opcBits, ImmOp, " += ", 0b00 >;
1863 def _SUB#NAME#_V4 : MemOp_ri_base <opc, opcBits, ImmOp, " -= ", 0b01 >;
1864 def _CLRBIT#NAME#_V4 : MemOp_ri_base<opc, opcBits, ImmOp, " =clrbit(", 0b10>;
1865 def _SETBIT#NAME#_V4 : MemOp_ri_base<opc, opcBits, ImmOp, " =setbit(", 0b11>;
1868 multiclass MemOp_base <string opc, bits<2> opcBits, Operand ImmOp> {
1869 defm r : MemOp_rr <opc, opcBits, ImmOp>;
1870 defm i : MemOp_ri <opc, opcBits, ImmOp>;
1873 // Define MemOp instructions.
1874 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0,
1875 validSubTargets =HasV4SubT in {
1876 let opExtentBits = 6, accessSize = ByteAccess in
1877 defm MemOPb : MemOp_base <"memb", 0b00, u6_0Ext>;
1879 let opExtentBits = 7, accessSize = HalfWordAccess in
1880 defm MemOPh : MemOp_base <"memh", 0b01, u6_1Ext>;
1882 let opExtentBits = 8, accessSize = WordAccess in
1883 defm MemOPw : MemOp_base <"memw", 0b10, u6_2Ext>;
1886 //===----------------------------------------------------------------------===//
1887 // Multiclass to define 'Def Pats' for ALU operations on the memory
1888 // Here value used for the ALU operation is an immediate value.
1889 // mem[bh](Rs+#0) += #U5
1890 // mem[bh](Rs+#u6) += #U5
1891 //===----------------------------------------------------------------------===//
1893 multiclass MemOpi_u5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf ExtPred,
1894 InstHexagon MI, SDNode OpNode> {
1895 let AddedComplexity = 180 in
1896 def : Pat < (stOp (OpNode (ldOp IntRegs:$addr), u5ImmPred:$addend),
1898 (MI IntRegs:$addr, #0, u5ImmPred:$addend )>;
1900 let AddedComplexity = 190 in
1901 def : Pat <(stOp (OpNode (ldOp (add IntRegs:$base, ExtPred:$offset)),
1903 (add IntRegs:$base, ExtPred:$offset)),
1904 (MI IntRegs:$base, ExtPred:$offset, u5ImmPred:$addend)>;
1907 multiclass MemOpi_u5ALUOp<PatFrag ldOp, PatFrag stOp, PatLeaf ExtPred,
1908 InstHexagon addMI, InstHexagon subMI> {
1909 defm : MemOpi_u5Pats<ldOp, stOp, ExtPred, addMI, add>;
1910 defm : MemOpi_u5Pats<ldOp, stOp, ExtPred, subMI, sub>;
1913 multiclass MemOpi_u5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
1915 defm : MemOpi_u5ALUOp <ldOpHalf, truncstorei16, u6_1ExtPred,
1916 MemOPh_ADDi_V4, MemOPh_SUBi_V4>;
1918 defm : MemOpi_u5ALUOp <ldOpByte, truncstorei8, u6ExtPred,
1919 MemOPb_ADDi_V4, MemOPb_SUBi_V4>;
1922 let Predicates = [HasV4T, UseMEMOP] in {
1923 defm : MemOpi_u5ExtType<zextloadi8, zextloadi16>; // zero extend
1924 defm : MemOpi_u5ExtType<sextloadi8, sextloadi16>; // sign extend
1925 defm : MemOpi_u5ExtType<extloadi8, extloadi16>; // any extend
1928 defm : MemOpi_u5ALUOp <load, store, u6_2ExtPred, MemOPw_ADDi_V4,
1932 //===----------------------------------------------------------------------===//
1933 // multiclass to define 'Def Pats' for ALU operations on the memory.
1934 // Here value used for the ALU operation is a negative value.
1935 // mem[bh](Rs+#0) += #m5
1936 // mem[bh](Rs+#u6) += #m5
1937 //===----------------------------------------------------------------------===//
1939 multiclass MemOpi_m5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf extPred,
1940 PatLeaf immPred, ComplexPattern addrPred,
1941 SDNodeXForm xformFunc, InstHexagon MI> {
1942 let AddedComplexity = 190 in
1943 def : Pat <(stOp (add (ldOp IntRegs:$addr), immPred:$subend),
1945 (MI IntRegs:$addr, #0, (xformFunc immPred:$subend) )>;
1947 let AddedComplexity = 195 in
1948 def : Pat<(stOp (add (ldOp (add IntRegs:$base, extPred:$offset)),
1950 (add IntRegs:$base, extPred:$offset)),
1951 (MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$subend))>;
1954 multiclass MemOpi_m5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
1956 defm : MemOpi_m5Pats <ldOpHalf, truncstorei16, u6_1ExtPred, m5HImmPred,
1957 ADDRriU6_1, MEMOPIMM_HALF, MemOPh_SUBi_V4>;
1959 defm : MemOpi_m5Pats <ldOpByte, truncstorei8, u6ExtPred, m5BImmPred,
1960 ADDRriU6_0, MEMOPIMM_BYTE, MemOPb_SUBi_V4>;
1963 let Predicates = [HasV4T, UseMEMOP] in {
1964 defm : MemOpi_m5ExtType<zextloadi8, zextloadi16>; // zero extend
1965 defm : MemOpi_m5ExtType<sextloadi8, sextloadi16>; // sign extend
1966 defm : MemOpi_m5ExtType<extloadi8, extloadi16>; // any extend
1969 defm : MemOpi_m5Pats <load, store, u6_2ExtPred, m5ImmPred,
1970 ADDRriU6_2, MEMOPIMM, MemOPw_SUBi_V4>;
1973 //===----------------------------------------------------------------------===//
1974 // Multiclass to define 'def Pats' for bit operations on the memory.
1975 // mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
1976 // mem[bhw](Rs+#u6) = [clrbit|setbit](#U5)
1977 //===----------------------------------------------------------------------===//
1979 multiclass MemOpi_bitPats <PatFrag ldOp, PatFrag stOp, PatLeaf immPred,
1980 PatLeaf extPred, ComplexPattern addrPred,
1981 SDNodeXForm xformFunc, InstHexagon MI, SDNode OpNode> {
1983 // mem[bhw](Rs+#u6:[012]) = [clrbit|setbit](#U5)
1984 let AddedComplexity = 250 in
1985 def : Pat<(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
1987 (add IntRegs:$base, extPred:$offset)),
1988 (MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$bitend))>;
1990 // mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
1991 let AddedComplexity = 225 in
1992 def : Pat <(stOp (OpNode (ldOp addrPred:$addr), immPred:$bitend),
1994 (MI IntRegs:$addr, #0, (xformFunc immPred:$bitend))>;
1997 multiclass MemOpi_bitExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
1999 defm : MemOpi_bitPats<ldOpByte, truncstorei8, Clr3ImmPred, u6ExtPred,
2000 ADDRriU6_0, CLRMEMIMM_BYTE, MemOPb_CLRBITi_V4, and>;
2002 defm : MemOpi_bitPats<ldOpByte, truncstorei8, Set3ImmPred, u6ExtPred,
2003 ADDRriU6_0, SETMEMIMM_BYTE, MemOPb_SETBITi_V4, or>;
2004 // Half Word - clrbit
2005 defm : MemOpi_bitPats<ldOpHalf, truncstorei16, Clr4ImmPred, u6_1ExtPred,
2006 ADDRriU6_1, CLRMEMIMM_SHORT, MemOPh_CLRBITi_V4, and>;
2007 // Half Word - setbit
2008 defm : MemOpi_bitPats<ldOpHalf, truncstorei16, Set4ImmPred, u6_1ExtPred,
2009 ADDRriU6_1, SETMEMIMM_SHORT, MemOPh_SETBITi_V4, or>;
2012 let Predicates = [HasV4T, UseMEMOP] in {
2013 // mem[bh](Rs+#0) = [clrbit|setbit](#U5)
2014 // mem[bh](Rs+#u6:[01]) = [clrbit|setbit](#U5)
2015 defm : MemOpi_bitExtType<zextloadi8, zextloadi16>; // zero extend
2016 defm : MemOpi_bitExtType<sextloadi8, sextloadi16>; // sign extend
2017 defm : MemOpi_bitExtType<extloadi8, extloadi16>; // any extend
2019 // memw(Rs+#0) = [clrbit|setbit](#U5)
2020 // memw(Rs+#u6:2) = [clrbit|setbit](#U5)
2021 defm : MemOpi_bitPats<load, store, Clr5ImmPred, u6_2ExtPred, ADDRriU6_2,
2022 CLRMEMIMM, MemOPw_CLRBITi_V4, and>;
2023 defm : MemOpi_bitPats<load, store, Set5ImmPred, u6_2ExtPred, ADDRriU6_2,
2024 SETMEMIMM, MemOPw_SETBITi_V4, or>;
2027 //===----------------------------------------------------------------------===//
2028 // Multiclass to define 'def Pats' for ALU operations on the memory
2029 // where addend is a register.
2030 // mem[bhw](Rs+#0) [+-&|]= Rt
2031 // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
2032 //===----------------------------------------------------------------------===//
2034 multiclass MemOpr_Pats <PatFrag ldOp, PatFrag stOp, ComplexPattern addrPred,
2035 PatLeaf extPred, InstHexagon MI, SDNode OpNode> {
2036 let AddedComplexity = 141 in
2037 // mem[bhw](Rs+#0) [+-&|]= Rt
2038 def : Pat <(stOp (OpNode (ldOp addrPred:$addr), (i32 IntRegs:$addend)),
2040 (MI IntRegs:$addr, #0, (i32 IntRegs:$addend) )>;
2042 // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
2043 let AddedComplexity = 150 in
2044 def : Pat <(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
2045 (i32 IntRegs:$orend)),
2046 (add IntRegs:$base, extPred:$offset)),
2047 (MI IntRegs:$base, extPred:$offset, (i32 IntRegs:$orend) )>;
2050 multiclass MemOPr_ALUOp<PatFrag ldOp, PatFrag stOp,
2051 ComplexPattern addrPred, PatLeaf extPred,
2052 InstHexagon addMI, InstHexagon subMI,
2053 InstHexagon andMI, InstHexagon orMI > {
2055 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, addMI, add>;
2056 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, subMI, sub>;
2057 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, andMI, and>;
2058 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, orMI, or>;
2061 multiclass MemOPr_ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2063 defm : MemOPr_ALUOp <ldOpHalf, truncstorei16, ADDRriU6_1, u6_1ExtPred,
2064 MemOPh_ADDr_V4, MemOPh_SUBr_V4,
2065 MemOPh_ANDr_V4, MemOPh_ORr_V4>;
2067 defm : MemOPr_ALUOp <ldOpByte, truncstorei8, ADDRriU6_0, u6ExtPred,
2068 MemOPb_ADDr_V4, MemOPb_SUBr_V4,
2069 MemOPb_ANDr_V4, MemOPb_ORr_V4>;
2072 // Define 'def Pats' for MemOps with register addend.
2073 let Predicates = [HasV4T, UseMEMOP] in {
2075 defm : MemOPr_ExtType<zextloadi8, zextloadi16>; // zero extend
2076 defm : MemOPr_ExtType<sextloadi8, sextloadi16>; // sign extend
2077 defm : MemOPr_ExtType<extloadi8, extloadi16>; // any extend
2079 defm : MemOPr_ALUOp <load, store, ADDRriU6_2, u6_2ExtPred, MemOPw_ADDr_V4,
2080 MemOPw_SUBr_V4, MemOPw_ANDr_V4, MemOPw_ORr_V4 >;
2083 //===----------------------------------------------------------------------===//
2085 //===----------------------------------------------------------------------===//
2087 // Hexagon V4 only supports these flavors of byte/half compare instructions:
2088 // EQ/GT/GTU. Other flavors like GE/GEU/LT/LTU/LE/LEU are not supported by
2089 // hardware. However, compiler can still implement these patterns through
2090 // appropriate patterns combinations based on current implemented patterns.
2091 // The implemented patterns are: EQ/GT/GTU.
2092 // Missing patterns are: GE/GEU/LT/LTU/LE/LEU.
2094 // Following instruction is not being extended as it results into the
2095 // incorrect code for negative numbers.
2096 // Pd=cmpb.eq(Rs,#u8)
2099 let isCompare = 1, validSubTargets = HasV4SubT in
2100 def CMPnotEQ_rr : ALU32_rr<(outs PredRegs:$dst),
2101 (ins IntRegs:$src1, IntRegs:$src2),
2102 "$dst = !cmp.eq($src1, $src2)",
2103 [(set (i1 PredRegs:$dst),
2104 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2)))]>,
2107 // p=!cmp.eq(r1,#s10)
2108 let isCompare = 1, validSubTargets = HasV4SubT in
2109 def CMPnotEQ_ri : ALU32_ri<(outs PredRegs:$dst),
2110 (ins IntRegs:$src1, s10Ext:$src2),
2111 "$dst = !cmp.eq($src1, #$src2)",
2112 [(set (i1 PredRegs:$dst),
2113 (setne (i32 IntRegs:$src1), s10ImmPred:$src2))]>,
2117 let isCompare = 1, validSubTargets = HasV4SubT in
2118 def CMPnotGT_rr : ALU32_rr<(outs PredRegs:$dst),
2119 (ins IntRegs:$src1, IntRegs:$src2),
2120 "$dst = !cmp.gt($src1, $src2)",
2121 [(set (i1 PredRegs:$dst),
2122 (not (setgt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>,
2125 // p=!cmp.gt(r1,#s10)
2126 let isCompare = 1, validSubTargets = HasV4SubT in
2127 def CMPnotGT_ri : ALU32_ri<(outs PredRegs:$dst),
2128 (ins IntRegs:$src1, s10Ext:$src2),
2129 "$dst = !cmp.gt($src1, #$src2)",
2130 [(set (i1 PredRegs:$dst),
2131 (not (setgt (i32 IntRegs:$src1), s10ImmPred:$src2)))]>,
2134 // p=!cmp.gtu(r1,r2)
2135 let isCompare = 1, validSubTargets = HasV4SubT in
2136 def CMPnotGTU_rr : ALU32_rr<(outs PredRegs:$dst),
2137 (ins IntRegs:$src1, IntRegs:$src2),
2138 "$dst = !cmp.gtu($src1, $src2)",
2139 [(set (i1 PredRegs:$dst),
2140 (not (setugt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>,
2143 // p=!cmp.gtu(r1,#u9)
2144 let isCompare = 1, validSubTargets = HasV4SubT in
2145 def CMPnotGTU_ri : ALU32_ri<(outs PredRegs:$dst),
2146 (ins IntRegs:$src1, u9Ext:$src2),
2147 "$dst = !cmp.gtu($src1, #$src2)",
2148 [(set (i1 PredRegs:$dst),
2149 (not (setugt (i32 IntRegs:$src1), u9ImmPred:$src2)))]>,
2152 let isCompare = 1, validSubTargets = HasV4SubT in
2153 def CMPbEQri_V4 : MInst<(outs PredRegs:$dst),
2154 (ins IntRegs:$src1, u8Imm:$src2),
2155 "$dst = cmpb.eq($src1, #$src2)",
2156 [(set (i1 PredRegs:$dst),
2157 (seteq (and (i32 IntRegs:$src1), 255), u8ImmPred:$src2))]>,
2160 def : Pat <(brcond (i1 (setne (and (i32 IntRegs:$src1), 255), u8ImmPred:$src2)),
2162 (JMP_f (CMPbEQri_V4 (i32 IntRegs:$src1), u8ImmPred:$src2),
2166 // Pd=cmpb.eq(Rs,Rt)
2167 let isCompare = 1, validSubTargets = HasV4SubT in
2168 def CMPbEQrr_ubub_V4 : MInst<(outs PredRegs:$dst),
2169 (ins IntRegs:$src1, IntRegs:$src2),
2170 "$dst = cmpb.eq($src1, $src2)",
2171 [(set (i1 PredRegs:$dst),
2172 (seteq (and (xor (i32 IntRegs:$src1),
2173 (i32 IntRegs:$src2)), 255), 0))]>,
2176 // Pd=cmpb.eq(Rs,Rt)
2177 let isCompare = 1, validSubTargets = HasV4SubT in
2178 def CMPbEQrr_sbsb_V4 : MInst<(outs PredRegs:$dst),
2179 (ins IntRegs:$src1, IntRegs:$src2),
2180 "$dst = cmpb.eq($src1, $src2)",
2181 [(set (i1 PredRegs:$dst),
2182 (seteq (shl (i32 IntRegs:$src1), (i32 24)),
2183 (shl (i32 IntRegs:$src2), (i32 24))))]>,
2186 // Pd=cmpb.gt(Rs,Rt)
2187 let isCompare = 1, validSubTargets = HasV4SubT in
2188 def CMPbGTrr_V4 : MInst<(outs PredRegs:$dst),
2189 (ins IntRegs:$src1, IntRegs:$src2),
2190 "$dst = cmpb.gt($src1, $src2)",
2191 [(set (i1 PredRegs:$dst),
2192 (setgt (shl (i32 IntRegs:$src1), (i32 24)),
2193 (shl (i32 IntRegs:$src2), (i32 24))))]>,
2196 // Pd=cmpb.gtu(Rs,#u7)
2197 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 7,
2198 isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPbGTU", InputType = "imm" in
2199 def CMPbGTUri_V4 : MInst<(outs PredRegs:$dst),
2200 (ins IntRegs:$src1, u7Ext:$src2),
2201 "$dst = cmpb.gtu($src1, #$src2)",
2202 [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),
2203 u7ExtPred:$src2))]>,
2204 Requires<[HasV4T]>, ImmRegRel;
2206 // SDNode for converting immediate C to C-1.
2207 def DEC_CONST_BYTE : SDNodeXForm<imm, [{
2208 // Return the byte immediate const-1 as an SDNode.
2209 int32_t imm = N->getSExtValue();
2210 return XformU7ToU7M1Imm(imm);
2214 // zext( seteq ( and(Rs, 255), u8))
2216 // Pd=cmpb.eq(Rs, #u8)
2217 // if (Pd.new) Rd=#1
2218 // if (!Pd.new) Rd=#0
2219 def : Pat <(i32 (zext (i1 (seteq (i32 (and (i32 IntRegs:$Rs), 255)),
2221 (i32 (TFR_condset_ii (i1 (CMPbEQri_V4 (i32 IntRegs:$Rs),
2227 // zext( setne ( and(Rs, 255), u8))
2229 // Pd=cmpb.eq(Rs, #u8)
2230 // if (Pd.new) Rd=#0
2231 // if (!Pd.new) Rd=#1
2232 def : Pat <(i32 (zext (i1 (setne (i32 (and (i32 IntRegs:$Rs), 255)),
2234 (i32 (TFR_condset_ii (i1 (CMPbEQri_V4 (i32 IntRegs:$Rs),
2240 // zext( seteq (Rs, and(Rt, 255)))
2242 // Pd=cmpb.eq(Rs, Rt)
2243 // if (Pd.new) Rd=#1
2244 // if (!Pd.new) Rd=#0
2245 def : Pat <(i32 (zext (i1 (seteq (i32 IntRegs:$Rt),
2246 (i32 (and (i32 IntRegs:$Rs), 255)))))),
2247 (i32 (TFR_condset_ii (i1 (CMPbEQrr_ubub_V4 (i32 IntRegs:$Rs),
2248 (i32 IntRegs:$Rt))),
2253 // zext( setne (Rs, and(Rt, 255)))
2255 // Pd=cmpb.eq(Rs, Rt)
2256 // if (Pd.new) Rd=#0
2257 // if (!Pd.new) Rd=#1
2258 def : Pat <(i32 (zext (i1 (setne (i32 IntRegs:$Rt),
2259 (i32 (and (i32 IntRegs:$Rs), 255)))))),
2260 (i32 (TFR_condset_ii (i1 (CMPbEQrr_ubub_V4 (i32 IntRegs:$Rs),
2261 (i32 IntRegs:$Rt))),
2266 // zext( setugt ( and(Rs, 255), u8))
2268 // Pd=cmpb.gtu(Rs, #u8)
2269 // if (Pd.new) Rd=#1
2270 // if (!Pd.new) Rd=#0
2271 def : Pat <(i32 (zext (i1 (setugt (i32 (and (i32 IntRegs:$Rs), 255)),
2273 (i32 (TFR_condset_ii (i1 (CMPbGTUri_V4 (i32 IntRegs:$Rs),
2279 // zext( setugt ( and(Rs, 254), u8))
2281 // Pd=cmpb.gtu(Rs, #u8)
2282 // if (Pd.new) Rd=#1
2283 // if (!Pd.new) Rd=#0
2284 def : Pat <(i32 (zext (i1 (setugt (i32 (and (i32 IntRegs:$Rs), 254)),
2286 (i32 (TFR_condset_ii (i1 (CMPbGTUri_V4 (i32 IntRegs:$Rs),
2292 // zext( setult ( Rs, Rt))
2294 // Pd=cmp.ltu(Rs, Rt)
2295 // if (Pd.new) Rd=#1
2296 // if (!Pd.new) Rd=#0
2297 // cmp.ltu(Rs, Rt) -> cmp.gtu(Rt, Rs)
2298 def : Pat <(i32 (zext (i1 (setult (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2299 (i32 (TFR_condset_ii (i1 (CMPGTUrr (i32 IntRegs:$Rt),
2300 (i32 IntRegs:$Rs))),
2305 // zext( setlt ( Rs, Rt))
2307 // Pd=cmp.lt(Rs, Rt)
2308 // if (Pd.new) Rd=#1
2309 // if (!Pd.new) Rd=#0
2310 // cmp.lt(Rs, Rt) -> cmp.gt(Rt, Rs)
2311 def : Pat <(i32 (zext (i1 (setlt (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2312 (i32 (TFR_condset_ii (i1 (CMPGTrr (i32 IntRegs:$Rt),
2313 (i32 IntRegs:$Rs))),
2318 // zext( setugt ( Rs, Rt))
2320 // Pd=cmp.gtu(Rs, Rt)
2321 // if (Pd.new) Rd=#1
2322 // if (!Pd.new) Rd=#0
2323 def : Pat <(i32 (zext (i1 (setugt (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2324 (i32 (TFR_condset_ii (i1 (CMPGTUrr (i32 IntRegs:$Rs),
2325 (i32 IntRegs:$Rt))),
2329 // This pattern interefers with coremark performance, not implementing at this
2332 // zext( setgt ( Rs, Rt))
2334 // Pd=cmp.gt(Rs, Rt)
2335 // if (Pd.new) Rd=#1
2336 // if (!Pd.new) Rd=#0
2339 // zext( setuge ( Rs, Rt))
2341 // Pd=cmp.ltu(Rs, Rt)
2342 // if (Pd.new) Rd=#0
2343 // if (!Pd.new) Rd=#1
2344 // cmp.ltu(Rs, Rt) -> cmp.gtu(Rt, Rs)
2345 def : Pat <(i32 (zext (i1 (setuge (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2346 (i32 (TFR_condset_ii (i1 (CMPGTUrr (i32 IntRegs:$Rt),
2347 (i32 IntRegs:$Rs))),
2352 // zext( setge ( Rs, Rt))
2354 // Pd=cmp.lt(Rs, Rt)
2355 // if (Pd.new) Rd=#0
2356 // if (!Pd.new) Rd=#1
2357 // cmp.lt(Rs, Rt) -> cmp.gt(Rt, Rs)
2358 def : Pat <(i32 (zext (i1 (setge (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2359 (i32 (TFR_condset_ii (i1 (CMPGTrr (i32 IntRegs:$Rt),
2360 (i32 IntRegs:$Rs))),
2365 // zext( setule ( Rs, Rt))
2367 // Pd=cmp.gtu(Rs, Rt)
2368 // if (Pd.new) Rd=#0
2369 // if (!Pd.new) Rd=#1
2370 def : Pat <(i32 (zext (i1 (setule (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2371 (i32 (TFR_condset_ii (i1 (CMPGTUrr (i32 IntRegs:$Rs),
2372 (i32 IntRegs:$Rt))),
2377 // zext( setle ( Rs, Rt))
2379 // Pd=cmp.gt(Rs, Rt)
2380 // if (Pd.new) Rd=#0
2381 // if (!Pd.new) Rd=#1
2382 def : Pat <(i32 (zext (i1 (setle (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2383 (i32 (TFR_condset_ii (i1 (CMPGTrr (i32 IntRegs:$Rs),
2384 (i32 IntRegs:$Rt))),
2389 // zext( setult ( and(Rs, 255), u8))
2390 // Use the isdigit transformation below
2392 // Generate code of the form 'mux_ii(cmpbgtu(Rdd, C-1),0,1)'
2393 // for C code of the form r = ((c>='0') & (c<='9')) ? 1 : 0;.
2394 // The isdigit transformation relies on two 'clever' aspects:
2395 // 1) The data type is unsigned which allows us to eliminate a zero test after
2396 // biasing the expression by 48. We are depending on the representation of
2397 // the unsigned types, and semantics.
2398 // 2) The front end has converted <= 9 into < 10 on entry to LLVM
2401 // retval = ((c>='0') & (c<='9')) ? 1 : 0;
2402 // The code is transformed upstream of llvm into
2403 // retval = (c-48) < 10 ? 1 : 0;
2404 let AddedComplexity = 139 in
2405 def : Pat <(i32 (zext (i1 (setult (i32 (and (i32 IntRegs:$src1), 255)),
2406 u7StrictPosImmPred:$src2)))),
2407 (i32 (MUX_ii (i1 (CMPbGTUri_V4 (i32 IntRegs:$src1),
2408 (DEC_CONST_BYTE u7StrictPosImmPred:$src2))),
2412 // Pd=cmpb.gtu(Rs,Rt)
2413 let isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPbGTU",
2414 InputType = "reg" in
2415 def CMPbGTUrr_V4 : MInst<(outs PredRegs:$dst),
2416 (ins IntRegs:$src1, IntRegs:$src2),
2417 "$dst = cmpb.gtu($src1, $src2)",
2418 [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),
2419 (and (i32 IntRegs:$src2), 255)))]>,
2420 Requires<[HasV4T]>, ImmRegRel;
2422 // Following instruction is not being extended as it results into the incorrect
2423 // code for negative numbers.
2425 // Signed half compare(.eq) ri.
2426 // Pd=cmph.eq(Rs,#s8)
2427 let isCompare = 1, validSubTargets = HasV4SubT in
2428 def CMPhEQri_V4 : MInst<(outs PredRegs:$dst),
2429 (ins IntRegs:$src1, s8Imm:$src2),
2430 "$dst = cmph.eq($src1, #$src2)",
2431 [(set (i1 PredRegs:$dst), (seteq (and (i32 IntRegs:$src1), 65535),
2432 s8ImmPred:$src2))]>,
2435 // Signed half compare(.eq) rr.
2436 // Case 1: xor + and, then compare:
2438 // r0=and(r0,#0xffff)
2440 // Pd=cmph.eq(Rs,Rt)
2441 let isCompare = 1, validSubTargets = HasV4SubT in
2442 def CMPhEQrr_xor_V4 : MInst<(outs PredRegs:$dst),
2443 (ins IntRegs:$src1, IntRegs:$src2),
2444 "$dst = cmph.eq($src1, $src2)",
2445 [(set (i1 PredRegs:$dst), (seteq (and (xor (i32 IntRegs:$src1),
2446 (i32 IntRegs:$src2)),
2450 // Signed half compare(.eq) rr.
2451 // Case 2: shift left 16 bits then compare:
2455 // Pd=cmph.eq(Rs,Rt)
2456 let isCompare = 1, validSubTargets = HasV4SubT in
2457 def CMPhEQrr_shl_V4 : MInst<(outs PredRegs:$dst),
2458 (ins IntRegs:$src1, IntRegs:$src2),
2459 "$dst = cmph.eq($src1, $src2)",
2460 [(set (i1 PredRegs:$dst),
2461 (seteq (shl (i32 IntRegs:$src1), (i32 16)),
2462 (shl (i32 IntRegs:$src2), (i32 16))))]>,
2465 /* Incorrect Pattern -- immediate should be right shifted before being
2466 used in the cmph.gt instruction.
2467 // Signed half compare(.gt) ri.
2468 // Pd=cmph.gt(Rs,#s8)
2470 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8,
2471 isCompare = 1, validSubTargets = HasV4SubT in
2472 def CMPhGTri_V4 : MInst<(outs PredRegs:$dst),
2473 (ins IntRegs:$src1, s8Ext:$src2),
2474 "$dst = cmph.gt($src1, #$src2)",
2475 [(set (i1 PredRegs:$dst),
2476 (setgt (shl (i32 IntRegs:$src1), (i32 16)),
2477 s8ExtPred:$src2))]>,
2481 // Signed half compare(.gt) rr.
2482 // Pd=cmph.gt(Rs,Rt)
2483 let isCompare = 1, validSubTargets = HasV4SubT in
2484 def CMPhGTrr_shl_V4 : MInst<(outs PredRegs:$dst),
2485 (ins IntRegs:$src1, IntRegs:$src2),
2486 "$dst = cmph.gt($src1, $src2)",
2487 [(set (i1 PredRegs:$dst),
2488 (setgt (shl (i32 IntRegs:$src1), (i32 16)),
2489 (shl (i32 IntRegs:$src2), (i32 16))))]>,
2492 // Unsigned half compare rr (.gtu).
2493 // Pd=cmph.gtu(Rs,Rt)
2494 let isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPhGTU",
2495 InputType = "reg" in
2496 def CMPhGTUrr_V4 : MInst<(outs PredRegs:$dst),
2497 (ins IntRegs:$src1, IntRegs:$src2),
2498 "$dst = cmph.gtu($src1, $src2)",
2499 [(set (i1 PredRegs:$dst),
2500 (setugt (and (i32 IntRegs:$src1), 65535),
2501 (and (i32 IntRegs:$src2), 65535)))]>,
2502 Requires<[HasV4T]>, ImmRegRel;
2504 // Unsigned half compare ri (.gtu).
2505 // Pd=cmph.gtu(Rs,#u7)
2506 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 7,
2507 isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPhGTU",
2508 InputType = "imm" in
2509 def CMPhGTUri_V4 : MInst<(outs PredRegs:$dst),
2510 (ins IntRegs:$src1, u7Ext:$src2),
2511 "$dst = cmph.gtu($src1, #$src2)",
2512 [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 65535),
2513 u7ExtPred:$src2))]>,
2514 Requires<[HasV4T]>, ImmRegRel;
2516 let validSubTargets = HasV4SubT in
2517 def NTSTBIT_rr : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2518 "$dst = !tstbit($src1, $src2)",
2519 [(set (i1 PredRegs:$dst),
2520 (seteq (and (shl 1, (i32 IntRegs:$src2)), (i32 IntRegs:$src1)), 0))]>,
2523 let validSubTargets = HasV4SubT in
2524 def NTSTBIT_ri : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2525 "$dst = !tstbit($src1, $src2)",
2526 [(set (i1 PredRegs:$dst),
2527 (seteq (and (shl 1, u5ImmPred:$src2), (i32 IntRegs:$src1)), 0))]>,
2530 //===----------------------------------------------------------------------===//
2532 //===----------------------------------------------------------------------===//
2534 //Deallocate frame and return.
2536 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicable = 1,
2537 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1 in {
2538 def DEALLOC_RET_V4 : NVInst_V4<(outs), (ins i32imm:$amt1),
2544 // Restore registers and dealloc return function call.
2545 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
2546 Defs = [R29, R30, R31, PC] in {
2547 def RESTORE_DEALLOC_RET_JMP_V4 : JInst<(outs),
2548 (ins calltarget:$dst),
2549 "jump $dst // Restore_and_dealloc_return",
2554 // Restore registers and dealloc frame before a tail call.
2555 let isCall = 1, isBarrier = 1,
2556 Defs = [R29, R30, R31, PC] in {
2557 def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : JInst<(outs),
2558 (ins calltarget:$dst),
2559 "call $dst // Restore_and_dealloc_before_tailcall",
2564 // Save registers function call.
2565 let isCall = 1, isBarrier = 1,
2566 Uses = [R29, R31] in {
2567 def SAVE_REGISTERS_CALL_V4 : JInst<(outs),
2568 (ins calltarget:$dst),
2569 "call $dst // Save_calle_saved_registers",
2574 // if (Ps) dealloc_return
2575 let isReturn = 1, isTerminator = 1,
2576 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
2577 isPredicated = 1 in {
2578 def DEALLOC_RET_cPt_V4 : NVInst_V4<(outs),
2579 (ins PredRegs:$src1, i32imm:$amt1),
2580 "if ($src1) dealloc_return",
2585 // if (!Ps) dealloc_return
2586 let isReturn = 1, isTerminator = 1,
2587 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
2588 isPredicated = 1 in {
2589 def DEALLOC_RET_cNotPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
2591 "if (!$src1) dealloc_return",
2596 // if (Ps.new) dealloc_return:nt
2597 let isReturn = 1, isTerminator = 1,
2598 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
2599 isPredicated = 1 in {
2600 def DEALLOC_RET_cdnPnt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
2602 "if ($src1.new) dealloc_return:nt",
2607 // if (!Ps.new) dealloc_return:nt
2608 let isReturn = 1, isTerminator = 1,
2609 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
2610 isPredicated = 1 in {
2611 def DEALLOC_RET_cNotdnPnt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
2613 "if (!$src1.new) dealloc_return:nt",
2618 // if (Ps.new) dealloc_return:t
2619 let isReturn = 1, isTerminator = 1,
2620 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
2621 isPredicated = 1 in {
2622 def DEALLOC_RET_cdnPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
2624 "if ($src1.new) dealloc_return:t",
2629 // if (!Ps.new) dealloc_return:nt
2630 let isReturn = 1, isTerminator = 1,
2631 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
2632 isPredicated = 1 in {
2633 def DEALLOC_RET_cNotdnPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
2635 "if (!$src1.new) dealloc_return:t",
2640 // Load/Store with absolute addressing mode
2643 multiclass ST_Abs_Predbase<string mnemonic, RegisterClass RC, bit isNot,
2645 let isPredicatedNew = isPredNew in
2646 def NAME#_V4 : STInst2<(outs),
2647 (ins PredRegs:$src1, u0AlwaysExt:$absaddr, RC: $src2),
2648 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
2649 ") ")#mnemonic#"(##$absaddr) = $src2",
2654 multiclass ST_Abs_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
2655 let isPredicatedFalse = PredNot in {
2656 defm _c#NAME : ST_Abs_Predbase<mnemonic, RC, PredNot, 0>;
2658 defm _cdn#NAME : ST_Abs_Predbase<mnemonic, RC, PredNot, 1>;
2662 let isNVStorable = 1, isExtended = 1, neverHasSideEffects = 1 in
2663 multiclass ST_Abs<string mnemonic, string CextOp, RegisterClass RC> {
2664 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
2665 let opExtendable = 0, isPredicable = 1 in
2666 def NAME#_V4 : STInst2<(outs),
2667 (ins u0AlwaysExt:$absaddr, RC:$src),
2668 mnemonic#"(##$absaddr) = $src",
2672 let opExtendable = 1, isPredicated = 1 in {
2673 defm Pt : ST_Abs_Pred<mnemonic, RC, 0>;
2674 defm NotPt : ST_Abs_Pred<mnemonic, RC, 1>;
2679 multiclass ST_Abs_Predbase_nv<string mnemonic, RegisterClass RC, bit isNot,
2681 let isPredicatedNew = isPredNew in
2682 def NAME#_nv_V4 : NVInst_V4<(outs),
2683 (ins PredRegs:$src1, u0AlwaysExt:$absaddr, RC: $src2),
2684 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
2685 ") ")#mnemonic#"(##$absaddr) = $src2.new",
2690 multiclass ST_Abs_Pred_nv<string mnemonic, RegisterClass RC, bit PredNot> {
2691 let isPredicatedFalse = PredNot in {
2692 defm _c#NAME : ST_Abs_Predbase_nv<mnemonic, RC, PredNot, 0>;
2694 defm _cdn#NAME : ST_Abs_Predbase_nv<mnemonic, RC, PredNot, 1>;
2698 let mayStore = 1, isNVStore = 1, isExtended = 1, neverHasSideEffects = 1 in
2699 multiclass ST_Abs_nv<string mnemonic, string CextOp, RegisterClass RC> {
2700 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
2701 let opExtendable = 0, isPredicable = 1 in
2702 def NAME#_nv_V4 : NVInst_V4<(outs),
2703 (ins u0AlwaysExt:$absaddr, RC:$src),
2704 mnemonic#"(##$absaddr) = $src.new",
2708 let opExtendable = 1, isPredicated = 1 in {
2709 defm Pt : ST_Abs_Pred_nv<mnemonic, RC, 0>;
2710 defm NotPt : ST_Abs_Pred_nv<mnemonic, RC, 1>;
2715 let addrMode = Absolute in {
2716 let accessSize = ByteAccess in
2717 defm STrib_abs : ST_Abs<"memb", "STrib", IntRegs>,
2718 ST_Abs_nv<"memb", "STrib", IntRegs>, AddrModeRel;
2720 let accessSize = HalfWordAccess in
2721 defm STrih_abs : ST_Abs<"memh", "STrih", IntRegs>,
2722 ST_Abs_nv<"memh", "STrih", IntRegs>, AddrModeRel;
2724 let accessSize = WordAccess in
2725 defm STriw_abs : ST_Abs<"memw", "STriw", IntRegs>,
2726 ST_Abs_nv<"memw", "STriw", IntRegs>, AddrModeRel;
2728 let accessSize = DoubleWordAccess, isNVStorable = 0 in
2729 defm STrid_abs : ST_Abs<"memd", "STrid", DoubleRegs>, AddrModeRel;
2732 let Predicates = [HasV4T], AddedComplexity = 30 in {
2733 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
2734 (HexagonCONST32 tglobaladdr:$absaddr)),
2735 (STrib_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
2737 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
2738 (HexagonCONST32 tglobaladdr:$absaddr)),
2739 (STrih_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
2741 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32 tglobaladdr:$absaddr)),
2742 (STriw_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
2744 def : Pat<(store (i64 DoubleRegs:$src1),
2745 (HexagonCONST32 tglobaladdr:$absaddr)),
2746 (STrid_abs_V4 tglobaladdr: $absaddr, DoubleRegs: $src1)>;
2749 //===----------------------------------------------------------------------===//
2750 // multiclass for store instructions with GP-relative addressing mode.
2751 // mem[bhwd](#global)=Rt
2752 // if ([!]Pv[.new]) mem[bhwd](##global) = Rt
2753 //===----------------------------------------------------------------------===//
2754 let mayStore = 1, isNVStorable = 1 in
2755 multiclass ST_GP<string mnemonic, string BaseOp, RegisterClass RC> {
2756 let BaseOpcode = BaseOp, isPredicable = 1 in
2757 def NAME#_V4 : STInst2<(outs),
2758 (ins globaladdress:$global, RC:$src),
2759 mnemonic#"(#$global) = $src",
2762 // When GP-relative instructions are predicated, their addressing mode is
2763 // changed to absolute and they are always constant extended.
2764 let BaseOpcode = BaseOp, isExtended = 1, opExtendable = 1,
2765 isPredicated = 1 in {
2766 defm Pt : ST_Abs_Pred <mnemonic, RC, 0>;
2767 defm NotPt : ST_Abs_Pred <mnemonic, RC, 1>;
2771 let mayStore = 1, isNVStore = 1 in
2772 multiclass ST_GP_nv<string mnemonic, string BaseOp, RegisterClass RC> {
2773 let BaseOpcode = BaseOp, isPredicable = 1 in
2774 def NAME#_nv_V4 : NVInst_V4<(outs),
2775 (ins u0AlwaysExt:$global, RC:$src),
2776 mnemonic#"(#$global) = $src.new",
2780 // When GP-relative instructions are predicated, their addressing mode is
2781 // changed to absolute and they are always constant extended.
2782 let BaseOpcode = BaseOp, isExtended = 1, opExtendable = 1,
2783 isPredicated = 1 in {
2784 defm Pt : ST_Abs_Pred_nv<mnemonic, RC, 0>;
2785 defm NotPt : ST_Abs_Pred_nv<mnemonic, RC, 1>;
2789 let validSubTargets = HasV4SubT, neverHasSideEffects = 1 in {
2790 let isNVStorable = 0 in
2791 defm STd_GP : ST_GP <"memd", "STd_GP", DoubleRegs>, PredNewRel;
2793 defm STb_GP : ST_GP<"memb", "STb_GP", IntRegs>,
2794 ST_GP_nv<"memb", "STb_GP", IntRegs>, NewValueRel;
2795 defm STh_GP : ST_GP<"memh", "STh_GP", IntRegs>,
2796 ST_GP_nv<"memh", "STh_GP", IntRegs>, NewValueRel;
2797 defm STw_GP : ST_GP<"memw", "STw_GP", IntRegs>,
2798 ST_GP_nv<"memw", "STw_GP", IntRegs>, NewValueRel;
2801 // 64 bit atomic store
2802 def : Pat <(atomic_store_64 (HexagonCONST32_GP tglobaladdr:$global),
2803 (i64 DoubleRegs:$src1)),
2804 (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2807 // Map from store(globaladdress) -> memd(#foo)
2808 let AddedComplexity = 100 in
2809 def : Pat <(store (i64 DoubleRegs:$src1),
2810 (HexagonCONST32_GP tglobaladdr:$global)),
2811 (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>;
2813 // 8 bit atomic store
2814 def : Pat < (atomic_store_8 (HexagonCONST32_GP tglobaladdr:$global),
2815 (i32 IntRegs:$src1)),
2816 (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
2818 // Map from store(globaladdress) -> memb(#foo)
2819 let AddedComplexity = 100 in
2820 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
2821 (HexagonCONST32_GP tglobaladdr:$global)),
2822 (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
2824 // Map from "i1 = constant<-1>; memw(CONST32(#foo)) = i1"
2825 // to "r0 = 1; memw(#foo) = r0"
2826 let AddedComplexity = 100 in
2827 def : Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
2828 (STb_GP_V4 tglobaladdr:$global, (TFRI 1))>;
2830 def : Pat<(atomic_store_16 (HexagonCONST32_GP tglobaladdr:$global),
2831 (i32 IntRegs:$src1)),
2832 (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
2834 // Map from store(globaladdress) -> memh(#foo)
2835 let AddedComplexity = 100 in
2836 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
2837 (HexagonCONST32_GP tglobaladdr:$global)),
2838 (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
2840 // 32 bit atomic store
2841 def : Pat<(atomic_store_32 (HexagonCONST32_GP tglobaladdr:$global),
2842 (i32 IntRegs:$src1)),
2843 (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
2845 // Map from store(globaladdress) -> memw(#foo)
2846 let AddedComplexity = 100 in
2847 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
2848 (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
2850 //===----------------------------------------------------------------------===//
2851 // Multiclass for the load instructions with absolute addressing mode.
2852 //===----------------------------------------------------------------------===//
2853 multiclass LD_Abs_Predbase<string mnemonic, RegisterClass RC, bit isNot,
2855 let isPredicatedNew = isPredNew in
2856 def NAME : LDInst2<(outs RC:$dst),
2857 (ins PredRegs:$src1, u0AlwaysExt:$absaddr),
2858 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
2859 ") ")#"$dst = "#mnemonic#"(##$absaddr)",
2864 multiclass LD_Abs_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
2865 let isPredicatedFalse = PredNot in {
2866 defm _c#NAME : LD_Abs_Predbase<mnemonic, RC, PredNot, 0>;
2868 defm _cdn#NAME : LD_Abs_Predbase<mnemonic, RC, PredNot, 1>;
2872 let isExtended = 1, neverHasSideEffects = 1 in
2873 multiclass LD_Abs<string mnemonic, string CextOp, RegisterClass RC> {
2874 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
2875 let opExtendable = 1, isPredicable = 1 in
2876 def NAME#_V4 : LDInst2<(outs RC:$dst),
2877 (ins u0AlwaysExt:$absaddr),
2878 "$dst = "#mnemonic#"(##$absaddr)",
2882 let opExtendable = 2, isPredicated = 1 in {
2883 defm Pt_V4 : LD_Abs_Pred<mnemonic, RC, 0>;
2884 defm NotPt_V4 : LD_Abs_Pred<mnemonic, RC, 1>;
2889 let addrMode = Absolute in {
2890 let accessSize = ByteAccess in {
2891 defm LDrib_abs : LD_Abs<"memb", "LDrib", IntRegs>, AddrModeRel;
2892 defm LDriub_abs : LD_Abs<"memub", "LDriub", IntRegs>, AddrModeRel;
2894 let accessSize = HalfWordAccess in {
2895 defm LDrih_abs : LD_Abs<"memh", "LDrih", IntRegs>, AddrModeRel;
2896 defm LDriuh_abs : LD_Abs<"memuh", "LDriuh", IntRegs>, AddrModeRel;
2898 let accessSize = WordAccess in
2899 defm LDriw_abs : LD_Abs<"memw", "LDriw", IntRegs>, AddrModeRel;
2901 let accessSize = DoubleWordAccess in
2902 defm LDrid_abs : LD_Abs<"memd", "LDrid", DoubleRegs>, AddrModeRel;
2905 let Predicates = [HasV4T], AddedComplexity = 30 in {
2906 def : Pat<(i32 (load (HexagonCONST32 tglobaladdr:$absaddr))),
2907 (LDriw_abs_V4 tglobaladdr: $absaddr)>;
2909 def : Pat<(i32 (sextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
2910 (LDrib_abs_V4 tglobaladdr:$absaddr)>;
2912 def : Pat<(i32 (zextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
2913 (LDriub_abs_V4 tglobaladdr:$absaddr)>;
2915 def : Pat<(i32 (sextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
2916 (LDrih_abs_V4 tglobaladdr:$absaddr)>;
2918 def : Pat<(i32 (zextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
2919 (LDriuh_abs_V4 tglobaladdr:$absaddr)>;
2922 //===----------------------------------------------------------------------===//
2923 // multiclass for load instructions with GP-relative addressing mode.
2924 // Rx=mem[bhwd](##global)
2925 // if ([!]Pv[.new]) Rx=mem[bhwd](##global)
2926 //===----------------------------------------------------------------------===//
2927 let neverHasSideEffects = 1, validSubTargets = HasV4SubT in
2928 multiclass LD_GP<string mnemonic, string BaseOp, RegisterClass RC> {
2929 let BaseOpcode = BaseOp in {
2930 let isPredicable = 1 in
2931 def NAME#_V4 : LDInst2<(outs RC:$dst),
2932 (ins globaladdress:$global),
2933 "$dst = "#mnemonic#"(#$global)",
2936 let isExtended = 1, opExtendable = 2, isPredicated = 1 in {
2937 defm Pt_V4 : LD_Abs_Pred<mnemonic, RC, 0>;
2938 defm NotPt_V4 : LD_Abs_Pred<mnemonic, RC, 1>;
2943 defm LDd_GP : LD_GP<"memd", "LDd_GP", DoubleRegs>, PredNewRel;
2944 defm LDb_GP : LD_GP<"memb", "LDb_GP", IntRegs>, PredNewRel;
2945 defm LDub_GP : LD_GP<"memub", "LDub_GP", IntRegs>, PredNewRel;
2946 defm LDh_GP : LD_GP<"memh", "LDh_GP", IntRegs>, PredNewRel;
2947 defm LDuh_GP : LD_GP<"memuh", "LDuh_GP", IntRegs>, PredNewRel;
2948 defm LDw_GP : LD_GP<"memw", "LDw_GP", IntRegs>, PredNewRel;
2950 def : Pat <(atomic_load_64 (HexagonCONST32_GP tglobaladdr:$global)),
2951 (i64 (LDd_GP_V4 tglobaladdr:$global))>;
2953 def : Pat <(atomic_load_32 (HexagonCONST32_GP tglobaladdr:$global)),
2954 (i32 (LDw_GP_V4 tglobaladdr:$global))>;
2956 def : Pat <(atomic_load_16 (HexagonCONST32_GP tglobaladdr:$global)),
2957 (i32 (LDuh_GP_V4 tglobaladdr:$global))>;
2959 def : Pat <(atomic_load_8 (HexagonCONST32_GP tglobaladdr:$global)),
2960 (i32 (LDub_GP_V4 tglobaladdr:$global))>;
2962 // Map from load(globaladdress) -> memw(#foo + 0)
2963 let AddedComplexity = 100 in
2964 def : Pat <(i64 (load (HexagonCONST32_GP tglobaladdr:$global))),
2965 (i64 (LDd_GP_V4 tglobaladdr:$global))>;
2967 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd
2968 let AddedComplexity = 100 in
2969 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
2970 (i1 (TFR_PdRs (i32 (LDb_GP_V4 tglobaladdr:$global))))>;
2972 // When the Interprocedural Global Variable optimizer realizes that a certain
2973 // global variable takes only two constant values, it shrinks the global to
2974 // a boolean. Catch those loads here in the following 3 patterns.
2975 let AddedComplexity = 100 in
2976 def : Pat <(i32 (extloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
2977 (i32 (LDb_GP_V4 tglobaladdr:$global))>;
2979 let AddedComplexity = 100 in
2980 def : Pat <(i32 (sextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
2981 (i32 (LDb_GP_V4 tglobaladdr:$global))>;
2983 // Map from load(globaladdress) -> memb(#foo)
2984 let AddedComplexity = 100 in
2985 def : Pat <(i32 (extloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
2986 (i32 (LDb_GP_V4 tglobaladdr:$global))>;
2988 // Map from load(globaladdress) -> memb(#foo)
2989 let AddedComplexity = 100 in
2990 def : Pat <(i32 (sextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
2991 (i32 (LDb_GP_V4 tglobaladdr:$global))>;
2993 let AddedComplexity = 100 in
2994 def : Pat <(i32 (zextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
2995 (i32 (LDub_GP_V4 tglobaladdr:$global))>;
2997 // Map from load(globaladdress) -> memub(#foo)
2998 let AddedComplexity = 100 in
2999 def : Pat <(i32 (zextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
3000 (i32 (LDub_GP_V4 tglobaladdr:$global))>;
3002 // Map from load(globaladdress) -> memh(#foo)
3003 let AddedComplexity = 100 in
3004 def : Pat <(i32 (extloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
3005 (i32 (LDh_GP_V4 tglobaladdr:$global))>;
3007 // Map from load(globaladdress) -> memh(#foo)
3008 let AddedComplexity = 100 in
3009 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
3010 (i32 (LDh_GP_V4 tglobaladdr:$global))>;
3012 // Map from load(globaladdress) -> memuh(#foo)
3013 let AddedComplexity = 100 in
3014 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
3015 (i32 (LDuh_GP_V4 tglobaladdr:$global))>;
3017 // Map from load(globaladdress) -> memw(#foo)
3018 let AddedComplexity = 100 in
3019 def : Pat <(i32 (load (HexagonCONST32_GP tglobaladdr:$global))),
3020 (i32 (LDw_GP_V4 tglobaladdr:$global))>;
3023 // Transfer global address into a register
3024 let isExtended = 1, opExtendable = 1, AddedComplexity=50, isMoveImm = 1,
3025 isAsCheapAsAMove = 1, isReMaterializable = 1, validSubTargets = HasV4SubT in
3026 def TFRI_V4 : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
3028 [(set IntRegs:$dst, (HexagonCONST32 tglobaladdr:$src1))]>,
3031 // Transfer a block address into a register
3032 def : Pat<(HexagonCONST32_GP tblockaddress:$src1),
3033 (TFRI_V4 tblockaddress:$src1)>,
3036 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
3037 def TFRI_cPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3038 (ins PredRegs:$src1, globaladdress:$src2),
3039 "if($src1) $dst = ##$src2",
3043 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
3044 def TFRI_cNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3045 (ins PredRegs:$src1, globaladdress:$src2),
3046 "if(!$src1) $dst = ##$src2",
3050 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
3051 def TFRI_cdnPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3052 (ins PredRegs:$src1, globaladdress:$src2),
3053 "if($src1.new) $dst = ##$src2",
3057 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
3058 def TFRI_cdnNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3059 (ins PredRegs:$src1, globaladdress:$src2),
3060 "if(!$src1.new) $dst = ##$src2",
3064 let AddedComplexity = 50, Predicates = [HasV4T] in
3065 def : Pat<(HexagonCONST32_GP tglobaladdr:$src1),
3066 (TFRI_V4 tglobaladdr:$src1)>;
3069 // Load - Indirect with long offset: These instructions take global address
3071 let isExtended = 1, opExtendable = 3, AddedComplexity = 40,
3072 validSubTargets = HasV4SubT in
3073 def LDrid_ind_lo_V4 : LDInst<(outs DoubleRegs:$dst),
3074 (ins IntRegs:$src1, u2Imm:$src2, globaladdressExt:$offset),
3075 "$dst=memd($src1<<#$src2+##$offset)",
3076 [(set (i64 DoubleRegs:$dst),
3077 (load (add (shl IntRegs:$src1, u2ImmPred:$src2),
3078 (HexagonCONST32 tglobaladdr:$offset))))]>,
3081 let AddedComplexity = 40 in
3082 multiclass LD_indirect_lo<string OpcStr, PatFrag OpNode> {
3083 let isExtended = 1, opExtendable = 3, validSubTargets = HasV4SubT in
3084 def _lo_V4 : LDInst<(outs IntRegs:$dst),
3085 (ins IntRegs:$src1, u2Imm:$src2, globaladdressExt:$offset),
3086 !strconcat("$dst = ",
3087 !strconcat(OpcStr, "($src1<<#$src2+##$offset)")),
3089 (i32 (OpNode (add (shl IntRegs:$src1, u2ImmPred:$src2),
3090 (HexagonCONST32 tglobaladdr:$offset)))))]>,
3094 defm LDrib_ind : LD_indirect_lo<"memb", sextloadi8>;
3095 defm LDriub_ind : LD_indirect_lo<"memub", zextloadi8>;
3096 defm LDriub_ind_anyext : LD_indirect_lo<"memub", extloadi8>;
3097 defm LDrih_ind : LD_indirect_lo<"memh", sextloadi16>;
3098 defm LDriuh_ind : LD_indirect_lo<"memuh", zextloadi16>;
3099 defm LDriuh_ind_anyext : LD_indirect_lo<"memuh", extloadi16>;
3100 defm LDriw_ind : LD_indirect_lo<"memw", load>;
3102 let AddedComplexity = 40 in
3103 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1,
3104 (NumUsesBelowThresCONST32 tglobaladdr:$offset)))),
3105 (i32 (LDrib_ind_lo_V4 IntRegs:$src1, 0, tglobaladdr:$offset))>,
3108 let AddedComplexity = 40 in
3109 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1,
3110 (NumUsesBelowThresCONST32 tglobaladdr:$offset)))),
3111 (i32 (LDriub_ind_lo_V4 IntRegs:$src1, 0, tglobaladdr:$offset))>,
3114 let Predicates = [HasV4T], AddedComplexity = 30 in {
3115 def : Pat<(truncstorei8 (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
3116 (STrib_abs_V4 u0AlwaysExtPred:$src2, IntRegs: $src1)>;
3118 def : Pat<(truncstorei16 (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
3119 (STrih_abs_V4 u0AlwaysExtPred:$src2, IntRegs: $src1)>;
3121 def : Pat<(store (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
3122 (STriw_abs_V4 u0AlwaysExtPred:$src2, IntRegs: $src1)>;
3125 let Predicates = [HasV4T], AddedComplexity = 30 in {
3126 def : Pat<(i32 (load u0AlwaysExtPred:$src)),
3127 (LDriw_abs_V4 u0AlwaysExtPred:$src)>;
3129 def : Pat<(i32 (sextloadi8 u0AlwaysExtPred:$src)),
3130 (LDrib_abs_V4 u0AlwaysExtPred:$src)>;
3132 def : Pat<(i32 (zextloadi8 u0AlwaysExtPred:$src)),
3133 (LDriub_abs_V4 u0AlwaysExtPred:$src)>;
3135 def : Pat<(i32 (sextloadi16 u0AlwaysExtPred:$src)),
3136 (LDrih_abs_V4 u0AlwaysExtPred:$src)>;
3138 def : Pat<(i32 (zextloadi16 u0AlwaysExtPred:$src)),
3139 (LDriuh_abs_V4 u0AlwaysExtPred:$src)>;
3142 // Indexed store word - global address.
3143 // memw(Rs+#u6:2)=#S8
3144 let AddedComplexity = 10 in
3145 def STriw_offset_ext_V4 : STInst<(outs),
3146 (ins IntRegs:$src1, u6_2Imm:$src2, globaladdress:$src3),
3147 "memw($src1+#$src2) = ##$src3",
3148 [(store (HexagonCONST32 tglobaladdr:$src3),
3149 (add IntRegs:$src1, u6_2ImmPred:$src2))]>,
3153 // Indexed store double word - global address.
3154 // memw(Rs+#u6:2)=#S8
3155 let AddedComplexity = 10 in
3156 def STrih_offset_ext_V4 : STInst<(outs),
3157 (ins IntRegs:$src1, u6_1Imm:$src2, globaladdress:$src3),
3158 "memh($src1+#$src2) = ##$src3",
3159 [(truncstorei16 (HexagonCONST32 tglobaladdr:$src3),
3160 (add IntRegs:$src1, u6_1ImmPred:$src2))]>,
3162 // Map from store(globaladdress + x) -> memd(#foo + x)
3163 let AddedComplexity = 100 in
3164 def : Pat<(store (i64 DoubleRegs:$src1),
3165 FoldGlobalAddrGP:$addr),
3166 (STrid_abs_V4 FoldGlobalAddrGP:$addr, (i64 DoubleRegs:$src1))>,
3169 def : Pat<(atomic_store_64 FoldGlobalAddrGP:$addr,
3170 (i64 DoubleRegs:$src1)),
3171 (STrid_abs_V4 FoldGlobalAddrGP:$addr, (i64 DoubleRegs:$src1))>,
3174 // Map from store(globaladdress + x) -> memb(#foo + x)
3175 let AddedComplexity = 100 in
3176 def : Pat<(truncstorei8 (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
3177 (STrib_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3180 def : Pat<(atomic_store_8 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
3181 (STrib_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3184 // Map from store(globaladdress + x) -> memh(#foo + x)
3185 let AddedComplexity = 100 in
3186 def : Pat<(truncstorei16 (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
3187 (STrih_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3190 def : Pat<(atomic_store_16 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
3191 (STrih_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3194 // Map from store(globaladdress + x) -> memw(#foo + x)
3195 let AddedComplexity = 100 in
3196 def : Pat<(store (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
3197 (STriw_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3200 def : Pat<(atomic_store_32 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
3201 (STriw_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3204 // Map from load(globaladdress + x) -> memd(#foo + x)
3205 let AddedComplexity = 100 in
3206 def : Pat<(i64 (load FoldGlobalAddrGP:$addr)),
3207 (i64 (LDrid_abs_V4 FoldGlobalAddrGP:$addr))>,
3210 def : Pat<(atomic_load_64 FoldGlobalAddrGP:$addr),
3211 (i64 (LDrid_abs_V4 FoldGlobalAddrGP:$addr))>,
3214 // Map from load(globaladdress + x) -> memb(#foo + x)
3215 let AddedComplexity = 100 in
3216 def : Pat<(i32 (extloadi8 FoldGlobalAddrGP:$addr)),
3217 (i32 (LDrib_abs_V4 FoldGlobalAddrGP:$addr))>,
3220 // Map from load(globaladdress + x) -> memb(#foo + x)
3221 let AddedComplexity = 100 in
3222 def : Pat<(i32 (sextloadi8 FoldGlobalAddrGP:$addr)),
3223 (i32 (LDrib_abs_V4 FoldGlobalAddrGP:$addr))>,
3226 //let AddedComplexity = 100 in
3227 let AddedComplexity = 100 in
3228 def : Pat<(i32 (extloadi16 FoldGlobalAddrGP:$addr)),
3229 (i32 (LDrih_abs_V4 FoldGlobalAddrGP:$addr))>,
3232 // Map from load(globaladdress + x) -> memh(#foo + x)
3233 let AddedComplexity = 100 in
3234 def : Pat<(i32 (sextloadi16 FoldGlobalAddrGP:$addr)),
3235 (i32 (LDrih_abs_V4 FoldGlobalAddrGP:$addr))>,
3238 // Map from load(globaladdress + x) -> memuh(#foo + x)
3239 let AddedComplexity = 100 in
3240 def : Pat<(i32 (zextloadi16 FoldGlobalAddrGP:$addr)),
3241 (i32 (LDriuh_abs_V4 FoldGlobalAddrGP:$addr))>,
3244 def : Pat<(atomic_load_16 FoldGlobalAddrGP:$addr),
3245 (i32 (LDriuh_abs_V4 FoldGlobalAddrGP:$addr))>,
3248 // Map from load(globaladdress + x) -> memub(#foo + x)
3249 let AddedComplexity = 100 in
3250 def : Pat<(i32 (zextloadi8 FoldGlobalAddrGP:$addr)),
3251 (i32 (LDriub_abs_V4 FoldGlobalAddrGP:$addr))>,
3254 def : Pat<(atomic_load_8 FoldGlobalAddrGP:$addr),
3255 (i32 (LDriub_abs_V4 FoldGlobalAddrGP:$addr))>,
3258 // Map from load(globaladdress + x) -> memw(#foo + x)
3259 let AddedComplexity = 100 in
3260 def : Pat<(i32 (load FoldGlobalAddrGP:$addr)),
3261 (i32 (LDriw_abs_V4 FoldGlobalAddrGP:$addr))>,
3264 def : Pat<(atomic_load_32 FoldGlobalAddrGP:$addr),
3265 (i32 (LDriw_abs_V4 FoldGlobalAddrGP:$addr))>,