1 //=- HexagonInstrInfoV4.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V4 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 let neverHasSideEffects = 1 in
15 class T_Immext<dag ins> :
16 EXTENDERInst<(outs), ins, "immext(#$imm)", []>,
19 def IMMEXT_b : T_Immext<(ins brtarget:$imm)>;
20 def IMMEXT_c : T_Immext<(ins calltarget:$imm)>;
21 def IMMEXT_g : T_Immext<(ins globaladdress:$imm)>;
22 def IMMEXT_i : T_Immext<(ins u26_6Imm:$imm)>;
24 // Fold (add (CONST32 tglobaladdr:$addr) <offset>) into a global address.
25 def FoldGlobalAddr : ComplexPattern<i32, 1, "foldGlobalAddress", [], []>;
27 // Fold (add (CONST32_GP tglobaladdr:$addr) <offset>) into a global address.
28 def FoldGlobalAddrGP : ComplexPattern<i32, 1, "foldGlobalAddressGP", [], []>;
30 def NumUsesBelowThresCONST32 : PatFrag<(ops node:$addr),
31 (HexagonCONST32 node:$addr), [{
32 return hasNumUsesBelowThresGA(N->getOperand(0).getNode());
35 // Hexagon V4 Architecture spec defines 8 instruction classes:
36 // LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the
40 // ========================================
41 // Loads (8/16/32/64 bit)
45 // ========================================
46 // Stores (8/16/32/64 bit)
49 // ALU32 Instructions:
50 // ========================================
51 // Arithmetic / Logical (32 bit)
54 // XTYPE Instructions (32/64 bit):
55 // ========================================
56 // Arithmetic, Logical, Bit Manipulation
57 // Multiply (Integer, Fractional, Complex)
58 // Permute / Vector Permute Operations
59 // Predicate Operations
60 // Shift / Shift with Add/Sub/Logical
62 // Vector Halfword (ALU, Shift, Multiply)
63 // Vector Word (ALU, Shift)
66 // ========================================
67 // Jump/Call PC-relative
70 // ========================================
73 // MEMOP Instructions:
74 // ========================================
75 // Operation on memory (8/16/32 bit)
78 // ========================================
83 // ========================================
84 // Control-Register Transfers
85 // Hardware Loop Setup
86 // Predicate Logicals & Reductions
88 // SYSTEM Instructions (not implemented in the compiler):
89 // ========================================
95 //===----------------------------------------------------------------------===//
97 //===----------------------------------------------------------------------===//
98 // Generate frame index addresses.
99 let neverHasSideEffects = 1, isReMaterializable = 1,
100 isExtended = 1, opExtendable = 2, validSubTargets = HasV4SubT in
101 def TFR_FI_immext_V4 : ALU32_ri<(outs IntRegs:$dst),
102 (ins IntRegs:$src1, s32Imm:$offset),
103 "$dst = add($src1, ##$offset)",
108 let validSubTargets = HasV4SubT, isExtendable = 1, opExtendable = 2,
109 isExtentSigned = 1, opExtentBits = 8 in
110 def V4_A4_rcmpeqi : ALU32_ri<(outs IntRegs:$Rd),
111 (ins IntRegs:$Rs, s8Ext:$s8),
112 "$Rd = cmp.eq($Rs, #$s8)",
113 [(set (i32 IntRegs:$Rd),
114 (i32 (zext (i1 (seteq (i32 IntRegs:$Rs),
115 s8ExtPred:$s8)))))]>,
118 // Preserve the TSTBIT generation
119 def : Pat <(i32 (zext (i1 (setne (i32 (and (i32 (shl 1, (i32 IntRegs:$src2))),
120 (i32 IntRegs:$src1))), 0)))),
121 (i32 (MUX_ii (i1 (TSTBIT_rr (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
124 // Interfered with tstbit generation, above pattern preserves, see : tstbit.ll
126 let validSubTargets = HasV4SubT, isExtendable = 1, opExtendable = 2,
127 isExtentSigned = 1, opExtentBits = 8 in
128 def V4_A4_rcmpneqi : ALU32_ri<(outs IntRegs:$Rd),
129 (ins IntRegs:$Rs, s8Ext:$s8),
130 "$Rd = !cmp.eq($Rs, #$s8)",
131 [(set (i32 IntRegs:$Rd),
132 (i32 (zext (i1 (setne (i32 IntRegs:$Rs),
133 s8ExtPred:$s8)))))]>,
137 let validSubTargets = HasV4SubT in
138 def V4_A4_rcmpeq : ALU32_ri<(outs IntRegs:$Rd),
139 (ins IntRegs:$Rs, IntRegs:$Rt),
140 "$Rd = cmp.eq($Rs, $Rt)",
141 [(set (i32 IntRegs:$Rd),
142 (i32 (zext (i1 (seteq (i32 IntRegs:$Rs),
147 let validSubTargets = HasV4SubT in
148 def V4_A4_rcmpneq : ALU32_ri<(outs IntRegs:$Rd),
149 (ins IntRegs:$Rs, IntRegs:$Rt),
150 "$Rd = !cmp.eq($Rs, $Rt)",
151 [(set (i32 IntRegs:$Rd),
152 (i32 (zext (i1 (setne (i32 IntRegs:$Rs),
156 //===----------------------------------------------------------------------===//
158 //===----------------------------------------------------------------------===//
161 //===----------------------------------------------------------------------===//
163 //===----------------------------------------------------------------------===//
166 // Rdd=combine(Rs, #s8)
167 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8,
168 neverHasSideEffects = 1, validSubTargets = HasV4SubT in
169 def COMBINE_rI_V4 : ALU32_ri<(outs DoubleRegs:$dst),
170 (ins IntRegs:$src1, s8Ext:$src2),
171 "$dst = combine($src1, #$src2)",
175 // Rdd=combine(#s8, Rs)
176 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 8,
177 neverHasSideEffects = 1, validSubTargets = HasV4SubT in
178 def COMBINE_Ir_V4 : ALU32_ir<(outs DoubleRegs:$dst),
179 (ins s8Ext:$src1, IntRegs:$src2),
180 "$dst = combine(#$src1, $src2)",
184 def HexagonWrapperCombineRI_V4 :
185 SDNode<"HexagonISD::WrapperCombineRI_V4", SDTHexagonI64I32I32>;
186 def HexagonWrapperCombineIR_V4 :
187 SDNode<"HexagonISD::WrapperCombineIR_V4", SDTHexagonI64I32I32>;
189 def : Pat <(HexagonWrapperCombineRI_V4 IntRegs:$r, s8ExtPred:$i),
190 (COMBINE_rI_V4 IntRegs:$r, s8ExtPred:$i)>,
193 def : Pat <(HexagonWrapperCombineIR_V4 s8ExtPred:$i, IntRegs:$r),
194 (COMBINE_Ir_V4 s8ExtPred:$i, IntRegs:$r)>,
197 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 6,
198 neverHasSideEffects = 1, validSubTargets = HasV4SubT in
199 def COMBINE_iI_V4 : ALU32_ii<(outs DoubleRegs:$dst),
200 (ins s8Imm:$src1, u6Ext:$src2),
201 "$dst = combine(#$src1, #$src2)",
205 //===----------------------------------------------------------------------===//
207 //===----------------------------------------------------------------------===//
209 //===----------------------------------------------------------------------===//
211 //===----------------------------------------------------------------------===//
212 //===----------------------------------------------------------------------===//
213 // Template class for load instructions with Absolute set addressing mode.
214 //===----------------------------------------------------------------------===//
215 let isExtended = 1, opExtendable = 2, neverHasSideEffects = 1,
216 validSubTargets = HasV4SubT in
217 class T_LD_abs_set<string mnemonic, RegisterClass RC>:
218 LDInst2<(outs RC:$dst1, IntRegs:$dst2),
219 (ins u0AlwaysExt:$addr),
220 "$dst1 = "#mnemonic#"($dst2=##$addr)",
224 def LDrid_abs_set_V4 : T_LD_abs_set <"memd", DoubleRegs>;
225 def LDrib_abs_set_V4 : T_LD_abs_set <"memb", IntRegs>;
226 def LDriub_abs_set_V4 : T_LD_abs_set <"memub", IntRegs>;
227 def LDrih_abs_set_V4 : T_LD_abs_set <"memh", IntRegs>;
228 def LDriw_abs_set_V4 : T_LD_abs_set <"memw", IntRegs>;
229 def LDriuh_abs_set_V4 : T_LD_abs_set <"memuh", IntRegs>;
232 // multiclass for load instructions with base + register offset
234 multiclass ld_idxd_shl_pbase<string mnemonic, RegisterClass RC, bit isNot,
236 let isPredicatedNew = isPredNew in
237 def NAME : LDInst2<(outs RC:$dst),
238 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset),
239 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
240 ") ")#"$dst = "#mnemonic#"($src2+$src3<<#$offset)",
241 []>, Requires<[HasV4T]>;
244 multiclass ld_idxd_shl_pred<string mnemonic, RegisterClass RC, bit PredNot> {
245 let isPredicatedFalse = PredNot in {
246 defm _c#NAME : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 0>;
248 defm _cdn#NAME : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 1>;
252 let neverHasSideEffects = 1 in
253 multiclass ld_idxd_shl<string mnemonic, string CextOp, RegisterClass RC> {
254 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
255 let isPredicable = 1 in
256 def NAME#_V4 : LDInst2<(outs RC:$dst),
257 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
258 "$dst = "#mnemonic#"($src1+$src2<<#$offset)",
259 []>, Requires<[HasV4T]>;
261 let isPredicated = 1 in {
262 defm Pt_V4 : ld_idxd_shl_pred<mnemonic, RC, 0 >;
263 defm NotPt_V4 : ld_idxd_shl_pred<mnemonic, RC, 1>;
268 let addrMode = BaseRegOffset in {
269 defm LDrib_indexed_shl: ld_idxd_shl<"memb", "LDrib", IntRegs>, AddrModeRel;
270 defm LDriub_indexed_shl: ld_idxd_shl<"memub", "LDriub", IntRegs>, AddrModeRel;
271 defm LDrih_indexed_shl: ld_idxd_shl<"memh", "LDrih", IntRegs>, AddrModeRel;
272 defm LDriuh_indexed_shl: ld_idxd_shl<"memuh", "LDriuh", IntRegs>, AddrModeRel;
273 defm LDriw_indexed_shl: ld_idxd_shl<"memw", "LDriw", IntRegs>, AddrModeRel;
274 defm LDrid_indexed_shl: ld_idxd_shl<"memd", "LDrid", DoubleRegs>, AddrModeRel;
277 // 'def pats' for load instructions with base + register offset and non-zero
278 // immediate value. Immediate value is used to left-shift the second
280 let AddedComplexity = 40 in {
281 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1,
282 (shl IntRegs:$src2, u2ImmPred:$offset)))),
283 (LDrib_indexed_shl_V4 IntRegs:$src1,
284 IntRegs:$src2, u2ImmPred:$offset)>,
287 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1,
288 (shl IntRegs:$src2, u2ImmPred:$offset)))),
289 (LDriub_indexed_shl_V4 IntRegs:$src1,
290 IntRegs:$src2, u2ImmPred:$offset)>,
293 def : Pat <(i32 (extloadi8 (add IntRegs:$src1,
294 (shl IntRegs:$src2, u2ImmPred:$offset)))),
295 (LDriub_indexed_shl_V4 IntRegs:$src1,
296 IntRegs:$src2, u2ImmPred:$offset)>,
299 def : Pat <(i32 (sextloadi16 (add IntRegs:$src1,
300 (shl IntRegs:$src2, u2ImmPred:$offset)))),
301 (LDrih_indexed_shl_V4 IntRegs:$src1,
302 IntRegs:$src2, u2ImmPred:$offset)>,
305 def : Pat <(i32 (zextloadi16 (add IntRegs:$src1,
306 (shl IntRegs:$src2, u2ImmPred:$offset)))),
307 (LDriuh_indexed_shl_V4 IntRegs:$src1,
308 IntRegs:$src2, u2ImmPred:$offset)>,
311 def : Pat <(i32 (extloadi16 (add IntRegs:$src1,
312 (shl IntRegs:$src2, u2ImmPred:$offset)))),
313 (LDriuh_indexed_shl_V4 IntRegs:$src1,
314 IntRegs:$src2, u2ImmPred:$offset)>,
317 def : Pat <(i32 (load (add IntRegs:$src1,
318 (shl IntRegs:$src2, u2ImmPred:$offset)))),
319 (LDriw_indexed_shl_V4 IntRegs:$src1,
320 IntRegs:$src2, u2ImmPred:$offset)>,
323 def : Pat <(i64 (load (add IntRegs:$src1,
324 (shl IntRegs:$src2, u2ImmPred:$offset)))),
325 (LDrid_indexed_shl_V4 IntRegs:$src1,
326 IntRegs:$src2, u2ImmPred:$offset)>,
331 // 'def pats' for load instruction base + register offset and
332 // zero immediate value.
333 let AddedComplexity = 10 in {
334 def : Pat <(i64 (load (add IntRegs:$src1, IntRegs:$src2))),
335 (LDrid_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
338 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1, IntRegs:$src2))),
339 (LDrib_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
342 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1, IntRegs:$src2))),
343 (LDriub_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
346 def : Pat <(i32 (extloadi8 (add IntRegs:$src1, IntRegs:$src2))),
347 (LDriub_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
350 def : Pat <(i32 (sextloadi16 (add IntRegs:$src1, IntRegs:$src2))),
351 (LDrih_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
354 def : Pat <(i32 (zextloadi16 (add IntRegs:$src1, IntRegs:$src2))),
355 (LDriuh_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
358 def : Pat <(i32 (extloadi16 (add IntRegs:$src1, IntRegs:$src2))),
359 (LDriuh_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
362 def : Pat <(i32 (load (add IntRegs:$src1, IntRegs:$src2))),
363 (LDriw_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
368 def : Pat <(i64 (zext (i1 PredRegs:$src1))),
369 (i64 (COMBINE_Ir_V4 0, (MUX_ii (i1 PredRegs:$src1), 1, 0)))>,
373 def : Pat <(i64 (zext (i32 IntRegs:$src1))),
374 (i64 (COMBINE_Ir_V4 0, (i32 IntRegs:$src1)))>,
377 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
378 (i64 (COMBINE_Ir_V4 0, (LDriub ADDRriS11_0:$src1)))>,
381 let AddedComplexity = 20 in
382 def: Pat <(i64 (zextloadi8 (add (i32 IntRegs:$src1),
383 s11_0ExtPred:$offset))),
384 (i64 (COMBINE_Ir_V4 0, (LDriub_indexed IntRegs:$src1,
385 s11_0ExtPred:$offset)))>,
389 def: Pat <(i64 (zextloadi1 ADDRriS11_0:$src1)),
390 (i64 (COMBINE_Ir_V4 0, (LDriub ADDRriS11_0:$src1)))>,
393 let AddedComplexity = 20 in
394 def: Pat <(i64 (zextloadi1 (add (i32 IntRegs:$src1),
395 s11_0ExtPred:$offset))),
396 (i64 (COMBINE_Ir_V4 0, (LDriub_indexed IntRegs:$src1,
397 s11_0ExtPred:$offset)))>,
401 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
402 (i64 (COMBINE_Ir_V4 0, (LDriuh ADDRriS11_1:$src1)))>,
405 let AddedComplexity = 20 in
406 def: Pat <(i64 (zextloadi16 (add (i32 IntRegs:$src1),
407 s11_1ExtPred:$offset))),
408 (i64 (COMBINE_Ir_V4 0, (LDriuh_indexed IntRegs:$src1,
409 s11_1ExtPred:$offset)))>,
413 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
414 (i64 (COMBINE_Ir_V4 0, (LDrih ADDRriS11_2:$src1)))>,
417 let AddedComplexity = 20 in
418 def: Pat <(i64 (extloadi16 (add (i32 IntRegs:$src1),
419 s11_1ExtPred:$offset))),
420 (i64 (COMBINE_Ir_V4 0, (LDrih_indexed IntRegs:$src1,
421 s11_1ExtPred:$offset)))>,
425 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
426 (i64 (COMBINE_Ir_V4 0, (LDriw ADDRriS11_2:$src1)))>,
429 let AddedComplexity = 100 in
430 def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
431 (i64 (COMBINE_Ir_V4 0, (LDriw_indexed IntRegs:$src1,
432 s11_2ExtPred:$offset)))>,
436 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
437 (i64 (COMBINE_Ir_V4 0, (LDriw ADDRriS11_2:$src1)))>,
440 let AddedComplexity = 100 in
441 def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
442 (i64 (COMBINE_Ir_V4 0, (LDriw_indexed IntRegs:$src1,
443 s11_2ExtPred:$offset)))>,
448 //===----------------------------------------------------------------------===//
450 //===----------------------------------------------------------------------===//
452 //===----------------------------------------------------------------------===//
454 //===----------------------------------------------------------------------===//
456 //===----------------------------------------------------------------------===//
457 // Template class for store instructions with Absolute set addressing mode.
458 //===----------------------------------------------------------------------===//
459 let isExtended = 1, opExtendable = 2, validSubTargets = HasV4SubT in
460 class T_ST_abs_set<string mnemonic, RegisterClass RC>:
461 STInst2<(outs IntRegs:$dst1),
462 (ins RC:$src1, u0AlwaysExt:$src2),
463 mnemonic#"($dst1=##$src2) = $src1",
467 def STrid_abs_set_V4 : T_ST_abs_set <"memd", DoubleRegs>;
468 def STrib_abs_set_V4 : T_ST_abs_set <"memb", IntRegs>;
469 def STrih_abs_set_V4 : T_ST_abs_set <"memh", IntRegs>;
470 def STriw_abs_set_V4 : T_ST_abs_set <"memw", IntRegs>;
472 //===----------------------------------------------------------------------===//
473 // multiclass for store instructions with base + register offset addressing
475 //===----------------------------------------------------------------------===//
476 multiclass ST_Idxd_shl_Pbase<string mnemonic, RegisterClass RC, bit isNot,
478 let isPredicatedNew = isPredNew in
479 def NAME : STInst2<(outs),
480 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
482 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
483 ") ")#mnemonic#"($src2+$src3<<#$src4) = $src5",
488 multiclass ST_Idxd_shl_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
489 let isPredicatedFalse = PredNot in {
490 defm _c#NAME : ST_Idxd_shl_Pbase<mnemonic, RC, PredNot, 0>;
492 defm _cdn#NAME : ST_Idxd_shl_Pbase<mnemonic, RC, PredNot, 1>;
496 let isNVStorable = 1 in
497 multiclass ST_Idxd_shl<string mnemonic, string CextOp, RegisterClass RC> {
498 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
499 let isPredicable = 1 in
500 def NAME#_V4 : STInst2<(outs),
501 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, RC:$src4),
502 mnemonic#"($src1+$src2<<#$src3) = $src4",
506 let isPredicated = 1 in {
507 defm Pt_V4 : ST_Idxd_shl_Pred<mnemonic, RC, 0 >;
508 defm NotPt_V4 : ST_Idxd_shl_Pred<mnemonic, RC, 1>;
513 // multiclass for new-value store instructions with base + register offset
515 multiclass ST_Idxd_shl_Pbase_nv<string mnemonic, RegisterClass RC, bit isNot,
517 let isPredicatedNew = isPredNew in
518 def NAME#_nv_V4 : NVInst_V4<(outs),
519 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
521 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
522 ") ")#mnemonic#"($src2+$src3<<#$src4) = $src5.new",
527 multiclass ST_Idxd_shl_Pred_nv<string mnemonic, RegisterClass RC, bit PredNot> {
528 let isPredicatedFalse = PredNot in {
529 defm _c#NAME : ST_Idxd_shl_Pbase_nv<mnemonic, RC, PredNot, 0>;
531 defm _cdn#NAME : ST_Idxd_shl_Pbase_nv<mnemonic, RC, PredNot, 1>;
535 let mayStore = 1, isNVStore = 1 in
536 multiclass ST_Idxd_shl_nv<string mnemonic, string CextOp, RegisterClass RC> {
537 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
538 let isPredicable = 1 in
539 def NAME#_nv_V4 : NVInst_V4<(outs),
540 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, RC:$src4),
541 mnemonic#"($src1+$src2<<#$src3) = $src4.new",
545 let isPredicated = 1 in {
546 defm Pt : ST_Idxd_shl_Pred_nv<mnemonic, RC, 0 >;
547 defm NotPt : ST_Idxd_shl_Pred_nv<mnemonic, RC, 1>;
552 let addrMode = BaseRegOffset, neverHasSideEffects = 1,
553 validSubTargets = HasV4SubT in {
554 defm STrib_indexed_shl: ST_Idxd_shl<"memb", "STrib", IntRegs>,
555 ST_Idxd_shl_nv<"memb", "STrib", IntRegs>, AddrModeRel;
557 defm STrih_indexed_shl: ST_Idxd_shl<"memh", "STrih", IntRegs>,
558 ST_Idxd_shl_nv<"memh", "STrih", IntRegs>, AddrModeRel;
560 defm STriw_indexed_shl: ST_Idxd_shl<"memw", "STriw", IntRegs>,
561 ST_Idxd_shl_nv<"memw", "STriw", IntRegs>, AddrModeRel;
563 let isNVStorable = 0 in
564 defm STrid_indexed_shl: ST_Idxd_shl<"memd", "STrid", DoubleRegs>, AddrModeRel;
567 let Predicates = [HasV4T], AddedComplexity = 10 in {
568 def : Pat<(truncstorei8 (i32 IntRegs:$src4),
569 (add IntRegs:$src1, (shl IntRegs:$src2,
571 (STrib_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
572 u2ImmPred:$src3, IntRegs:$src4)>;
574 def : Pat<(truncstorei16 (i32 IntRegs:$src4),
575 (add IntRegs:$src1, (shl IntRegs:$src2,
577 (STrih_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
578 u2ImmPred:$src3, IntRegs:$src4)>;
580 def : Pat<(store (i32 IntRegs:$src4),
581 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
582 (STriw_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
583 u2ImmPred:$src3, IntRegs:$src4)>;
585 def : Pat<(store (i64 DoubleRegs:$src4),
586 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
587 (STrid_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
588 u2ImmPred:$src3, DoubleRegs:$src4)>;
591 let isExtended = 1, opExtendable = 2 in
592 class T_ST_LongOff <string mnemonic, PatFrag stOp, RegisterClass RC, ValueType VT> :
594 (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, RC:$src4),
595 mnemonic#"($src1<<#$src2+##$src3) = $src4",
596 [(stOp (VT RC:$src4),
597 (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
598 u0AlwaysExtPred:$src3))]>,
601 let isExtended = 1, opExtendable = 2, mayStore = 1, isNVStore = 1 in
602 class T_ST_LongOff_nv <string mnemonic> :
604 (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, IntRegs:$src4),
605 mnemonic#"($src1<<#$src2+##$src3) = $src4.new",
609 multiclass ST_LongOff <string mnemonic, string BaseOp, PatFrag stOp> {
610 let BaseOpcode = BaseOp#"_shl" in {
611 let isNVStorable = 1 in
612 def NAME#_V4 : T_ST_LongOff<mnemonic, stOp, IntRegs, i32>;
614 def NAME#_nv_V4 : T_ST_LongOff_nv<mnemonic>;
618 let AddedComplexity = 10, validSubTargets = HasV4SubT in {
619 def STrid_shl_V4 : T_ST_LongOff<"memd", store, DoubleRegs, i64>;
620 defm STrib_shl : ST_LongOff <"memb", "STrib", truncstorei8>, NewValueRel;
621 defm STrih_shl : ST_LongOff <"memh", "Strih", truncstorei16>, NewValueRel;
622 defm STriw_shl : ST_LongOff <"memw", "STriw", store>, NewValueRel;
625 let AddedComplexity = 40 in
626 multiclass T_ST_LOff_Pats <InstHexagon I, RegisterClass RC, ValueType VT,
628 def : Pat<(stOp (VT RC:$src4),
629 (add (shl IntRegs:$src1, u2ImmPred:$src2),
630 (NumUsesBelowThresCONST32 tglobaladdr:$src3))),
631 (I IntRegs:$src1, u2ImmPred:$src2, tglobaladdr:$src3, RC:$src4)>;
633 def : Pat<(stOp (VT RC:$src4),
635 (NumUsesBelowThresCONST32 tglobaladdr:$src3))),
636 (I IntRegs:$src1, 0, tglobaladdr:$src3, RC:$src4)>;
639 defm : T_ST_LOff_Pats<STrid_shl_V4, DoubleRegs, i64, store>;
640 defm : T_ST_LOff_Pats<STriw_shl_V4, IntRegs, i32, store>;
641 defm : T_ST_LOff_Pats<STrib_shl_V4, IntRegs, i32, truncstorei8>;
642 defm : T_ST_LOff_Pats<STrih_shl_V4, IntRegs, i32, truncstorei16>;
644 // memd(Rx++#s4:3)=Rtt
645 // memd(Rx++#s4:3:circ(Mu))=Rtt
646 // memd(Rx++I:circ(Mu))=Rtt
648 // memd(Rx++Mu:brev)=Rtt
649 // memd(gp+#u16:3)=Rtt
651 // Store doubleword conditionally.
652 // if ([!]Pv[.new]) memd(#u6)=Rtt
653 // TODO: needs to be implemented.
655 //===----------------------------------------------------------------------===//
656 // multiclass for store instructions with base + immediate offset
657 // addressing mode and immediate stored value.
658 // mem[bhw](Rx++#s4:3)=#s8
659 // if ([!]Pv[.new]) mem[bhw](Rx++#s4:3)=#s6
660 //===----------------------------------------------------------------------===//
661 multiclass ST_Imm_Pbase<string mnemonic, Operand OffsetOp, bit isNot,
663 let isPredicatedNew = isPredNew in
664 def NAME : STInst2<(outs),
665 (ins PredRegs:$src1, IntRegs:$src2, OffsetOp:$src3, s6Ext:$src4),
666 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
667 ") ")#mnemonic#"($src2+#$src3) = #$src4",
672 multiclass ST_Imm_Pred<string mnemonic, Operand OffsetOp, bit PredNot> {
673 let isPredicatedFalse = PredNot in {
674 defm _c#NAME : ST_Imm_Pbase<mnemonic, OffsetOp, PredNot, 0>;
676 defm _cdn#NAME : ST_Imm_Pbase<mnemonic, OffsetOp, PredNot, 1>;
680 let isExtendable = 1, isExtentSigned = 1, neverHasSideEffects = 1 in
681 multiclass ST_Imm<string mnemonic, string CextOp, Operand OffsetOp> {
682 let CextOpcode = CextOp, BaseOpcode = CextOp#_imm in {
683 let opExtendable = 2, opExtentBits = 8, isPredicable = 1 in
684 def NAME#_V4 : STInst2<(outs),
685 (ins IntRegs:$src1, OffsetOp:$src2, s8Ext:$src3),
686 mnemonic#"($src1+#$src2) = #$src3",
690 let opExtendable = 3, opExtentBits = 6, isPredicated = 1 in {
691 defm Pt_V4 : ST_Imm_Pred<mnemonic, OffsetOp, 0>;
692 defm NotPt_V4 : ST_Imm_Pred<mnemonic, OffsetOp, 1 >;
697 let addrMode = BaseImmOffset, InputType = "imm",
698 validSubTargets = HasV4SubT in {
699 defm STrib_imm : ST_Imm<"memb", "STrib", u6_0Imm>, ImmRegRel, PredNewRel;
700 defm STrih_imm : ST_Imm<"memh", "STrih", u6_1Imm>, ImmRegRel, PredNewRel;
701 defm STriw_imm : ST_Imm<"memw", "STriw", u6_2Imm>, ImmRegRel, PredNewRel;
704 let Predicates = [HasV4T], AddedComplexity = 10 in {
705 def: Pat<(truncstorei8 s8ExtPred:$src3, (add IntRegs:$src1, u6_0ImmPred:$src2)),
706 (STrib_imm_V4 IntRegs:$src1, u6_0ImmPred:$src2, s8ExtPred:$src3)>;
708 def: Pat<(truncstorei16 s8ExtPred:$src3, (add IntRegs:$src1,
710 (STrih_imm_V4 IntRegs:$src1, u6_1ImmPred:$src2, s8ExtPred:$src3)>;
712 def: Pat<(store s8ExtPred:$src3, (add IntRegs:$src1, u6_2ImmPred:$src2)),
713 (STriw_imm_V4 IntRegs:$src1, u6_2ImmPred:$src2, s8ExtPred:$src3)>;
716 let AddedComplexity = 6 in
717 def : Pat <(truncstorei8 s8ExtPred:$src2, (i32 IntRegs:$src1)),
718 (STrib_imm_V4 IntRegs:$src1, 0, s8ExtPred:$src2)>,
721 // memb(Rx++#s4:0:circ(Mu))=Rt
722 // memb(Rx++I:circ(Mu))=Rt
724 // memb(Rx++Mu:brev)=Rt
725 // memb(gp+#u16:0)=Rt
729 // TODO: needs to be implemented
731 // memh(Rs+#s11:1)=Rt.H
732 let AddedComplexity = 6 in
733 def : Pat <(truncstorei16 s8ExtPred:$src2, (i32 IntRegs:$src1)),
734 (STrih_imm_V4 IntRegs:$src1, 0, s8ExtPred:$src2)>,
737 // memh(Rs+Ru<<#u2)=Rt.H
738 // TODO: needs to be implemented.
740 // memh(Ru<<#u2+#U6)=Rt.H
741 // memh(Rx++#s4:1:circ(Mu))=Rt.H
742 // memh(Rx++#s4:1:circ(Mu))=Rt
743 // memh(Rx++I:circ(Mu))=Rt.H
744 // memh(Rx++I:circ(Mu))=Rt
747 // memh(Rx++Mu:brev)=Rt.H
748 // memh(Rx++Mu:brev)=Rt
749 // memh(gp+#u16:1)=Rt
750 // if ([!]Pv[.new]) memh(#u6)=Rt.H
751 // if ([!]Pv[.new]) memh(#u6)=Rt
754 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt.H
755 // TODO: needs to be implemented.
757 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt.H
758 // TODO: Needs to be implemented.
762 // TODO: Needs to be implemented.
765 let neverHasSideEffects = 1 in
766 def STriw_pred_V4 : STInst2<(outs),
767 (ins MEMri:$addr, PredRegs:$src1),
768 "Error; should not emit",
772 let AddedComplexity = 6 in
773 def : Pat <(store s8ExtPred:$src2, (i32 IntRegs:$src1)),
774 (STriw_imm_V4 IntRegs:$src1, 0, s8ExtPred:$src2)>,
777 // memw(Rx++#s4:2)=Rt
778 // memw(Rx++#s4:2:circ(Mu))=Rt
779 // memw(Rx++I:circ(Mu))=Rt
781 // memw(Rx++Mu:brev)=Rt
783 //===----------------------------------------------------------------------===
785 //===----------------------------------------------------------------------===
788 //===----------------------------------------------------------------------===//
790 //===----------------------------------------------------------------------===//
792 // multiclass for new-value store instructions with base + immediate offset.
794 multiclass ST_Idxd_Pbase_nv<string mnemonic, RegisterClass RC,
795 Operand predImmOp, bit isNot, bit isPredNew> {
796 let isPredicatedNew = isPredNew in
797 def NAME#_nv_V4 : NVInst_V4<(outs),
798 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4),
799 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
800 ") ")#mnemonic#"($src2+#$src3) = $src4.new",
805 multiclass ST_Idxd_Pred_nv<string mnemonic, RegisterClass RC, Operand predImmOp,
807 let isPredicatedFalse = PredNot in {
808 defm _c#NAME : ST_Idxd_Pbase_nv<mnemonic, RC, predImmOp, PredNot, 0>;
810 defm _cdn#NAME : ST_Idxd_Pbase_nv<mnemonic, RC, predImmOp, PredNot, 1>;
814 let mayStore = 1, isNVStore = 1, neverHasSideEffects = 1, isExtendable = 1 in
815 multiclass ST_Idxd_nv<string mnemonic, string CextOp, RegisterClass RC,
816 Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
817 bits<5> PredImmBits> {
819 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
820 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
822 def NAME#_nv_V4 : NVInst_V4<(outs),
823 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
824 mnemonic#"($src1+#$src2) = $src3.new",
828 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits,
829 isPredicated = 1 in {
830 defm Pt : ST_Idxd_Pred_nv<mnemonic, RC, predImmOp, 0>;
831 defm NotPt : ST_Idxd_Pred_nv<mnemonic, RC, predImmOp, 1>;
836 let addrMode = BaseImmOffset, validSubTargets = HasV4SubT in {
837 defm STrib_indexed: ST_Idxd_nv<"memb", "STrib", IntRegs, s11_0Ext,
838 u6_0Ext, 11, 6>, AddrModeRel;
839 defm STrih_indexed: ST_Idxd_nv<"memh", "STrih", IntRegs, s11_1Ext,
840 u6_1Ext, 12, 7>, AddrModeRel;
841 defm STriw_indexed: ST_Idxd_nv<"memw", "STriw", IntRegs, s11_2Ext,
842 u6_2Ext, 13, 8>, AddrModeRel;
845 // multiclass for new-value store instructions with base + immediate offset.
846 // and MEMri operand.
847 multiclass ST_MEMri_Pbase_nv<string mnemonic, RegisterClass RC, bit isNot,
849 let isPredicatedNew = isPredNew in
850 def NAME#_nv_V4 : NVInst_V4<(outs),
851 (ins PredRegs:$src1, MEMri:$addr, RC: $src2),
852 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
853 ") ")#mnemonic#"($addr) = $src2.new",
858 multiclass ST_MEMri_Pred_nv<string mnemonic, RegisterClass RC, bit PredNot> {
859 let isPredicatedFalse = PredNot in {
860 defm _c#NAME : ST_MEMri_Pbase_nv<mnemonic, RC, PredNot, 0>;
863 defm _cdn#NAME : ST_MEMri_Pbase_nv<mnemonic, RC, PredNot, 1>;
867 let mayStore = 1, isNVStore = 1, isExtendable = 1, neverHasSideEffects = 1 in
868 multiclass ST_MEMri_nv<string mnemonic, string CextOp, RegisterClass RC,
869 bits<5> ImmBits, bits<5> PredImmBits> {
871 let CextOpcode = CextOp, BaseOpcode = CextOp in {
872 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
874 def NAME#_nv_V4 : NVInst_V4<(outs),
875 (ins MEMri:$addr, RC:$src),
876 mnemonic#"($addr) = $src.new",
880 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits,
881 neverHasSideEffects = 1, isPredicated = 1 in {
882 defm Pt : ST_MEMri_Pred_nv<mnemonic, RC, 0>;
883 defm NotPt : ST_MEMri_Pred_nv<mnemonic, RC, 1>;
888 let addrMode = BaseImmOffset, isMEMri = "true", validSubTargets = HasV4SubT,
890 defm STrib: ST_MEMri_nv<"memb", "STrib", IntRegs, 11, 6>, AddrModeRel;
891 defm STrih: ST_MEMri_nv<"memh", "STrih", IntRegs, 12, 7>, AddrModeRel;
892 defm STriw: ST_MEMri_nv<"memw", "STriw", IntRegs, 13, 8>, AddrModeRel;
895 //===----------------------------------------------------------------------===//
896 // Post increment store
897 // mem[bhwd](Rx++#s4:[0123])=Nt.new
898 //===----------------------------------------------------------------------===//
900 multiclass ST_PostInc_Pbase_nv<string mnemonic, RegisterClass RC, Operand ImmOp,
901 bit isNot, bit isPredNew> {
902 let isPredicatedNew = isPredNew in
903 def NAME#_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
904 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3),
905 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
906 ") ")#mnemonic#"($src2++#$offset) = $src3.new",
912 multiclass ST_PostInc_Pred_nv<string mnemonic, RegisterClass RC,
913 Operand ImmOp, bit PredNot> {
914 let isPredicatedFalse = PredNot in {
915 defm _c#NAME : ST_PostInc_Pbase_nv<mnemonic, RC, ImmOp, PredNot, 0>;
917 let Predicates = [HasV4T], validSubTargets = HasV4SubT in
918 defm _cdn#NAME : ST_PostInc_Pbase_nv<mnemonic, RC, ImmOp, PredNot, 1>;
922 let hasCtrlDep = 1, isNVStore = 1, neverHasSideEffects = 1 in
923 multiclass ST_PostInc_nv<string mnemonic, string BaseOp, RegisterClass RC,
926 let BaseOpcode = "POST_"#BaseOp in {
927 let isPredicable = 1 in
928 def NAME#_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
929 (ins IntRegs:$src1, ImmOp:$offset, RC:$src2),
930 mnemonic#"($src1++#$offset) = $src2.new",
935 let isPredicated = 1 in {
936 defm Pt : ST_PostInc_Pred_nv<mnemonic, RC, ImmOp, 0 >;
937 defm NotPt : ST_PostInc_Pred_nv<mnemonic, RC, ImmOp, 1 >;
942 let validSubTargets = HasV4SubT in {
943 defm POST_STbri: ST_PostInc_nv <"memb", "STrib", IntRegs, s4_0Imm>, AddrModeRel;
944 defm POST_SThri: ST_PostInc_nv <"memh", "STrih", IntRegs, s4_1Imm>, AddrModeRel;
945 defm POST_STwri: ST_PostInc_nv <"memw", "STriw", IntRegs, s4_2Imm>, AddrModeRel;
948 // memb(Rx++#s4:0:circ(Mu))=Nt.new
949 // memb(Rx++I:circ(Mu))=Nt.new
950 // memb(Rx++Mu)=Nt.new
951 // memb(Rx++Mu:brev)=Nt.new
952 // memh(Rx++#s4:1:circ(Mu))=Nt.new
953 // memh(Rx++I:circ(Mu))=Nt.new
954 // memh(Rx++Mu)=Nt.new
955 // memh(Rx++Mu:brev)=Nt.new
957 // memw(Rx++#s4:2:circ(Mu))=Nt.new
958 // memw(Rx++I:circ(Mu))=Nt.new
959 // memw(Rx++Mu)=Nt.new
960 // memw(Rx++Mu:brev)=Nt.new
962 //===----------------------------------------------------------------------===//
964 //===----------------------------------------------------------------------===//
966 //===----------------------------------------------------------------------===//
968 //===----------------------------------------------------------------------===//
970 multiclass NVJ_type_basic_reg<string NotStr, string OpcStr, string TakenStr> {
971 def _ie_nv_V4 : NVInst_V4<(outs),
972 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
973 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
974 !strconcat("($src1.new, $src2)) jump:",
975 !strconcat(TakenStr, " $offset"))))),
979 def _nv_V4 : NVInst_V4<(outs),
980 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
981 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
982 !strconcat("($src1.new, $src2)) jump:",
983 !strconcat(TakenStr, " $offset"))))),
988 multiclass NVJ_type_basic_2ndDotNew<string NotStr, string OpcStr,
990 def _ie_nv_V4 : NVInst_V4<(outs),
991 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
992 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
993 !strconcat("($src1, $src2.new)) jump:",
994 !strconcat(TakenStr, " $offset"))))),
998 def _nv_V4 : NVInst_V4<(outs),
999 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
1000 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
1001 !strconcat("($src1, $src2.new)) jump:",
1002 !strconcat(TakenStr, " $offset"))))),
1007 multiclass NVJ_type_basic_imm<string NotStr, string OpcStr, string TakenStr> {
1008 def _ie_nv_V4 : NVInst_V4<(outs),
1009 (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
1010 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
1011 !strconcat("($src1.new, #$src2)) jump:",
1012 !strconcat(TakenStr, " $offset"))))),
1016 def _nv_V4 : NVInst_V4<(outs),
1017 (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
1018 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
1019 !strconcat("($src1.new, #$src2)) jump:",
1020 !strconcat(TakenStr, " $offset"))))),
1025 multiclass NVJ_type_basic_neg<string NotStr, string OpcStr, string TakenStr> {
1026 def _ie_nv_V4 : NVInst_V4<(outs),
1027 (ins IntRegs:$src1, nOneImm:$src2, brtarget:$offset),
1028 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
1029 !strconcat("($src1.new, #$src2)) jump:",
1030 !strconcat(TakenStr, " $offset"))))),
1034 def _nv_V4 : NVInst_V4<(outs),
1035 (ins IntRegs:$src1, nOneImm:$src2, brtarget:$offset),
1036 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
1037 !strconcat("($src1.new, #$src2)) jump:",
1038 !strconcat(TakenStr, " $offset"))))),
1043 multiclass NVJ_type_basic_tstbit<string NotStr, string OpcStr,
1045 def _ie_nv_V4 : NVInst_V4<(outs),
1046 (ins IntRegs:$src1, u1Imm:$src2, brtarget:$offset),
1047 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
1048 !strconcat("($src1.new, #$src2)) jump:",
1049 !strconcat(TakenStr, " $offset"))))),
1053 def _nv_V4 : NVInst_V4<(outs),
1054 (ins IntRegs:$src1, u1Imm:$src2, brtarget:$offset),
1055 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
1056 !strconcat("($src1.new, #$src2)) jump:",
1057 !strconcat(TakenStr, " $offset"))))),
1062 // Multiclass for regular dot new of Ist operand register.
1063 multiclass NVJ_type_br_pred_reg<string NotStr, string OpcStr> {
1064 defm Pt : NVJ_type_basic_reg<NotStr, OpcStr, "t">;
1065 defm Pnt : NVJ_type_basic_reg<NotStr, OpcStr, "nt">;
1068 // Multiclass for dot new of 2nd operand register.
1069 multiclass NVJ_type_br_pred_2ndDotNew<string NotStr, string OpcStr> {
1070 defm Pt : NVJ_type_basic_2ndDotNew<NotStr, OpcStr, "t">;
1071 defm Pnt : NVJ_type_basic_2ndDotNew<NotStr, OpcStr, "nt">;
1074 // Multiclass for 2nd operand immediate, including -1.
1075 multiclass NVJ_type_br_pred_imm<string NotStr, string OpcStr> {
1076 defm Pt : NVJ_type_basic_imm<NotStr, OpcStr, "t">;
1077 defm Pnt : NVJ_type_basic_imm<NotStr, OpcStr, "nt">;
1078 defm Ptneg : NVJ_type_basic_neg<NotStr, OpcStr, "t">;
1079 defm Pntneg : NVJ_type_basic_neg<NotStr, OpcStr, "nt">;
1082 // Multiclass for 2nd operand immediate, excluding -1.
1083 multiclass NVJ_type_br_pred_imm_only<string NotStr, string OpcStr> {
1084 defm Pt : NVJ_type_basic_imm<NotStr, OpcStr, "t">;
1085 defm Pnt : NVJ_type_basic_imm<NotStr, OpcStr, "nt">;
1088 // Multiclass for tstbit, where 2nd operand is always #0.
1089 multiclass NVJ_type_br_pred_tstbit<string NotStr, string OpcStr> {
1090 defm Pt : NVJ_type_basic_tstbit<NotStr, OpcStr, "t">;
1091 defm Pnt : NVJ_type_basic_tstbit<NotStr, OpcStr, "nt">;
1094 // Multiclass for GT.
1095 multiclass NVJ_type_rr_ri<string OpcStr> {
1096 defm rrNot : NVJ_type_br_pred_reg<"!", OpcStr>;
1097 defm rr : NVJ_type_br_pred_reg<"", OpcStr>;
1098 defm rrdnNot : NVJ_type_br_pred_2ndDotNew<"!", OpcStr>;
1099 defm rrdn : NVJ_type_br_pred_2ndDotNew<"", OpcStr>;
1100 defm riNot : NVJ_type_br_pred_imm<"!", OpcStr>;
1101 defm ri : NVJ_type_br_pred_imm<"", OpcStr>;
1104 // Multiclass for EQ.
1105 multiclass NVJ_type_rr_ri_no_2ndDotNew<string OpcStr> {
1106 defm rrNot : NVJ_type_br_pred_reg<"!", OpcStr>;
1107 defm rr : NVJ_type_br_pred_reg<"", OpcStr>;
1108 defm riNot : NVJ_type_br_pred_imm<"!", OpcStr>;
1109 defm ri : NVJ_type_br_pred_imm<"", OpcStr>;
1112 // Multiclass for GTU.
1113 multiclass NVJ_type_rr_ri_no_nOne<string OpcStr> {
1114 defm rrNot : NVJ_type_br_pred_reg<"!", OpcStr>;
1115 defm rr : NVJ_type_br_pred_reg<"", OpcStr>;
1116 defm rrdnNot : NVJ_type_br_pred_2ndDotNew<"!", OpcStr>;
1117 defm rrdn : NVJ_type_br_pred_2ndDotNew<"", OpcStr>;
1118 defm riNot : NVJ_type_br_pred_imm_only<"!", OpcStr>;
1119 defm ri : NVJ_type_br_pred_imm_only<"", OpcStr>;
1122 // Multiclass for tstbit.
1123 multiclass NVJ_type_r0<string OpcStr> {
1124 defm r0Not : NVJ_type_br_pred_tstbit<"!", OpcStr>;
1125 defm r0 : NVJ_type_br_pred_tstbit<"", OpcStr>;
1128 // Base Multiclass for New Value Jump.
1129 multiclass NVJ_type {
1130 defm GT : NVJ_type_rr_ri<"cmp.gt">;
1131 defm EQ : NVJ_type_rr_ri_no_2ndDotNew<"cmp.eq">;
1132 defm GTU : NVJ_type_rr_ri_no_nOne<"cmp.gtu">;
1133 defm TSTBIT : NVJ_type_r0<"tstbit">;
1136 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC] in {
1137 defm JMP_ : NVJ_type;
1140 //===----------------------------------------------------------------------===//
1142 //===----------------------------------------------------------------------===//
1144 //===----------------------------------------------------------------------===//
1146 //===----------------------------------------------------------------------===//
1148 // Add and accumulate.
1149 // Rd=add(Rs,add(Ru,#s6))
1150 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 6,
1151 validSubTargets = HasV4SubT in
1152 def ADDr_ADDri_V4 : MInst<(outs IntRegs:$dst),
1153 (ins IntRegs:$src1, IntRegs:$src2, s6Ext:$src3),
1154 "$dst = add($src1, add($src2, #$src3))",
1155 [(set (i32 IntRegs:$dst),
1156 (add (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),
1157 s6_16ExtPred:$src3)))]>,
1160 // Rd=add(Rs,sub(#s6,Ru))
1161 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 6,
1162 validSubTargets = HasV4SubT in
1163 def ADDr_SUBri_V4 : MInst<(outs IntRegs:$dst),
1164 (ins IntRegs:$src1, s6Ext:$src2, IntRegs:$src3),
1165 "$dst = add($src1, sub(#$src2, $src3))",
1166 [(set (i32 IntRegs:$dst),
1167 (add (i32 IntRegs:$src1), (sub s6_10ExtPred:$src2,
1168 (i32 IntRegs:$src3))))]>,
1171 // Generates the same instruction as ADDr_SUBri_V4 but matches different
1173 // Rd=add(Rs,sub(#s6,Ru))
1174 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 6,
1175 validSubTargets = HasV4SubT in
1176 def ADDri_SUBr_V4 : MInst<(outs IntRegs:$dst),
1177 (ins IntRegs:$src1, s6Ext:$src2, IntRegs:$src3),
1178 "$dst = add($src1, sub(#$src2, $src3))",
1179 [(set (i32 IntRegs:$dst),
1180 (sub (add (i32 IntRegs:$src1), s6_10ExtPred:$src2),
1181 (i32 IntRegs:$src3)))]>,
1185 // Add or subtract doublewords with carry.
1187 // Rdd=add(Rss,Rtt,Px):carry
1189 // Rdd=sub(Rss,Rtt,Px):carry
1192 // Logical doublewords.
1193 // Rdd=and(Rtt,~Rss)
1194 let validSubTargets = HasV4SubT in
1195 def ANDd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),
1196 (ins DoubleRegs:$src1, DoubleRegs:$src2),
1197 "$dst = and($src1, ~$src2)",
1198 [(set (i64 DoubleRegs:$dst), (and (i64 DoubleRegs:$src1),
1199 (not (i64 DoubleRegs:$src2))))]>,
1203 let validSubTargets = HasV4SubT in
1204 def ORd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),
1205 (ins DoubleRegs:$src1, DoubleRegs:$src2),
1206 "$dst = or($src1, ~$src2)",
1207 [(set (i64 DoubleRegs:$dst),
1208 (or (i64 DoubleRegs:$src1), (not (i64 DoubleRegs:$src2))))]>,
1212 // Logical-logical doublewords.
1213 // Rxx^=xor(Rss,Rtt)
1214 let validSubTargets = HasV4SubT in
1215 def XORd_XORdd: MInst_acc<(outs DoubleRegs:$dst),
1216 (ins DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
1217 "$dst ^= xor($src2, $src3)",
1218 [(set (i64 DoubleRegs:$dst),
1219 (xor (i64 DoubleRegs:$src1), (xor (i64 DoubleRegs:$src2),
1220 (i64 DoubleRegs:$src3))))],
1225 // Logical-logical words.
1226 // Rx=or(Ru,and(Rx,#s10))
1227 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 10,
1228 validSubTargets = HasV4SubT in
1229 def ORr_ANDri_V4 : MInst_acc<(outs IntRegs:$dst),
1230 (ins IntRegs:$src1, IntRegs: $src2, s10Ext:$src3),
1231 "$dst = or($src1, and($src2, #$src3))",
1232 [(set (i32 IntRegs:$dst),
1233 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1234 s10ExtPred:$src3)))],
1238 // Rx[&|^]=and(Rs,Rt)
1240 let validSubTargets = HasV4SubT in
1241 def ANDr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
1242 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1243 "$dst &= and($src2, $src3)",
1244 [(set (i32 IntRegs:$dst),
1245 (and (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1246 (i32 IntRegs:$src3))))],
1251 let validSubTargets = HasV4SubT, CextOpcode = "ORr_ANDr", InputType = "reg" in
1252 def ORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
1253 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1254 "$dst |= and($src2, $src3)",
1255 [(set (i32 IntRegs:$dst),
1256 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1257 (i32 IntRegs:$src3))))],
1259 Requires<[HasV4T]>, ImmRegRel;
1262 let validSubTargets = HasV4SubT in
1263 def XORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
1264 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1265 "$dst ^= and($src2, $src3)",
1266 [(set (i32 IntRegs:$dst),
1267 (xor (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1268 (i32 IntRegs:$src3))))],
1272 // Rx[&|^]=and(Rs,~Rt)
1274 let validSubTargets = HasV4SubT in
1275 def ANDr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
1276 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1277 "$dst &= and($src2, ~$src3)",
1278 [(set (i32 IntRegs:$dst),
1279 (and (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1280 (not (i32 IntRegs:$src3)))))],
1285 let validSubTargets = HasV4SubT in
1286 def ORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
1287 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1288 "$dst |= and($src2, ~$src3)",
1289 [(set (i32 IntRegs:$dst),
1290 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1291 (not (i32 IntRegs:$src3)))))],
1296 let validSubTargets = HasV4SubT in
1297 def XORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
1298 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1299 "$dst ^= and($src2, ~$src3)",
1300 [(set (i32 IntRegs:$dst),
1301 (xor (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1302 (not (i32 IntRegs:$src3)))))],
1306 // Rx[&|^]=or(Rs,Rt)
1308 let validSubTargets = HasV4SubT in
1309 def ANDr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1310 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1311 "$dst &= or($src2, $src3)",
1312 [(set (i32 IntRegs:$dst),
1313 (and (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
1314 (i32 IntRegs:$src3))))],
1319 let validSubTargets = HasV4SubT, CextOpcode = "ORr_ORr", InputType = "reg" in
1320 def ORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1321 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1322 "$dst |= or($src2, $src3)",
1323 [(set (i32 IntRegs:$dst),
1324 (or (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
1325 (i32 IntRegs:$src3))))],
1327 Requires<[HasV4T]>, ImmRegRel;
1330 let validSubTargets = HasV4SubT in
1331 def XORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1332 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1333 "$dst ^= or($src2, $src3)",
1334 [(set (i32 IntRegs:$dst),
1335 (xor (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
1336 (i32 IntRegs:$src3))))],
1340 // Rx[&|^]=xor(Rs,Rt)
1342 let validSubTargets = HasV4SubT in
1343 def ANDr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1344 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1345 "$dst &= xor($src2, $src3)",
1346 [(set (i32 IntRegs:$dst),
1347 (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
1348 (i32 IntRegs:$src3))))],
1353 let validSubTargets = HasV4SubT in
1354 def ORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1355 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1356 "$dst |= xor($src2, $src3)",
1357 [(set (i32 IntRegs:$dst),
1358 (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
1359 (i32 IntRegs:$src3))))],
1364 let validSubTargets = HasV4SubT in
1365 def XORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1366 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1367 "$dst ^= xor($src2, $src3)",
1368 [(set (i32 IntRegs:$dst),
1369 (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
1370 (i32 IntRegs:$src3))))],
1375 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 10,
1376 validSubTargets = HasV4SubT, CextOpcode = "ORr_ANDr", InputType = "imm" in
1377 def ORr_ANDri2_V4 : MInst_acc<(outs IntRegs:$dst),
1378 (ins IntRegs:$src1, IntRegs: $src2, s10Ext:$src3),
1379 "$dst |= and($src2, #$src3)",
1380 [(set (i32 IntRegs:$dst),
1381 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1382 s10ExtPred:$src3)))],
1384 Requires<[HasV4T]>, ImmRegRel;
1387 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 10,
1388 validSubTargets = HasV4SubT, CextOpcode = "ORr_ORr", InputType = "imm" in
1389 def ORr_ORri_V4 : MInst_acc<(outs IntRegs:$dst),
1390 (ins IntRegs:$src1, IntRegs: $src2, s10Ext:$src3),
1391 "$dst |= or($src2, #$src3)",
1392 [(set (i32 IntRegs:$dst),
1393 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1394 s10ExtPred:$src3)))],
1396 Requires<[HasV4T]>, ImmRegRel;
1400 // Rd=modwrap(Rs,Rt)
1402 // Rd=cround(Rs,#u5)
1404 // Rd=round(Rs,#u5)[:sat]
1405 // Rd=round(Rs,Rt)[:sat]
1406 // Vector reduce add unsigned halfwords
1407 // Rd=vraddh(Rss,Rtt)
1409 // Rdd=vaddb(Rss,Rtt)
1410 // Vector conditional negate
1411 // Rdd=vcnegh(Rss,Rt)
1412 // Rxx+=vrcnegh(Rss,Rt)
1413 // Vector maximum bytes
1414 // Rdd=vmaxb(Rtt,Rss)
1415 // Vector reduce maximum halfwords
1416 // Rxx=vrmaxh(Rss,Ru)
1417 // Rxx=vrmaxuh(Rss,Ru)
1418 // Vector reduce maximum words
1419 // Rxx=vrmaxuw(Rss,Ru)
1420 // Rxx=vrmaxw(Rss,Ru)
1421 // Vector minimum bytes
1422 // Rdd=vminb(Rtt,Rss)
1423 // Vector reduce minimum halfwords
1424 // Rxx=vrminh(Rss,Ru)
1425 // Rxx=vrminuh(Rss,Ru)
1426 // Vector reduce minimum words
1427 // Rxx=vrminuw(Rss,Ru)
1428 // Rxx=vrminw(Rss,Ru)
1429 // Vector subtract bytes
1430 // Rdd=vsubb(Rss,Rtt)
1432 //===----------------------------------------------------------------------===//
1434 //===----------------------------------------------------------------------===//
1437 //===----------------------------------------------------------------------===//
1439 //===----------------------------------------------------------------------===//
1441 // Multiply and user lower result.
1442 // Rd=add(#u6,mpyi(Rs,#U6))
1443 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 6,
1444 validSubTargets = HasV4SubT in
1445 def ADDi_MPYri_V4 : MInst<(outs IntRegs:$dst),
1446 (ins u6Ext:$src1, IntRegs:$src2, u6Imm:$src3),
1447 "$dst = add(#$src1, mpyi($src2, #$src3))",
1448 [(set (i32 IntRegs:$dst),
1449 (add (mul (i32 IntRegs:$src2), u6ImmPred:$src3),
1450 u6ExtPred:$src1))]>,
1453 // Rd=add(##,mpyi(Rs,#U6))
1454 def : Pat <(add (mul (i32 IntRegs:$src2), u6ImmPred:$src3),
1455 (HexagonCONST32 tglobaladdr:$src1)),
1456 (i32 (ADDi_MPYri_V4 tglobaladdr:$src1, IntRegs:$src2,
1459 // Rd=add(#u6,mpyi(Rs,Rt))
1460 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 6,
1461 validSubTargets = HasV4SubT, InputType = "imm", CextOpcode = "ADD_MPY" in
1462 def ADDi_MPYrr_V4 : MInst<(outs IntRegs:$dst),
1463 (ins u6Ext:$src1, IntRegs:$src2, IntRegs:$src3),
1464 "$dst = add(#$src1, mpyi($src2, $src3))",
1465 [(set (i32 IntRegs:$dst),
1466 (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
1467 u6ExtPred:$src1))]>,
1468 Requires<[HasV4T]>, ImmRegRel;
1470 // Rd=add(##,mpyi(Rs,Rt))
1471 def : Pat <(add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
1472 (HexagonCONST32 tglobaladdr:$src1)),
1473 (i32 (ADDi_MPYrr_V4 tglobaladdr:$src1, IntRegs:$src2,
1476 // Rd=add(Ru,mpyi(#u6:2,Rs))
1477 let validSubTargets = HasV4SubT in
1478 def ADDr_MPYir_V4 : MInst<(outs IntRegs:$dst),
1479 (ins IntRegs:$src1, u6Imm:$src2, IntRegs:$src3),
1480 "$dst = add($src1, mpyi(#$src2, $src3))",
1481 [(set (i32 IntRegs:$dst),
1482 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src3),
1483 u6_2ImmPred:$src2)))]>,
1486 // Rd=add(Ru,mpyi(Rs,#u6))
1487 let isExtendable = 1, opExtendable = 3, isExtentSigned = 0, opExtentBits = 6,
1488 validSubTargets = HasV4SubT, InputType = "imm", CextOpcode = "ADD_MPY" in
1489 def ADDr_MPYri_V4 : MInst<(outs IntRegs:$dst),
1490 (ins IntRegs:$src1, IntRegs:$src2, u6Ext:$src3),
1491 "$dst = add($src1, mpyi($src2, #$src3))",
1492 [(set (i32 IntRegs:$dst),
1493 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
1494 u6ExtPred:$src3)))]>,
1495 Requires<[HasV4T]>, ImmRegRel;
1497 // Rx=add(Ru,mpyi(Rx,Rs))
1498 let validSubTargets = HasV4SubT, InputType = "reg", CextOpcode = "ADD_MPY" in
1499 def ADDr_MPYrr_V4 : MInst_acc<(outs IntRegs:$dst),
1500 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1501 "$dst = add($src1, mpyi($src2, $src3))",
1502 [(set (i32 IntRegs:$dst),
1503 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
1504 (i32 IntRegs:$src3))))],
1506 Requires<[HasV4T]>, ImmRegRel;
1509 // Polynomial multiply words
1511 // Rxx^=pmpyw(Rs,Rt)
1513 // Vector reduce multiply word by signed half (32x16)
1514 // Rdd=vrmpyweh(Rss,Rtt)[:<<1]
1515 // Rdd=vrmpywoh(Rss,Rtt)[:<<1]
1516 // Rxx+=vrmpyweh(Rss,Rtt)[:<<1]
1517 // Rxx+=vrmpywoh(Rss,Rtt)[:<<1]
1519 // Multiply and use upper result
1520 // Rd=mpy(Rs,Rt.H):<<1:sat
1521 // Rd=mpy(Rs,Rt.L):<<1:sat
1522 // Rd=mpy(Rs,Rt):<<1
1523 // Rd=mpy(Rs,Rt):<<1:sat
1525 // Rx+=mpy(Rs,Rt):<<1:sat
1526 // Rx-=mpy(Rs,Rt):<<1:sat
1528 // Vector multiply bytes
1529 // Rdd=vmpybsu(Rs,Rt)
1530 // Rdd=vmpybu(Rs,Rt)
1531 // Rxx+=vmpybsu(Rs,Rt)
1532 // Rxx+=vmpybu(Rs,Rt)
1534 // Vector polynomial multiply halfwords
1535 // Rdd=vpmpyh(Rs,Rt)
1536 // Rxx^=vpmpyh(Rs,Rt)
1538 //===----------------------------------------------------------------------===//
1540 //===----------------------------------------------------------------------===//
1543 //===----------------------------------------------------------------------===//
1545 //===----------------------------------------------------------------------===//
1547 // Shift by immediate and accumulate.
1548 // Rx=add(#u8,asl(Rx,#U5))
1549 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1550 validSubTargets = HasV4SubT in
1551 def ADDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
1552 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1553 "$dst = add(#$src1, asl($src2, #$src3))",
1554 [(set (i32 IntRegs:$dst),
1555 (add (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
1560 // Rx=add(#u8,lsr(Rx,#U5))
1561 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1562 validSubTargets = HasV4SubT in
1563 def ADDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
1564 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1565 "$dst = add(#$src1, lsr($src2, #$src3))",
1566 [(set (i32 IntRegs:$dst),
1567 (add (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
1572 // Rx=sub(#u8,asl(Rx,#U5))
1573 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1574 validSubTargets = HasV4SubT in
1575 def SUBi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
1576 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1577 "$dst = sub(#$src1, asl($src2, #$src3))",
1578 [(set (i32 IntRegs:$dst),
1579 (sub (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
1584 // Rx=sub(#u8,lsr(Rx,#U5))
1585 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1586 validSubTargets = HasV4SubT in
1587 def SUBi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
1588 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1589 "$dst = sub(#$src1, lsr($src2, #$src3))",
1590 [(set (i32 IntRegs:$dst),
1591 (sub (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
1597 //Shift by immediate and logical.
1598 //Rx=and(#u8,asl(Rx,#U5))
1599 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1600 validSubTargets = HasV4SubT in
1601 def ANDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
1602 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1603 "$dst = and(#$src1, asl($src2, #$src3))",
1604 [(set (i32 IntRegs:$dst),
1605 (and (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
1610 //Rx=and(#u8,lsr(Rx,#U5))
1611 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1612 validSubTargets = HasV4SubT in
1613 def ANDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
1614 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1615 "$dst = and(#$src1, lsr($src2, #$src3))",
1616 [(set (i32 IntRegs:$dst),
1617 (and (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
1622 //Rx=or(#u8,asl(Rx,#U5))
1623 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1624 AddedComplexity = 30, validSubTargets = HasV4SubT in
1625 def ORi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
1626 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1627 "$dst = or(#$src1, asl($src2, #$src3))",
1628 [(set (i32 IntRegs:$dst),
1629 (or (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
1634 //Rx=or(#u8,lsr(Rx,#U5))
1635 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1636 AddedComplexity = 30, validSubTargets = HasV4SubT in
1637 def ORi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
1638 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1639 "$dst = or(#$src1, lsr($src2, #$src3))",
1640 [(set (i32 IntRegs:$dst),
1641 (or (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
1647 //Shift by register.
1649 let validSubTargets = HasV4SubT in {
1650 def LSLi_V4 : MInst<(outs IntRegs:$dst), (ins s6Imm:$src1, IntRegs:$src2),
1651 "$dst = lsl(#$src1, $src2)",
1652 [(set (i32 IntRegs:$dst), (shl s6ImmPred:$src1,
1653 (i32 IntRegs:$src2)))]>,
1657 //Shift by register and logical.
1659 def ASLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
1660 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
1661 "$dst ^= asl($src2, $src3)",
1662 [(set (i64 DoubleRegs:$dst),
1663 (xor (i64 DoubleRegs:$src1), (shl (i64 DoubleRegs:$src2),
1664 (i32 IntRegs:$src3))))],
1669 def ASRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
1670 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
1671 "$dst ^= asr($src2, $src3)",
1672 [(set (i64 DoubleRegs:$dst),
1673 (xor (i64 DoubleRegs:$src1), (sra (i64 DoubleRegs:$src2),
1674 (i32 IntRegs:$src3))))],
1679 def LSLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
1680 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
1681 "$dst ^= lsl($src2, $src3)",
1682 [(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1),
1683 (shl (i64 DoubleRegs:$src2),
1684 (i32 IntRegs:$src3))))],
1689 def LSRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
1690 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
1691 "$dst ^= lsr($src2, $src3)",
1692 [(set (i64 DoubleRegs:$dst),
1693 (xor (i64 DoubleRegs:$src1), (srl (i64 DoubleRegs:$src2),
1694 (i32 IntRegs:$src3))))],
1699 //===----------------------------------------------------------------------===//
1701 //===----------------------------------------------------------------------===//
1703 //===----------------------------------------------------------------------===//
1704 // MEMOP: Word, Half, Byte
1705 //===----------------------------------------------------------------------===//
1707 def MEMOPIMM : SDNodeXForm<imm, [{
1708 // Call the transformation function XformM5ToU5Imm to get the negative
1709 // immediate's positive counterpart.
1710 int32_t imm = N->getSExtValue();
1711 return XformM5ToU5Imm(imm);
1714 def MEMOPIMM_HALF : SDNodeXForm<imm, [{
1715 // -1 .. -31 represented as 65535..65515
1716 // assigning to a short restores our desired signed value.
1717 // Call the transformation function XformM5ToU5Imm to get the negative
1718 // immediate's positive counterpart.
1719 int16_t imm = N->getSExtValue();
1720 return XformM5ToU5Imm(imm);
1723 def MEMOPIMM_BYTE : SDNodeXForm<imm, [{
1724 // -1 .. -31 represented as 255..235
1725 // assigning to a char restores our desired signed value.
1726 // Call the transformation function XformM5ToU5Imm to get the negative
1727 // immediate's positive counterpart.
1728 int8_t imm = N->getSExtValue();
1729 return XformM5ToU5Imm(imm);
1732 def SETMEMIMM : SDNodeXForm<imm, [{
1733 // Return the bit position we will set [0-31].
1735 int32_t imm = N->getSExtValue();
1736 return XformMskToBitPosU5Imm(imm);
1739 def CLRMEMIMM : SDNodeXForm<imm, [{
1740 // Return the bit position we will clear [0-31].
1742 // we bit negate the value first
1743 int32_t imm = ~(N->getSExtValue());
1744 return XformMskToBitPosU5Imm(imm);
1747 def SETMEMIMM_SHORT : SDNodeXForm<imm, [{
1748 // Return the bit position we will set [0-15].
1750 int16_t imm = N->getSExtValue();
1751 return XformMskToBitPosU4Imm(imm);
1754 def CLRMEMIMM_SHORT : SDNodeXForm<imm, [{
1755 // Return the bit position we will clear [0-15].
1757 // we bit negate the value first
1758 int16_t imm = ~(N->getSExtValue());
1759 return XformMskToBitPosU4Imm(imm);
1762 def SETMEMIMM_BYTE : SDNodeXForm<imm, [{
1763 // Return the bit position we will set [0-7].
1765 int8_t imm = N->getSExtValue();
1766 return XformMskToBitPosU3Imm(imm);
1769 def CLRMEMIMM_BYTE : SDNodeXForm<imm, [{
1770 // Return the bit position we will clear [0-7].
1772 // we bit negate the value first
1773 int8_t imm = ~(N->getSExtValue());
1774 return XformMskToBitPosU3Imm(imm);
1777 //===----------------------------------------------------------------------===//
1778 // Template class for MemOp instructions with the register value.
1779 //===----------------------------------------------------------------------===//
1780 class MemOp_rr_base <string opc, bits<2> opcBits, Operand ImmOp,
1781 string memOp, bits<2> memOpBits> :
1783 (ins IntRegs:$base, ImmOp:$offset, IntRegs:$delta),
1784 opc#"($base+#$offset)"#memOp#"$delta",
1786 Requires<[HasV4T, UseMEMOP]> {
1791 bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
1793 let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
1794 !if (!eq(opcBits, 0b01), offset{6-1},
1795 !if (!eq(opcBits, 0b10), offset{7-2},0)));
1797 let IClass = 0b0011;
1798 let Inst{27-24} = 0b1110;
1799 let Inst{22-21} = opcBits;
1800 let Inst{20-16} = base;
1802 let Inst{12-7} = offsetBits;
1803 let Inst{6-5} = memOpBits;
1804 let Inst{4-0} = delta;
1807 //===----------------------------------------------------------------------===//
1808 // Template class for MemOp instructions with the immediate value.
1809 //===----------------------------------------------------------------------===//
1810 class MemOp_ri_base <string opc, bits<2> opcBits, Operand ImmOp,
1811 string memOp, bits<2> memOpBits> :
1813 (ins IntRegs:$base, ImmOp:$offset, u5Imm:$delta),
1814 opc#"($base+#$offset)"#memOp#"#$delta"
1815 #!if(memOpBits{1},")", ""), // clrbit, setbit - include ')'
1817 Requires<[HasV4T, UseMEMOP]> {
1822 bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
1824 let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
1825 !if (!eq(opcBits, 0b01), offset{6-1},
1826 !if (!eq(opcBits, 0b10), offset{7-2},0)));
1828 let IClass = 0b0011;
1829 let Inst{27-24} = 0b1111;
1830 let Inst{22-21} = opcBits;
1831 let Inst{20-16} = base;
1833 let Inst{12-7} = offsetBits;
1834 let Inst{6-5} = memOpBits;
1835 let Inst{4-0} = delta;
1838 // multiclass to define MemOp instructions with register operand.
1839 multiclass MemOp_rr<string opc, bits<2> opcBits, Operand ImmOp> {
1840 def _ADD#NAME#_V4 : MemOp_rr_base <opc, opcBits, ImmOp, " += ", 0b00>; // add
1841 def _SUB#NAME#_V4 : MemOp_rr_base <opc, opcBits, ImmOp, " -= ", 0b01>; // sub
1842 def _AND#NAME#_V4 : MemOp_rr_base <opc, opcBits, ImmOp, " &= ", 0b10>; // and
1843 def _OR#NAME#_V4 : MemOp_rr_base <opc, opcBits, ImmOp, " |= ", 0b11>; // or
1846 // multiclass to define MemOp instructions with immediate Operand.
1847 multiclass MemOp_ri<string opc, bits<2> opcBits, Operand ImmOp> {
1848 def _ADD#NAME#_V4 : MemOp_ri_base <opc, opcBits, ImmOp, " += ", 0b00 >;
1849 def _SUB#NAME#_V4 : MemOp_ri_base <opc, opcBits, ImmOp, " -= ", 0b01 >;
1850 def _CLRBIT#NAME#_V4 : MemOp_ri_base<opc, opcBits, ImmOp, " =clrbit(", 0b10>;
1851 def _SETBIT#NAME#_V4 : MemOp_ri_base<opc, opcBits, ImmOp, " =setbit(", 0b11>;
1854 multiclass MemOp_base <string opc, bits<2> opcBits, Operand ImmOp> {
1855 defm r : MemOp_rr <opc, opcBits, ImmOp>;
1856 defm i : MemOp_ri <opc, opcBits, ImmOp>;
1859 // Define MemOp instructions.
1860 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0,
1861 validSubTargets =HasV4SubT in {
1862 let opExtentBits = 6, accessSize = ByteAccess in
1863 defm MemOPb : MemOp_base <"memb", 0b00, u6_0Ext>;
1865 let opExtentBits = 7, accessSize = HalfWordAccess in
1866 defm MemOPh : MemOp_base <"memh", 0b01, u6_1Ext>;
1868 let opExtentBits = 8, accessSize = WordAccess in
1869 defm MemOPw : MemOp_base <"memw", 0b10, u6_2Ext>;
1872 //===----------------------------------------------------------------------===//
1873 // Multiclass to define 'Def Pats' for ALU operations on the memory
1874 // Here value used for the ALU operation is an immediate value.
1875 // mem[bh](Rs+#0) += #U5
1876 // mem[bh](Rs+#u6) += #U5
1877 //===----------------------------------------------------------------------===//
1879 multiclass MemOpi_u5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf ExtPred,
1880 InstHexagon MI, SDNode OpNode> {
1881 let AddedComplexity = 180 in
1882 def : Pat < (stOp (OpNode (ldOp IntRegs:$addr), u5ImmPred:$addend),
1884 (MI IntRegs:$addr, #0, u5ImmPred:$addend )>;
1886 let AddedComplexity = 190 in
1887 def : Pat <(stOp (OpNode (ldOp (add IntRegs:$base, ExtPred:$offset)),
1889 (add IntRegs:$base, ExtPred:$offset)),
1890 (MI IntRegs:$base, ExtPred:$offset, u5ImmPred:$addend)>;
1893 multiclass MemOpi_u5ALUOp<PatFrag ldOp, PatFrag stOp, PatLeaf ExtPred,
1894 InstHexagon addMI, InstHexagon subMI> {
1895 defm : MemOpi_u5Pats<ldOp, stOp, ExtPred, addMI, add>;
1896 defm : MemOpi_u5Pats<ldOp, stOp, ExtPred, subMI, sub>;
1899 multiclass MemOpi_u5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
1901 defm : MemOpi_u5ALUOp <ldOpHalf, truncstorei16, u6_1ExtPred,
1902 MemOPh_ADDi_V4, MemOPh_SUBi_V4>;
1904 defm : MemOpi_u5ALUOp <ldOpByte, truncstorei8, u6ExtPred,
1905 MemOPb_ADDi_V4, MemOPb_SUBi_V4>;
1908 let Predicates = [HasV4T, UseMEMOP] in {
1909 defm : MemOpi_u5ExtType<zextloadi8, zextloadi16>; // zero extend
1910 defm : MemOpi_u5ExtType<sextloadi8, sextloadi16>; // sign extend
1911 defm : MemOpi_u5ExtType<extloadi8, extloadi16>; // any extend
1914 defm : MemOpi_u5ALUOp <load, store, u6_2ExtPred, MemOPw_ADDi_V4,
1918 //===----------------------------------------------------------------------===//
1919 // multiclass to define 'Def Pats' for ALU operations on the memory.
1920 // Here value used for the ALU operation is a negative value.
1921 // mem[bh](Rs+#0) += #m5
1922 // mem[bh](Rs+#u6) += #m5
1923 //===----------------------------------------------------------------------===//
1925 multiclass MemOpi_m5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf extPred,
1926 PatLeaf immPred, ComplexPattern addrPred,
1927 SDNodeXForm xformFunc, InstHexagon MI> {
1928 let AddedComplexity = 190 in
1929 def : Pat <(stOp (add (ldOp IntRegs:$addr), immPred:$subend),
1931 (MI IntRegs:$addr, #0, (xformFunc immPred:$subend) )>;
1933 let AddedComplexity = 195 in
1934 def : Pat<(stOp (add (ldOp (add IntRegs:$base, extPred:$offset)),
1936 (add IntRegs:$base, extPred:$offset)),
1937 (MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$subend))>;
1940 multiclass MemOpi_m5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
1942 defm : MemOpi_m5Pats <ldOpHalf, truncstorei16, u6_1ExtPred, m5HImmPred,
1943 ADDRriU6_1, MEMOPIMM_HALF, MemOPh_SUBi_V4>;
1945 defm : MemOpi_m5Pats <ldOpByte, truncstorei8, u6ExtPred, m5BImmPred,
1946 ADDRriU6_0, MEMOPIMM_BYTE, MemOPb_SUBi_V4>;
1949 let Predicates = [HasV4T, UseMEMOP] in {
1950 defm : MemOpi_m5ExtType<zextloadi8, zextloadi16>; // zero extend
1951 defm : MemOpi_m5ExtType<sextloadi8, sextloadi16>; // sign extend
1952 defm : MemOpi_m5ExtType<extloadi8, extloadi16>; // any extend
1955 defm : MemOpi_m5Pats <load, store, u6_2ExtPred, m5ImmPred,
1956 ADDRriU6_2, MEMOPIMM, MemOPw_SUBi_V4>;
1959 //===----------------------------------------------------------------------===//
1960 // Multiclass to define 'def Pats' for bit operations on the memory.
1961 // mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
1962 // mem[bhw](Rs+#u6) = [clrbit|setbit](#U5)
1963 //===----------------------------------------------------------------------===//
1965 multiclass MemOpi_bitPats <PatFrag ldOp, PatFrag stOp, PatLeaf immPred,
1966 PatLeaf extPred, ComplexPattern addrPred,
1967 SDNodeXForm xformFunc, InstHexagon MI, SDNode OpNode> {
1969 // mem[bhw](Rs+#u6:[012]) = [clrbit|setbit](#U5)
1970 let AddedComplexity = 250 in
1971 def : Pat<(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
1973 (add IntRegs:$base, extPred:$offset)),
1974 (MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$bitend))>;
1976 // mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
1977 let AddedComplexity = 225 in
1978 def : Pat <(stOp (OpNode (ldOp addrPred:$addr), immPred:$bitend),
1980 (MI IntRegs:$addr, #0, (xformFunc immPred:$bitend))>;
1983 multiclass MemOpi_bitExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
1985 defm : MemOpi_bitPats<ldOpByte, truncstorei8, Clr3ImmPred, u6ExtPred,
1986 ADDRriU6_0, CLRMEMIMM_BYTE, MemOPb_CLRBITi_V4, and>;
1988 defm : MemOpi_bitPats<ldOpByte, truncstorei8, Set3ImmPred, u6ExtPred,
1989 ADDRriU6_0, SETMEMIMM_BYTE, MemOPb_SETBITi_V4, or>;
1990 // Half Word - clrbit
1991 defm : MemOpi_bitPats<ldOpHalf, truncstorei16, Clr4ImmPred, u6_1ExtPred,
1992 ADDRriU6_1, CLRMEMIMM_SHORT, MemOPh_CLRBITi_V4, and>;
1993 // Half Word - setbit
1994 defm : MemOpi_bitPats<ldOpHalf, truncstorei16, Set4ImmPred, u6_1ExtPred,
1995 ADDRriU6_1, SETMEMIMM_SHORT, MemOPh_SETBITi_V4, or>;
1998 let Predicates = [HasV4T, UseMEMOP] in {
1999 // mem[bh](Rs+#0) = [clrbit|setbit](#U5)
2000 // mem[bh](Rs+#u6:[01]) = [clrbit|setbit](#U5)
2001 defm : MemOpi_bitExtType<zextloadi8, zextloadi16>; // zero extend
2002 defm : MemOpi_bitExtType<sextloadi8, sextloadi16>; // sign extend
2003 defm : MemOpi_bitExtType<extloadi8, extloadi16>; // any extend
2005 // memw(Rs+#0) = [clrbit|setbit](#U5)
2006 // memw(Rs+#u6:2) = [clrbit|setbit](#U5)
2007 defm : MemOpi_bitPats<load, store, Clr5ImmPred, u6_2ExtPred, ADDRriU6_2,
2008 CLRMEMIMM, MemOPw_CLRBITi_V4, and>;
2009 defm : MemOpi_bitPats<load, store, Set5ImmPred, u6_2ExtPred, ADDRriU6_2,
2010 SETMEMIMM, MemOPw_SETBITi_V4, or>;
2013 //===----------------------------------------------------------------------===//
2014 // Multiclass to define 'def Pats' for ALU operations on the memory
2015 // where addend is a register.
2016 // mem[bhw](Rs+#0) [+-&|]= Rt
2017 // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
2018 //===----------------------------------------------------------------------===//
2020 multiclass MemOpr_Pats <PatFrag ldOp, PatFrag stOp, ComplexPattern addrPred,
2021 PatLeaf extPred, InstHexagon MI, SDNode OpNode> {
2022 let AddedComplexity = 141 in
2023 // mem[bhw](Rs+#0) [+-&|]= Rt
2024 def : Pat <(stOp (OpNode (ldOp addrPred:$addr), (i32 IntRegs:$addend)),
2026 (MI IntRegs:$addr, #0, (i32 IntRegs:$addend) )>;
2028 // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
2029 let AddedComplexity = 150 in
2030 def : Pat <(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
2031 (i32 IntRegs:$orend)),
2032 (add IntRegs:$base, extPred:$offset)),
2033 (MI IntRegs:$base, extPred:$offset, (i32 IntRegs:$orend) )>;
2036 multiclass MemOPr_ALUOp<PatFrag ldOp, PatFrag stOp,
2037 ComplexPattern addrPred, PatLeaf extPred,
2038 InstHexagon addMI, InstHexagon subMI,
2039 InstHexagon andMI, InstHexagon orMI > {
2041 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, addMI, add>;
2042 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, subMI, sub>;
2043 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, andMI, and>;
2044 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, orMI, or>;
2047 multiclass MemOPr_ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2049 defm : MemOPr_ALUOp <ldOpHalf, truncstorei16, ADDRriU6_1, u6_1ExtPred,
2050 MemOPh_ADDr_V4, MemOPh_SUBr_V4,
2051 MemOPh_ANDr_V4, MemOPh_ORr_V4>;
2053 defm : MemOPr_ALUOp <ldOpByte, truncstorei8, ADDRriU6_0, u6ExtPred,
2054 MemOPb_ADDr_V4, MemOPb_SUBr_V4,
2055 MemOPb_ANDr_V4, MemOPb_ORr_V4>;
2058 // Define 'def Pats' for MemOps with register addend.
2059 let Predicates = [HasV4T, UseMEMOP] in {
2061 defm : MemOPr_ExtType<zextloadi8, zextloadi16>; // zero extend
2062 defm : MemOPr_ExtType<sextloadi8, sextloadi16>; // sign extend
2063 defm : MemOPr_ExtType<extloadi8, extloadi16>; // any extend
2065 defm : MemOPr_ALUOp <load, store, ADDRriU6_2, u6_2ExtPred, MemOPw_ADDr_V4,
2066 MemOPw_SUBr_V4, MemOPw_ANDr_V4, MemOPw_ORr_V4 >;
2069 //===----------------------------------------------------------------------===//
2071 //===----------------------------------------------------------------------===//
2073 // Hexagon V4 only supports these flavors of byte/half compare instructions:
2074 // EQ/GT/GTU. Other flavors like GE/GEU/LT/LTU/LE/LEU are not supported by
2075 // hardware. However, compiler can still implement these patterns through
2076 // appropriate patterns combinations based on current implemented patterns.
2077 // The implemented patterns are: EQ/GT/GTU.
2078 // Missing patterns are: GE/GEU/LT/LTU/LE/LEU.
2080 // Following instruction is not being extended as it results into the
2081 // incorrect code for negative numbers.
2082 // Pd=cmpb.eq(Rs,#u8)
2085 let isCompare = 1, validSubTargets = HasV4SubT in
2086 def CMPnotEQ_rr : ALU32_rr<(outs PredRegs:$dst),
2087 (ins IntRegs:$src1, IntRegs:$src2),
2088 "$dst = !cmp.eq($src1, $src2)",
2089 [(set (i1 PredRegs:$dst),
2090 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2)))]>,
2093 // p=!cmp.eq(r1,#s10)
2094 let isCompare = 1, validSubTargets = HasV4SubT in
2095 def CMPnotEQ_ri : ALU32_ri<(outs PredRegs:$dst),
2096 (ins IntRegs:$src1, s10Ext:$src2),
2097 "$dst = !cmp.eq($src1, #$src2)",
2098 [(set (i1 PredRegs:$dst),
2099 (setne (i32 IntRegs:$src1), s10ImmPred:$src2))]>,
2103 let isCompare = 1, validSubTargets = HasV4SubT in
2104 def CMPnotGT_rr : ALU32_rr<(outs PredRegs:$dst),
2105 (ins IntRegs:$src1, IntRegs:$src2),
2106 "$dst = !cmp.gt($src1, $src2)",
2107 [(set (i1 PredRegs:$dst),
2108 (not (setgt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>,
2111 // p=!cmp.gt(r1,#s10)
2112 let isCompare = 1, validSubTargets = HasV4SubT in
2113 def CMPnotGT_ri : ALU32_ri<(outs PredRegs:$dst),
2114 (ins IntRegs:$src1, s10Ext:$src2),
2115 "$dst = !cmp.gt($src1, #$src2)",
2116 [(set (i1 PredRegs:$dst),
2117 (not (setgt (i32 IntRegs:$src1), s10ImmPred:$src2)))]>,
2120 // p=!cmp.gtu(r1,r2)
2121 let isCompare = 1, validSubTargets = HasV4SubT in
2122 def CMPnotGTU_rr : ALU32_rr<(outs PredRegs:$dst),
2123 (ins IntRegs:$src1, IntRegs:$src2),
2124 "$dst = !cmp.gtu($src1, $src2)",
2125 [(set (i1 PredRegs:$dst),
2126 (not (setugt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>,
2129 // p=!cmp.gtu(r1,#u9)
2130 let isCompare = 1, validSubTargets = HasV4SubT in
2131 def CMPnotGTU_ri : ALU32_ri<(outs PredRegs:$dst),
2132 (ins IntRegs:$src1, u9Ext:$src2),
2133 "$dst = !cmp.gtu($src1, #$src2)",
2134 [(set (i1 PredRegs:$dst),
2135 (not (setugt (i32 IntRegs:$src1), u9ImmPred:$src2)))]>,
2138 let isCompare = 1, validSubTargets = HasV4SubT in
2139 def CMPbEQri_V4 : MInst<(outs PredRegs:$dst),
2140 (ins IntRegs:$src1, u8Imm:$src2),
2141 "$dst = cmpb.eq($src1, #$src2)",
2142 [(set (i1 PredRegs:$dst),
2143 (seteq (and (i32 IntRegs:$src1), 255), u8ImmPred:$src2))]>,
2146 def : Pat <(brcond (i1 (setne (and (i32 IntRegs:$src1), 255), u8ImmPred:$src2)),
2148 (JMP_f (CMPbEQri_V4 (i32 IntRegs:$src1), u8ImmPred:$src2),
2152 // Pd=cmpb.eq(Rs,Rt)
2153 let isCompare = 1, validSubTargets = HasV4SubT in
2154 def CMPbEQrr_ubub_V4 : MInst<(outs PredRegs:$dst),
2155 (ins IntRegs:$src1, IntRegs:$src2),
2156 "$dst = cmpb.eq($src1, $src2)",
2157 [(set (i1 PredRegs:$dst),
2158 (seteq (and (xor (i32 IntRegs:$src1),
2159 (i32 IntRegs:$src2)), 255), 0))]>,
2162 // Pd=cmpb.eq(Rs,Rt)
2163 let isCompare = 1, validSubTargets = HasV4SubT in
2164 def CMPbEQrr_sbsb_V4 : MInst<(outs PredRegs:$dst),
2165 (ins IntRegs:$src1, IntRegs:$src2),
2166 "$dst = cmpb.eq($src1, $src2)",
2167 [(set (i1 PredRegs:$dst),
2168 (seteq (shl (i32 IntRegs:$src1), (i32 24)),
2169 (shl (i32 IntRegs:$src2), (i32 24))))]>,
2172 // Pd=cmpb.gt(Rs,Rt)
2173 let isCompare = 1, validSubTargets = HasV4SubT in
2174 def CMPbGTrr_V4 : MInst<(outs PredRegs:$dst),
2175 (ins IntRegs:$src1, IntRegs:$src2),
2176 "$dst = cmpb.gt($src1, $src2)",
2177 [(set (i1 PredRegs:$dst),
2178 (setgt (shl (i32 IntRegs:$src1), (i32 24)),
2179 (shl (i32 IntRegs:$src2), (i32 24))))]>,
2182 // Pd=cmpb.gtu(Rs,#u7)
2183 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 7,
2184 isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPbGTU", InputType = "imm" in
2185 def CMPbGTUri_V4 : MInst<(outs PredRegs:$dst),
2186 (ins IntRegs:$src1, u7Ext:$src2),
2187 "$dst = cmpb.gtu($src1, #$src2)",
2188 [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),
2189 u7ExtPred:$src2))]>,
2190 Requires<[HasV4T]>, ImmRegRel;
2192 // SDNode for converting immediate C to C-1.
2193 def DEC_CONST_BYTE : SDNodeXForm<imm, [{
2194 // Return the byte immediate const-1 as an SDNode.
2195 int32_t imm = N->getSExtValue();
2196 return XformU7ToU7M1Imm(imm);
2200 // zext( seteq ( and(Rs, 255), u8))
2202 // Pd=cmpb.eq(Rs, #u8)
2203 // if (Pd.new) Rd=#1
2204 // if (!Pd.new) Rd=#0
2205 def : Pat <(i32 (zext (i1 (seteq (i32 (and (i32 IntRegs:$Rs), 255)),
2207 (i32 (TFR_condset_ii (i1 (CMPbEQri_V4 (i32 IntRegs:$Rs),
2213 // zext( setne ( and(Rs, 255), u8))
2215 // Pd=cmpb.eq(Rs, #u8)
2216 // if (Pd.new) Rd=#0
2217 // if (!Pd.new) Rd=#1
2218 def : Pat <(i32 (zext (i1 (setne (i32 (and (i32 IntRegs:$Rs), 255)),
2220 (i32 (TFR_condset_ii (i1 (CMPbEQri_V4 (i32 IntRegs:$Rs),
2226 // zext( seteq (Rs, and(Rt, 255)))
2228 // Pd=cmpb.eq(Rs, Rt)
2229 // if (Pd.new) Rd=#1
2230 // if (!Pd.new) Rd=#0
2231 def : Pat <(i32 (zext (i1 (seteq (i32 IntRegs:$Rt),
2232 (i32 (and (i32 IntRegs:$Rs), 255)))))),
2233 (i32 (TFR_condset_ii (i1 (CMPbEQrr_ubub_V4 (i32 IntRegs:$Rs),
2234 (i32 IntRegs:$Rt))),
2239 // zext( setne (Rs, and(Rt, 255)))
2241 // Pd=cmpb.eq(Rs, Rt)
2242 // if (Pd.new) Rd=#0
2243 // if (!Pd.new) Rd=#1
2244 def : Pat <(i32 (zext (i1 (setne (i32 IntRegs:$Rt),
2245 (i32 (and (i32 IntRegs:$Rs), 255)))))),
2246 (i32 (TFR_condset_ii (i1 (CMPbEQrr_ubub_V4 (i32 IntRegs:$Rs),
2247 (i32 IntRegs:$Rt))),
2252 // zext( setugt ( and(Rs, 255), u8))
2254 // Pd=cmpb.gtu(Rs, #u8)
2255 // if (Pd.new) Rd=#1
2256 // if (!Pd.new) Rd=#0
2257 def : Pat <(i32 (zext (i1 (setugt (i32 (and (i32 IntRegs:$Rs), 255)),
2259 (i32 (TFR_condset_ii (i1 (CMPbGTUri_V4 (i32 IntRegs:$Rs),
2265 // zext( setugt ( and(Rs, 254), u8))
2267 // Pd=cmpb.gtu(Rs, #u8)
2268 // if (Pd.new) Rd=#1
2269 // if (!Pd.new) Rd=#0
2270 def : Pat <(i32 (zext (i1 (setugt (i32 (and (i32 IntRegs:$Rs), 254)),
2272 (i32 (TFR_condset_ii (i1 (CMPbGTUri_V4 (i32 IntRegs:$Rs),
2278 // zext( setult ( Rs, Rt))
2280 // Pd=cmp.ltu(Rs, Rt)
2281 // if (Pd.new) Rd=#1
2282 // if (!Pd.new) Rd=#0
2283 // cmp.ltu(Rs, Rt) -> cmp.gtu(Rt, Rs)
2284 def : Pat <(i32 (zext (i1 (setult (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2285 (i32 (TFR_condset_ii (i1 (CMPGTUrr (i32 IntRegs:$Rt),
2286 (i32 IntRegs:$Rs))),
2291 // zext( setlt ( Rs, Rt))
2293 // Pd=cmp.lt(Rs, Rt)
2294 // if (Pd.new) Rd=#1
2295 // if (!Pd.new) Rd=#0
2296 // cmp.lt(Rs, Rt) -> cmp.gt(Rt, Rs)
2297 def : Pat <(i32 (zext (i1 (setlt (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2298 (i32 (TFR_condset_ii (i1 (CMPGTrr (i32 IntRegs:$Rt),
2299 (i32 IntRegs:$Rs))),
2304 // zext( setugt ( Rs, Rt))
2306 // Pd=cmp.gtu(Rs, Rt)
2307 // if (Pd.new) Rd=#1
2308 // if (!Pd.new) Rd=#0
2309 def : Pat <(i32 (zext (i1 (setugt (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2310 (i32 (TFR_condset_ii (i1 (CMPGTUrr (i32 IntRegs:$Rs),
2311 (i32 IntRegs:$Rt))),
2315 // This pattern interefers with coremark performance, not implementing at this
2318 // zext( setgt ( Rs, Rt))
2320 // Pd=cmp.gt(Rs, Rt)
2321 // if (Pd.new) Rd=#1
2322 // if (!Pd.new) Rd=#0
2325 // zext( setuge ( Rs, Rt))
2327 // Pd=cmp.ltu(Rs, Rt)
2328 // if (Pd.new) Rd=#0
2329 // if (!Pd.new) Rd=#1
2330 // cmp.ltu(Rs, Rt) -> cmp.gtu(Rt, Rs)
2331 def : Pat <(i32 (zext (i1 (setuge (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2332 (i32 (TFR_condset_ii (i1 (CMPGTUrr (i32 IntRegs:$Rt),
2333 (i32 IntRegs:$Rs))),
2338 // zext( setge ( Rs, Rt))
2340 // Pd=cmp.lt(Rs, Rt)
2341 // if (Pd.new) Rd=#0
2342 // if (!Pd.new) Rd=#1
2343 // cmp.lt(Rs, Rt) -> cmp.gt(Rt, Rs)
2344 def : Pat <(i32 (zext (i1 (setge (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2345 (i32 (TFR_condset_ii (i1 (CMPGTrr (i32 IntRegs:$Rt),
2346 (i32 IntRegs:$Rs))),
2351 // zext( setule ( Rs, Rt))
2353 // Pd=cmp.gtu(Rs, Rt)
2354 // if (Pd.new) Rd=#0
2355 // if (!Pd.new) Rd=#1
2356 def : Pat <(i32 (zext (i1 (setule (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2357 (i32 (TFR_condset_ii (i1 (CMPGTUrr (i32 IntRegs:$Rs),
2358 (i32 IntRegs:$Rt))),
2363 // zext( setle ( Rs, Rt))
2365 // Pd=cmp.gt(Rs, Rt)
2366 // if (Pd.new) Rd=#0
2367 // if (!Pd.new) Rd=#1
2368 def : Pat <(i32 (zext (i1 (setle (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2369 (i32 (TFR_condset_ii (i1 (CMPGTrr (i32 IntRegs:$Rs),
2370 (i32 IntRegs:$Rt))),
2375 // zext( setult ( and(Rs, 255), u8))
2376 // Use the isdigit transformation below
2378 // Generate code of the form 'mux_ii(cmpbgtu(Rdd, C-1),0,1)'
2379 // for C code of the form r = ((c>='0') & (c<='9')) ? 1 : 0;.
2380 // The isdigit transformation relies on two 'clever' aspects:
2381 // 1) The data type is unsigned which allows us to eliminate a zero test after
2382 // biasing the expression by 48. We are depending on the representation of
2383 // the unsigned types, and semantics.
2384 // 2) The front end has converted <= 9 into < 10 on entry to LLVM
2387 // retval = ((c>='0') & (c<='9')) ? 1 : 0;
2388 // The code is transformed upstream of llvm into
2389 // retval = (c-48) < 10 ? 1 : 0;
2390 let AddedComplexity = 139 in
2391 def : Pat <(i32 (zext (i1 (setult (i32 (and (i32 IntRegs:$src1), 255)),
2392 u7StrictPosImmPred:$src2)))),
2393 (i32 (MUX_ii (i1 (CMPbGTUri_V4 (i32 IntRegs:$src1),
2394 (DEC_CONST_BYTE u7StrictPosImmPred:$src2))),
2398 // Pd=cmpb.gtu(Rs,Rt)
2399 let isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPbGTU",
2400 InputType = "reg" in
2401 def CMPbGTUrr_V4 : MInst<(outs PredRegs:$dst),
2402 (ins IntRegs:$src1, IntRegs:$src2),
2403 "$dst = cmpb.gtu($src1, $src2)",
2404 [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),
2405 (and (i32 IntRegs:$src2), 255)))]>,
2406 Requires<[HasV4T]>, ImmRegRel;
2408 // Following instruction is not being extended as it results into the incorrect
2409 // code for negative numbers.
2411 // Signed half compare(.eq) ri.
2412 // Pd=cmph.eq(Rs,#s8)
2413 let isCompare = 1, validSubTargets = HasV4SubT in
2414 def CMPhEQri_V4 : MInst<(outs PredRegs:$dst),
2415 (ins IntRegs:$src1, s8Imm:$src2),
2416 "$dst = cmph.eq($src1, #$src2)",
2417 [(set (i1 PredRegs:$dst), (seteq (and (i32 IntRegs:$src1), 65535),
2418 s8ImmPred:$src2))]>,
2421 // Signed half compare(.eq) rr.
2422 // Case 1: xor + and, then compare:
2424 // r0=and(r0,#0xffff)
2426 // Pd=cmph.eq(Rs,Rt)
2427 let isCompare = 1, validSubTargets = HasV4SubT in
2428 def CMPhEQrr_xor_V4 : MInst<(outs PredRegs:$dst),
2429 (ins IntRegs:$src1, IntRegs:$src2),
2430 "$dst = cmph.eq($src1, $src2)",
2431 [(set (i1 PredRegs:$dst), (seteq (and (xor (i32 IntRegs:$src1),
2432 (i32 IntRegs:$src2)),
2436 // Signed half compare(.eq) rr.
2437 // Case 2: shift left 16 bits then compare:
2441 // Pd=cmph.eq(Rs,Rt)
2442 let isCompare = 1, validSubTargets = HasV4SubT in
2443 def CMPhEQrr_shl_V4 : MInst<(outs PredRegs:$dst),
2444 (ins IntRegs:$src1, IntRegs:$src2),
2445 "$dst = cmph.eq($src1, $src2)",
2446 [(set (i1 PredRegs:$dst),
2447 (seteq (shl (i32 IntRegs:$src1), (i32 16)),
2448 (shl (i32 IntRegs:$src2), (i32 16))))]>,
2451 /* Incorrect Pattern -- immediate should be right shifted before being
2452 used in the cmph.gt instruction.
2453 // Signed half compare(.gt) ri.
2454 // Pd=cmph.gt(Rs,#s8)
2456 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8,
2457 isCompare = 1, validSubTargets = HasV4SubT in
2458 def CMPhGTri_V4 : MInst<(outs PredRegs:$dst),
2459 (ins IntRegs:$src1, s8Ext:$src2),
2460 "$dst = cmph.gt($src1, #$src2)",
2461 [(set (i1 PredRegs:$dst),
2462 (setgt (shl (i32 IntRegs:$src1), (i32 16)),
2463 s8ExtPred:$src2))]>,
2467 // Signed half compare(.gt) rr.
2468 // Pd=cmph.gt(Rs,Rt)
2469 let isCompare = 1, validSubTargets = HasV4SubT in
2470 def CMPhGTrr_shl_V4 : MInst<(outs PredRegs:$dst),
2471 (ins IntRegs:$src1, IntRegs:$src2),
2472 "$dst = cmph.gt($src1, $src2)",
2473 [(set (i1 PredRegs:$dst),
2474 (setgt (shl (i32 IntRegs:$src1), (i32 16)),
2475 (shl (i32 IntRegs:$src2), (i32 16))))]>,
2478 // Unsigned half compare rr (.gtu).
2479 // Pd=cmph.gtu(Rs,Rt)
2480 let isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPhGTU",
2481 InputType = "reg" in
2482 def CMPhGTUrr_V4 : MInst<(outs PredRegs:$dst),
2483 (ins IntRegs:$src1, IntRegs:$src2),
2484 "$dst = cmph.gtu($src1, $src2)",
2485 [(set (i1 PredRegs:$dst),
2486 (setugt (and (i32 IntRegs:$src1), 65535),
2487 (and (i32 IntRegs:$src2), 65535)))]>,
2488 Requires<[HasV4T]>, ImmRegRel;
2490 // Unsigned half compare ri (.gtu).
2491 // Pd=cmph.gtu(Rs,#u7)
2492 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 7,
2493 isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPhGTU",
2494 InputType = "imm" in
2495 def CMPhGTUri_V4 : MInst<(outs PredRegs:$dst),
2496 (ins IntRegs:$src1, u7Ext:$src2),
2497 "$dst = cmph.gtu($src1, #$src2)",
2498 [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 65535),
2499 u7ExtPred:$src2))]>,
2500 Requires<[HasV4T]>, ImmRegRel;
2502 let validSubTargets = HasV4SubT in
2503 def NTSTBIT_rr : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2504 "$dst = !tstbit($src1, $src2)",
2505 [(set (i1 PredRegs:$dst),
2506 (seteq (and (shl 1, (i32 IntRegs:$src2)), (i32 IntRegs:$src1)), 0))]>,
2509 let validSubTargets = HasV4SubT in
2510 def NTSTBIT_ri : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2511 "$dst = !tstbit($src1, $src2)",
2512 [(set (i1 PredRegs:$dst),
2513 (seteq (and (shl 1, u5ImmPred:$src2), (i32 IntRegs:$src1)), 0))]>,
2516 //===----------------------------------------------------------------------===//
2518 //===----------------------------------------------------------------------===//
2520 //Deallocate frame and return.
2522 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicable = 1,
2523 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1 in {
2524 def DEALLOC_RET_V4 : NVInst_V4<(outs), (ins i32imm:$amt1),
2530 // Restore registers and dealloc return function call.
2531 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
2532 Defs = [R29, R30, R31, PC] in {
2533 def RESTORE_DEALLOC_RET_JMP_V4 : JInst<(outs),
2534 (ins calltarget:$dst),
2535 "jump $dst // Restore_and_dealloc_return",
2540 // Restore registers and dealloc frame before a tail call.
2541 let isCall = 1, isBarrier = 1,
2542 Defs = [R29, R30, R31, PC] in {
2543 def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : JInst<(outs),
2544 (ins calltarget:$dst),
2545 "call $dst // Restore_and_dealloc_before_tailcall",
2550 // Save registers function call.
2551 let isCall = 1, isBarrier = 1,
2552 Uses = [R29, R31] in {
2553 def SAVE_REGISTERS_CALL_V4 : JInst<(outs),
2554 (ins calltarget:$dst),
2555 "call $dst // Save_calle_saved_registers",
2560 // if (Ps) dealloc_return
2561 let isReturn = 1, isTerminator = 1,
2562 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
2563 isPredicated = 1 in {
2564 def DEALLOC_RET_cPt_V4 : NVInst_V4<(outs),
2565 (ins PredRegs:$src1, i32imm:$amt1),
2566 "if ($src1) dealloc_return",
2571 // if (!Ps) dealloc_return
2572 let isReturn = 1, isTerminator = 1,
2573 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
2574 isPredicated = 1 in {
2575 def DEALLOC_RET_cNotPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
2577 "if (!$src1) dealloc_return",
2582 // if (Ps.new) dealloc_return:nt
2583 let isReturn = 1, isTerminator = 1,
2584 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
2585 isPredicated = 1 in {
2586 def DEALLOC_RET_cdnPnt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
2588 "if ($src1.new) dealloc_return:nt",
2593 // if (!Ps.new) dealloc_return:nt
2594 let isReturn = 1, isTerminator = 1,
2595 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
2596 isPredicated = 1 in {
2597 def DEALLOC_RET_cNotdnPnt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
2599 "if (!$src1.new) dealloc_return:nt",
2604 // if (Ps.new) dealloc_return:t
2605 let isReturn = 1, isTerminator = 1,
2606 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
2607 isPredicated = 1 in {
2608 def DEALLOC_RET_cdnPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
2610 "if ($src1.new) dealloc_return:t",
2615 // if (!Ps.new) dealloc_return:nt
2616 let isReturn = 1, isTerminator = 1,
2617 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
2618 isPredicated = 1 in {
2619 def DEALLOC_RET_cNotdnPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
2621 "if (!$src1.new) dealloc_return:t",
2626 // Load/Store with absolute addressing mode
2629 multiclass ST_Abs_Predbase<string mnemonic, RegisterClass RC, bit isNot,
2631 let isPredicatedNew = isPredNew in
2632 def NAME#_V4 : STInst2<(outs),
2633 (ins PredRegs:$src1, u0AlwaysExt:$absaddr, RC: $src2),
2634 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
2635 ") ")#mnemonic#"(##$absaddr) = $src2",
2640 multiclass ST_Abs_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
2641 let isPredicatedFalse = PredNot in {
2642 defm _c#NAME : ST_Abs_Predbase<mnemonic, RC, PredNot, 0>;
2644 defm _cdn#NAME : ST_Abs_Predbase<mnemonic, RC, PredNot, 1>;
2648 let isNVStorable = 1, isExtended = 1, neverHasSideEffects = 1 in
2649 multiclass ST_Abs<string mnemonic, string CextOp, RegisterClass RC> {
2650 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
2651 let opExtendable = 0, isPredicable = 1 in
2652 def NAME#_V4 : STInst2<(outs),
2653 (ins u0AlwaysExt:$absaddr, RC:$src),
2654 mnemonic#"(##$absaddr) = $src",
2658 let opExtendable = 1, isPredicated = 1 in {
2659 defm Pt : ST_Abs_Pred<mnemonic, RC, 0>;
2660 defm NotPt : ST_Abs_Pred<mnemonic, RC, 1>;
2665 multiclass ST_Abs_Predbase_nv<string mnemonic, RegisterClass RC, bit isNot,
2667 let isPredicatedNew = isPredNew in
2668 def NAME#_nv_V4 : NVInst_V4<(outs),
2669 (ins PredRegs:$src1, u0AlwaysExt:$absaddr, RC: $src2),
2670 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
2671 ") ")#mnemonic#"(##$absaddr) = $src2.new",
2676 multiclass ST_Abs_Pred_nv<string mnemonic, RegisterClass RC, bit PredNot> {
2677 let isPredicatedFalse = PredNot in {
2678 defm _c#NAME : ST_Abs_Predbase_nv<mnemonic, RC, PredNot, 0>;
2680 defm _cdn#NAME : ST_Abs_Predbase_nv<mnemonic, RC, PredNot, 1>;
2684 let mayStore = 1, isNVStore = 1, isExtended = 1, neverHasSideEffects = 1 in
2685 multiclass ST_Abs_nv<string mnemonic, string CextOp, RegisterClass RC> {
2686 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
2687 let opExtendable = 0, isPredicable = 1 in
2688 def NAME#_nv_V4 : NVInst_V4<(outs),
2689 (ins u0AlwaysExt:$absaddr, RC:$src),
2690 mnemonic#"(##$absaddr) = $src.new",
2694 let opExtendable = 1, isPredicated = 1 in {
2695 defm Pt : ST_Abs_Pred_nv<mnemonic, RC, 0>;
2696 defm NotPt : ST_Abs_Pred_nv<mnemonic, RC, 1>;
2701 let addrMode = Absolute in {
2702 let accessSize = ByteAccess in
2703 defm STrib_abs : ST_Abs<"memb", "STrib", IntRegs>,
2704 ST_Abs_nv<"memb", "STrib", IntRegs>, AddrModeRel;
2706 let accessSize = HalfWordAccess in
2707 defm STrih_abs : ST_Abs<"memh", "STrih", IntRegs>,
2708 ST_Abs_nv<"memh", "STrih", IntRegs>, AddrModeRel;
2710 let accessSize = WordAccess in
2711 defm STriw_abs : ST_Abs<"memw", "STriw", IntRegs>,
2712 ST_Abs_nv<"memw", "STriw", IntRegs>, AddrModeRel;
2714 let accessSize = DoubleWordAccess, isNVStorable = 0 in
2715 defm STrid_abs : ST_Abs<"memd", "STrid", DoubleRegs>, AddrModeRel;
2718 let Predicates = [HasV4T], AddedComplexity = 30 in {
2719 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
2720 (HexagonCONST32 tglobaladdr:$absaddr)),
2721 (STrib_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
2723 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
2724 (HexagonCONST32 tglobaladdr:$absaddr)),
2725 (STrih_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
2727 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32 tglobaladdr:$absaddr)),
2728 (STriw_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
2730 def : Pat<(store (i64 DoubleRegs:$src1),
2731 (HexagonCONST32 tglobaladdr:$absaddr)),
2732 (STrid_abs_V4 tglobaladdr: $absaddr, DoubleRegs: $src1)>;
2735 //===----------------------------------------------------------------------===//
2736 // multiclass for store instructions with GP-relative addressing mode.
2737 // mem[bhwd](#global)=Rt
2738 // if ([!]Pv[.new]) mem[bhwd](##global) = Rt
2739 //===----------------------------------------------------------------------===//
2740 let mayStore = 1, isNVStorable = 1 in
2741 multiclass ST_GP<string mnemonic, string BaseOp, RegisterClass RC> {
2742 let BaseOpcode = BaseOp, isPredicable = 1 in
2743 def NAME#_V4 : STInst2<(outs),
2744 (ins globaladdress:$global, RC:$src),
2745 mnemonic#"(#$global) = $src",
2748 // When GP-relative instructions are predicated, their addressing mode is
2749 // changed to absolute and they are always constant extended.
2750 let BaseOpcode = BaseOp, isExtended = 1, opExtendable = 1,
2751 isPredicated = 1 in {
2752 defm Pt : ST_Abs_Pred <mnemonic, RC, 0>;
2753 defm NotPt : ST_Abs_Pred <mnemonic, RC, 1>;
2757 let mayStore = 1, isNVStore = 1 in
2758 multiclass ST_GP_nv<string mnemonic, string BaseOp, RegisterClass RC> {
2759 let BaseOpcode = BaseOp, isPredicable = 1 in
2760 def NAME#_nv_V4 : NVInst_V4<(outs),
2761 (ins u0AlwaysExt:$global, RC:$src),
2762 mnemonic#"(#$global) = $src.new",
2766 // When GP-relative instructions are predicated, their addressing mode is
2767 // changed to absolute and they are always constant extended.
2768 let BaseOpcode = BaseOp, isExtended = 1, opExtendable = 1,
2769 isPredicated = 1 in {
2770 defm Pt : ST_Abs_Pred_nv<mnemonic, RC, 0>;
2771 defm NotPt : ST_Abs_Pred_nv<mnemonic, RC, 1>;
2775 let validSubTargets = HasV4SubT, neverHasSideEffects = 1 in {
2776 let isNVStorable = 0 in
2777 defm STd_GP : ST_GP <"memd", "STd_GP", DoubleRegs>, PredNewRel;
2779 defm STb_GP : ST_GP<"memb", "STb_GP", IntRegs>,
2780 ST_GP_nv<"memb", "STb_GP", IntRegs>, NewValueRel;
2781 defm STh_GP : ST_GP<"memh", "STh_GP", IntRegs>,
2782 ST_GP_nv<"memh", "STh_GP", IntRegs>, NewValueRel;
2783 defm STw_GP : ST_GP<"memw", "STw_GP", IntRegs>,
2784 ST_GP_nv<"memw", "STw_GP", IntRegs>, NewValueRel;
2787 // 64 bit atomic store
2788 def : Pat <(atomic_store_64 (HexagonCONST32_GP tglobaladdr:$global),
2789 (i64 DoubleRegs:$src1)),
2790 (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2793 // Map from store(globaladdress) -> memd(#foo)
2794 let AddedComplexity = 100 in
2795 def : Pat <(store (i64 DoubleRegs:$src1),
2796 (HexagonCONST32_GP tglobaladdr:$global)),
2797 (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>;
2799 // 8 bit atomic store
2800 def : Pat < (atomic_store_8 (HexagonCONST32_GP tglobaladdr:$global),
2801 (i32 IntRegs:$src1)),
2802 (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
2804 // Map from store(globaladdress) -> memb(#foo)
2805 let AddedComplexity = 100 in
2806 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
2807 (HexagonCONST32_GP tglobaladdr:$global)),
2808 (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
2810 // Map from "i1 = constant<-1>; memw(CONST32(#foo)) = i1"
2811 // to "r0 = 1; memw(#foo) = r0"
2812 let AddedComplexity = 100 in
2813 def : Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
2814 (STb_GP_V4 tglobaladdr:$global, (TFRI 1))>;
2816 def : Pat<(atomic_store_16 (HexagonCONST32_GP tglobaladdr:$global),
2817 (i32 IntRegs:$src1)),
2818 (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
2820 // Map from store(globaladdress) -> memh(#foo)
2821 let AddedComplexity = 100 in
2822 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
2823 (HexagonCONST32_GP tglobaladdr:$global)),
2824 (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
2826 // 32 bit atomic store
2827 def : Pat<(atomic_store_32 (HexagonCONST32_GP tglobaladdr:$global),
2828 (i32 IntRegs:$src1)),
2829 (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
2831 // Map from store(globaladdress) -> memw(#foo)
2832 let AddedComplexity = 100 in
2833 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
2834 (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
2836 //===----------------------------------------------------------------------===//
2837 // Multiclass for the load instructions with absolute addressing mode.
2838 //===----------------------------------------------------------------------===//
2839 multiclass LD_Abs_Predbase<string mnemonic, RegisterClass RC, bit isNot,
2841 let isPredicatedNew = isPredNew in
2842 def NAME : LDInst2<(outs RC:$dst),
2843 (ins PredRegs:$src1, u0AlwaysExt:$absaddr),
2844 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
2845 ") ")#"$dst = "#mnemonic#"(##$absaddr)",
2850 multiclass LD_Abs_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
2851 let isPredicatedFalse = PredNot in {
2852 defm _c#NAME : LD_Abs_Predbase<mnemonic, RC, PredNot, 0>;
2854 defm _cdn#NAME : LD_Abs_Predbase<mnemonic, RC, PredNot, 1>;
2858 let isExtended = 1, neverHasSideEffects = 1 in
2859 multiclass LD_Abs<string mnemonic, string CextOp, RegisterClass RC> {
2860 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
2861 let opExtendable = 1, isPredicable = 1 in
2862 def NAME#_V4 : LDInst2<(outs RC:$dst),
2863 (ins u0AlwaysExt:$absaddr),
2864 "$dst = "#mnemonic#"(##$absaddr)",
2868 let opExtendable = 2, isPredicated = 1 in {
2869 defm Pt_V4 : LD_Abs_Pred<mnemonic, RC, 0>;
2870 defm NotPt_V4 : LD_Abs_Pred<mnemonic, RC, 1>;
2875 let addrMode = Absolute in {
2876 let accessSize = ByteAccess in {
2877 defm LDrib_abs : LD_Abs<"memb", "LDrib", IntRegs>, AddrModeRel;
2878 defm LDriub_abs : LD_Abs<"memub", "LDriub", IntRegs>, AddrModeRel;
2880 let accessSize = HalfWordAccess in {
2881 defm LDrih_abs : LD_Abs<"memh", "LDrih", IntRegs>, AddrModeRel;
2882 defm LDriuh_abs : LD_Abs<"memuh", "LDriuh", IntRegs>, AddrModeRel;
2884 let accessSize = WordAccess in
2885 defm LDriw_abs : LD_Abs<"memw", "LDriw", IntRegs>, AddrModeRel;
2887 let accessSize = DoubleWordAccess in
2888 defm LDrid_abs : LD_Abs<"memd", "LDrid", DoubleRegs>, AddrModeRel;
2891 let Predicates = [HasV4T], AddedComplexity = 30 in {
2892 def : Pat<(i32 (load (HexagonCONST32 tglobaladdr:$absaddr))),
2893 (LDriw_abs_V4 tglobaladdr: $absaddr)>;
2895 def : Pat<(i32 (sextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
2896 (LDrib_abs_V4 tglobaladdr:$absaddr)>;
2898 def : Pat<(i32 (zextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
2899 (LDriub_abs_V4 tglobaladdr:$absaddr)>;
2901 def : Pat<(i32 (sextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
2902 (LDrih_abs_V4 tglobaladdr:$absaddr)>;
2904 def : Pat<(i32 (zextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
2905 (LDriuh_abs_V4 tglobaladdr:$absaddr)>;
2908 //===----------------------------------------------------------------------===//
2909 // multiclass for load instructions with GP-relative addressing mode.
2910 // Rx=mem[bhwd](##global)
2911 // if ([!]Pv[.new]) Rx=mem[bhwd](##global)
2912 //===----------------------------------------------------------------------===//
2913 let neverHasSideEffects = 1, validSubTargets = HasV4SubT in
2914 multiclass LD_GP<string mnemonic, string BaseOp, RegisterClass RC> {
2915 let BaseOpcode = BaseOp in {
2916 let isPredicable = 1 in
2917 def NAME#_V4 : LDInst2<(outs RC:$dst),
2918 (ins globaladdress:$global),
2919 "$dst = "#mnemonic#"(#$global)",
2922 let isExtended = 1, opExtendable = 2, isPredicated = 1 in {
2923 defm Pt_V4 : LD_Abs_Pred<mnemonic, RC, 0>;
2924 defm NotPt_V4 : LD_Abs_Pred<mnemonic, RC, 1>;
2929 defm LDd_GP : LD_GP<"memd", "LDd_GP", DoubleRegs>, PredNewRel;
2930 defm LDb_GP : LD_GP<"memb", "LDb_GP", IntRegs>, PredNewRel;
2931 defm LDub_GP : LD_GP<"memub", "LDub_GP", IntRegs>, PredNewRel;
2932 defm LDh_GP : LD_GP<"memh", "LDh_GP", IntRegs>, PredNewRel;
2933 defm LDuh_GP : LD_GP<"memuh", "LDuh_GP", IntRegs>, PredNewRel;
2934 defm LDw_GP : LD_GP<"memw", "LDw_GP", IntRegs>, PredNewRel;
2936 def : Pat <(atomic_load_64 (HexagonCONST32_GP tglobaladdr:$global)),
2937 (i64 (LDd_GP_V4 tglobaladdr:$global))>;
2939 def : Pat <(atomic_load_32 (HexagonCONST32_GP tglobaladdr:$global)),
2940 (i32 (LDw_GP_V4 tglobaladdr:$global))>;
2942 def : Pat <(atomic_load_16 (HexagonCONST32_GP tglobaladdr:$global)),
2943 (i32 (LDuh_GP_V4 tglobaladdr:$global))>;
2945 def : Pat <(atomic_load_8 (HexagonCONST32_GP tglobaladdr:$global)),
2946 (i32 (LDub_GP_V4 tglobaladdr:$global))>;
2948 // Map from load(globaladdress) -> memw(#foo + 0)
2949 let AddedComplexity = 100 in
2950 def : Pat <(i64 (load (HexagonCONST32_GP tglobaladdr:$global))),
2951 (i64 (LDd_GP_V4 tglobaladdr:$global))>;
2953 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd
2954 let AddedComplexity = 100 in
2955 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
2956 (i1 (TFR_PdRs (i32 (LDb_GP_V4 tglobaladdr:$global))))>;
2958 // When the Interprocedural Global Variable optimizer realizes that a certain
2959 // global variable takes only two constant values, it shrinks the global to
2960 // a boolean. Catch those loads here in the following 3 patterns.
2961 let AddedComplexity = 100 in
2962 def : Pat <(i32 (extloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
2963 (i32 (LDb_GP_V4 tglobaladdr:$global))>;
2965 let AddedComplexity = 100 in
2966 def : Pat <(i32 (sextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
2967 (i32 (LDb_GP_V4 tglobaladdr:$global))>;
2969 // Map from load(globaladdress) -> memb(#foo)
2970 let AddedComplexity = 100 in
2971 def : Pat <(i32 (extloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
2972 (i32 (LDb_GP_V4 tglobaladdr:$global))>;
2974 // Map from load(globaladdress) -> memb(#foo)
2975 let AddedComplexity = 100 in
2976 def : Pat <(i32 (sextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
2977 (i32 (LDb_GP_V4 tglobaladdr:$global))>;
2979 let AddedComplexity = 100 in
2980 def : Pat <(i32 (zextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
2981 (i32 (LDub_GP_V4 tglobaladdr:$global))>;
2983 // Map from load(globaladdress) -> memub(#foo)
2984 let AddedComplexity = 100 in
2985 def : Pat <(i32 (zextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
2986 (i32 (LDub_GP_V4 tglobaladdr:$global))>;
2988 // Map from load(globaladdress) -> memh(#foo)
2989 let AddedComplexity = 100 in
2990 def : Pat <(i32 (extloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
2991 (i32 (LDh_GP_V4 tglobaladdr:$global))>;
2993 // Map from load(globaladdress) -> memh(#foo)
2994 let AddedComplexity = 100 in
2995 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
2996 (i32 (LDh_GP_V4 tglobaladdr:$global))>;
2998 // Map from load(globaladdress) -> memuh(#foo)
2999 let AddedComplexity = 100 in
3000 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
3001 (i32 (LDuh_GP_V4 tglobaladdr:$global))>;
3003 // Map from load(globaladdress) -> memw(#foo)
3004 let AddedComplexity = 100 in
3005 def : Pat <(i32 (load (HexagonCONST32_GP tglobaladdr:$global))),
3006 (i32 (LDw_GP_V4 tglobaladdr:$global))>;
3009 // Transfer global address into a register
3010 let AddedComplexity=50, isMoveImm = 1, isReMaterializable = 1 in
3011 def TFRI_V4 : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$src1),
3013 [(set IntRegs:$dst, (HexagonCONST32 tglobaladdr:$src1))]>,
3016 // Transfer a block address into a register
3017 def : Pat<(HexagonCONST32_GP tblockaddress:$src1),
3018 (TFRI_V4 tblockaddress:$src1)>,
3021 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
3022 def TFRI_cPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3023 (ins PredRegs:$src1, globaladdress:$src2),
3024 "if($src1) $dst = ##$src2",
3028 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
3029 def TFRI_cNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3030 (ins PredRegs:$src1, globaladdress:$src2),
3031 "if(!$src1) $dst = ##$src2",
3035 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
3036 def TFRI_cdnPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3037 (ins PredRegs:$src1, globaladdress:$src2),
3038 "if($src1.new) $dst = ##$src2",
3042 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
3043 def TFRI_cdnNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3044 (ins PredRegs:$src1, globaladdress:$src2),
3045 "if(!$src1.new) $dst = ##$src2",
3049 let AddedComplexity = 50, Predicates = [HasV4T] in
3050 def : Pat<(HexagonCONST32_GP tglobaladdr:$src1),
3051 (TFRI_V4 tglobaladdr:$src1)>;
3054 // Load - Indirect with long offset: These instructions take global address
3056 let isExtended = 1, opExtendable = 3, AddedComplexity = 40,
3057 validSubTargets = HasV4SubT in
3058 def LDrid_ind_lo_V4 : LDInst<(outs DoubleRegs:$dst),
3059 (ins IntRegs:$src1, u2Imm:$src2, globaladdressExt:$offset),
3060 "$dst=memd($src1<<#$src2+##$offset)",
3061 [(set (i64 DoubleRegs:$dst),
3062 (load (add (shl IntRegs:$src1, u2ImmPred:$src2),
3063 (HexagonCONST32 tglobaladdr:$offset))))]>,
3066 let AddedComplexity = 40 in
3067 multiclass LD_indirect_lo<string OpcStr, PatFrag OpNode> {
3068 let isExtended = 1, opExtendable = 3, validSubTargets = HasV4SubT in
3069 def _lo_V4 : LDInst<(outs IntRegs:$dst),
3070 (ins IntRegs:$src1, u2Imm:$src2, globaladdressExt:$offset),
3071 !strconcat("$dst = ",
3072 !strconcat(OpcStr, "($src1<<#$src2+##$offset)")),
3074 (i32 (OpNode (add (shl IntRegs:$src1, u2ImmPred:$src2),
3075 (HexagonCONST32 tglobaladdr:$offset)))))]>,
3079 defm LDrib_ind : LD_indirect_lo<"memb", sextloadi8>;
3080 defm LDriub_ind : LD_indirect_lo<"memub", zextloadi8>;
3081 defm LDriub_ind_anyext : LD_indirect_lo<"memub", extloadi8>;
3082 defm LDrih_ind : LD_indirect_lo<"memh", sextloadi16>;
3083 defm LDriuh_ind : LD_indirect_lo<"memuh", zextloadi16>;
3084 defm LDriuh_ind_anyext : LD_indirect_lo<"memuh", extloadi16>;
3085 defm LDriw_ind : LD_indirect_lo<"memw", load>;
3087 let AddedComplexity = 40 in
3088 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1,
3089 (NumUsesBelowThresCONST32 tglobaladdr:$offset)))),
3090 (i32 (LDrib_ind_lo_V4 IntRegs:$src1, 0, tglobaladdr:$offset))>,
3093 let AddedComplexity = 40 in
3094 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1,
3095 (NumUsesBelowThresCONST32 tglobaladdr:$offset)))),
3096 (i32 (LDriub_ind_lo_V4 IntRegs:$src1, 0, tglobaladdr:$offset))>,
3099 let Predicates = [HasV4T], AddedComplexity = 30 in {
3100 def : Pat<(truncstorei8 (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
3101 (STrib_abs_V4 u0AlwaysExtPred:$src2, IntRegs: $src1)>;
3103 def : Pat<(truncstorei16 (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
3104 (STrih_abs_V4 u0AlwaysExtPred:$src2, IntRegs: $src1)>;
3106 def : Pat<(store (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
3107 (STriw_abs_V4 u0AlwaysExtPred:$src2, IntRegs: $src1)>;
3110 let Predicates = [HasV4T], AddedComplexity = 30 in {
3111 def : Pat<(i32 (load u0AlwaysExtPred:$src)),
3112 (LDriw_abs_V4 u0AlwaysExtPred:$src)>;
3114 def : Pat<(i32 (sextloadi8 u0AlwaysExtPred:$src)),
3115 (LDrib_abs_V4 u0AlwaysExtPred:$src)>;
3117 def : Pat<(i32 (zextloadi8 u0AlwaysExtPred:$src)),
3118 (LDriub_abs_V4 u0AlwaysExtPred:$src)>;
3120 def : Pat<(i32 (sextloadi16 u0AlwaysExtPred:$src)),
3121 (LDrih_abs_V4 u0AlwaysExtPred:$src)>;
3123 def : Pat<(i32 (zextloadi16 u0AlwaysExtPred:$src)),
3124 (LDriuh_abs_V4 u0AlwaysExtPred:$src)>;
3127 // Indexed store word - global address.
3128 // memw(Rs+#u6:2)=#S8
3129 let AddedComplexity = 10 in
3130 def STriw_offset_ext_V4 : STInst<(outs),
3131 (ins IntRegs:$src1, u6_2Imm:$src2, globaladdress:$src3),
3132 "memw($src1+#$src2) = ##$src3",
3133 [(store (HexagonCONST32 tglobaladdr:$src3),
3134 (add IntRegs:$src1, u6_2ImmPred:$src2))]>,
3138 // Indexed store double word - global address.
3139 // memw(Rs+#u6:2)=#S8
3140 let AddedComplexity = 10 in
3141 def STrih_offset_ext_V4 : STInst<(outs),
3142 (ins IntRegs:$src1, u6_1Imm:$src2, globaladdress:$src3),
3143 "memh($src1+#$src2) = ##$src3",
3144 [(truncstorei16 (HexagonCONST32 tglobaladdr:$src3),
3145 (add IntRegs:$src1, u6_1ImmPred:$src2))]>,
3147 // Map from store(globaladdress + x) -> memd(#foo + x)
3148 let AddedComplexity = 100 in
3149 def : Pat<(store (i64 DoubleRegs:$src1),
3150 FoldGlobalAddrGP:$addr),
3151 (STrid_abs_V4 FoldGlobalAddrGP:$addr, (i64 DoubleRegs:$src1))>,
3154 def : Pat<(atomic_store_64 FoldGlobalAddrGP:$addr,
3155 (i64 DoubleRegs:$src1)),
3156 (STrid_abs_V4 FoldGlobalAddrGP:$addr, (i64 DoubleRegs:$src1))>,
3159 // Map from store(globaladdress + x) -> memb(#foo + x)
3160 let AddedComplexity = 100 in
3161 def : Pat<(truncstorei8 (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
3162 (STrib_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3165 def : Pat<(atomic_store_8 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
3166 (STrib_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3169 // Map from store(globaladdress + x) -> memh(#foo + x)
3170 let AddedComplexity = 100 in
3171 def : Pat<(truncstorei16 (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
3172 (STrih_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3175 def : Pat<(atomic_store_16 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
3176 (STrih_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3179 // Map from store(globaladdress + x) -> memw(#foo + x)
3180 let AddedComplexity = 100 in
3181 def : Pat<(store (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
3182 (STriw_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3185 def : Pat<(atomic_store_32 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
3186 (STriw_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3189 // Map from load(globaladdress + x) -> memd(#foo + x)
3190 let AddedComplexity = 100 in
3191 def : Pat<(i64 (load FoldGlobalAddrGP:$addr)),
3192 (i64 (LDrid_abs_V4 FoldGlobalAddrGP:$addr))>,
3195 def : Pat<(atomic_load_64 FoldGlobalAddrGP:$addr),
3196 (i64 (LDrid_abs_V4 FoldGlobalAddrGP:$addr))>,
3199 // Map from load(globaladdress + x) -> memb(#foo + x)
3200 let AddedComplexity = 100 in
3201 def : Pat<(i32 (extloadi8 FoldGlobalAddrGP:$addr)),
3202 (i32 (LDrib_abs_V4 FoldGlobalAddrGP:$addr))>,
3205 // Map from load(globaladdress + x) -> memb(#foo + x)
3206 let AddedComplexity = 100 in
3207 def : Pat<(i32 (sextloadi8 FoldGlobalAddrGP:$addr)),
3208 (i32 (LDrib_abs_V4 FoldGlobalAddrGP:$addr))>,
3211 //let AddedComplexity = 100 in
3212 let AddedComplexity = 100 in
3213 def : Pat<(i32 (extloadi16 FoldGlobalAddrGP:$addr)),
3214 (i32 (LDrih_abs_V4 FoldGlobalAddrGP:$addr))>,
3217 // Map from load(globaladdress + x) -> memh(#foo + x)
3218 let AddedComplexity = 100 in
3219 def : Pat<(i32 (sextloadi16 FoldGlobalAddrGP:$addr)),
3220 (i32 (LDrih_abs_V4 FoldGlobalAddrGP:$addr))>,
3223 // Map from load(globaladdress + x) -> memuh(#foo + x)
3224 let AddedComplexity = 100 in
3225 def : Pat<(i32 (zextloadi16 FoldGlobalAddrGP:$addr)),
3226 (i32 (LDriuh_abs_V4 FoldGlobalAddrGP:$addr))>,
3229 def : Pat<(atomic_load_16 FoldGlobalAddrGP:$addr),
3230 (i32 (LDriuh_abs_V4 FoldGlobalAddrGP:$addr))>,
3233 // Map from load(globaladdress + x) -> memub(#foo + x)
3234 let AddedComplexity = 100 in
3235 def : Pat<(i32 (zextloadi8 FoldGlobalAddrGP:$addr)),
3236 (i32 (LDriub_abs_V4 FoldGlobalAddrGP:$addr))>,
3239 def : Pat<(atomic_load_8 FoldGlobalAddrGP:$addr),
3240 (i32 (LDriub_abs_V4 FoldGlobalAddrGP:$addr))>,
3243 // Map from load(globaladdress + x) -> memw(#foo + x)
3244 let AddedComplexity = 100 in
3245 def : Pat<(i32 (load FoldGlobalAddrGP:$addr)),
3246 (i32 (LDriw_abs_V4 FoldGlobalAddrGP:$addr))>,
3249 def : Pat<(atomic_load_32 FoldGlobalAddrGP:$addr),
3250 (i32 (LDriw_abs_V4 FoldGlobalAddrGP:$addr))>,